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* drm/nouveau/dp: remove reliance on vbios for native displayportBen Skeggs2011-09-206-63/+126
* drm/nouveau/dp: rewrite auxch transaction routinesBen Skeggs2011-09-202-105/+132
* drm/nouveau: workaround semaphore hw bug causing unnecessary interruptsBen Skeggs2011-09-201-1/+1
* drm/nouveau/tmr: fix miscalculation of ratio on pre-nv4x chipsetsBen Skeggs2011-09-201-26/+2
* drm/nva3/pm: fixup for NVAF specialBen Skeggs2011-09-201-1/+7
* drm/nva3/pm: use crystal freq where appropriateBen Skeggs2011-09-201-3/+4
* drm/nouveau: determine timing crystal freq from strapsBen Skeggs2011-09-202-1/+19
* drm/nva3/pm: pll disabled if bit 0 of ctrl not setBen Skeggs2011-09-201-19/+23
* drm/nouveau: magic to make auxch on new macbooks booted in EFI mode workBen Skeggs2011-09-201-1/+4
* drm/nouveau/pm: Document and expose CL and WR for 0x1002CxRoy Spliet2011-09-202-14/+21
* drm/nouveau/pm: add initial NV3x/NVCx memtiming support, improve other cardsRoy Spliet2011-09-204-143/+206
* drm/nouveau: remove special-casing of hotplug detection typeBen Skeggs2011-09-201-9/+5
* drm/nvd0: no page flipping at the momentBen Skeggs2011-09-201-1/+1
* drm/nvc0/gr: remove max tpc count infoBen Skeggs2011-09-201-6/+2
* drm/nvd0: lets not attempt to dereference a nv50_display pointerBen Skeggs2011-09-201-4/+8
* drm/nouveau: enable hwmon support when both nouveau/hwmon are built as modules.Ken Milmore2011-09-201-3/+3
* drm/nvd0/disp: tidy up what we have so farBen Skeggs2011-09-202-64/+39
* drm/nvd0/disp: rewrite irq handler, should be somewhat sturdier nowBen Skeggs2011-09-201-81/+111
* drm/nvd0/disp: do modeset irq handling from taskletBen Skeggs2011-09-201-7/+22
* drm/nvd0/disp: untested LVDS supportBen Skeggs2011-09-201-16/+66
* drm/nvd0/disp: track down fb positioning methodBen Skeggs2011-09-201-2/+2
* drm/nvd0/disp: determine U table config in or_mode_set()Ben Skeggs2011-09-201-21/+15
* drm/nvd0/disp: dac load detectBen Skeggs2011-09-201-1/+16
* drm/nvd0/disp: handle sync polarity, kill off some unknownBen Skeggs2011-09-201-6/+10
* drm/nvd0/disp: scalingBen Skeggs2011-09-201-5/+32
* drm/nvd0/disp: push the update button in mode_set_base()Ben Skeggs2011-09-201-0/+4
* drm/nvd0/disp: fixup clut so it actually worksBen Skeggs2011-09-201-4/+6
* drm/nvd0/disp: initial attempt at modeset irq handlingBen Skeggs2011-09-201-0/+130
* drm/nvd0/disp: stub dac load detect, prevents oopsBen Skeggs2011-09-201-0/+7
* drm/nvd0/disp: dac encoder moduleBen Skeggs2011-09-201-0/+137
* drm/nvd0/disp: extend the init voodoo to cover crtcsBen Skeggs2011-09-201-19/+27
* drm/nvd0/disp: remove lp reordering from vram dmaobj, create fb dmaobjsBen Skeggs2011-09-201-5/+22
* drm/nvd0/disp: some magic to make evo happeirBen Skeggs2011-09-201-0/+12
* drm/nvd0/disp: they moved the linear flag..Ben Skeggs2011-09-201-3/+6
* drm/nvd0/disp: initial crtc object implementationBen Skeggs2011-09-201-1/+456
* drm/nvd0/disp: skeletal handling of modeset interruptsBen Skeggs2011-09-201-0/+60
* drm/nvd0/disp: start on SOR encoder functionsBen Skeggs2011-09-201-1/+202
* drm/nvd0/disp: setup a couple of dma objects we'll needBen Skeggs2011-09-201-2/+41
* drm/nvd0/disp: start on interrupt handlingBen Skeggs2011-09-201-0/+42
* drm/nvd0/disp: whip up some basic dma handling for the evo channelsBen Skeggs2011-09-201-3/+65
* drm/nvd0/disp: very initial evo setupBen Skeggs2011-09-204-3/+179
* drm/nouveau/bios: allow passing in crtc to the init table parserBen Skeggs2011-09-206-36/+41
* drm/nvd0/pm: enable clock/voltage hooksBen Skeggs2011-09-201-0/+3
* drm/nouveau/bios: fix INIT_GPIO for new chipsetsBen Skeggs2011-09-201-22/+51
* drm/nvd0/gpio: initial implementationBen Skeggs2011-09-204-4/+48
* drm/nvd0/i2c: initial implementationBen Skeggs2011-09-201-16/+35
* drm/nouveau: initial chipset description for nvdX chipsetsBen Skeggs2011-09-201-2/+46
* drm/nouveau: allow modeset module option to select 'headless mode'Ben Skeggs2011-09-203-1/+11
* drm/nouveau: fixup init/fini sequence to deal with no CRTCsBen Skeggs2011-09-202-38/+30
* drm/nouveau: make general drm modesetting init commonBen Skeggs2011-09-208-67/+32