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* clk: stm32f4: fix error handlingChristophe JAILLET2016-07-071-1/+1
| | | | | | | | | This is likely that checking 'clks[idx]' instead of 'clks[n]' is expected here. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1467526003-13318-1-git-send-email-christophe.jaillet@wanadoo.fr
* Merge branch 'clk-lpc32xx' into clk-nextMichael Turquette2016-07-071-2/+1
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| * clk: lpc32xx: allow peripheral clock selection in device treeSylvain Lemieux2016-07-071-2/+1
| | | | | | | | | | | | | | | | | | | | | | This patch add the support to select the peripheral clock (PERIPH) as a parent clock source using the "assigned-clock-parents" parameter in the device tree. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1464982475-24738-1-git-send-email-slemieux.tyco@gmail.com
* | clk: sunxi: make clk-* explicitly non-modularPaul Gortmaker2016-07-076-65/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have the following file --> Kconfig mapping: sunxi/clk-factors.c obj-y sunxi/clk-sun6i-apb0-gates.c CONFIG_MFD_SUN6I_PRCM (bool) sunxi/clk-sun6i-apb0.c CONFIG_MFD_SUN6I_PRCM sunxi/clk-sun6i-ar100.c CONFIG_MFD_SUN6I_PRCM sunxi/clk-sun8i-apb0.c CONFIG_MFD_SUN6I_PRCM sunxi/clk-sun9i-mmc.c obj-y Hence none of these are being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the drivers there is no doubt they are builtin-only. All drivers get mostly the same changes, so they are handled in batch. Changes are (1) convert to builtin_platform_register, (2) use the init.h header, (3) delete the MODULE_LICENCE/MODULE_AUTHOR and associated tags, and (4) delete any ".remove" functions. There was a stray module.h in a file not using any init.h or module.h stuff, so we simply removed that one. In two cases, we explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. We delete the MODULE_LICENSE etc. tags since all that information is already contained at the top of each file in the comments. Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-9-paul.gortmaker@windriver.com
* | clk: oxnas: make it explicitly non-modularPaul Gortmaker2016-07-071-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: drivers/clk/Kconfig:config COMMON_CLK_OXNAS drivers/clk/Kconfig: bool "Clock driver for the OXNAS SoC Family" ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. Cc: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-6-paul.gortmaker@windriver.com
* | clk: Kconfig: Name RK818 in Kconfig for COMMON_CLK_RK808Wadim Egorov2016-07-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | The RK808 and RK818 PMICs are using a similar register map. We can reuse the clk driver for the RK818 PMIC. So let's add the RK818 in the Kconfig description. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1464850228-17244-4-git-send-email-w.egorov@phytec.de
* | clk: hi6220: Change syspll and media_syspll clk to 1.19GHzXinliang Liu2016-07-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the bootloader of HiKey/96boards, syspll and media_syspll clk was initialized to 1.19GHz. So, here changes it in kernel accordingly. 1.19GHz was chosen over 1.2GHz because at 1.19GHz we get more precise HDMI pixel clock (1.19G/16 = 74.4MHz) for 1280x720p@60Hz HDMI (74.25MHz required by standards). Closer pixel clock means better compatibility to HDMI monitors. Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1467189955-21694-1-git-send-email-guodong.xu@linaro.org
* | clk: meson: make gxbb explicitly non-modularPaul Gortmaker2016-07-071-14/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: drivers/clk/meson/Kconfig:config COMMON_CLK_GXBB drivers/clk/meson/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE and ALIAS are no-op for non-modules. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-amlogic@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-3-paul.gortmaker@windriver.com
* | clk: meson8b: make it explicitly non-modularPaul Gortmaker2016-07-071-15/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: drivers/clk/meson/Kconfig:config COMMON_CLK_MESON8B drivers/clk/meson/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. However a recent commit added a bunch of modular boilerplate to this driver. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Also note that MODULE DEVICE_TABLE/ALIAS are no-op when non-modular. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-amlogic@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-2-paul.gortmaker@windriver.com
* | clk: qcom: add EBI2 clocks to the MSM8660 GCCLinus Walleij2016-07-021-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the EBI2 2X and EBI2 clocks to the MSM8660/APQ8060 GCC. This is necessary to enable clocking of the external bus interface so that peripherals on it can be mounted. These two clocks are simple gated branch clocks. In the vendor tree clock-8x60, these clocks have some kind of dependency, the EBI2 clock has .depends = &ebi2_2x_clk.c, what this means is undocumented, it doesn't seem like there is a parent/child relationship, so the solution I chose was to just have the EBI2 driver get and enable both clocks. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: imx7d: only enable minimum required clocksDong Aisheng2016-07-021-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Formerly clk core does not support imx7d clock type well that all its clock operations requires the parent clock on. Therefore we enabled all clocks by default in clock driver initialization for other module clocks operate well. After patch 'clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE', clk core can handle such clock type well, so we don't have to enable them all by default anymore. Instead, we only enable a minimum required set of clocks. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLEDong Aisheng2016-07-021-357/+357
| | | | | | | | | | | | | | | | | | | | | | | | i.MX7D requires all clocks operations including enable/disable, rate change and re-parent with its parent clock on. Changing to the correct APIs to tell clk core such requirement. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: imx: add clk api for supporting CLK_OPS_PARENT_ENABLE clocksDong Aisheng2016-07-021-0/+32
| | | | | | | | | | | | | | | | | | | | | | IMX SoCs like i.MX7D requires using CLK_OPS_PARENT_ENABLE flags, adding the corresponding clock APIs variants for easily to use. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: imx: re-order and concentrate the same type of clk apiDong Aisheng2016-07-021-29/+29
| | | | | | | | | | | | | | | | | | Re-order and concentrate the same type of clk api for better code maintenance. Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: core: support clocks which requires parents enable (part 2)Dong Aisheng2016-07-021-15/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Freescale i.MX7D platform, all clocks operations, including enable/disable, rate change and re-parent, requires its parent clock on. Current clock core can not support it well. This patch adding flag CLK_OPS_PARENT_ENABLE to handle this special case in clock core that enable its parent clock firstly for each operation and disable it later after operation complete. The patch part 2 fixes set clock rate and set parent while its parent is off. The most special case is for set_parent() operation which requires all parents including both old and new one to be enabled at the same time during the operation. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@codeaurora.org: Move set_rate tracepoint after prepare_enable] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: core: support clocks which requires parents enable (part 1)Dong Aisheng2016-07-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Freescale i.MX7D platform, all clocks operations, including enable/disable, rate change and re-parent, requires its parent clock enable. Current clock core can not support it well. This patch introduce a new flag CLK_OPS_PARENT_ENABLE to handle this special case in clock core that enable its parent clock firstly for each operation and disable it later after operation complete. The patch part 1 fixes the possible disabling clocks while its parent is off during kernel booting phase in clk_disable_unused_subtree(). Before the completion of kernel booting, clock tree is still not built completely, there may be a case that the child clock is on but its parent is off which could be caused by either HW initial reset state or bootloader initialization. Taking bootloader as an example, we may enable all clocks in HW by default. And during kernel booting time, the parent clock could be disabled in its driver probe due to calling clk_prepare_enable and clk_disable_unprepare. Because it's child clock is only enabled in HW while its SW usecount in clock tree is still 0, so clk_disable of parent clock will gate the parent clock in both HW and SW usecount ultimately. Then there will be a child clock is still on in HW but its parent is already off. Later in clk_disable_unused(), this clock disable accessing while its parent off will cause system hang due to the limitation of HW which must require its parent on. This patch simply enables the parent clock first before disabling if flag CLK_OPS_PARENT_ENABLE is set in clk_disable_unused_subtree(). This is a simple solution and only affects booting time. After kernel booting up the clock tree is already created, there will be no case that child is off but its parent is off. So no need do this checking for normal clk_disable() later. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: move clk_disable_unused after clk_core_disable_unprepare functionDong Aisheng2016-07-021-98/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | No function level change, just moving code place. clk_disable_unused function will need to call clk_core_prepare_enable/ clk_core_disable_unprepare when adding CLK_OPS_PARENT_ENABLE features. So move it after clk_core_disable_unprepare to avoid adding forward declared functions later. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: introduce clk_core_enable_lock and clk_core_disable_lock functionsDong Aisheng2016-07-021-22/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This can be useful when clock core wants to enable/disable clocks. Then we don't have to convert the struct clk_core to struct clk to call clk_enable/clk_disable which is a bit un-align with exist using. And after introduce clk_core_{enable|disable}_lock, we can refine clk_enable and clk_disable a bit. As well as clk_core_{enable|disable}_lock, we also added clk_core_{prepare|unprepare}_lock and clk_core_prepare_enable/ clk_core_unprepare_disable for clock core to easily use. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge tag 'v4.8-rockchip-clk1' of ↵Stephen Boyd2016-07-022-52/+84
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: Placeholder for the rk3399 watchdog pclk, some newly exported rk3228 clockids and a small fix for the not yet used spdif to displayport clock on the rk3399. * tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits clk: rockchip: export rk3228 MAC clocks clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk clk: rockchip: export rk3228 audio clocks clk: rockchip: include rk3228 downstream muxes into fractional dividers clk: rockchip: fix incorrect rk3228 clock registers clk: rockchip: add clock-ids for rk3228 MAC clocks clk: rockchip: add clock-ids for rk3228 audio clocks clk: rockchip: add a dummy clock for the watchdog pclk on rk3399
| * | clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bitsXing Zheng2016-07-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx, it should be bit_8, let's fix it. Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399") Reported-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Cc: stable@vger.kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: export rk3228 MAC clocksXing Zheng2016-07-011-11/+11
| | | | | | | | | | | | | | | | | | | | | This patch exports related MAC clocks for dts reference. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclkXing Zheng2016-07-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | The sclk_macphy_50m is confusing, the sclk_mac_extclk describes a external clock clearly. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: export rk3228 audio clocksXing Zheng2016-07-011-4/+4
| | | | | | | | | | | | | | | | | | | | | This patch exports related i2s/spdif clocks for dts reference. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: include rk3228 downstream muxes into fractional dividersXing Zheng2016-07-011-29/+52
| | | | | | | | | | | | | | | | | | | | | | | | During the initial conversion to the newly introduced combined fractional dividers+muxes the rk3228 clocks were left out, so convert them now. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: fix incorrect rk3228 clock registersXing Zheng2016-06-221-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | Due to copy and paste carelessly, RK3288_CLKxxx references are incorrect, we need to fix them. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: add a dummy clock for the watchdog pclk on rk3399Xing Zheng2016-05-301-0/+9
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Like rk3288, the pclk supplying the watchdog is controlled via the SGRF register area. Additionally the SGRF isn't even writable in every boot mode. But still the clock control is available and in the future someone might want to use it. Therefore define a simple clock for the time being so that the watchdog driver can read its rate. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Stephen Barber <smbarber@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | Merge tag 'tegra-for-4.8-clk' of ↵Stephen Boyd2016-07-028-666/+602
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next Pull tegra clk driver updates from Thierry Reding: Fixes and enhancements mostly for Tegra210 clocks that allow DSI and HDMI to work on Tegra X1. There's also a refactoring, including fixes, the USB PLL. * tag 'tegra-for-4.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Initialize UTMI PLL when enabling PLLU clk: tegra: Micro-optimize Tegra210 clock setup clk: tegra: Make sor_safe the parent of dpaux and dpaux1 clk: tegra: Mark timer clock as critical clk: tegra: Enable sor1 and sor1_src on Tegra210 clk: tegra: Squash sor1 safe/brick/src into a single mux clk: tegra: Disable spread spectrum on pll_d2 clk: tegra: Fixup post dividers on Tegra210
| * | clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker2016-06-306-598/+531
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the UTMI PLL initialization code form clk-tegra<chip>.c files into clk-pll.c. UTMI PLL was being configured and set in HW control right after registration. However, when the clock init_table is processed and child clks of PLLU are enabled, it will call in and enable PLLU as well, and initiate SW enabling sequence even though PLLU is already in HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status. Doing the initialization once during pllu_enable means we configure it properly into HW control. A side effect of the commonization/localization of the UTMI PLL init code, is that it corrects some errors that were present for earlier generations. For instance, in clk-tegra124.c, it used to have: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) when the correct shift to use is present in the new version: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) which matches the Tegra124 TRM register definition. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> [rklein: Merged in some later fixes for potential deadlocks] Signed-off-by: Rhyland Klein <rklein@nvidia.com> [treding: coding style bike-shedding, remove unused variable] Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: Micro-optimize Tegra210 clock setupThierry Reding2016-06-231-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sor_safe being the parent of the dpaux and dpaux1 clocks, it's not only natural, but also slightly more efficient, to initialize it before its children. This avoids orphaning the dpaux and dpaux1 clocks only to get them reparented when the sor_safe clock is registered. Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: Make sor_safe the parent of dpaux and dpaux1Thierry Reding2016-06-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that sor_safe, rather than pll_p, is the parent of the dpaux and dpaux1 clocks. Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: Mark timer clock as criticalThierry Reding2016-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer clock feeds the timer block, which, among other things, is used to drive the SOR lane sequencer. Since the Tegra timer driver is not enabled on 64-bit ARM, nothing currently claims that clock and it gets disabled by the common clock framework at late_init time. Given the non-obvious dependencies, the timer clock can be considered a critical part of the SoC infrastructure, requiring its clock source to be always on. Acked-by: Rhyland Klein <rklein@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: Enable sor1 and sor1_src on Tegra210Thierry Reding2016-06-171-0/+2
| | | | | | | | | | | | | | | | | | | | | Make the sor1 and sor1_src clocks available on Tegra210. They will be used by the display driver to support HDMI and DP. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: Squash sor1 safe/brick/src into a single muxThierry Reding2016-06-172-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sor1 clock on Tegra210 is structured in the following way: +-------+ | pllp |---+ +-------+ | +--------------+ +-----------+ +----| | | sor_safe | +-------+ | | +-----------+ | plld |--------| | | +-------+ | | +-----------+ | sor1_src |-------| | +-------+ | | +-----------+ | plld2 |--------| | | +-------+ | | | +----| | | +-------+ | +--------------+ | | clkm |---+ +-----------+ +-------+ +--------------+ | | | sor1_brick |-------| sor1 | +--------------+ | | +-----------+ This is impractical to represent in a clock tree, though, because there is no name for the mux that has sor_safe and sor1_src as parents. It is also much more cumbersome to deal with the additional mux because users of these clocks (the display driver) would have to juggle with an extra mux for no real reason. To simply things, the above is squashed into two muxes instead, so that it looks like this: +-------+ | pllp |---+ +-------+ | +--------------+ +-----------+ +----| | | sor_safe | +-------+ | | +-----------+ | plld |--------| | | +-------+ | | +-----------+ | sor1_src |-------| sor1 | +-------+ | | +-----------+ | plld2 |--------| | | | +-------+ | | | | +----| | | | +-------+ | +--------------+ | | | clkm |---+ | | +-------+ +--------------+ | | | sor1_brick |-----------+---+ +--------------+ This still very accurately represents the hardware. Note that sor1 has sor1_brick as input twice, that's because bit 1 in the mux selects the sor1_brick irrespective of bit 0. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: Disable spread spectrum on pll_d2Thierry Reding2016-06-171-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling spread spectrum on pll_d2 can lead to issues with display modes. HDMI monitors, for example, would report "Signal Error" and some modes driven over DisplayPort would generate fuzzy horizontal bands. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | clk: tegra: Fixup post dividers on Tegra210Thierry Reding2016-06-101-47/+47
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 86c679a52294 ("clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate") changed the PLL divider computation logic to consistently use P-divider values from tables as real dividers rather than the hardware values. Unfortunately for some reason many of the Tegra210 clocks didn't have their tables updated (most likely an over- sight by me when applying the patches). This commit fixes them all up. Cc: Jon Hunter <jonathanh@nvidia.com> Cc: Rhyland Klein <rklein@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | clk: fixed-factor: Allow for a few clocks to change the parent rateMaxime Ripard2016-07-021-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The only way for a fixed factor clock to change its rate would be to change its parent rate. Since passing blindly CLK_SET_RATE_PARENT might break a lot of platforms that were relying on the fact that the parent rate wouldn't change, introduce a compatible-based whitelist that will allow clocks to opt-in that flag. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge tag 'imx-clk-4.8' of ↵Stephen Boyd2016-06-306-49/+53
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull i.MX clk driver updates from Shawn Guo: - A few correction and improvements on pllv3 driver around AV pll clock rate calculation, parent setting and power bit handling - Correct i.MX6UL GPT2 clock names - A couple of minor fixes on i.MX7D clock driver on DRAM clocks * tag 'imx-clk-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx6ul: fix gpt2 clock names clk: imx: refine the powerdown bit of clk-pllv3 clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit clk: imx: fix pll clock parents clk: imx7d: correct dram pll type clk: imx7d: correct dram root clk parent select clk: imx: correct AV PLL rate formula
| * | clk: imx6ul: fix gpt2 clock namesDong Aisheng2016-06-161-2/+2
| | | | | | | | | | | | | | | | | | | | | fix gpt2 clock names Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | clk: imx: refine the powerdown bit of clk-pllv3Dong Aisheng2016-06-161-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | The powerdown bit is a bit confused, let's change it to power_bit to relfect both powerdown and powerup case according to different plls. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bitDong Aisheng2016-06-131-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit f53947456f98 ("ARM: clk: imx: update pllv3 to support imx7"), the former used BM_PLL_POWER bit is not correct anymore for IMX7 ENET. Instead, pll->powerdown holds the correct bit, so using powerdown bit in clk_pllv3_{prepare | unprepare} functions. Fixes: f53947456f98 ("ARM: clk: imx: update pllv3 to support imx7") Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | clk: imx: fix pll clock parentsDong Aisheng2016-06-125-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pllx_bypass_src mux shouldn't be the parent of pllx clock since it's only valid when when pllx BYPASS bit is set. Thus it is actually one parent of pllx_bypass only. Instead, pllx parent should be fixed to osc according to reference manual. Other plls have the same issue. e.g. before fix, the pll tree is: osc 6 6 24000000 0 0 pll1_bypass_src 0 0 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 After the fix, it's: osc 6 6 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | clk: imx7d: correct dram pll typeAnson Huang2016-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | DRAM PLL is a audio/video type PLL, need to correct it to get correct ops of PLL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | clk: imx7d: correct dram root clk parent selectAnson Huang2016-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | DRAM root clk should be either from pll dram main clk or dram alt root clk. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | clk: imx: correct AV PLL rate formulaAnson Huang2016-06-121-2/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The audio/video PLL's rate calculation is as below in RM: Fref * (DIV_SELECT + NUM / DENOM), in origin clk-pllv3's code, below code is used: (parent_rate * div) + ((parent_rate / mfd) * mfn as it does NOT consider the float data using div, so below formula should be used as a decent method: (parent_rate * div) + ((parent_rate * mfn) / mfd) and we also need to consider parent_rate * mfd may overflow a 32 bit value, 64 bit value should be used. After updating this formula, the dram PLL's rate is 1066MHz, which is correct, while the old formula gets 1056MHz. [Aisheng: fix clk_pllv3_av_round_rate too] Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | Merge branch 'clk-hw-unregister-fixed-rate' into clk-nextStephen Boyd2016-06-301-0/+11
|\ \ | | | | | | | | | | | | * clk-hw-unregister-fixed-rate: clk: fixed-rate: add clk_hw_unregister_fixed_rate()
| * | clk: fixed-rate: add clk_hw_unregister_fixed_rate()Masahiro Yamada2016-06-301-0/+11
| |/ | | | | | | | | | | | | This will be used to migrate to the clk_hw APIs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: hisilicon: hi3519: add driver remove path and fix some issuesJiancheng Xue2016-06-301-16/+100
| | | | | | | | | | | | | | | | | | | | 1. Add driver remove path. 2. Fix some issues. -Fix the ordering issue about clock provider being published. -Add error checking upon registering clocks. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: hisilicon: add hisi_clk_unregister_* functionsJiancheng Xue2016-06-301-0/+21
| | | | | | | | | | | | | | Add hisi_clk_unregister_* functions. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: hisilicon: add error processing for hisi_clk_register_* functionsJiancheng Xue2016-06-302-15/+55
| | | | | | | | | | | | | | Add error processing for hisi_clk_register_* functions. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: hisilicon: add hisi_clk_alloc function.Jiancheng Xue2016-06-302-0/+32
| | | | | | | | | | | | | | | | | | | | | | Before, there was an ordering issue that the clock provider had been published in hisi_clk_init before it could provide valid clocks to consumers. hisi_clk_alloc is just used to allocate memory space for struct hisi_clock_data. It makes it possible to publish the provider after the clocks are ready. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-18 19:33:01 +0100