summaryrefslogtreecommitdiffstats
path: root/drivers (follow)
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds2013-09-1048-1073/+2961
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...
| * clk: only call get_parent if there is oneAlex Elder2013-09-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In __clk_init(), after a clock is mostly initialized, a scan is done of the orphan clocks to see if the clock being registered is the parent of any of them. This code assumes that any clock that provides a get_parent method actually has at least one parent, and that's not a valid assumption. As a result, an orphan clock with no parent can return *something* as the parent index, and that value is blindly used to dereference the orphan's parent_names[] array (which will be ZERO_SIZE_PTR or NULL). Fix this by ensuring get_parent is only called for orphans with at least one parent. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos5250: Simplify registration of PLL rate tablesTomasz Figa2013-09-061-10/+2
| | | | | | | | | | | | | | | | | | | | | | Since the _get_rate() helper has been modified to use __clk_lookup() internally, checking of PLL input rates can be done using it and so the registration code can be simplified. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Register PLL rate tables for Exynos4x12Tomasz Figa2013-09-061-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4x12 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Register PLL rate tables for Exynos4210Tomasz Figa2013-09-061-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Reorder registration of mout_vpllsrcTomasz Figa2013-09-061-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since PLL input frequency must be known before PLL registration, mout_vpllsrc clock which is a reference clock of VPLL must be registered before VPLL. This patch reorders clock registration to register mout_vpllsrc before VPLL. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Add support for rate configuration of PLL46xxTomasz Figa2013-09-062-1/+135
| | | | | | | | | | | | | | | | | | | | This patch implements round_rate and set_rate callbacks of PLL46xx driver to allow reconfiguration of PLL at runtime. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Use new registration method for PLL46xxTomasz Figa2013-09-063-65/+14
| | | | | | | | | | | | | | | | | | | | This patch modifies PLL46xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Add support for rate configuration of PLL45xxTomasz Figa2013-09-062-1/+119
| | | | | | | | | | | | | | | | | | | | This patch implements round_rate and set_rate callbacks of PLL45xx driver to allow reconfiguration of PLL at runtime. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: pll: Use new registration method for PLL45xxTomasz Figa2013-09-063-62/+20
| | | | | | | | | | | | | | | | | | | | This patch modifies PLL45xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_pllsTomasz Figa2013-09-061-3/+3
| | | | | | | | | | | | | | | | | | | | This array defines PLLs specific to Exynos 4x12 SoCs and not for all Exynos 4 SoCs, so the name should represent that. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Remove checks for DT nodeTomasz Figa2013-09-061-7/+4
| | | | | | | | | | | | | | | | | | | | Exynos 4 supports only DT based bootup, so non-DT cases does not need to be handled anymore. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Remove unused static clkdev aliasesTomasz Figa2013-09-061-184/+172
| | | | | | | | | | | | | | | | | | | | | | Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: Modify _get_rate() helper to use __clk_lookup()Tomasz Figa2013-09-063-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to use clkdev inside the clock driver to retrieve the clocks for internal use. Instead __clk_lookup() helper can be used to look up clocks by their platform name. This patch modifies the behavior of _get_rate() helper to look up clocks by platform name and adjusts all users of it to pass platform names instead of clkdev aliases. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: samsung: exynos4: Use separate aliases for cpufreq related clocksTomasz Figa2013-09-061-8/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos cpufreq driver is the only remaining piece of code that needs static clkdev aliases for operation, because it can not do device tree based clock lookups yet. This patch moves clock alias definitions for those clocks to separate arrays that can be used with samsung_clk_register_alias() helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clocksource: samsung_pwm_timer: Get clock from device treeTomasz Figa2013-09-061-4/+8
| | | | | | | | | | | | | | | | | | | | | | When booting with device tree static clkdev aliases should not be used. This patch modifies the samsung_pwm_timer driver to use DT-based clock lookup when booting with device tree. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: Move symbol export to proper locationThierry Reding2013-09-031-1/+1
| | | | | | | | | | | | | | | | | | The __clk_get_flags() symbol is exported immediately following the clk_unprepare_unused_subtree() function. This is unusual, since a symbol export typically follows body of the function that it exports. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: fix new_parent dereference before null checkJames Hogan2013-08-301-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 71472c0 (clk: add support for clock reparent on set_rate) added a dereference of the new_parent pointer in clk_reparent(), but as detected by smatch clk_reparent() later checks whether new_parent is NULL. The dereference was in order to clear the new parent's new_child pointer to avoid duplicate POST_RATE_CHANGE notifications, so clearly isn't necessary if the new parent is NULL, so move it inside the "if (new_parent)" block. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: wm831x: Initialise wm831x pointer on initMark Brown2013-08-301-0/+2
| | | | | | | | | | | | | | | | | | Otherwise any attempt to interact with the hardware will crash. This is what happens when drivers get written blind. Signed-off-by: Mark Brown <broonie@linaro.org> Cc: stable@vger.kernel.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: assign dout_pixel id to pixel clock dividerRahul Sharma2013-08-301-1/+4
| | | | | | | | | | | | | | | | | | | | dout_pixel is a new ID allocated for pixel clock divider. It is queried in the driver to pass as the parent to hdmi clock while switching between parents. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: add hdmi mux to change parents in hdmi driverRahul Sharma2013-08-301-1/+4
| | | | | | | | | | | | | | | | | | | | | | hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: fix the order of parents of hdmi muxRahul Sharma2013-08-301-1/+1
| | | | | | | | | | | | | | | | | | Listing sclk_hdmiphy at 0th position in the list of parents is causing wrong configuration in reg SRC_DISP10. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: add gate clock for mixer sysmmuRahul Sharma2013-08-301-1/+2
| | | | | | | | | | | | | | | | Adding sysmmu clock for mixer for exynos5420. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5420: add sclk_hdmiphy to the list of special clocksRahul Sharma2013-08-301-2/+2
| | | | | | | | | | | | | | | | | | Add sclk_hdmiphy to the list of exposed clocks. This is required by hdmi driver to change the parent of hdmi clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: wm831x: Provide is_prepared() rather than is_enabled()Mark Brown2013-08-301-7/+7
| | | | | | | | | | | | | | | | | | Since the driver was written an is_prepared() operation has been made possible. Since the driver uses I2C I/O only prepare operations are provided so move the is_enabled() operation over to is_prepared(). Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystemRahul Sharma2013-08-291-2/+2
| | | | | | | | | | | | | | | | | | parent of hdmi and mixer block is mentioned as aclk200 which is not correct. It is clocked by the ouput of aclk200_disp1. Hence parent for mixer and hdmi clocks is changed to aclk200_disp1. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: tegra30: Don't wait for PLL_U lock bitTuomas Tynkkynen2013-08-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | The lock bit on PLL_U does not seem to be working correctly and sometimes never gets set when waiting for the PLL to come up. Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: s3c64xx: Fix incorrect placement of __initdataSachin Kamat2013-08-281-2/+2
| | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: sunxi: Fix incorrect placement of __initconstSachin Kamat2013-08-281-30/+30
| | | | | | | | | | | | | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: refreshed patch based on sunxi changes]
| * clk: kirkwood: Fix incorrect placement of __initconstSachin Kamat2013-08-281-7/+7
| | | | | | | | | | | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: dove: Fix incorrect placement of __initconstSachin Kamat2013-08-281-6/+6
| | | | | | | | | | | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: armada-xp: Fix incorrect placement of __initconstSachin Kamat2013-08-281-6/+6
| | | | | | | | | | | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: armada-370: Fix incorrect placement of __initconstSachin Kamat2013-08-281-7/+7
| | | | | | | | | | | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: u300: Fix incorrect placement of __initconstSachin Kamat2013-08-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. While at it also make 'u300_clk_lookup' static as it is used only in this file. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: nomadik: Fix incorrect placement of __initconstSachin Kamat2013-08-281-2/+2
| | | | | | | | | | | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: bcm2835: Fix incorrect placement of __initconstSachin Kamat2013-08-281-1/+1
| | | | | | | | | | | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * Merge tag 'sunxi-clk-for-3.12' of https://github.com/mripard/linux into ↵Mike Turquette2013-08-281-38/+194
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next-sunxi Allwinner clock changes for 3.12 These patches mostly do some cleanup to introduce the basic gated clocks for the Allwinner A10s, A20 and A31 SoCs. Conflicts: drivers/clk/sunxi/clk-sunxi.c
| | * clk: sunxi: Add Allwinner A20 gatesMaxime Ripard2013-08-261-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A20 is almost identical to the earlier A10 SoC from Allwinner on many aspects, including the clocks tree. However, since the A20 has some additionnal IPs compared to the A10, the clock tree isn't exactly the same, especially when it comes to the gated clocks available. We thus need to register different clock gates for the A20. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sunxi: Add A31 clocks supportMaxime Ripard2013-08-261-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A31 has a mostly different clock set compared to the other older SoCs currently supported in the Allwinner clock driver. Add support for the basic useful clocks. The other ones will come in eventually. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sunxi: Allow to specify the divider width from the dividers dataMaxime Ripard2013-08-261-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | The divider width used to be hardcoded. Some A31 dividers are no longer with the hardcoded width, so we need to make it specific to each divider and set it in the dividers data. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sunxi: Rename the structure to prepare the addition of sun6iMaxime Ripard2013-08-261-27/+27
| | | | | | | | | | | | | | | | | | | | | | | | Rename all the generic-named structure to sun4i to avoid confusion when we will introduce the sun6i (A31) clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sunxi: fix initialization of basic clocksEmilio López2013-08-261-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the recent move towards CLK_OF_DECLARE(...), the driver stopped initializing osc32k, which is compatible "fixed-clock". This is because we never called of_clk_init(NULL). Fix this by moving the only other simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL) to initialize both of them. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Mike Turquette <mturquette@linaro.org>
| | * clk: sunxi: Add A10s gatesMaxime Ripard2013-08-261-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A10s has a slightly different gates set than the A10 and A13, so add these gates to the clk driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Emilio López <emilio@elopez.com.ar>
| * | clk: wrap I/O access for improved portabilityGerhard Sittig2013-08-283-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the common clock drivers were motivated/initiated by ARM development and apparently assume little endian peripherals wrap register/peripherals access in the common code (div, gate, mux) in preparation of adding COMMON_CLK support for other platforms Signed-off-by: Gerhard Sittig <gsi@denx.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | Merge branch 'clk-next-s3c64xx-delta' into clk-nextMike Turquette2013-08-282-98/+13
| |\ \
| | * | clk: samsung: pll: Use new registration method for PLL6552 and PLL6553Tomasz Figa2013-08-272-98/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies PLL6552 and PLL6553 clock drivers to use recently added common Samsung PLL registration method. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk: get matching entry under lock in of_clk_init()Alex Elder2013-08-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently of_clk_init() finds a matching device node while holding the device tree spinlock. When a matching device node is found, the lock is dropped and then re-acquired in order to get a reference to the matching device id structure. Acquiring the spinlock twice is unnecessary (and it opens a vulnerable window that could conceivably lead to errors). There already exists an interface for both finding and taking a reference to a device id under lock, so use it. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk: sunxi: fix initialization of basic clocksEmilio López2013-08-281-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the recent move towards CLK_OF_DECLARE(...), the driver stopped initializing osc32k, which is compatible "fixed-clock". This is because we never called of_clk_init(NULL). Fix this by moving the only other simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL) to initialize both of them. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk: mvebu: add missing iounmapJisheng Zhang2013-08-232-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing iounmap to setup error path. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk: handle NULL struct clk gracefullyMike Turquette2013-08-221-1/+7
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | At some point changes to clk_set_rate and clk_set_parent introduced a bug whereby NULL struct clk pointers were treated as an error. This is in violation of the API in include/linux/clk.h. Reintroduce graceful handling of NULL clk's by bailing from clk_set_rate and clk_set_parent with return codes of zero. Signed-off-by: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 16:08:02 +0100