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* gpio: of: Fix logic inversionLinus Walleij2019-01-241-1/+1
| | | | | | | | | | | | The SPI chip selects were not properly inspected due to a logic inversion. This made SPI GPIOs not work. Cc: Jan Kotas <jank@cadence.com> Reported-by: Jan Kotas <jank@cadence.com> Tested-by: Jan Kotas <jank@cadence.com> Fixes: f3186dd87669 ("spi: Optionally use GPIO descriptors for CS GPIOs") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: cadence: Fix default polarity of native chipselectLinus Walleij2019-01-241-3/+3
| | | | | | | | | | | | | | | | | | | | The Cadence controller also supports platforms specifying native chipselects. When I enforce the use of high CS for drivers opting in for using GPIO descriptors, I inadvertedly switched the driver to also use active high chip select for native chip selects. Fix this by inverting the logic in the callback for the native chip select. Rename the parameter from "is_high" (which is interpreted as being high when 0, which is confusing, I will not make any drug-related jokes here) to "enabled" which is more intuitive, especially now that it is true when CS is supposed to be enabled. Cc: Wei Yongjun <weiyongjun1@huawei.com> Fixes: cfeefa79dc37 ("spi: cadence: Convert to use CS GPIO descriptors") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Fix default polarity of native chipselectLinus Walleij2019-01-241-3/+2
| | | | | | | | | | | | | | | | | | | | The DW controller also supports platforms specifying native chipselects. When I enforce the use of high CS for drivers opting in for using GPIO descriptors, I inadvertedly switched the driver to also use active high chip select for native chip selects. As it turns out, the DW hardware driving chip selects also thinks it is weird with active low chip selects so all we need to do is remove an inversion in the driver. Cc: Jan Kotas <jank@cadence.com> Reported-by: Jan Kotas <jank@cadence.com> Tested-by: Jan Kotas <jank@cadence.com> Fixes: 9400c41e77b8 ("spi: dw: Convert to use CS GPIO descriptors") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Support high CS when using descriptorsLinus Walleij2019-01-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | All controllers using GPIO descriptors can by definition support high CS connections, so just enforce this when registering an SPI controller. This fixes a regression where controllers were missing SPI_CS_HIGH, the drivers would fail like this: spi spi0.0: setup: unsupported mode bits 4 cdns-spi fd0b0000.spi: can't setup spi0.0, status -22 This is because as using descriptors moves the CS inversion logic over to gpiolib, all such controllers are registered with CS active high. Cc: Jan Kotas <jank@cadence.com> Reported-by: Jan Kotas <jank@cadence.com> Tested-by: Jan Kotas <jank@cadence.com> Fixes: f3186dd87669 ("spi: Optionally use GPIO descriptors for CS GPIOs") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Go back to immediate teardownMark Brown2019-01-231-89/+33
| | | | | | | | | | | | Commit 412e6037324 ("spi: core: avoid waking pump thread from spi_sync instead run teardown delayed") introduced regressions on some boards, apparently connected to spi_mem not triggering shutdown properly any more. Since we've thus far been unable to figure out exactly where the breakage is revert the optimisation for now. Reported-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: kernel@martin.sperl.org
* pxa2xx: replace spi_master with spi_controllerLubomir Rintel2019-01-234-111/+111
| | | | | | | | | It's also a slave controller driver now, calling it "master" is slightly misleading. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: bcm2835aux: remove unneeded NULL check of devm_clk_getYueHaibing2019-01-231-1/+1
| | | | | | | | | | | | Fix a static code checker warning: drivers/spi/spi-bcm2835aux.c:460 bcm2835aux_spi_probe() warn: passing zero to 'PTR_ERR' In case of error, the function devm_clk_get() returns ERR_PTR() and not returns NULL. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-mem: Add devm_spi_mem_dirmap_{create,destroy}()Boris Brezillon2019-01-211-0/+69
| | | | | | | | | | Since direct mapping descriptors usually the same lifetime as the SPI MEM device adding devm_ variants of the spi_mem_dirmap_{create,destroy}() should greatly simplify error/remove path of spi-mem drivers making use of the direct mapping API. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: sh-msiof: Use DMA if possibleHoan Nguyen An2019-01-181-6/+2
| | | | | | | | | | | | | Currently, this driver only supports feature for DMA 32-bits. In this case, only if the data length is divisible by 4 to use DMA, otherwise PIO will be used. This patch will suggest use the DMA 32-bits with 4bytes of words, then the remaining data will be transmitted by PIO mode. Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: sh-msiof: fix *info pointer in request_dma()Hoan Nguyen An2019-01-181-1/+1
| | | | | | | | | sh_msiof_spi_info *info struct pointer was initialized in the probe() function no need to get back and keep consistency. Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: sh-hspi: Remove error messages on out-of-memory conditionsGeert Uytterhoeven2019-01-181-4/+1
| | | | | | | | There is no need to print an error message when memory allocations or related operations fail, as the core will take care of that. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: ath79: Remove now useless codeAlban Bedel2019-01-171-41/+2
| | | | | | | | | The custom setup/cleanup routines included in the ath79 driver only take care of setting the initial CS state. However that is already handled by the bitbang code, so this code can be removed. Signed-off-by: Alban Bedel <albeu@free.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: ath79: Enable support for compile testAlban Bedel2019-01-172-4/+13
| | | | | | | | | | | To allow building this driver in compile test we need to remove all dependency on headers from arch/mips/include. To allow this we explicitly define all the registers locally instead of using ar71xx_regs.h and we move the platform data struct definition to include/linux/platform_data/spi-ath79.h. Signed-off-by: Alban Bedel <albeu@free.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: ath79: Simplify ath79_spi_chipselect()Alban Bedel2019-01-172-32/+10
| | | | | | | | | | | | | | | First of all this callback was slightly misused to setup the clock polarity at the beginning of a transfer. Beside being at the wrong place, it is also useless as only SPI mode 1 is supported. Instead just make sure the base value used for IOC is suitable to start a transfer by clearing the clock and data bits during the controller setup. This also remove the last direct usage of the GPIO API, so we can remove the direct dependency on GPIOLIB. Signed-off-by: Alban Bedel <albeu@free.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: bitbang: Don't call chipselect() in spi_bitbang_setup()Alban Bedel2019-01-171-13/+0
| | | | | | | | | | spi_setup() already call spi_set_cs() right after calling the controller setup method, so there is no need for the bitbang driver to do that. Because of this the chipselect() callback was confusingly still called when CS is GPIO based. Signed-off-by: Alban Bedel <albeu@free.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: cadence: Correct initialisation of runtime PMCharles Keepax2019-01-141-7/+4
| | | | | | | | | | | | | | | | | | | | Currently the driver calls pm_runtime_put_autosuspend but without ever having done a pm_runtime_get, this causes the reference count in the pm runtime core to become -1. The bad reference count causes the core to sometimes suspend whilst an active SPI transfer is in progress. arizona spi0.1: SPI transfer timed out spi_master spi0: failed to transfer one message from queue The correct proceedure is to do all the initialisation that requires the hardware to be powered up before enabling the PM runtime, then enable the PM runtime having called pm_runtime_set_active to inform it that the hardware is currently powered up. The core will then power it down at it's leisure and no explicit pm_runtime_put is required. Fixes: d36ccd9f7ea4 ("spi: cadence: Runtime pm adaptation") Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-geni-qcom: Get rid of forward declarationStephen Boyd2019-01-141-29/+26
| | | | | | | | | | | | We don't need this forward declaration. Move the function to where it needed so we can drop it and shave some lines of code. CC: Girish Mahadevan <girishm@codeaurora.org> CC: Dilip Kota <dkota@codeaurora.org> CC: Alok Chauhan <alokc@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-geni-qcom: Don't initialize completion for normal messageStephen Boyd2019-01-141-1/+0
| | | | | | | | | | | | | | | We only use this completion when we're doing something that isn't a message transfer. For example, changing CS or aborting/canceling a command. All of those situations properly reinitialize the completion before sending the GENI the special command to change CS or cancel, etc. Given that, let's remove the initialization here. Cc: Girish Mahadevan <girishm@codeaurora.org> Cc: Dilip Kota <dkota@codeaurora.org> Cc: Alok Chauhan <alokc@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: davinci: Get rid of dangling variableLinus Walleij2019-01-101-1/+0
| | | | | | | | | | | | The previous commit left a variable unused, my bad. Clean it up. Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: David Lechner <david@lechnology.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Fixes: 101a68e74fe0 ("spi: davinci: Convert to use CS GPIO descriptors") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: fix warning unused variable 'ret'Anders Roxell2019-01-101-1/+0
| | | | | | | | | | | | | | | | | When CONFIG_SPI_DESIGNWARE are enabled we see the unused variable warning in dw_spi_setup. ../drivers/spi/spi-dw.c: In function ‘dw_spi_setup’: ../drivers/spi/spi-dw.c:400:6: warning: unused variable ‘ret’ [-Wunused-variable] int ret; ^~~ Remove the unused varable. Fixes: 9400c41e77b8 ("spi: dw: Convert to use CS GPIO descriptors") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Anders Roxell <anders.roxell@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: core: avoid waking pump thread from spi_sync instead run teardown delayedMartin Sperl2019-01-091-33/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When spi_sync is running alone with no other spi devices connected to the bus the worker thread is woken during spi_finalize_current_message to run the teardown code every time. This is totally unnecessary in the case that there is no message queued. On a multi-core system this results in one wakeup of the thread for each spi_message processed via spi_sync where in most cases the teardown does not happen as the hw is already in use. This patch now delays the teardown by 1 second by using a separate kthread_delayed_work for the teardown. This avoids waking the kthread too often. For spi_sync transfers in a tight loop (say 40k messages/s) this avoids the penalty of waking the worker thread 40k times/s. On a rasperry pi 3 with 4 cores the results in 32% of a single core only to find out that there is nothing in the queue and it can go back to sleep. With this patch applied the spi-worker is woken exactly once: after the load finishes and the spi bus is idle for 1 second. I believe I have also seen situations where during a spi_sync loop the worker thread (triggered by the last message finished) is slightly faster and _wins_ the race to process the message, so we are actually running the kthread and letting it do some work... This is also no longer observed with this patch applied as. Tested with a new CAN controller driver for the mcp2517fd which uses spi_sync for interrupt handling and spi_async for scheduling of can frames for transmission (in a different thread) Some statistics when receiving 100000 CAN frames with the mcp25xxfd driver on a Raspberry pi 3: without the patch: ------------------ root@raspcm3:~# for x in $(pgrep spi0) $(pgrep irq/94-mcp25xxf) ; do awk '{printf "%-20s %6i\n", $2,$15}' /proc/$x/stat; done (spi0) 5 (irq/94-mcp25xxf) 0 root@raspcm3:~# vmstat 1 procs -----------memory---------- ---swap-- -----io---- -system-- ------cpu----- r b swpd free buff cache si so bi bo in cs us sy id wa st 1 0 0 821960 13592 50848 0 0 80 2 1986 105 1 2 97 0 0 0 0 0 821968 13592 50876 0 0 0 0 8046 30 0 0 100 0 0 0 0 0 821936 13592 50876 0 0 0 0 8032 24 0 0 100 0 0 0 0 0 821936 13592 50876 0 0 0 0 8035 30 0 0 100 0 0 0 0 0 821936 13592 50876 0 0 0 0 8033 22 0 0 100 0 0 2 0 0 821936 13592 50876 0 0 0 0 11598 7129 0 3 97 0 0 1 0 0 821872 13592 50876 0 0 0 0 37741 59003 0 31 69 0 0 2 0 0 821840 13592 50876 0 0 0 0 37762 59078 0 29 71 0 0 2 0 0 821776 13592 50876 0 0 0 0 37593 58792 0 28 72 0 0 1 0 0 821744 13592 50876 0 0 0 0 37642 58881 0 30 70 0 0 2 0 0 821680 13592 50876 0 0 0 0 37490 58602 0 27 73 0 0 1 0 0 821648 13592 50876 0 0 0 0 37412 58418 0 29 71 0 0 1 0 0 821584 13592 50876 0 0 0 0 37337 58288 0 27 73 0 0 1 0 0 821552 13592 50876 0 0 0 0 37584 58774 0 27 73 0 0 0 0 0 821520 13592 50876 0 0 0 0 18363 20566 0 9 91 0 0 0 0 0 821520 13592 50876 0 0 0 0 8037 32 0 0 100 0 0 0 0 0 821520 13592 50876 0 0 0 0 8031 23 0 0 100 0 0 0 0 0 821520 13592 50876 0 0 0 0 8034 26 0 0 100 0 0 0 0 0 821520 13592 50876 0 0 0 0 8033 24 0 0 100 0 0 ^C root@raspcm3:~# for x in $(pgrep spi0) $(pgrep irq/94-mcp25xxf) ; do awk '{printf "%-20s %6i\n", $2,$15}' /proc/$x/stat; done (spi0) 228 (irq/94-mcp25xxf) 794 root@raspcm3:~# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 17: 34 0 0 0 ARMCTRL-level 1 Edge 3f00b880.mailbox 27: 1 0 0 0 ARMCTRL-level 35 Edge timer 33: 1416870 0 0 0 ARMCTRL-level 41 Edge 3f980000.usb, dwc2_hsotg:usb1 34: 1 0 0 0 ARMCTRL-level 42 Edge vc4 35: 0 0 0 0 ARMCTRL-level 43 Edge 3f004000.txp 40: 1753 0 0 0 ARMCTRL-level 48 Edge DMA IRQ 42: 11 0 0 0 ARMCTRL-level 50 Edge DMA IRQ 44: 11 0 0 0 ARMCTRL-level 52 Edge DMA IRQ 45: 0 0 0 0 ARMCTRL-level 53 Edge DMA IRQ 66: 0 0 0 0 ARMCTRL-level 74 Edge vc4 crtc 69: 0 0 0 0 ARMCTRL-level 77 Edge vc4 crtc 70: 0 0 0 0 ARMCTRL-level 78 Edge vc4 crtc 77: 20 0 0 0 ARMCTRL-level 85 Edge 3f205000.i2c, 3f804000.i2c, 3f805000.i2c 78: 6346 0 0 0 ARMCTRL-level 86 Edge 3f204000.spi 80: 205 0 0 0 ARMCTRL-level 88 Edge mmc0 81: 493 0 0 0 ARMCTRL-level 89 Edge uart-pl011 89: 0 0 0 0 bcm2836-timer 0 Edge arch_timer 90: 4291 3821 2180 1649 bcm2836-timer 1 Edge arch_timer 94: 14289 0 0 0 pinctrl-bcm2835 16 Level mcp25xxfd IPI0: 0 0 0 0 CPU wakeup interrupts IPI1: 0 0 0 0 Timer broadcast interrupts IPI2: 3645 242371 7919 1328 Rescheduling interrupts IPI3: 112 543 273 194 Function call interrupts IPI4: 0 0 0 0 CPU stop interrupts IPI5: 1 0 0 0 IRQ work interrupts IPI6: 0 0 0 0 completion interrupts Err: 0 top shows 93% for the mcp25xxfd interrupt handler, 31% for spi0. with the patch: --------------- root@raspcm3:~# for x in $(pgrep spi0) $(pgrep irq/94-mcp25xxf) ; do awk '{printf "%-20s %6i\n", $2,$15}' /proc/$x/stat; done (spi0) 0 (irq/94-mcp25xxf) 0 root@raspcm3:~# vmstat 1 procs -----------memory---------- ---swap-- -----io---- -system-- ------cpu----- 0 0 0 804768 13584 62628 0 0 0 0 8038 24 0 0 100 0 0 0 0 0 804768 13584 62628 0 0 0 0 8042 25 0 0 100 0 0 1 0 0 804704 13584 62628 0 0 0 0 9603 2967 0 20 80 0 0 1 0 0 804672 13584 62628 0 0 0 0 9828 3380 0 24 76 0 0 1 0 0 804608 13584 62628 0 0 0 0 9823 3375 0 23 77 0 0 1 0 0 804608 13584 62628 0 0 0 12 9829 3394 0 23 77 0 0 1 0 0 804544 13584 62628 0 0 0 0 9816 3362 0 22 78 0 0 1 0 0 804512 13584 62628 0 0 0 0 9817 3367 0 23 77 0 0 1 0 0 804448 13584 62628 0 0 0 0 9822 3370 0 22 78 0 0 1 0 0 804416 13584 62628 0 0 0 0 9815 3367 0 23 77 0 0 0 0 0 804352 13584 62628 0 0 0 84 9222 2250 0 14 86 0 0 0 0 0 804352 13592 62620 0 0 0 24 8131 209 0 0 93 7 0 0 0 0 804320 13592 62628 0 0 0 0 8041 27 0 0 100 0 0 0 0 0 804352 13592 62628 0 0 0 0 8040 26 0 0 100 0 0 root@raspcm3:~# for x in $(pgrep spi0) $(pgrep irq/94-mcp25xxf) ; do awk '{printf "%-20s %6i\n", $2,$15}' /proc/$x/stat; done (spi0) 0 (irq/94-mcp25xxf) 767 root@raspcm3:~# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 17: 29 0 0 0 ARMCTRL-level 1 Edge 3f00b880.mailbox 27: 1 0 0 0 ARMCTRL-level 35 Edge timer 33: 1024412 0 0 0 ARMCTRL-level 41 Edge 3f980000.usb, dwc2_hsotg:usb1 34: 1 0 0 0 ARMCTRL-level 42 Edge vc4 35: 0 0 0 0 ARMCTRL-level 43 Edge 3f004000.txp 40: 1773 0 0 0 ARMCTRL-level 48 Edge DMA IRQ 42: 11 0 0 0 ARMCTRL-level 50 Edge DMA IRQ 44: 11 0 0 0 ARMCTRL-level 52 Edge DMA IRQ 45: 0 0 0 0 ARMCTRL-level 53 Edge DMA IRQ 66: 0 0 0 0 ARMCTRL-level 74 Edge vc4 crtc 69: 0 0 0 0 ARMCTRL-level 77 Edge vc4 crtc 70: 0 0 0 0 ARMCTRL-level 78 Edge vc4 crtc 77: 20 0 0 0 ARMCTRL-level 85 Edge 3f205000.i2c, 3f804000.i2c, 3f805000.i2c 78: 6417 0 0 0 ARMCTRL-level 86 Edge 3f204000.spi 80: 237 0 0 0 ARMCTRL-level 88 Edge mmc0 81: 489 0 0 0 ARMCTRL-level 89 Edge uart-pl011 89: 0 0 0 0 bcm2836-timer 0 Edge arch_timer 90: 4048 3704 2383 1892 bcm2836-timer 1 Edge arch_timer 94: 14287 0 0 0 pinctrl-bcm2835 16 Level mcp25xxfd IPI0: 0 0 0 0 CPU wakeup interrupts IPI1: 0 0 0 0 Timer broadcast interrupts IPI2: 2361 2948 7890 1616 Rescheduling interrupts IPI3: 65 617 301 166 Function call interrupts IPI4: 0 0 0 0 CPU stop interrupts IPI5: 1 0 0 0 IRQ work interrupts IPI6: 0 0 0 0 completion interrupts Err: 0 top shows 91% for the mcp25xxfd interrupt handler, 0% for spi0 So we see that spi0 is no longer getting scheduled wasting CPU cycles There are a lot less context switches and corresponding Rescheduling interrupts All of these show that this improves efficiency of the system and reduces CPU utilization. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: Convert to use CS GPIO descriptorsLinus Walleij2019-01-092-30/+1
| | | | | | | | | | | | | | | | | | | | This converts the DesignWare (dw) SPI master driver to use GPIO descriptors for chip select handling. This driver has a duplicate DT parser in addition to the one in the core, sets up the line as non-asserted and relies on the core to drive the GPIOs. It is a pretty straight-forward conversion. Cc: Talel Shenhar <talel@amazon.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Linuxarm <linuxarm@huawei.com> Tested-by: Jay Fang <f.fangjian@huawei.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: davinci: Convert to use CS GPIO descriptorsLinus Walleij2019-01-091-40/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | This converts the DaVinci SPI master driver to use GPIO descriptors for chip select handling. DaVinci parses the device tree a second time for the chip select GPIOs (no relying on the parsing already happening in the SPI core) and handles inversion semantics locally. We simply drop the extra parsing and set up and move the CS handling to the core and gpiolib. The fact that the driver is actively driving the GPIO in the davinci_spi_chipselect() callback is confusing since the host does not set SPI_MASTER_GPIO_SS so this should not ever get called when using GPIO CS. I put in a comment about this. This driver also supports instantiation from board files, but these are all using native chip selects so no problem with GPIO lines here. Cc: David Lechner <david@lechnology.com> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: Linuxarm <linuxarm@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: clps711x: Convert to use CS GPIO descriptorsLinus Walleij2019-01-091-21/+2
| | | | | | | | | | | | | | This converts the CLPS711x SPI master driver to use GPIO descriptors for chip select handling. The CLPS711x driver was merely requesting the GPIO and setting the CS line non-asserted so this was a pretty straight-forward conversion. The setup callback goes away. Cc: Alexander Shiyan <shc_work@mail.ru> Cc: Linuxarm <linuxarm@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: cadence: Convert to use CS GPIO descriptorsLinus Walleij2019-01-091-65/+2
| | | | | | | | | | | | | | | | | | | | | | | This converts the Cadence SPI master driver to use GPIO descriptors for chip select handling. The Cadence driver was allocating a state container just to hold the requested GPIO line and contained lots of polarity inversion code. As this is all handled by gpiolib and a simple devm_* request in the core, and as the driver is fully device tree only, most of this code chunk goes away in favour of central handling. The setup/cleanup callbacks goes away. This driver does NOT drive the CS line by setting the value of the GPIO so it relies on the SPI core to do this, which should work just fine with the descriptors. Cc: Wei Yongjun <weiyongjun1@huawei.com> Cc: Janek Kotas <jank@cadence.com> Cc: Linuxarm <linuxarm@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: atmel: Convert to use CS GPIO descriptorsLinus Walleij2019-01-091-66/+27
| | | | | | | | | | | | | | | | | | | | | | | | | This converts the Atmel SPI master driver to use GPIO descriptors for chip select handling. The Atmel driver has duplicate code to look up and initialize CS GPIOs from the device tree, so this is removed. It further has code to retrieve a CS GPIO from .controller_data but this seems to be completely unused in the kernel (legacy codepath?) so I deleted this support. It keeps track of polarity when switching the CS, but this is not needed anymore since we moved this over to the gpiolib. The local handling of the "npcs_pin" (I guess this might mean "negative polarity chip select pin") is preserved, but I strongly suspect this can be switched over to handling by the core and using the SPI_MASTER_GPIO_SS flag on the master to assure that the additional CS handling in the driver is also done. Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Radu Pirea <radu.pirea@microchip.com> Cc: Linuxarm <linuxarm@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: ath79: Convert to use CS GPIO descriptorsLinus Walleij2019-01-091-28/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | This converts the ATH79 SPI master driver to use GPIO descriptors for chip select handling. The ATH79 driver was requesting the GPIO and driving it from the bitbang .chipselect callback. Do not request it anymore as the SPI core will request it, remove the line inversion semantics for the GPIO case (handled by gpiolib) and let the SPI core deal with requesting the GPIO line from the device tree node of the controller. This driver can be instantiated from a board file (no device tree) but the board files only use native CS (no GPIO lines) so we should be fine just letting the SPI core grab the GPIO from the device. The fact that the driver is actively driving the GPIO in the ath79_spi_chipselect() callback is confusing since the host does not set SPI_MASTER_GPIO_SS so this should not ever get called when using GPIO CS. I put in a comment about this. Cc: Felix Fietkau <nbd@nbd.name> Cc: Alban Bedel <albeu@free.fr> Cc: Linuxarm <linuxarm@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Optionally use GPIO descriptors for CS GPIOsLinus Walleij2019-01-091-10/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This augments the SPI core to optionally use GPIO descriptors for chip select on a per-master-driver opt-in basis. Drivers using this will rely on the SPI core to look up GPIO descriptors associated with the device, such as when using device tree or board files with GPIO descriptor tables. When getting descriptors from the device tree, this will in turn activate the code in gpiolib that was added in commit 6953c57ab172 ("gpio: of: Handle SPI chipselect legacy bindings") which means that these descriptors are aware of the active low semantics that is the default for SPI CS GPIO lines and we can assume that all of these are "active high" and thus assign SPI_CS_HIGH to all CS lines on the DT path. The previously used gpio_set_value() would call down into gpiod_set_raw_value() and ignore the polarity inversion semantics. It seems like many drivers go to great lengths to set up the CS GPIO line as non-asserted, respecting SPI_CS_HIGH. We pull this out of the SPI drivers and into the core, and by simply requesting the line as GPIOD_OUT_LOW when retrieveing it from the device and relying on the gpiolib to handle any inversion semantics. This way a lot of code can be simplified and removed in each converted driver. The end goal after dealing with each driver in turn, is to delete the non-descriptor path (of_spi_register_master() for example) and let the core deal with only descriptors. The different SPI drivers have complex interactions with the core so we cannot simply change them all over, we need to use a stepwise, bisectable approach so that each driver can be converted and fixed in isolation. This patch has the intended side effect of adding support for ACPI GPIOs as it starts relying on gpiod_get_*() to get the GPIO handle associated with the device. Cc: Linuxarm <linuxarm@huawei.com> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com> Tested-by: Fangjian (Turing) <f.fangjian@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: add support for STM32F4Cezary Gapinski2019-01-071-7/+482
| | | | | | | | | | | Add routines, registers & bitfield definition. Also baud rate divisor definitions for STM32F4 SPI. This version supports full-duplex, simplex TX and half-duplex TX communication with 8 or 16-bit per word. DMA capability is optionally supported for transfer longer than 16 bytes. For transfer less than 16 bytes frames can be send in discontinuous mode. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: introduce compatible data cfgCezary Gapinski2019-01-071-101/+236
| | | | | | | | | | | | | | | | Prepare support for STM32F4 spi variant by introducing compatible configuration data. Move STM32H7 specific stuff to compatible data structure: - registers & bit fields - routines to control driver - baud rate divisor definitions - fifo availability - split IRQ functions to parts to be called when the IRQ occurs and for threaded interrupt what helps to provide less discontinuous mode for drivers without FIFO. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: add start dma transfer functionCezary Gapinski2019-01-071-9/+18
| | | | | | | | Add transfer_one_dma_start function to be more generic for other stm32 SPI family drivers. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: split transfer one setup functionCezary Gapinski2019-01-071-78/+192
| | | | | | | | Split stm32_spi_transfer_one_setup function into smaller chunks to be more generic for other stm32 SPI family drivers. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: rename interrupt functionCezary Gapinski2019-01-071-3/+3
| | | | | | | | Interrupt function is used as a thread so rename it to express meaning directly by more clear function name. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: rename STM32 SPI registers to STM32H7Cezary Gapinski2019-01-071-182/+199
| | | | | | | | Rename STM32 SPI registers to be related to STM32H7 SPI driver and not STM32 generally. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: remove SPI LOOP modeCezary Gapinski2019-01-071-1/+1
| | | | | | | | This driver does not support SPI LOOP mode by configuration in registers. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: use explicit CPOL and CPHA mode bitsCezary Gapinski2019-01-071-1/+1
| | | | | | | | | Driver supports SPI mode 0 to 3 not only the mode 3. Use SPI_CPOL and SPI_CPHA indicates that these bits can be changed to obtain modes 0 - 3. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: fix typo in SPI_STM32 help textCezary Gapinski2019-01-071-1/+1
| | | | | | | Fix typo from STMicroelectonics to STMicroelectronics. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: fix DMA configuration with only one channelCezary Gapinski2019-01-071-8/+12
| | | | | | | | | | | | | When SPI driver is configured to work only with TX or RX DMA channel then dmaengine functions can dereferene NULL pointer. Running full-duplex mode when when only RX or TX DMA channel is available can cause overrun condition or incorrect writing to transmit buffer so disable this types of DMA configuration and go back to interrupt mode. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: use NULL pointer instead of plain integerCezary Gapinski2019-01-071-1/+1
| | | | | | | | Patch fixes sparse warning: Using plain integer as NULL pointer. Replaces second argument of function devm_clk_get from 0 to NULL. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: switch to SPDX identifierCezary Gapinski2019-01-071-20/+7
| | | | | | | | Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: dw: fix potential variable assignment errorshaftarger2019-01-071-1/+2
| | | | | | | | | | | | | spi::mode is defined by framework for several SPI capabilities, such as polarity, phase, bit-endian, wire number. Directly use this variable for setting controller's polarity and phase causes other bit in register being set. Since SPI framework has its definition, SPI_CPOL and SPI_CPHA offset may be changed by framwork change. Instead of just mask off the relevant bits, fetch required bit in spi::mode and set to register. Signed-off-by: shaftarger <shol@livemail.tw> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: add cpu details to fsl-dspi Kconfig helpAngelo Dureghello2019-01-071-1/+1
| | | | | | | | Add some cpu families that are actually using the fsl-dspi module in the related Kconfig description. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Signed-off-by: Mark Brown <broonie@kernel.org>
* mtd: fsl-quadspi: Remove the driver as it was replaced by spi-fsl-qspi.cFrieder Schrempf2019-01-071-1224/+0
| | | | | | | | | | | | | | | There's a new driver using the SPI memory interface of the SPI framework at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to replace the functionality of this SPI NOR driver. The new driver is already in use and this code is not compiled anymore, so let's remove it. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Han Xu <han.xu@nxp.com> Tested-by: Han Xu <han.xu@nxp.com> Acked-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Add a driver for the Freescale/NXP QuadSPI controllerFrieder Schrempf2019-01-075-10/+978
| | | | | | | | | | | | | | | | | | | | This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface of the SPI framework to issue flash memory operations to up to four connected flash chips (2 buses with 2 CS each). The controller does not support generic SPI messages. This patch also disables the build of the "old" driver and reuses its Kconfig option CONFIG_SPI_FSL_QUADSPI to replace it. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Han Xu <han.xu@nxp.com> Reviewed-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Tested-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Tested-by: Han Xu <han.xu@nxp.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge tag 'tag-chrome-platform-for-v4.21' of ↵Linus Torvalds2019-01-061-5/+17
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/bleung/chrome-platform Pull chrome platform updates from Benson Leung: - Changes for EC_MKBP_EVENT_SENSOR_FIFO handling. - Also, maintainership changes. Olofj out, Enric balletbo in. * tag 'tag-chrome-platform-for-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/bleung/chrome-platform: MAINTAINERS: add maintainers for ChromeOS EC sub-drivers MAINTAINERS: platform/chrome: Add Enric as a maintainer MAINTAINERS: platform/chrome: remove myself as maintainer platform/chrome: don't report EC_MKBP_EVENT_SENSOR_FIFO as wakeup platform/chrome: straighten out cros_ec_get_{next,host}_event() error codes
| * platform/chrome: don't report EC_MKBP_EVENT_SENSOR_FIFO as wakeupBrian Norris2018-11-141-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC_MKBP_EVENT_SENSOR_FIFO events can be triggered for a variety of reasons, and there are very few cases in which they should be treated as wakeup interrupts (particularly, when a certain MOTIONSENSE_MODULE_FLAG_* is set, but this is not even supported in the mainline cros_ec_sensor driver yet). Most of the time, they are benign sensor readings. In any case, the top-level cros_ec device doesn't know enough to determine that they should wake the system, and so it should not report the event. This would be the job of the cros_ec_sensors driver to parse. This patch adds checks to cros_ec_get_next_event() such that it doesn't signal 'wakeup' for events of type EC_MKBP_EVENT_SENSOR_FIFO. This patch is particularly relevant on devices like Scarlet (Rockchip RK3399 tablet, known as Acer Chromebook Tab 10), where the EC firmware reports sensor events much more frequently. This was causing /sys/power/wakeup_count to increase very frequently, often needlessly interrupting our ability to suspend the system. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Benson Leung <bleung@chromium.org>
| * platform/chrome: straighten out cros_ec_get_{next,host}_event() error codesBrian Norris2018-11-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cros_ec_get_next_event() is documented to return 0 for success and negative for errors. It currently returns negative for some errors, and non-negative (number of bytes received) for success (including some "no data available" responses as zero). This mostly works out OK, because the callers were more or less ignoring the documentation, and only treating positive values as success (and indepdently checking the modification of 'wakeup'). Let's button this up by avoiding pretending to handle event/wakeup distinctions when no event info was retrieved (i.e., returned 0 bytes). And fix the documentation of cros_ec_get_host_event() and cros_ec_get_next_event() to accurately describe their behavior. Signed-off-by: Brian Norris <briannorris@chromium.org> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Benson Leung <bleung@chromium.org>
* | Merge tag 'hwlock-v4.21' of git://github.com/andersson/remoteprocLinus Torvalds2019-01-063-0/+166
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull hwspinlock updates from Bjorn Andersson: "This adds support for the hardware semaphores found in STM32MP1" * tag 'hwlock-v4.21' of git://github.com/andersson/remoteproc: hwspinlock: fix return value check in stm32_hwspinlock_probe() hwspinlock: add STM32 hwspinlock device dt-bindings: hwlock: Document STM32 hwspinlock bindings
| * | hwspinlock: fix return value check in stm32_hwspinlock_probe()Wei Yongjun2019-01-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function devm_ioremap_resource() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Fixes: f24fcff1d267 ("hwspinlock: add STM32 hwspinlock device") Acked-by: Benjamin Gaignard <benjamin.gaignard@gmail.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| * | hwspinlock: add STM32 hwspinlock deviceBenjamin Gaignard2018-12-053-0/+166
| |/ | | | | | | | | | | | | | | | | This patch adds support of hardware semaphores for stm32mp1 SoC. The hardware block provides 32 semaphores. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-23 16:18:11 +0100