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* drm/vmwgfx: Assign eviction priorities to resourcesThomas Hellstrom2019-08-158-20/+140
| | | | | | | | | | | | | | | | TTM provides a means to assign eviction priorities to buffer object. This means that all buffer objects with a lower priority will be evicted first on memory pressure. Use this to make sure surfaces and in particular non-dirty surfaces are evicted first. Evicting in particular shaders, cotables and contexts imply a significant performance hit on vmwgfx, so make sure these resources are evicted last. Some buffer objects are sub-allocated in user-space which means we can have many resources attached to a single buffer object or resource. In that case the buffer object is given the highest priority of the attached resources. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Deepak Rawat <drawat@vmware.com>
* drm/vmwgfx: drop reminaing users of drmP.hSam Ravnborg2019-08-1512-31/+36
| | | | | | | | | | | | | | | | | | | | | | Drop use of the deprecated drmP.h file from the remaining files. In several cases the drmP.h include could be removed without furter fixes. Other files required a few header files to be added. In all files divided includes files in blocks and sort them. v2: - fix warning in i386 build wiht HIGHMEM disabled Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reported-by: kbuild test robot <lkp@intel.com> [warning in i386 build] Cc: VMware Graphics <linux-graphics-maintainer@vmware.com> Cc: Thomas Hellstrom <thellstrom@vmware.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Reviewed-by: Deepak Rawat <drawat@vmware.com> Signed-off-by: Deepak Rawat <drawat@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
* drm/vmwgfx: drop use of drmP.h in header filesSam Ravnborg2019-08-1512-27/+59
| | | | | | | | | | | | | | | | | | | | | | To facilitate removal of drmP.h in the .c files remove the use from header files first. Fix fallout in the other files. Sorted include files in blocks and sorted files within each block in alphabetical order. This revealed a dependency from an uapi header to a header located below drivers/gpu/drm/vmwgfx/. Added FIXME to remind someone to fix this. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Cc: VMware Graphics <linux-graphics-maintainer@vmware.com> Cc: Thomas Hellstrom <thellstrom@vmware.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Reviewed-by: Deepak Rawat <drawat@vmware.com> Signed-off-by: Deepak Rawat <drawat@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
* drm/vmwgfx: Kill unneeded legacy security featuresThomas Hellstrom2019-08-155-312/+3
| | | | | | | | | | | | | | | | | At one point, the GPU command verifier and user-space handle manager couldn't properly protect GPU clients from accessing each other's data. Instead there was an elaborate mechanism to make sure only the active master's primary clients could render. The other clients were either put to sleep or even killed (if the master had exited). VRAM was evicted on master switch. With the advent of render-node functionality, we relaxed the VRAM eviction, but the other mechanisms stayed in place. Now that the GPU command verifier and ttm object manager properly isolates primary clients from different master realms we can remove the master switch related code and drop those legacy features. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Deepak Rawat <drawat@vmware.com>
* drm/vmwgfx: Use VMW_DEBUG_KMS for vmwgfx mode-setting user errorsDeepak Rawat2019-08-141-5/+10
| | | | | | | | | For errors during layout change ioctl use VMW_DEBUG_KMS instead of DRM_ERROR. Signed-off-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
* drm/vmwgfx: Add debug message for layout change ioctlDeepak Rawat2019-08-142-0/+16
| | | | | | | | Add debug code to check user-space layout change request. Signed-off-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
* Merge tag 'drm-next-5.4-2019-08-09' of ↵Dave Airlie2019-08-12259-5046/+120846
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~agd5f/linux into drm-next drm-next-5.4-2019-08-09: Same as drm-next-5.4-2019-08-06, but with the readq/writeq stuff fixed and 5.3-rc3 backmerged. amdgpu: - Add navi14 support - Add navi12 support - Add Arcturus support - Enable mclk DPM for Navi - Misc DC display fixes - Add perfmon support for DF - Add scatter/gather display support for Raven - Improve SMU handling for GPU reset - RAS support for GFX - Drop last of drmP.h - Add support for wiping memory on buffer release - Allow cursor async updates for fb swaps - Misc fixes and cleanups amdkfd: - Add navi14 support - Add navi12 support - Add Arcturus support - CWSR trap handlers updates for gfx9, 10 - Drop last of drmP.h - Update MAINTAINERS radeon: - Misc fixes and cleanups - Make kexec more reliable by tearing down the GPU ttm: - Add release_notify callback uapi: - Add wipe memory on release flag for buffer creation Signed-off-by: Dave Airlie <airlied@redhat.com> [airlied: resolved conflicts with ttm resv moving] From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190809184807.3381-1-alexander.deucher@amd.com
| * Merge tag 'v5.3-rc3' into drm-next-5.4Alex Deucher2019-08-096558-204675/+207301
| |\ | | | | | | | | | | | | | | | Linux 5.3-rc3 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: remove RREG64/WREG64Tao Zhou2019-08-092-37/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | atomic 64 bits REG operations are useless currently Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: implement UMC 64 bits REG operationsTao Zhou2019-08-092-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | implement 64 bits operations via 32 bits interface v2: make use of lower_32_bits() and upper_32_bits() macros Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: replace readq/writeq with atomic64 operationsTao Zhou2019-08-091-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | what we really want is a read or write that is guaranteed to be 64 bits at a time, atomic64 operations are supported on all architectures Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | gpu: drm: amd: powerplay: Remove logically dead codeHariprasad Kelam2019-08-061-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Result of pointer airthmentic is never null fix coverity defect:1451876 Signed-off-by: Hariprasad Kelam <hariprasad.kelam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: Zero initialize some variablesNathan Chancellor2019-08-062-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clang warns (only Navi warning shown but Arcturus warns as well): drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1534:4: warning: variable 'asic_default_power_limit' is used uninitialized whenever '?:' condition is false [-Wsometimes-uninitialized] smu_read_smc_arg(smu, &asic_default_power_limit); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:588:3: note: expanded from macro 'smu_read_smc_arg' ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0) ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1550:30: note: uninitialized use occurs here smu->default_power_limit = asic_default_power_limit; ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1534:4: note: remove the '?:' if its condition is always true smu_read_smc_arg(smu, &asic_default_power_limit); ^ drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:588:3: note: expanded from macro 'smu_read_smc_arg' ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0) ^ drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1517:35: note: initialize the variable 'asic_default_power_limit' to silence this warning uint32_t asic_default_power_limit; ^ = 0 1 warning generated. As the code is currently written, if read_smc_arg were ever NULL, arg would fail to be initialized but the code would continue executing as normal because the return value would just be zero. There are a few different possible solutions to resolve this class of warnings which have appeared in these drivers before: 1. Assume the function pointer will never be NULL and eliminate the wrapper macros. 2. Have the wrapper macros initialize arg when the function pointer is NULL. 3. Have the wrapper macros return an error code instead of 0 when the function pointer is NULL so that the callsites can properly bail out before arg can be used. 4. Initialize arg at the top of its function. Number four is the path of least resistance right now as every other change will be driver wide so do that here. I only make the comment now as food for thought. Fixes: b4af964e75c4 ("drm/amd/powerplay: make power limit retrieval as asic specific") Link: https://github.com/ClangBuiltLinux/linux/issues/627 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Fix GPU reset crash regression.Andrey Grodzovsky2019-08-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | amdgpu_ip_block.status.hw for GMC wasn't set to false on suspend during GPU reset and so on resume gmc_v9_0_resume wasn't called. Caused by 'drm/amdgpu: fix double ucode load by PSP(v3)' Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: check before issuing messages for max sustainable clocksEvan Quan2019-08-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Those messages are not supported on Arcturus and should not be issued. Affected ASIC: Arcturus Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/discovery: move common discovery code out of navi1*_reg_base_init()Xiaojie Yuan2019-08-063-28/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | move amdgpu_discovery_reg_base_init() from navi1*_reg_base_init() to a common function nv_reg_base_init(). Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/soc15: fix external_rev_id for navi14tiancyin2019-08-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | fix the hard code external_rev_id. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: update ras sysfs feature infoTao Zhou2019-08-061-12/+5
| | | | | | | | | | | | | | | | | | | | | | | | remove confused ras error type info Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: skip pcie params override on Arcturus V2Evan Quan2019-08-061-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is not supported on Arcturus. Affected ASIC: Arcturus V2: minor cosmetic fix Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Fix panic during gpu resetxinhui pan2019-08-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Clear the flag after hw suspend, otherwise it skips the corresponding hw resume. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: pin the csb buffer on hw init for gfx v8Likun Gao2019-08-061-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this pin, the csb buffer will be filled with inconsistent data after S3 resume. And that will causes gfx hang on gfxoff exit since this csb will be executed then. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Tested-by: Paul Gover <pmw.gover@yahoo.co.uk> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Block immediate flips for non-fast updatesNicholas Kazlauskas2019-08-062-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Underflow can occur in the case where we change buffer pitch, DCC state, rotation or mirroring for a plane while also performing an immediate flip. It can also generate a p-state warning stack trace on DCN1 which is typically observed during the cursor handler pipe locking because of how frequent cursor updates can occur. [How] Store the update type on each CRTC - every plane will have access to the CRTC state if it's flipping. If the update type is not UPDATE_TYPE_FAST then the immediate flip should be disallowed. No changes to the target vblank sequencing need to be done, we just need to ensure that the surface registers do a double buffered update. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <david.francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Validate dc_plane_info and dc_plane_size in atomic checkNicholas Kazlauskas2019-08-061-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Pitch, DCC, rotation and mirroring can result in updates that are not UPDATE_TYPE_FAST but UPDATE_TYPE_MED instead. DC needs dc_plane_info and dc_plane_size to make this determination and we aren't currently passing this into DC during atomic check. Underflow (visible or non-visible) can occur if we don't validate this correctly. This also will generally trigger p-state warnings, typically via the cursor handler when locking. [How] Get the framebuffer tiling flags and generate the required structures for DC in dm_determine_update_type_for_commit. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <david.francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable Navi12 kfd support for amdgpushaoyunl2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Navi12 has the same interface as Navi10 Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add missing NV12 asic IDsRoman Li2019-08-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add missing navi12 asic ids. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Add nv12 DC ip blockLeo Li2019-08-022-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Load DC and amdgpu display manager Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add ASICREV_IS_NAVI macrosLeo Li2019-08-021-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | They are used by DC to determine ASIC revs. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable DPG mode for Navi12Boyuan Zhang2019-08-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable Dynamic Power Gating VCN for Navi12. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add VCN ip block for Navi12Boyuan Zhang2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add VCN2 ip block for Navi12 Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add Navi12 VCN firmware supportBoyuan Zhang2019-08-021-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | Add Navi12 to VCN family Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add psp ip block for navi12Xiaojie Yuan2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add smu ip block for navi12Xiaojie Yuan2019-08-021-0/+6
| | | | | | | | | | | | | | | | | | Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: start autoload till RLCG fw for navi12Xiaojie Yuan2019-08-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | rlc save restore list is not ready yet for navi12 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/psp11: add psp support for navi12Xiaojie Yuan2019-08-022-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/smu11: add smu support for navi12Xiaojie Yuan2019-08-022-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Same as other Navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: correct smu rlc handshake enablement bitJack Xiao2019-08-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Correct the enablement bit of SMU RLC handshake. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc headerXiaojie Yuan2019-08-022-0/+41
| | | | | | | | | | | | | | | | | | | | | gc 10.1.2 introduced this new register Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/sdma5: add golden settings for navi12 (v2)Xiaojie Yuan2019-08-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | common golden settings are put in golden_settings_sdma_5 array v2: update settings (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: add golden settings for navi12 (v2)Xiaojie Yuan2019-08-021-5/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial golden settings for navi12 gfx. v2: update settings Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable virtual display for navi12Xiaojie Yuan2019-08-022-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Virtual display is a sw display interface for bring up and virtualization or for cards without display hardware. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: set tcp harvest for navi12Xiaojie Yuan2019-08-021-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add ip blocks for navi12Xiaojie Yuan2019-08-021-0/+7
| | | | | | | | | | | | | | | | | | Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gmc10: set gart size and vm size for navi12Xiaojie Yuan2019-08-021-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/sdma5: add placeholder for navi12 golden settingsXiaojie Yuan2019-08-021-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | None yet. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/sdma5: declare sdma firmwares for navi12Xiaojie Yuan2019-08-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Declare the firmwares and load the proper ones for navi12. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: set rlc funcs for navi12Xiaojie Yuan2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: set number of me(c)/pipe/queue for navi12Xiaojie Yuan2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: add placeholder for navi12 golden settingsXiaojie Yuan2019-08-021-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Not used yet. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: declare cp/rlc firmwares for navi12Xiaojie Yuan2019-08-021-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Set the name properly to load the right ucode. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: add gfx config for navi12Xiaojie Yuan2019-08-021-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | got from mmCP_MAX_CONTEXT and mmPA_SC_FIFO_SIZE v2: squash all navi asics together because the settings are the same. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>