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* Merge branch 'pci/host-xgene' into nextBjorn Helgaas2017-11-141-2/+2
|\ | | | | | | | | * pci/host-xgene: PCI: xgene: Rename xgene_pcie_probe_bridge() to xgene_pcie_probe()
| * PCI: xgene: Rename xgene_pcie_probe_bridge() to xgene_pcie_probe()Bjorn Helgaas2017-11-101-2/+2
| | | | | | | | | | | | | | Rename xgene_pcie_probe_bridge() to xgene_pcie_probe() to follow the convention of other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* | Merge branch 'pci/host-v3-semi' into nextBjorn Helgaas2017-11-143-0/+966
|\ \ | | | | | | | | | | | | | | | * pci/host-v3-semi: PCI: v3-semi: Add V3 Semiconductor PCI host driver PCI: v3: Update the device tree bindings
| * | PCI: v3-semi: Add V3 Semiconductor PCI host driverLinus Walleij2017-10-053-0/+966
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This PCI host bridge from V3 Semiconductor needs no further introduction. An ancient driver for it has been sitting in arch/arm/mach-integrator/pci_v3.* since before v2.6.12 and the initial migration to git. But we need to get the drivers out of arch/arm/* and get proper handling of the old drivers, rewrite and clean up so the PCI maintainer can control the mass of drivers without having to run all over the kernel. We also switch swiftly to all the new infrastructure found in the PCI hosts as of late. Some code is preserved so I have added an extensive list of authors in the top comment section. This driver probes with the following result: OF: PCI: host bridge /pciv3@62000000 ranges: OF: PCI: No bus range found for /pciv3@62000000, using [bus 00-ff] OF: PCI: IO 0x60000000..0x6000ffff -> 0x00000000 OF: PCI: MEM 0x40000000..0x4fffffff -> 0x40000000 OF: PCI: MEM 0x50000000..0x5fffffff -> 0x50000000 pci-v3-semi 62000000.pciv3: initialized PCI V3 Integrator/AP integration pci-v3-semi 62000000.pciv3: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [bus 00-ff] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff pref] pci-v3-semi 62000000.pciv3: parity error interrupt pci-v3-semi 62000000.pciv3: master abort error interrupt pci-v3-semi 62000000.pciv3: PCI target LB->PCI READ abort interrupt pci-v3-semi 62000000.pciv3: master abort error interrupt (repeats a few times) pci 0000:00:09.0: [1011:0024] type 01 class 0x060400 pci-v3-semi 62000000.pciv3: master abort error interrupt pci-v3-semi 62000000.pciv3: PCI target LB->PCI READ abort interrupt pci 0000:00:0b.0: [8086:1229] type 00 class 0x020000 pci 0000:00:0b.0: reg 0x10: [mem 0x00000000-0x00000fff pref] pci 0000:00:0b.0: reg 0x14: [io 0x0000-0x001f] pci 0000:00:0b.0: reg 0x18: [mem 0x00000000-0x000fffff] pci 0000:00:0b.0: reg 0x30: [mem 0x00000000-0x000fffff pref] pci 0000:00:0b.0: supports D1 D2 pci 0000:00:0b.0: PME# supported from D0 D1 D2 D3hot pci 0000:00:0c.0: [5333:8811] type 00 class 0x030000 pci 0000:00:0c.0: reg 0x10: [mem 0x00000000-0x03ffffff] pci 0000:00:0c.0: reg 0x30: [mem 0x00000000-0x0000ffff pref] pci 0000:00:0c.0: vgaarb: VGA device added: decodes=io+mem,owns=io,locks=none PCI: bus0: Fast back to back transfers disabled PCI: bus1: Fast back to back transfers enabled pci 0000:00:0c.0: BAR 0: assigned [mem 0x40000000-0x43ffffff] pci 0000:00:0b.0: BAR 2: assigned [mem 0x44000000-0x440fffff] pci 0000:00:0b.0: BAR 6: assigned [mem 0x50000000-0x500fffff pref] pci 0000:00:0c.0: BAR 6: assigned [mem 0x50100000-0x5010ffff pref] pci 0000:00:0b.0: BAR 0: assigned [mem 0x50110000-0x50110fff pref] pci 0000:00:0b.0: BAR 1: assigned [io 0x1000-0x101f] pci 0000:00:09.0: PCI bridge to [bus 01] pci 0000:00:0b.0: Firmware left e100 interrupts enabled; disabling (...) e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI e100: Copyright(c) 1999-2006 Intel Corporation e100 0000:00:0b.0: enabling device (0146 -> 0147) e100 0000:00:0b.0 eth0: addr 0x50110000, irq 31, MAC addr 00:08:c7:99:d2:57 > lspci 00:0b.0 Class 0200: 8086:1229 00:09.0 Class 0604: 1011:0024 00:0c.0 Class 0300: 5333:8811 > cat /proc/iomem 40000000-4fffffff : V3 PCI NON-PRE-MEM 40000000-43ffffff : 0000:00:0c.0 44000000-440fffff : 0000:00:0b.0 44000000-440fffff : e100 50000000-5fffffff : V3 PCI PRE-MEM 50000000-500fffff : 0000:00:0b.0 50100000-5010ffff : 0000:00:0c.0 50110000-50110fff : 0000:00:0b.0 50110000-50110fff : e100 61000000-61ffffff : /pciv3@62000000 62000000-6200ffff : /pciv3@62000000 Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [bhelgaas: fold in %pR fixes from Arnd Bergmann <arnd@arndb.de>: http://lkml.kernel.org/r/20171011140224.3770968-1-arnd@arndb.de] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
* | Merge branch 'pci/host-thunder' into nextBjorn Helgaas2017-11-142-0/+15
|\ \ | | | | | | | | | | | | | | | | | | * pci/host-thunder: PCI: Avoid slot reset if bridge itself is broken PCI: Avoid bus reset if bridge itself is broken PCI: Mark Cavium CN8xxx to avoid bus reset
| * | PCI: Avoid slot reset if bridge itself is brokenJan Glauber2017-10-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When checking to see if a PCI slot can safely be reset, we previously checked to see if any of the children had their PCI_DEV_FLAGS_NO_BUS_RESET flag set. Some PCIe root port bridges do not behave well after a slot reset, and may cause the device in the slot to become unusable. Add a check for PCI_DEV_FLAGS_NO_BUS_RESET being set in the bridge device to prevent the slot from being reset. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
| * | PCI: Avoid bus reset if bridge itself is brokenDavid Daney2017-10-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When checking to see if a PCI bus can safely be reset, we previously checked to see if any of the children had their PCI_DEV_FLAGS_NO_BUS_RESET flag set. Children marked with that flag are known not to behave well after a bus reset. Some PCIe root port bridges also do not behave well after a bus reset, sometimes causing the devices behind the bridge to become unusable. Add a check for PCI_DEV_FLAGS_NO_BUS_RESET being set in the bridge device to allow these bridges to be flagged, and prevent their secondary buses from being reset. Signed-off-by: David Daney <david.daney@cavium.com> [jglauber@cavium.com: fixed typo] Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
| * | PCI: Mark Cavium CN8xxx to avoid bus resetDavid Daney2017-10-111-0/+7
| |/ | | | | | | | | | | | | | | | | | | | | Root ports of cn8xxx do not function after bus reset when used with some e1000e and LSI HBA devices. Add a quirk to prevent bus reset on these root ports. Signed-off-by: David Daney <david.daney@cavium.com> [jglauber@cavium.com: fixed typo and whitespaces] Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
* | Merge branch 'pci/host-tegra' into nextBjorn Helgaas2017-11-141-27/+131
|\ \ | | | | | | | | | | | | | | | | | | * pci/host-tegra: PCI: tegra: Add Tegra186 PCIe support dt-bindings: pci: tegra: Document Tegra186 PCIe DT PCI: tegra: Use generic accessors where possible
| * | PCI: tegra: Add Tegra186 PCIe supportManikanta Maddireddy2017-10-181-25/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Tegra186 PCIe support. UPHY programming is performed by BPMP; PHY enable calls are not required for Tegra186 PCIe. Power partition ungate is done by BPMP powergate driver. The Tegra186 DT description must include a "power-domains" property, which results in dev->pm_domain being set. Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> [bhelgaas: add "power-domains" reference] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Use generic accessors where possibleThierry Reding2017-10-111-2/+22
| |/ | | | | | | | | | | | | | | The Tegra PCI host controller can generate configuration space accesses with byte, word and dword granularity for devices. Only root ports can't have their configuration space accessed in this way. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/host-tango' into nextBjorn Helgaas2017-11-147-101/+223
|\ \ | | | | | | | | | | | | | | | | | | * pci/host-tango: PCI: tango: Add MSI controller support PCI: Use of_pci_dma_range_parser_init() to reduce duplication of/pci: Add of_pci_dma_range_parser_init() for dma-ranges parsing support
| * | PCI: tango: Add MSI controller supportMarc Gonzalez2017-10-051-3/+202
| | | | | | | | | | | | | | | | | | | | | Add support for the MSI controller in Tango, which supports 256 message-signaled interrupts and a single doorbell address. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Use of_pci_dma_range_parser_init() to reduce duplicationMarc Gonzalez2017-10-055-95/+5
| | | | | | | | | | | | | | | | | | | | | Use the new of_pci_dma_range_parser_init() to reduce code duplication. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * | of/pci: Add of_pci_dma_range_parser_init() for dma-ranges parsing supportMarc Gonzalez2017-10-051-3/+16
| |/ | | | | | | | | | | | | | | | | | | | | Several host bridge drivers duplicate of_pci_range_parser_init() in order to parse their dma-ranges property. Provide of_pci_dma_range_parser_init() for that use case. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge branch 'pci/host-layerscape' into nextBjorn Helgaas2017-11-143-0/+21
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-layerscape: PCI: layerscape: Change default error response behavior PCI: Disable MSI for Freescale Layerscape PCIe RC mode arm64: dts: ls1046a: Add PCIe controller DT nodes arm64: dts: ls1012a: Add PCIe controller DT node PCI: layerscape: Add support for ls1012a arm64: dts: ls1012a: Add MSI controller DT node irqchip/ls-scfg-msi: Add LS1012a MSI support
| * | PCI: layerscape: Change default error response behaviorMinghuan Lian2017-10-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default, when the PCIe controller experiences an erroneous completion from an external completer for its outbound non-posted request, it sends an OKAY response to the device's internal AXI slave system interface. However, this default system error response behavior cannot be used for other types of outbound non-posted requests. For example, the outbound memory read transaction requires an actual ERROR response, like UR completion or completion timeout. Fix this by forwarding the error response of the non-posted request. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Disable MSI for Freescale Layerscape PCIe RC modeHou Zhiqiang2017-10-201-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale PCIe controller advertises the MSI/MSI-X capability in both RC and Endpoint mode, but in RC mode it doesn't support MSI/MSI-X by itself; it can only transfer MSI/MSI-X from downstream devices. Add a quirk to prevent use of MSI/MSI-X in RC mode. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
| * | PCI: layerscape: Add support for ls1012aHou Zhiqiang2017-10-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for ls1012a. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
| * | irqchip/ls-scfg-msi: Add LS1012a MSI supportHou Zhiqiang2017-10-111-0/+1
| |/ | | | | | | | | | | | | | | | | | | The ls1012a implements only 1 MSI controller, and it is the same as ls1043a. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
* | Merge branch 'pci/host-iproc' into nextBjorn Helgaas2017-11-141-7/+12
|\ \ | | | | | | | | | | | | * pci/host-iproc: PCI: iproc: Allow allocation of multiple MSIs
| * | PCI: iproc: Allow allocation of multiple MSIsSandor Bodo-Merle2017-10-171-7/+12
| |/ | | | | | | | | | | | | | | | | | | | | Add support for allocating multiple MSIs at the same time, so that the MSI_FLAG_MULTI_PCI_MSI flag can be added to the msi_domain_info structure. Avoid storing the hwirq in the low 5 bits of the message data, as it is used by the device. Also fix an endianness problem by using readl(). Signed-off-by: Sandor Bodo-Merle <sbodomerle@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com>
* | Merge branch 'pci/host-hv' into nextBjorn Helgaas2017-11-141-3/+5
|\ \ | | | | | | | | | | | | * pci/host-hv: PCI: hv: Use effective affinity mask
| * | PCI: hv: Use effective affinity maskDexuan Cui2017-11-081-3/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The effective_affinity_mask is always set when an interrupt is assigned in __assign_irq_vector() -> apic->cpu_mask_to_apicid(), e.g. for struct apic apic_physflat: -> default_cpu_mask_to_apicid() -> irq_data_update_effective_affinity(), but it looks d->common->affinity remains all-1's before the user space or the kernel changes it later. In the early allocation/initialization phase of an IRQ, we should use the effective_affinity_mask, otherwise Hyper-V may not deliver the interrupt to the expected CPU. Without the patch, if we assign 7 Mellanox ConnectX-3 VFs to a 32-vCPU VM, one of the VFs may fail to receive interrupts. Tested-by: Adrian Suhov <v-adsuho@microsoft.com> Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jake Oshins <jakeo@microsoft.com> Cc: stable@vger.kernel.org Cc: Jork Loeser <jloeser@microsoft.com> Cc: Stephen Hemminger <sthemmin@microsoft.com> Cc: K. Y. Srinivasan <kys@microsoft.com>
* | Merge branch 'pci/host-hisi' into nextBjorn Helgaas2017-11-143-0/+481
|\ \ | | | | | | | | | | | | * pci/host-hisi: PCI: hisi: Add HiSilicon STB SoC PCIe controller driver
| * | PCI: hisi: Add HiSilicon STB SoC PCIe controller driverJianguo Sun2017-10-243-0/+481
| |/ | | | | | | | | | | | | | | Add a HiSilicon STB SoC PCIe controller driver. This controller is based on the DesignWare PCIe core. Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/host-generic' into nextBjorn Helgaas2017-11-141-0/+43
|\ \ | | | | | | | | | | | | | | | * pci/host-generic: dt-bindings: PCI: designware: Add binding for Designware PCIe in ECAM mode PCI: generic: Add support for Synopsys DesignWare RC in ECAM mode
| * | PCI: generic: Add support for Synopsys DesignWare RC in ECAM modeArd Biesheuvel2017-10-071-0/+43
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some implementations of the Synopsys DesignWare PCIe controller implement a so-called ECAM shift mode, which allows a static memory window to be configured that covers the configuration space of the entire bus range. Usually, when the firmware performs all the low level configuration that is required to expose this controller in a fully ECAM compatible manner, we can simply describe it as "pci-host-ecam-generic" and be done with it. However, in some cases (e.g., the Marvell Armada 80x0 as well as the Socionext SynQuacer Soc), the IP was synthesized with an ATU window granularity that does not allow the first bus to be mapped in a way that prevents the device on the downstream port from appearing more than once, and so we still need special handling in software to drive this static almost-ECAM configuration. So extend the pci-host-generic driver so it can support these controllers as well, by adding special config space accessors that take the above quirk into account. Note that, unlike most drivers for this IP, this driver does not expose a fake bridge device at B/D/F 00:00.0. There is no point in doing so, given that this is not a true bridge, and does not require any windows to be configured in order for the downstream device to operate correctly. Omitting it also prevents the PCI resource allocation routines from handing out BAR space to it unnecessarily. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> [bhelgaas: factor out pci_dw_valid_device(), add pci_dw_ecam_map_bus() and use generic read/write functions] Signed-off-by: Bjorn Helgaas <helgaas@kernel.org> Acked-by: Will Deacon <will.deacon@arm.com>
* | Merge branch 'pci/host-faraday' into nextBjorn Helgaas2017-11-141-1/+1
|\ \ | | | | | | | | | | | | * pci/host-faraday: PCI: faraday: Fix wrong pointer passed to PTR_ERR()
| * | PCI: faraday: Fix wrong pointer passed to PTR_ERR()Wei Yongjun2017-10-211-1/+1
| |/ | | | | | | | | | | | | | | | | PTR_ERR should access the value just tested by IS_ERR, otherwise the wrong error code will be returned. Fixes: 2eeb02b28579 ("PCI: faraday: Add clock handling") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge branch 'pci/host-dra7xx' into nextBjorn Helgaas2017-11-141-0/+17
|\ \ | | | | | | | | | | | | * pci/host-dra7xx: PCI: dra7xx: Add shutdown handler to cleanly turn off clocks
| * | PCI: dra7xx: Add shutdown handler to cleanly turn off clocksKeerthy2017-10-111-0/+17
| |/ | | | | | | | | | | | | | | Add shutdown handler to cleanly turn off clocks. This will help in cases of kexec where in a new kernel can boot abruptly. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
* | Merge branch 'pci/host-altera' into nextBjorn Helgaas2017-11-141-4/+4
|\ \ | | | | | | | | | | | | * pci/host-altera: PCI: altera: Rename altera_pcie_link_is_up() to altera_pcie_link_up()
| * | PCI: altera: Rename altera_pcie_link_is_up() to altera_pcie_link_up()Bjorn Helgaas2017-11-091-4/+4
| |/ | | | | | | | | | | | | | | Rename altera_pcie_link_is_up() to altera_pcie_link_up() to follow the convention of other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | Merge branch 'pci/virtualization' into nextBjorn Helgaas2017-11-147-59/+89
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/virtualization: PCI: Document reset method return values PCI: Detach driver before procfs & sysfs teardown on device remove PCI: Apply Cavium ThunderX ACS quirk to more Root Ports PCI: Set Cavium ACS capability quirk flags to assert RR/CR/SV/UF PCI: Restore ARI Capable Hierarchy before setting numVFs PCI: Create SR-IOV virtfn/physfn links before attaching driver PCI: Expose SR-IOV offset, stride, and VF device ID via sysfs PCI: Cache the VF device ID in the SR-IOV structure PCI: Add Kconfig PCI_IOV dependency for PCI_REALLOC_ENABLE_AUTO PCI: Remove unused function __pci_reset_function() PCI: Remove reset argument from pci_iov_{add,remove}_virtfn()
| * | PCI: Document reset method return valuesBjorn Helgaas2017-10-261-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_reset_function() path may try several different reset methods: device-specific resets, PCIe Function Level Resets, PCI Advanced Features Function Level Reset, etc. Add a comment about what the return values from these methods mean. If one of the methods fails, in some cases we want to continue and try the next one in the list, but sometimes we want to stop trying. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Detach driver before procfs & sysfs teardown on device removeAlex Williamson2017-10-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When removing a device, for example a VF being removed due to SR-IOV teardown, a "soft" hot-unplug via 'echo 1 > remove' in sysfs, or an actual hot-unplug, we first remove the procfs and sysfs attributes for the device before attempting to release the device from any driver bound to it. Unbinding the driver from the device can take time. The device might need to write out data or it might be actively in use. If it's in use by userspace through a vfio driver, the unbind might block until the user releases the device. This leads to a potentially non-trivial amount of time where the device exists, but we've torn down the interfaces that userspace uses to examine devices, for instance lspci might generate this sort of error: pcilib: Cannot open /sys/bus/pci/devices/0000:01:0a.3/config lspci: Unable to read the standard configuration space header of device 0000:01:0a.3 We don't seem to have any dependence on this teardown ordering in the kernel, so let's unbind the driver first, which is also more symmetric with the instantiation of the device in pci_bus_add_device(). Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Apply Cavium ThunderX ACS quirk to more Root PortsVadim Lomovtsev2017-10-191-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the Cavium ThunderX ACS quirk to cover more device IDs and restrict it to only Root Ports. Signed-off-by: Vadim Lomovtsev <Vadim.Lomovtsev@cavium.com> [bhelgaas: changelog, stable tag] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # v4.12+
| * | PCI: Set Cavium ACS capability quirk flags to assert RR/CR/SV/UFVadim Lomovtsev2017-10-191-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cavium ThunderX (CN8XXX) family of PCIe Root Ports does not advertise an ACS capability. However, the RTL internally implements similar protection as if ACS had Request Redirection, Completion Redirection, Source Validation, and Upstream Forwarding features enabled. Change Cavium ACS capabilities quirk flags accordingly. Fixes: b404bcfbf035 ("PCI: Add ACS quirk for all Cavium devices") Signed-off-by: Vadim Lomovtsev <Vadim.Lomovtsev@cavium.com> [bhelgaas: tidy changelog, comment, stable tag] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # v4.6+: b77d537d00d0: PCI: Apply Cavium ACS quirk only to CN81xx/CN83xx/CN88xx devices
| * | PCI: Restore ARI Capable Hierarchy before setting numVFsTony Nguyen2017-10-111-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the restore path, we previously read PCI_SRIOV_VF_OFFSET and PCI_SRIOV_VF_STRIDE before restoring PCI_SRIOV_CTRL_ARI: pci_restore_state pci_restore_iov_state sriov_restore_state pci_iov_set_numvfs pci_read_config_word(... PCI_SRIOV_VF_OFFSET, &iov->offset) pci_read_config_word(... PCI_SRIOV_VF_STRIDE, &iov->stride) pci_write_config_word(... PCI_SRIOV_CTRL, iov->ctrl) But per SR-IOV r1.1, sec 3.3.3.5, the device can use PCI_SRIOV_CTRL_ARI to determine PCI_SRIOV_VF_OFFSET and PCI_SRIOV_VF_STRIDE. Therefore, this path, which is used for suspend/resume and AER recovery, can corrupt iov->offset and iov->stride. Since the iov state is associated with the device, not the driver, if we reload the driver, it will use the the corrupted data, which may cause crashes like this: kernel BUG at drivers/pci/iov.c:157! RIP: 0010:pci_iov_add_virtfn+0x2eb/0x350 Call Trace: pci_enable_sriov+0x353/0x440 ixgbe_pci_sriov_configure+0xd5/0x1f0 [ixgbe] sriov_numvfs_store+0xf7/0x170 dev_attr_store+0x18/0x30 sysfs_kf_write+0x37/0x40 kernfs_fop_write+0x120/0x1b0 vfs_write+0xb5/0x1a0 SyS_write+0x55/0xc0 Restore PCI_SRIOV_CTRL_ARI before calling pci_iov_set_numvfs(), then restore the rest of PCI_SRIOV_CTRL (which may set PCI_SRIOV_CTRL_VFE) afterwards. Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> [bhelgaas: changelog, add comment, also clear ARI if necessary] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alexander Duyck <alexander.h.duyck@intel.com> CC: Emil Tantilov <emil.s.tantilov@intel.com>
| * | PCI: Create SR-IOV virtfn/physfn links before attaching driverStuart Hayes2017-10-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When creating virtual functions, create the "virtfn%u" and "physfn" links in sysfs *before* attaching the driver instead of after. When we attach the driver to the new virtual network interface first, there is a race when the driver attaches to the new sends out an "add" udev event, and the network interface naming software (biosdevname or systemd, for example) tries to look at these links. Signed-off-by: Stuart Hayes <stuart.w.hayes@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Expose SR-IOV offset, stride, and VF device ID via sysfsFilippo Sironi2017-10-111-0/+33
| | | | | | | | | | | | | | | | | | | | | Expose the SR-IOV device offset, stride, and VF device ID via sysfs to make it easier for userspace applications to consume them. Signed-off-by: Filippo Sironi <sironi@amazon.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Cache the VF device ID in the SR-IOV structureFilippo Sironi2017-10-052-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Cache the VF device ID in the SR-IOV structure and use it instead of reading it over and over from the PF config space capability. Signed-off-by: Filippo Sironi <sironi@amazon.de> [bhelgaas: rename to "vf_device" to match pci_dev->device] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add Kconfig PCI_IOV dependency for PCI_REALLOC_ENABLE_AUTOSascha El-Sharkawy2017-10-051-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Ensure only valid Kconfig configurations for PCI_REALLOC_ENABLE_AUTO. This is done by selecting PCI_IOV, which is required by PCI_REALLOC_ENABLE_AUTO to work. Signed-off-by: Sascha El-Sharkawy <elscha@sse.uni-hildesheim.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Remove unused function __pci_reset_function()Jan H. Schönherr2017-10-051-32/+3
| | | | | | | | | | | | | | | | | | | | | The last caller of __pci_reset_function() has been removed. Remove the function as well. Signed-off-by: Jan H. Schönherr <jschoenh@amazon.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Remove reset argument from pci_iov_{add,remove}_virtfn()Jan H. Schönherr2017-10-051-13/+5
| |/ | | | | | | | | | | | | | | | | | | | | The "reset" argument passed to pci_iov_add_virtfn() and pci_iov_remove_virtfn() is always zero since 46cb7b1bd86f ("PCI: Remove unused SR-IOV VF Migration support") Remove the argument together with the associated code. Signed-off-by: Jan H. Schönherr <jschoenh@amazon.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Russell Currey <ruscur@russell.cc>
* | Merge branch 'pci/switchtec' into nextBjorn Helgaas2017-11-141-1/+1
|\ \ | | | | | | | | | | | | * pci/switchtec: switchtec: Make struct event_regs static
| * | switchtec: Make struct event_regs staticColin Ian King2017-10-051-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | The structure event_regs is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: symbol 'event_regs' was not declared. Should it be static Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Logan Gunthorpe <logang@deltatee.com>
* | Merge branch 'pci/resource' into nextBjorn Helgaas2017-11-145-15/+286
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/resource: PCI: Fail pci_map_rom() if the option ROM is invalid PCI: Move pci_map_rom() error path x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 00-1f, 30-3f, 60-7f) PCI: Add pci_resize_resource() for resizing BARs PCI: Add resizable BAR infrastructure PCI: Add PCI resource type mask #define
| * | PCI: Fail pci_map_rom() if the option ROM is invalidChangbin Du2017-11-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we detect a invalid PCI option ROM (e.g., invalid ROM header signature), we should unmap it immediately and fail. It doesn't make any sense to return a mapped area with size of 0. I have seen this case on Intel GVTg vGPU, which has no VBIOS. It will not cause a real problem, but we should skip it as early as possible. Signed-off-by: Changbin Du <changbin.du@intel.com> [bhelgaas: split non-functional change into separate patch] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-08 13:54:56 +0100