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* clk: at91: Remove CLK_IS_ROOTStephen Boyd2016-03-032-2/+2
| | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: bcm: Remove CLK_IS_ROOTStephen Boyd2016-03-031-6/+3
| | | | | | | | This flag is a no-op now. Remove usage of the flag. Cc: Lee Jones <lee@kernel.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'imx-clk-4.6' of ↵Stephen Boyd2016-03-022-59/+138
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull i.MX clk updates from Shawn Guo: The i.MX clock update for 4.6: - Add the clock driver support for the latest i.MX6 family SoCs addition - i.MX6QP. - Clean up the whitespace in i.MX6UL clock driver and add the missing KPP clock. - Correct pwm7 clock name in i.MX6UL clock driver. * tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx: add kpp clock for i.MX6UL clk: imx: whitespace cleanup; no functional change clk: imx: correct pwm7 clock name in driver for i.MX6UL clk: imx: Add clock support for imx6qp
| * clk: imx: add kpp clock for i.MX6ULLothar Waßmann2016-02-281-0/+1
| | | | | | | | | | | | | | | | Add the necessary clock to use the KPP interface on i.MX6UL. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx: whitespace cleanup; no functional changeLothar Waßmann2016-02-281-31/+31
| | | | | | | | | | | | | | | | remove whitespace before TAB. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx: correct pwm7 clock name in driver for i.MX6ULAnatolij Gustschin2016-02-181-1/+1
| | | | | | | | | | | | | | | | Don't capitalize p in the pwm7 clock name. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx: Add clock support for imx6qpBai Ping2016-02-141-27/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | most of the clock tree structures on i.MX6 Quad Plus are same as on i.MX6Q. there still some differences between these two SOCs. compared to the i.XM6Q, the differents of clocks on i.MX6QP is mainly on: 1. New clock gate added to support the PRE and PRG modules 2. 24MHz OSC clock option added to the UART, IPG, ECSPI, and CAN clock roots. 3. MMDC channel 1 clock gate is now controllable. 4. clock gating added to the LDB_DIx_IPU clocks on i.MX6QP 5. EMI clock root divider fix 6. other updates fo CSCMRx, CSCDRx and CS2CDR registers. detailed infomation, please refer to the i.MX6QP RM. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | Merge tag 'sunxi-clocks-for-4.6' of ↵Stephen Boyd2016-03-0214-836/+687
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clk updates from Maxime Ripard: Allwinner clocks additions for 4.6 A bunch of things, mostly: - Finally switched everything over to OF_CLK_DECLARE, which should remove orphans clocks entirely - Reworked the clk-factors to be able to add new parameters - Improved the error reporting - A bunch of new clocks for new SoCs. * tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits) clk: sunxi: Add apb0 gates for H3 clk: sunxi: Improve divs_clk error handling and reporting clk: sunxi: improve divider_clk error handling and reporting clk: sunxi: improve mux_clk error handling and reporting clk: sunxi: Fix sun8i-a23-apb0-clk divider flags clk: sunxi: Remove clk_register_clkdev calls clk: sunxi: Remove old probe and protection code clk: sunxi: convert current clocks registration to CLK_OF_DECLARE clk: sunxi: Make clocks setup functions take const pointer clk: sunxi: Make clocks setup functions return their clock clk: sunxi: improve error reporting for the mux clock clk: sunxi: don't mark sun6i_ar100_data __initconst clk: sunxi: add bus gates for A83T clk: sunxi: Add apb0 gates for A83T clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk clk: sunxi: rewrite sun6i-ar100 using factors clk clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalc clk: sunxi: factors: Drop round_rate from clk ops clk: sunxi: factors: Support custom formulas clk: sunxi: factors: Consolidate get_factors parameters into a struct ...
| * | clk: sunxi: Add apb0 gates for H3Krzysztof Adamski2016-02-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for APB0 in H3. It seems to be compatible with earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR, etc). Since this gates behave just like any Allwinner clock gate, add a generic compatible that can be reused if we don't have any clock to protect. Signed-off-by: Krzysztof Adamski <k@japko.eu> [Maxime: Removed the H3 compatible from the simple-gates driver, reworked the commit log a bit] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: Improve divs_clk error handling and reportingAndre Przywara2016-02-221-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | We catch errors in the base clock registration, failure to ioremap and failures in the final of_clk_add_provider() call. Also we unmap the registers when we need to rollback. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: improve divider_clk error handling and reportingAndre Przywara2016-02-221-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We now report a failing ioremap, failing output names parsing, failures in table registration and in the final step. Also there was a bug where clk_register_divider_table() would return an ERR_PTR value instead of NULL, which we were checking for. We now implement proper rollback in case of an error. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: improve mux_clk error handling and reportingAndre Przywara2016-02-221-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | We now catch and report a failing ioremap, also a failure in the final step of the clock registration is now handled and reported. Also warnings are turned into errors. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: Fix sun8i-a23-apb0-clk divider flagsChen-Yu Tsai2016-02-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The APB0 clock on A23 is a zero-based divider, not a power-of-two based divider. Note that this patch does not apply cleanly to kernels before 4.5-rc1, which added CLK_OF_DECLARE support to this driver. Fixes: 57a1fbf28424 ("clk: sunxi: Add A23 APB0 divider clock support") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: Remove clk_register_clkdev callsMaxime Ripard2016-02-118-19/+4
| | | | | | | | | | | | | | | | | | | | | Now that our protection code doesn't use the global name lookup anymore, we can remove the clkdev registrations. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: Remove old probe and protection codeMaxime Ripard2016-02-111-108/+0
| | | | | | | | | | | | | | | | | | | | | Now that we don't have any user left for the old registration code, we can remove it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: convert current clocks registration to CLK_OF_DECLAREMaxime Ripard2016-02-111-17/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current clock registration and protection code has a few drawbacks, the two main ones being that we create a lot of orphans clock in the registration phase, which will be troublesome when we will start being less relaxed about them. The protection code also relies on clkdev, which we don't really use but for this particular case. Fix both at the same time by moving everyone to the CLK_OF_DECLARE that will probe our clock tree in the right and thus avoid orphans, and by protecting directly the clock returned by our registration function. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: Make clocks setup functions take const pointerMaxime Ripard2016-02-111-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the data structure that we pass to the clocks setup functions are declared const, while our setup functions expects a regular pointer. This was hidden by the fact that we cast a void * pointer back to these structures, which made it go unnoticed. Fix the functions prototype. Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: Make clocks setup functions return their clockMaxime Ripard2016-02-111-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clocks registration code in clk-sunxi was most of the time not returning the struct clk (or struct clk array) that was registered, preventing the users of such functions to manipulate it, for example to protect it. Make them return it so that we can start using it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: improve error reporting for the mux clockAndre Przywara2016-02-021-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_register_mux returns a pointer wrapped error value in case of failure, so a simple NULL check is not sufficient to catch errors. Fix that and elaborate on the failure reason on the way. The whole function does not return any error value, so silently failing may leave users scratching their heads because the kernel does not provide any clues on what's wrong. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: don't mark sun6i_ar100_data __initconstArnd Bergmann2016-02-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clk-sun6i-ar100 clk driver is a platform driver that may use deferred probing, so its probe function must not access __init symbols. Kbuild warns about this: WARNING: drivers/clk/sunxi/built-in.o(.text+0x15f0): Section mismatch in reference from the function sun6i_a31_ar100_clk_probe() to the (unknown reference) .init.rodata:(unknown) The function sun6i_a31_ar100_clk_probe() references the (unknown reference) __initconst (unknown). This is often because sun6i_a31_ar100_clk_probe lacks a __initconst annotation or the annotation of (unknown) is wrong. Removing the __initconst annotation avoids the warning and makes deferred probing work. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 3ca2377b6fed ("clk: sunxi: rewrite sun6i-ar100 using factors clk") Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: add bus gates for A83TVishnu Patekar2016-02-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A83T has similar bus gates that of H3, including single gating register has different clock parent. As per H3 and A83T datasheet, usbhost is under AHB2. However,below shows allwinner source code assignment: bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T. bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3 bits 29, 30, 31(ohci0,1,2) => AHB2 for H3. until, this confusion is cleared keep it H3 way. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: Add apb0 gates for A83TVishnu Patekar2016-02-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | APB0 is part of PRCM, and is compatible with earlier SOCs. apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks. This patch adds support for APB0 gates for A83T. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clkChen-Yu Tsai2016-01-291-45/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very complicated clocks, but is not really needed here. Convert sun8i-a23-mbus-clk to use clk_composite, as it is a gate + mux + divider. This makes the code easier to understand. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: rewrite sun6i-ar100 using factors clkChen-Yu Tsai2016-01-291-174/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | sun6i's AR100 clock is a classic factors clk case: AR100 = ((parent mux) >> p) / (m + 1) Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalcChen-Yu Tsai2016-01-291-208/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | The factors clk implementation has been extended to support custom recalc callbacks to support clocks that use one factor for certain parents only, like a pre-divider. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: factors: Drop round_rate from clk opsChen-Yu Tsai2016-01-291-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The common clock framework requires either determine_rate or round_rate to be implemented. We use determine_rate so we can pass the parent index to the get_factors callback. This cannot be done easily with round_rate, so just drop it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: factors: Support custom formulasChen-Yu Tsai2016-01-292-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some clocks cannot be modelled using the standard factors clk formula, such as clocks with special pre-dividers on one parent, or clocks with all power-of-two dividers. Add support for a custom .recalc callback for factors clk. Also pass the current parent index to the .get_factor and .recalc callbacks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: factors: Consolidate get_factors parameters into a structChen-Yu Tsai2016-01-276-219/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The .get_factors callback of factors_clk has 6 parameters. To extend factors_clk in any way that requires adding parameters to .get_factors would make that list even longer, not to mention changing all the function declarations. Do this once now and consolidate all the parameters into a struct. Also drop the space before function pointer arguments, since checkpatch complains. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: factors: Add unregister functionChen-Yu Tsai2016-01-272-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sunxi's factors clk did not have an unregister function. This means multiple structs were leaked whenever a factors clk was unregistered. Add an unregister function for it. Also keep pointers to the mux and gate structs so they can be freed. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: factors: Add clk cleanup in sunxi_factors_register() error pathChen-Yu Tsai2016-01-271-15/+29
| | | | | | | | | | | | | | | | | | | | | | | | sunxi_factors_register() does not check for failures or cleanup after clk_register_composite() or other clk-related calls. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: factors: Make struct clk_factors_config table constChen-Yu Tsai2016-01-275-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | struct clk_factors_config contains shifts/widths for the factors of the factors clk. This is used to read out the factors from the register value. In no case is it written to, so make it const. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: usb: Sort clk providers by chip family and nameChen-Yu Tsai2016-01-251-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | The latest addition of H3 USB clocks placed them at the bottom. Move it before A80 (sun9i), so they are sorted by SoC family then name. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | clk: sunxi: Drop clk.h includeStephen Boyd2016-01-241-1/+0
| |/ | | | | | | | | | | | | | | | | | | This file is a clock provider, not a clk consumer. Drop the clk.h include. Cc: Jens Kuske <jenskuske@gmail.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | clk: qcom: msm8960: Fix ce3_src register offsetStephen Boyd2016-03-021-1/+1
| | | | | | | | | | | | | | | | | | | | The offset seems to have been copied from the sata clk. Fix it so that enabling the crypto engine source clk works. Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge branch 'clk-ti' into clk-nextMichael Turquette2016-03-026-1/+1050
|\ \ | | | | | | | | | | | | Conflicts: drivers/clk/Kconfig
| * | clk: ti: Fix some errors found by static checkersStephen Boyd2016-03-022-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/clk/ti/clk-814x.c:34:12: warning: symbol 'dm814x_adpll_early_init' was not declared. Should it be static? drivers/clk/ti/clk-814x.c:58:12: warning: symbol 'dm814x_adpll_enable_init_clocks' was not declared. Should it be static? drivers/clk/ti/adpll.c:465 ti_adpll_recalc_rate() warn: should '__readw(d->regs + 20) << 18' be a 64 bit type? drivers/clk/ti/adpll.c:945 ti_adpll_probe() error: we previously assumed 'd->clocks' could be null (see line 921) The last one looks like a real bug because we don't return an error on allocation failure. Cc: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: ti: Allow COMPILE_TEST to build selected driversTony Lindgren2016-03-022-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | The arch independent drivers can be build testeed with COMPILE_TEST. Let's allow that for drivers/clk/ti. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | clk: ti: Add support for dm814x ADPLLTony Lindgren2016-03-025-0/+1045
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The ADPLLs have several dividers and muxes controlled by a shared control register for each PLL. Note that for the clocks to work as device drivers for booting on dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall levels to postcore_initcall" that has already been merged. Also note that this patch does not implement clk_set_rate for the PLL, that will be posted later on when available. Cc: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | clk: qcom: Fix pre-divider usage for pixel RCGArchit Taneja2016-02-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading its current value from the NS register. Using the pre-divider wasn't really intended when creating these ops. The pixel RCG was only intended to achieve fractional multiplication provided in the pixel_table array. Leaving the pre-divider to the existing register value results in a wrong pixel clock when the bootloader sets up the display. This was left unidentified because the IFC6410 Plus board on which this was verified didn't have a bootloader that configured the display. Don't set the RCG pre-divider in freq_tbl to the existing NS register value. Force it to 1 and only use the M/N counter to achieve the desired fractional multiplication. Cc: Vinay Simha <vinaysimha@inforcecomputing.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: h8300: Properly cast to __iomem pointerStephen Boyd2016-02-271-1/+1
| | | | | | | | | | | | | | | | | | | | Sparse complains here because we dropped the __iomem annotation when casting the aligned address. Add __iomem back so that sparse stops complaining. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: <uclinux-h8-devel@lists.sourceforge.jp> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | simplefb: Remove impossible check for of_clk_get_parent_count() < 0Stephen Boyd2016-02-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The check for < 0 is impossible now that of_clk_get_parent_count() returns an unsigned int. Simplify the code and update the types. Cc: Hans de Goede <hdegoede@redhat.com> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: <linux-fbdev@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | usb: dwc3: Remove impossible check for of_clk_get_parent_count() < 0Stephen Boyd2016-02-271-4/+5
| | | | | | | | | | | | | | | | | | | | The check for < 0 is impossible now that of_clk_get_parent_count() returns an unsigned int. Simplify the code and update the types. Acked-by: Felipe Balbi <balbi@kernel.org> Cc: <linux-usb@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: ti: Update for of_clk_get_parent_count() returning unsigned intStephen Boyd2016-02-274-8/+8
| | | | | | | | | | | | | | | | | | | | Change the types here to unsigned int instead of int and update the checks for == 0 instead < 1 to be more explicit about what's going on now that of_clk_get_parent_count() has changed return types. Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: sunxi: Use proper type for of_clk_get_parent_count() return valueStephen Boyd2016-02-271-1/+1
| | | | | | | | | | | | | | | | | | | | The return type of of_clk_get_parent_count() is an unsigned int now, so let's update the code here to be more explicit about the range of values we can test for. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: st: Remove impossible check for of_clk_get_parent_count() < 0Stephen Boyd2016-02-272-4/+4
| | | | | | | | | | | | | | | | | | The checks for < 0 are impossible now that of_clk_get_parent_count() returns an unsigned int. Simplify the code and update the types. Cc: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: h8300: Remove impossible check for of_clk_get_parent_count()Stephen Boyd2016-02-272-4/+4
| | | | | | | | | | | | | | | | | | | | The checks for < 1 can be simplified now that of_clk_get_parent_count() returns an unsigned int. Update the code to reflect the int to unsigned int change. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: <uclinux-h8-devel@lists.sourceforge.jp> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: gpio: Remove impossible check for of_clk_get_parent_count() < 0Stephen Boyd2016-02-271-4/+2
| | | | | | | | | | | | | | | | The check for < 0 is impossible now that of_clk_get_parent_count() returns an unsigned int. Simplify the code and update the type here. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: at91: Remove impossible checks for of_clk_get_parent_count()Stephen Boyd2016-02-277-15/+15
| | | | | | | | | | | | | | | | | | These checks for < 0 are impossible now that of_clk_get_parent_count() returns an unsigned int. Change the checks for == 0 and update the type. Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: Make of_clk_get_parent_count() return unsigned intsStephen Boyd2016-02-271-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Russell King recently pointed out a bug in the clk-gpio code where it fails to register the clk if of_clk_get_parent_count() returns an error because the "clocks" property isn't present in the DT node. If we're trying to count parents from DT we'd like to know the count, not if there is a "clocks" property or not. Furthermore, some drivers are assigning the return value to their clk_init_data::num_parents member which is unsigned, leading to potentially large numbers of parents when the property isn't present. Let's change the API to return an unsigned int instead of an int. All the callers just want to know the count anyway, and this avoids the bug that was in the clk-gpio driver. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: Ignore disabled DT clock providersGeert Uytterhoeven2016-02-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_clk_init() uses for_each_matching_node_and_match() to find clock providers, which returns all matching device nodes, whether they are enabled or not. Hence clock providers that are disabled explicitly in DT using e.g. "status = "disabled"; are still activated. Add a check to ignore device nodes that are not enabled, like of_irq_init() does. Reported-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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