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* pinctrl: tegra: Set specific GPIO compatible stringThierry Reding2019-06-253-3/+3
| | | | | | | | | | | Rather than reuse the nvidia,tegra30-gpio compatible string to find the GPIO controller on Tegra30, Tegra114, Tegra124 and Tegra210, use the most specific compatible string for each SoC generation for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mvebu: Add support for MV98DX1135Chris Packham2019-06-251-279/+297
| | | | | | | | | The 98DX1135 is a switch chip with an integrated CPU. This is similar to the 98DX4122 except the MPP assignments differ. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: freescale: Add i.MX8MN pinctrl driver supportAnson Huang2019-06-253-0/+356
| | | | | | | | Add the pinctrl driver support for i.MX8MN. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Minimize SPDX hamming distanceLinus Walleij2019-06-203-3/+2
| | | | | | | | | | | OK so some automatic scripts were fixing the SPDX tags in the mainline branch while we were patching other stuff, and yeah it is more correct to have "GPL-2.0-only" rather than "GPL-2.0" so let's conform to what is already upstream so we don't end up getting the wrong license on the merged result later. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'ib-qcom-acpi' into develLinus Walleij2019-06-124-2/+55
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| * pinctrl: qcom: sdm845: Provide ACPI supportLee Jones2019-06-122-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides basic support for booting with ACPI instead of the currently supported Device Tree. When doing so there are a couple of differences which we need to taken into consideration. Firstly, the SDM850 ACPI tables omit information pertaining to the 4 reserved GPIOs on the platform. If Linux attempts to touch/ initialise any of these lines, the firmware will restart the platform. Secondly, when booting with ACPI, it is expected that the firmware will set-up things like; Regulators, Clocks, Pin Functions, etc in their ideal configuration. Thus, the possible Pin Functions available to this platform are not advertised when providing the higher GPIOD/Pinctrl APIs with pin information. Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: msm: Add ability for drivers to supply a reserved GPIO listLee Jones2019-06-122-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting MSM based platforms with Device Tree or some ACPI implementations, it is possible to provide a list of reserved pins via the 'gpio-reserved-ranges' and 'gpios' properties respectively. However some ACPI tables are not populated with this information, thus it has to come from a knowledgable device driver instead. Here we provide the MSM common driver with additional support to parse this informtion and correctly populate the widely used 'valid_mask'. Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: remove unused pin_is_valid()Masahiro Yamada2019-06-121-23/+0
| | | | | | | | | | | | | | | | | | | | | | This function was used by pin_request() to pointlessly double-check the pin validity, and it was the only user ever. Since commit d2f6a1c6fb0e ("pinctrl: remove double pin validity check."), no one has ever used it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: remove unneeded initializer for list_for_each_entry() iteratorMasahiro Yamada2019-06-121-4/+4
| | | | | | | | | | | | | | The iterator is initialized in list_for_each_entry(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'sh-pfc-for-v5.3-tag1' of ↵Linus Walleij2019-06-0823-1059/+1245
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.3 - Add more checks for pinctrl table validation, - Add TPU (Timer Pulse Unit / PWM) pin groups on R-Car H3, M3-W, and M3-N, - Rework description of pins without GPIO functionality, - Small fixes and cleanups.
| * | pinctrl: sh-pfc: Remove obsolete SH_PFC_PIN_NAMED*() macrosGeert Uytterhoeven2019-06-041-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now all Renesas pin control drivers have been converted to use the new non-GPIO helper macros, SH_PFC_PIN_NAMED() and SH_PFC_PIN_NAMED_CFG() are no longer used. Remove them. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: sh73a0: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the SH-Mobile AG5 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the SH-Mobile AG5 SoC (in 34x34 BGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: r8a77990: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-46/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car E3 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car E3 SoC (in 25x25 FCBGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: r8a77965: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-156/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car M3-N pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M3-N SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: r8a7796: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-156/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car M3-W pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M3-W SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: r8a7795: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-159/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car H3 ES2.0 and later pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H3 ES2.0 SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: r8a7795-es1: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-170/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car H3 ES1.x pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H3 ES1.x SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: r8a7790: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car H2 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H2 SoC (in 31x31 FCBGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: r8a7778: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-13/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the R-Car M1A pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M1A SoC (in 25x25 FCBGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: emev2: Use new macros for non-GPIO pinsGeert Uytterhoeven2019-06-041-36/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the EMMA Mobile EV2 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the EMMA Mobile EV2 SoC (in 23x23 BGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: Add new non-GPIO helper macrosGeert Uytterhoeven2019-06-041-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new macros for describing pins without GPIO functionality: - NOGP_ALL() expands to a list of PIN_id values, to be used for generating symbolic enum values, - PINMUX_NOGP_ALL() expands to a list of sh_pfc_pin entries, to list all pins and their capabilities. Both macros depend on an SoC-specific CPU_ALL_NOGP() macro, to be provided by each individual SoC pin control driver. The new macros offer two advantages over the existing SH_PFC_PIN_NAMED() and SH_PFC_PIN_NAMED_CFG() macros: 1. They do not rely on PIN_NUMBER() macros and physical pin numbering, hence do not suffer from pin numbering confusion among different SoC/SiP packages. 2. They are similar in spirit to the existing scheme for handling pins with GPIO functionality. Note that internal to the driver, non-GPIO pins use a sequential numbering scheme which starts after the highest GPIO pin number in use. This value is calculated automatically, using two new helper macros, for systems with either 32-port bank (GP port style) or linear (PORT style) pin space. Sample expansion: GP_LAST = sizeof(union { char dummy[0] __attribute__((deprecated, deprecated)); char GP_0_0[(0 * 32) + 0] __attribute__((deprecated, deprecated)); char GP_0_1[(0 * 32) + 1] __attribute__((deprecated, deprecated)); ... char GP_7_3[(7 * 32) + 3] __attribute__((deprecated, deprecated)); }) Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | pinctrl: sh-pfc: r8a7778: Use common PORT_GP_CFG_27() macroGeert Uytterhoeven2019-05-211-17/+1
| | | | | | | | | | | | | | | | | | | | | | | | Get rid of the custom PORT_GP_PUP_27() macro by using the common PORT_GP_CFG_27() macro instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: Add PORT_GP_27 helper macroGeert Uytterhoeven2019-05-211-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | This follows the style of the existing PORT_GP_X macros, and will be used by a follow-up patch for the r8a7778 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a77965: Add TPU pins, groups and functionsGeert Uytterhoeven2019-05-211-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on the R-Car M3-N SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a7796: Add TPU pins, groups and functionsGeert Uytterhoeven2019-05-211-2/+44
| | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on the R-Car M3-W and RZ/G2M SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a7795: Add TPU pins, groups and functionsGeert Uytterhoeven2019-05-211-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on revisions ES2.x and later of the R-Car H3 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a7795-es1: Add TPU pins, groups and functionsGeert Uytterhoeven2019-05-211-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on revision ES1.x of the R-Car H3 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: r8a77970: Remove MMC_{CD,WP}Geert Uytterhoeven2019-05-211-22/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware Manual Errata for rev. 1.50 of March 26, 2019 removed the bit definitions for MMC_CD and MMC_WP in the documentation for the IPSR6 and IPSR7 registers, as these pin functionalities do not exist on R-Car V3M. Remove the definitions, and the corrresponding pins and groups. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
| * | pinctrl: sh-pfc: Move PIN_NONE to shared header fileGeert Uytterhoeven2019-05-217-194/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | | Several drivers have identical definitions for PIN_NONE. Provide a definition with a SH_PFC_ prefix for general use in sh_pfc.h, and convert all drivers over to use it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthandGeert Uytterhoeven2019-05-2110-35/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is very common for a pin to support both pull-up and pull-down functionality. Hence add a shorthand SH_PFC_PIN_CFG_PULL_UP_DOWN. This not only reduces typing, but also avoids the need for several line breaks, and makes many overly long lines shorter, improving readability. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variantGeert Uytterhoeven2019-05-2117-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two variants of the CPU_ALL_PORT() macro in use: 1. A three-parameter variant, to be provided for SoCs with a linear GPIO pin space ("PORT style"), 2. A two-parameter variant, to be provided for SoCs with 32-port GPIO banks ("GP port style"). Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and to increase naming consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: Validate pin tables at runtimeGeert Uytterhoeven2019-05-211-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the run-time debug code with checks to ensure there are no conflicting pin names, numbers, or enumeration values. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: Add check for empty pinmux groups/functionsGeert Uytterhoeven2019-05-211-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinmux groups and functions arrays may contain two parts, to ease supporting SoCs that expose pin subsets of other related SoCs. Both parts need to be declared with explicit sizes, which thus need to be updated when adding support for more groups and functions. If a size is too small, the compiler will detect this at build time ("excess elements in array initializer"). If a size is too large, this may go undetected (for pin groups), lead to pin controller registration failures (for pin functions: "pinmux ops has no name for functionN"), or crash the optional run-time debug code (for pin groups). Extend the run-time debug code with checks to detect this, to help catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: Mark run-time debug code __initGeert Uytterhoeven2019-05-211-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | All run-time debug code is called from sh_pfc_init(), which is __init. Fixes: 6161b39a14380815 ("pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| * | pinctrl: sh-pfc: Correct printk level of group reference warningGeert Uytterhoeven2019-05-211-2/+2
| |/ | | | | | | | | | | | | | | Improve wording while at it. Fixes: 6161b39a14380815 ("pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* | pinctrl: nomadik: Fix SPDX tagsLinus Walleij2019-06-085-17/+6
| | | | | | | | | | | | | | Some files were missing the appropriate SPDX tags so fixed it up. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: tb10x: Use flexible-array member and struct_size() helperGustavo A. R. Silva2019-06-081-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the code to use a flexible array member instead of a pointer in structure tb10x_pinctrl and use the struct_size() helper: struct tb10x_pinctrl { ... struct tb10x_of_pinfunc pinfuncs[]; }; Also, make use of the struct_size() helper instead of an open-coded version in order to avoid any potential type mistakes. So, replace the following form: sizeof(struct tb10x_pinctrl) + of_get_child_count(of_node) * sizeof(struct tb10x_of_pinfunc) with: struct_size(state, pinfuncs, of_get_child_count(of_node)) This code was detected with the help of Coccinelle. Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: aspeed: Add SGPM pinmuxHongwei Zhang2019-06-081-0/+4
| | | | | | | | | | | | | | | | | | Add SGPM pinmux to ast2500-pinctrl function and group, to prepare for supporting SGPIO in AST2500 SoC. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: qcom: sdm845: Expose ufs_reset as gpioBjorn Andersson2019-06-081-6/+6
| | | | | | | | | | | | | | | | | | | | | | The ufs_reset pin is expected to be wired to the reset pin of the primary UFS memory but is pretty much just a general purpose output pinr Reorder the pins and expose it as gpio 150, so that the UFS driver can toggle it. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Add drive strength support for BM1880 SoCManivannan Sadhasivam2019-06-081-3/+287
| | | | | | | | | | | | | | Add drive strength support for Bitmain BM1880 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: ns2: Fix potential NULL dereferenceYoung Xiao2019-06-081-0/+2
| | | | | | | | | | | | | | | | | | | | platform_get_resource() may fail and return NULL, so we should better check it's return value to avoid a NULL pointer dereference a bit later in the code. Signed-off-by: Young Xiao <92siuyang@gmail.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: u300: Fix SPDX tagsLinus Walleij2019-06-082-1/+2
| | | | | | | | | | | | | | Some files were missing the appropriate SPDX tags so fixed it up. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: bcm2835: Fix build error without CONFIG_OFYueHaibing2019-06-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | drivers/pinctrl/bcm/pinctrl-bcm2835.c: In function bcm2835_pctl_dt_node_to_map: drivers/pinctrl/bcm/pinctrl-bcm2835.c:720:8: error: implicit declaration of function pinconf_generic_dt_node_to_map_all; drivers/pinctrl/bcm/pinctrl-bcm2835.c: In function bcm2835_pinctrl_probe: drivers/pinctrl/bcm/pinctrl-bcm2835.c:1022:15: error: struct gpio_chip has no member named of_node pc->gpio_chip.of_node = np; Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 0de704955ee4 ("pinctrl: bcm2835: Add support for generic pinctrl binding") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: stm32: Add links to consumersLinus Walleij2019-06-011-0/+1
| | | | | | | | | | | | | | | | | | | | Using STM32 as guinea pig after Alex's initial positive test to see if this is something we should encourage in general and make default behaviour. Cc: Benjamin Gaignard <benjamin.gaignard@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mediatek: mt8183: Add pm_opsNicolas Boichat2019-06-011-0/+1
| | | | | | | | | | | | | | | | | | | | Setting this up will configure wake from suspend properly, and wake only for the interrupts that are setup in wake_mask, not all interrupts. Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Acked-by: Sean Wang <sean.wang@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: mediatek: Add pm_ops to pinctrl-parisNicolas Boichat2019-06-012-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pinctrl variants that include pinctrl-paris.h (and not pinctrl-mtk-common.h) also need to use pm_ops to setup wake mask properly, so copy over the pm_ops from common to paris variant. It is not easy to merge the 2 copies (or move mtk_eint_suspend/resume to mtk-eint.c), as we need to dereference pctrl->eint, and struct mtk_pinctrl *pctl has a different structure definition for v1 and v2 (which is what paris variant uses). Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Acked-by: Sean Wang <sean.wang@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: meson: update with SPDX Licence identifierNeil Armstrong2019-06-018-56/+8
| | | | | | | | | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: tegra: Add Tegra194 pinmux driverKrishna Yarlagadda2019-06-013-0/+175
| | | | | | | | | | | | | | | | | | | | | | | | Tegra194 has PCIE L5 rst and clkreq pins which need to be controlled dynamically at runtime. This driver supports change pinmux for these pins. Pinmux for rest of the pins is set statically by bootloader and will not be changed by this driver Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com> Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: tegra: Support 32 bit register accessKrishna Yarlagadda2019-06-012-8/+8
| | | | | | | | | | | | | | | | | | | | Tegra194 chip has 32 bit pinctrl registers. Existing register defines in header are only 16 bit. Modified common pinctrl-tegra driver to support 32 bit registers of Tegra 194 and later chips. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | pinctrl: Add pinconf support for BM1880 SoCManivannan Sadhasivam2019-05-241-0/+134
| | | | | | | | | | | | | | | | | | Add pinconf support for Bitmain BM1880 SoC. Pinconf support includes pin bias, slew rate and schmitt trigger. Drive strength support will be added later. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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