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* drm/i915: Serialise updates to GGTT with access through GGTT on BraswellChris Wilson2015-11-172-0/+25
* drm/i915: force link training when requested by SinkShubhangi Shrivastava2015-11-171-1/+3
* drm/i915: Cleanup test data during long/short hotplugShubhangi Shrivastava2015-11-171-8/+22
* drm/i915/skl: Correct other-pipe watermark update condition check (v2)Kumar, Mahesh2015-11-171-7/+5
* drm/i915: Model PSR AUX register selection more like the normal AUX codeVille Syrjälä2015-11-161-6/+21
* drm/i915: Add dev_priv->psr_mmio_baseVille Syrjälä2015-11-164-21/+27
* drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]Ville Syrjälä2015-11-162-10/+85
* drm/i915: Remove the magic AUX_CTL is at DP + foo tricksVille Syrjälä2015-11-162-76/+105
* drm/i915: Parametrize AUX registersVille Syrjälä2015-11-163-63/+62
* drm/i915: Replace the aux ddc name switch statement with kasprintf()Ville Syrjälä2015-11-161-29/+46
* drm/i915: Replace aux_ch_ctl_reg check with port checkVille Syrjälä2015-11-161-1/+1
* drm/i915/skl: Update DDI translation tables for SKLjim.bride@linux.intel.com2015-11-131-11/+11
* drm/i915: Fix SKL i_boost levelAnder Conselvan de Oliveira2015-11-131-3/+3
* drm/i915/skl: Removed assert for csr-fw-loading check during disabling dc6Animesh Manna2015-11-121-1/+0
* drm/i915/gen9: flush DMC fw loading work during system suspendImre Deak2015-11-121-0/+3
* drm/i915/gen9: Use flush_work to synchronize with dmc loaderAnimesh Manna2015-11-122-2/+2
* drm/i915: Use request_firmware and our own async workDaniel Vetter2015-11-122-13/+14
* drm/i915/gen9: extract parse_csr_fwDaniel Vetter2015-11-121-19/+31
* drm/i915/gen9: Use dev_priv in csr functionsDaniel Vetter2015-11-124-24/+18
* drm/i915/gen9: Don't try to load garbage dmc firmware on resumeDaniel Vetter2015-11-121-1/+1
* drm/i915/gen9: Simplify csr loading failure printing.Daniel Vetter2015-11-123-23/+4
* drm/i915/gen9: Align line continuations in intel_csr.c.Daniel Vetter2015-11-121-15/+15
* drm/i915/gen9: Remove csr.state, csr_lock and related code.Daniel Vetter2015-11-126-83/+5
* drm/i915/gen9: move assert_csr_loaded into intel_rpm.cDaniel Vetter2015-11-123-11/+8
* drm/i915: use correct power domain for csr loadingDaniel Vetter2015-11-121-2/+2
* drm/i915/gen9: csr_init after runtime pm enableAnimesh Manna2015-11-121-3/+2
* drm/i915: refactor stepping info retrievalJani Nikula2015-11-121-23/+23
* drm/i915: constify bxt stepping infoJani Nikula2015-11-121-1/+1
* drm/i915: fix indentation on skl stepping infoJani Nikula2015-11-121-3/+3
* drm/i915: Remove redundant check in i915_gem_obj_to_vmaTvrtko Ursulin2015-11-121-4/+2
* drm/i915: Clean up LVDS register handling harderLukas Wunner2015-11-111-2/+1
* drm/i915: Move the fbdev async_schedule() into intel_fbdev.cVille Syrjälä2015-11-113-5/+9
* drm/i915: Do fbdev fini first during unloadVille Syrjälä2015-11-111-2/+2
* drm/i915: Kill intel_runtime_pm_disable()Ville Syrjälä2015-11-111-17/+0
* drm/i915: Setup DDI clk for MST on SKLVille Syrjälä2015-11-103-27/+32
* drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on()Ville Syrjälä2015-11-101-26/+19
* drm/i915: Use intel_dp->DP in eDP PLL setupVille Syrjälä2015-11-101-27/+14
* drm/i915: Clean up eDP PLL state assertsVille Syrjälä2015-11-101-15/+39
* drm/i915: Remove ILK-A eDP PLL workaround notesVille Syrjälä2015-11-101-4/+0
* drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/Ville Syrjälä2015-11-102-6/+6
* drm/i915: Hide underruns from eDP PLL and port enable on ILKVille Syrjälä2015-11-101-3/+31
* drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaroundVille Syrjälä2015-11-104-0/+42
* drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder()Ville Syrjälä2015-11-101-1/+1
* drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPTVille Syrjälä2015-11-103-31/+103
* drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabledVille Syrjälä2015-11-101-0/+13
* drm/i915: Enable PCH FIFO underruns later on HSW+Ville Syrjälä2015-11-101-7/+9
* drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVBVille Syrjälä2015-11-101-4/+8
* drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTLVille Syrjälä2015-11-101-2/+4
* drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config...Ville Syrjälä2015-11-101-5/+2
* drm/i915: remove in_dbg_master check from intel_fbc.cPaulo Zanoni2015-11-101-6/+0
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