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* Merge tag 'mxs-clk-dt-lookup' of ↵Olof Johansson2012-09-132-148/+20
|\ | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt It replaces clk_register_clkdev in mxs clock driver with DT lookup. * tag 'mxs-clk-dt-lookup' of git://git.linaro.org/people/shawnguo/linux-2.6: clk: mxs: replace imx23 clk_register_clkdev with clock DT lookup clk: mxs: replace imx28 clk_register_clkdev with clock DT lookup
| * clk: mxs: replace imx23 clk_register_clkdev with clock DT lookupShawn Guo2012-09-111-45/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | It really becomes a maintenance issue that every time a device needs to look up (clk_get) a clock we have to patch kernel clock file to call clk_register_clkdev for that clock. Since clock DT support which is meant to resolve clock lookup in device tree is in place, the patch moves imx23 client devices' clock lookup over to device tree, so that any new lookup to be added at later time can just get done in DT instead of kernel. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * clk: mxs: replace imx28 clk_register_clkdev with clock DT lookupShawn Guo2012-09-111-103/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | It really becomes a maintenance issue that every time a device needs to look up (clk_get) a clock we have to patch kernel clock file to call clk_register_clkdev for that clock. Since clock DT support which is meant to resolve clock lookup in device tree is in place, the patch moves imx28 client devices' clock lookup over to device tree, so that any new lookup to be added at later time can just get done in DT instead of kernel. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | Merge branch 'clk-3.7' of git://git.linaro.org/people/mturquette/linux into ↵Olof Johansson2012-09-1325-21/+4301
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/dt * 'clk-3.7' of git://git.linaro.org/people/mturquette/linux: clk: add of_clk_src_onecell_get() support clk: ux500: Define smp_twd clock for u8500 mfd: dbx500: Provide a more accurate smp_twd clock clk: ux500: Support for prmcu_rate clock clk: Provide option for clk_get_rate to issue hw for new rate clock: max77686: Add driver for Maxim 77686 32Khz crystal oscillator. ARM: ux500: Switch to use common clock framework clk: ux500: Clock definitions for u8500 clk: ux500: First version of clock definitions for ux500 clk: ux500: Adapt PRCMU and PRCC clocks for common clk clk: versatile: make config option boolean clk: add Loongson1B clock support arm: mmp: make all SOCs use common clock by default clk: mmp: add clock definition for mmp2 clk: mmp: add clock definition for pxa910 clk: mmp: add clock definition for pxa168 clk: mmp: add mmp specific clocks clk: convert ARM RealView to common clk clk: prima2: move from arch/arm/mach to drivers/clk ARM: PRIMA2: convert to common clk and finish full clk tree
| * | clk: add of_clk_src_onecell_get() supportShawn Guo2012-09-081-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For those SoCs that have hundreds of clock outputs, their clock DT bindings could reasonably define #clock-cells as 1 and require the client device specify the index of the clock it consumes in the cell of its "clocks" phandle. Add a generic of_clk_src_onecell_get() function for this purpose. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: ux500: Define smp_twd clock for u8500Ulf Hansson2012-09-071-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | The smp_twd clock is based upon a prcmu_rate clock type for the PRCMU_ARMSS clock. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | mfd: dbx500: Provide a more accurate smp_twd clockMichel Jaouen2012-09-072-1/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The local timer clock is based on ARM subsystem clock. This patch obtains a more exact value of that clock by reading PRCMU registers. Using this increases the accuracy of the local timer events. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Rickard Andersson <rickard.andersson@stericsson.com> Signed-off-by: Michel Jaouen <michel.jaouen@stericsson.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: ux500: Support for prmcu_rate clockUlf Hansson2012-09-072-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | The prmcu_rate clock is not gateable and has a rate which only can be fetched. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: Provide option for clk_get_rate to issue hw for new rateUlf Hansson2012-09-071-19/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | By using CLK_GET_RATE_NOCACHE flag, we tell the clk_get_rate API to issue the hw for an updated clock rate. This can be used for a clock which rate may be updated without a client necessary modifying it. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clock: max77686: Add driver for Maxim 77686 32Khz crystal oscillator.Jonghwa Lee2012-09-073-0/+251
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports max77686 mfd's clock driver using common clock frame work. max77686 has 3 clock ouputs which all are generated from crystal oscillator and SOC can enable/disable them via I2C bus. All clocks are fixed-rate clock sources so that it doesn't supply interface for changing clock rate. Driver uses regmap API to communicate with internal register. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | ARM: ux500: Switch to use common clock frameworkUlf Hansson2012-09-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove machine specific clock implementation and switch to use new common clock framework. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: ux500: Clock definitions for u8500Ulf Hansson2012-09-071-1/+453
| | | | | | | | | | | | | | | | | | | | | | | | | | | First version of clock definitions of PRCMU and PRCC clocks for the u8500 platform. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: ux500: First version of clock definitions for ux500Ulf Hansson2012-09-074-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | In this first version of the clock definitions, the structure for ux500 are set. Support for u8500, u9540 and u8540 are prepared. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: ux500: Adapt PRCMU and PRCC clocks for common clkUlf Hansson2012-09-074-0/+452
| | | | | | | | | | | | | | | | | | | | | | | | | | | First version of common clock implementation of PRCMU clocks and PRCC clocks for ux500 platforms. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: versatile: make config option booleanLinus Walleij2012-09-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is no choice to have the RealView clocks as module for sure, so turn this config option into a boolean. Reported-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: add Loongson1B clock supportKelvin Cheung2012-08-312-0/+112
| | | | | | | | | | | | | | | | | | | | | | | | This adds clock support to Loongson1B SoC using the common clock infrastructure. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: mmp: add clock definition for mmp2Chao Xie2012-08-282-0/+450
| | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize the clocks for mmp2 Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: mmp: add clock definition for pxa910Chao Xie2012-08-282-0/+321
| | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize the clocks for pxa910 Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: mmp: add clock definition for pxa168Chao Xie2012-08-282-0/+348
| | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize the clocks for pxa168 Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: mmp: add mmp specific clocksChao Xie2012-08-286-0/+445
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add mmp specific clocks including apbc cloks, apmu clocks, and pll2, fraction clocks Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: convert ARM RealView to common clkLinus Walleij2012-08-254-1/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts the ARM RealView machine over to using the common clock. The approach is similar to the one used for the Integrator, and we're reusing the ICST wrapper code. We have to put the clock intialization in the timer init function for the clocks to be available when initializing the timer, keeping them in early_init() is too early for the common clk. Since we now have to go down and compile drivers/clk/versatile a CONFIG_COMMON_CLK_VERSATILE symbol has been added so the proper code gets compiled into the kernel for either machine. A leftover CLK_VERSATILE in the Integrator Kconfig was fixed up to use the new symbol as well. Tested on ARM RealView PB1176. Cc: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: prima2: move from arch/arm/mach to drivers/clkBarry Song2012-08-242-0/+1172
| | | | | | | | | | | | | | | | | | Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | Merge branch 'pinmux-dt' of ↵Olof Johansson2012-09-0642-203/+379
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel into next/dt This branch enables device tree bindings for the CSR Prima pin control subsystem. All patches acked by Linus W (pinctrl maintainer). * 'pinmux-dt' of git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel: pinctrl: sirf: add DT-binding pinmux mapping support ARM: PRIMA2: rename prima2-cb.dts to prima2.dtsi as it only has SoC features ARM: PRIMA2: add missing interrupts property for pinctrl node + sync to Linux 3.6-rc4
| * | | pinctrl: sirf: add DT-binding pinmux mapping supportBarry Song2012-09-051-1/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes us possible to define pinmux mapping in board-specific DTS. prima2.dtsi provides all possible (groups,functions) configuration, and device in .dts select configurations from dtsi files. Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge branch 'for-linus' of ↵Linus Torvalds2012-09-012-6/+3
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux Pull s390 fixes from Martin Schwidefsky: "A couple of s390 bug fixes for 3.5-rc4" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: s390/32: Don't clobber personality flags on exec s390/smp: add missing smp_store_status() for !SMP s390/dasd: fix ioctl return value s390: Always use "long" for ssize_t to match size_t
| | * | | s390/dasd: fix ioctl return valueHeiko Carstens2012-08-282-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For unimplemented ioctls the dasd driver should return -ENOTTY. Reported-by: Wanlong Gao <gaowanlong@cn.fujitsu.com> Acked-by: Stefan Weinhuber <wein@de.ibm.com> Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
| * | | | Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds2012-08-3016-123/+169
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull drm fixes from Dave Airlie: "A bunch of scattered fixes ati/intel/nouveau, couple of core ones, nothing too shocking or different." * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm: Add EDID_QUIRK_FORCE_REDUCED_BLANKING for ASUS VW222S gma500: Consider CRTC initially active. drm/radeon: fix dig encoder selection on DCE61 drm/radeon: fix double free in radeon_gpu_reset drm/radeon: force dma32 to fix regression rs4xx,rs6xx,rs740 drm/radeon: rework panel mode setup drm/radeon/atom: powergating fixes for DCE6 drm/radeon/atom: rework DIG modesetting on DCE3+ drm/radeon: don't disable plls that are in use by other crtcs drm/radeon: add proper checking of RESOLVE_BOX command for r600-r700 drm/radeon: initialize tracked CS state drm/radeon: fix reading CB_COLORn_MASK from the CS drm/nvc0/copy: check PUNITS to determine which copy engines are disabled i915: Quirk no_lvds on Gigabyte GA-D525TUD ITX motherboard drm/i915: Use the correct size of the GTT for placing the per-process entries drm: Check for invalid cursor flags drm: Initialize object type when using DRM_MODE() macro drm/i915: fix color order for BGR formats on IVB drm/i915: fix wrong order of parameters in port checking functions
| | * | | | drm: Add EDID_QUIRK_FORCE_REDUCED_BLANKING for ASUS VW222SPaul Menzel2012-08-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Connecting an ASUS VW222S [1] over VGA a garbled screen is shown with vertical stripes in the top half. In commit bc42aabc [2] commit bc42aabc6a01b92b0f961d65671564e0e1cd7592 Author: Adam Jackson <ajax@redhat.com> Date: Wed May 23 16:26:54 2012 -0400 drm/edid/quirks: ViewSonic VA2026w Adam Jackson added the quirk `EDID_QUIRK_FORCE_REDUCED_BLANKING` which is also needed for this ASUS monitor. All log files and output from `xrandr` is included in the referenced Bugzilla report #17629. Please note that this monitor only has a VGA (D-Sub) connector [1]. [1] http://www.asus.com/Display/LCD_Monitors/VW222S/ [2] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commit;h=bc42aabc6a01b92b0f961d65671564e0e1cd7592 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=17629 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Cc: <dri-devel@lists.freedesktop.org> Cc: Adam Jackson <ajax@redhat.com> Cc: Ian Pilcher <arequipeno@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
| | * | | | Merge branch 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2012-08-308-111/+141
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-fixes Alex writes: Highlights: - fix a gart regression on older IGP chips - more MSAA fixes - fix a double free in gpu reset code - modesetting fixes - trinity dig encoder fix. * 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: fix dig encoder selection on DCE61 drm/radeon: fix double free in radeon_gpu_reset drm/radeon: force dma32 to fix regression rs4xx,rs6xx,rs740 drm/radeon: rework panel mode setup drm/radeon/atom: powergating fixes for DCE6 drm/radeon/atom: rework DIG modesetting on DCE3+ drm/radeon: don't disable plls that are in use by other crtcs drm/radeon: add proper checking of RESOLVE_BOX command for r600-r700 drm/radeon: initialize tracked CS state drm/radeon: fix reading CB_COLORn_MASK from the CS
| | | * | | | drm/radeon: fix dig encoder selection on DCE61Alex Deucher2012-08-301-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Was using the DCE41 code which was wrong. Fixes blank displays on a number of Trinity systems. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| | | * | | | drm/radeon: fix double free in radeon_gpu_resetChristian König2012-08-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | radeon_ring_restore is freeing the memory for the saved ring data. We need to remember that, otherwise we try to restore the ring data again on the next try. Additional to that it shouldn't try the reset infinitely if we have saved ring data. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| | | * | | | drm/radeon: force dma32 to fix regression rs4xx,rs6xx,rs740Jerome Glisse2012-08-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems some of those IGP dislike non dma32 page despite what documentation says. Fix regression since we allowed non dma32 pages. It seems it only affect some revision of those IGP chips as we don't know which one just force dma32 for all of them. https://bugzilla.redhat.com/show_bug.cgi?id=785375 Signed-off-by: Jerome Glisse <jglisse@redhat.com> Cc: <stable@vger.kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | | * | | | drm/radeon: rework panel mode setupAlex Deucher2012-08-291-17/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the panel mode setup to match the behavior of the vbios. Rather than checking for specific bridge chip ids, just check the eDP configuration register. This saves extra aux transactions and works across DP bridge chips without requiring additional per chip id checking. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | | * | | | drm/radeon/atom: powergating fixes for DCE6Alex Deucher2012-08-291-20/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Power gating is per crtc pair, but the powergating registers should be called individually. The hw handles power up/down properly. The pair is powered up if either crtc in the pair is powered up and the pair is not powered down until both crtcs in the pair are powered down. This simplifies programming and should save additional power as the previous code never actually power gated the crtc pair. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| | | * | | | drm/radeon/atom: rework DIG modesetting on DCE3+Alex Deucher2012-08-291-62/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ordering is important and the current drm code wasn't cutting it for modern DIG encoders. We need to have information about crtc before setting up the encoders so I've shifted the ordering a bit. Probably we'll need a full rework akin to danvet's recent intel patchs. This patch fixes numerous issues with DP bridge chips and makes link training much more reliable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| | | * | | | drm/radeon: don't disable plls that are in use by other crtcsAlex Deucher2012-08-291-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some plls are shared for DP. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
| | | * | | | drm/radeon: add proper checking of RESOLVE_BOX command for r600-r700Marek Olšák2012-08-294-4/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Checking of the second colorbuffer was skipped on r700, because CB_TARGET_MASK was 0xf. With r600, CB_TARGET_MASK is changed to 0xff, so we must set the number of samples of the second colorbuffer to 1 in order to pass the CS checker. The DRM version is bumped, because RESOLVE_BOX is always rejected without this fix on r600. Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | | * | | | drm/radeon: initialize tracked CS stateMarek Olšák2012-08-291-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should help catch uninitialized registers and reject commands because of that. Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | | * | | | drm/radeon: fix reading CB_COLORn_MASK from the CSMarek Olšák2012-08-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | | | gma500: Consider CRTC initially active.Forest Bond2012-08-301-0/+3
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [this one ideally should make 3.6 - it fixes the very annoying mode setting bug] This causes the pipe to be forced off prior to initial mode set, which roughly mirrors the behavior of the i915 driver. It fixes initial mode setting on my Intel DN2800MT (Cedarview) board. Without it, mode setting triggers an out-of-range error from the monitor for most modes, but only on initial configuration (i.e. they can be configured successfully from userspace after that). Signed-off-by: Forest Bond <forest.bond@rapidrollout.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
| | * | | | Merge branch 'drm-intel-fixes' of ↵Dave Airlie2012-08-294-9/+17
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~danvet/drm-intel into drm-fixes Daniel writes: "Just a few smaller things: - Fix up a pipe vs. plane confusion from a refactoring, fixes a regression from 3.1 (Anhua Xu). - Fix ivb sprite pixel formats (Vijay). - Fixup ppgtt pde placement for machines where the Bios artifically limits the availbale gtt space in the name of ... product differentiation (Chris). This fixes an oops. - Yet another no_lvds quirk entry." * 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: i915: Quirk no_lvds on Gigabyte GA-D525TUD ITX motherboard drm/i915: Use the correct size of the GTT for placing the per-process entries drm/i915: fix color order for BGR formats on IVB drm/i915: fix wrong order of parameters in port checking functions
| | | * | | | i915: Quirk no_lvds on Gigabyte GA-D525TUD ITX motherboardCalvin Walton2012-08-241-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is incorrectly detected as having an LVDS connector, resulting in the VGA output (the only available output on the board) showing the console only in the top-left 1024x768 pixels, and an extra LVDS connector appearing in X. It's a desktop Mini-ITX board using an Atom D525 CPU with an NM10 chipset. I've had this board for about a year, but this is the first time I noticed the issue because I've been running it headless for most of its life. Signed-off-by: Calvin Walton <calvin.walton@kepstin.ca>
| | | * | | | drm/i915: Use the correct size of the GTT for placing the per-process entriesChris Wilson2012-08-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current layout is to place the per-process tables at the end of the GTT. However, this is currently using a hardcoded maximum size for the GTT and not taking in account limitations imposed by the BIOS. Use the value for the total number of entries allocated in the table as provided by the configuration registers. Reported-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Matthew Garret <mjg@redhat.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | | * | | | drm/i915: fix color order for BGR formats on IVBVijay Purushothaman2012-08-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is already fixed for ILK and SNB in the below commit but somehow IVB is missed. commit ab2f9df10dd955f1fc0a8650e377588c98f1c029 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Mon Feb 27 12:40:10 2012 -0800 drm/i915: fix color order for BGR formats on SNB Had the wrong bits and field definitions. Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | | * | | | drm/i915: fix wrong order of parameters in port checking functionsXu, Anhua2012-08-231-6/+6
| | | | |/ / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wrong order of parameters passed-in when calling hdmi/adpa /lvds_pipe_enabled(), 2nd and 3rd parameters are reversed. This bug was indroduced by commit 1519b9956eb4b4180fa3f47c73341463cdcfaa37 Author: Keith Packard <keithp@keithp.com> Date: Sat Aug 6 10:35:34 2011 -0700 drm/i915: Fix PCH port pipe select in CPT disable paths The reachable tag for this commit is v3.1-rc1-3-g1519b99 Signed-off-by: Anhua Xu <anhua.xu@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44876 Tested-by: Daniel Schroeder <sec@dschroeder.info> Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | * | | | Merge branch 'drm-nouveau-fixes' of ↵Dave Airlie2012-08-291-2/+4
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-fixes Ben says its just a single fix to avoid the wrong pcopy units being used. * 'drm-nouveau-fixes' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nvc0/copy: check PUNITS to determine which copy engines are disabled
| | | * | | | drm/nvc0/copy: check PUNITS to determine which copy engines are disabledBen Skeggs2012-08-291-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some Fermi chipsets (NVCE particularly) PCOPY1 doesn't exist. And if what I've seen on Kepler is true of Fermi too, chipsets of the same type can have different PCOPY units available. This should fix a v3.5 regression reported by a number of people effecting suspend/resume on NVC8/NVCE chipsets. Cc: stable@vger.kernel.org [3.5] Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| | * | | | | drm: Check for invalid cursor flagsJakob Bornecrantz2012-08-241-1/+1
| | | |/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jakob Bornecrantz <jakob@vmware.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | | | | watchdog: da9052: Remove duplicate inclusion of delay.hSachin Kamat2012-08-291-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | delay.h header file was included twice. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| * | | | | Merge tag 'hwmon-for-linus' of ↵Linus Torvalds2012-08-261-0/+6
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging Pull a hwmon fix from Guenter Roeck: "Fix sensor readings for Asus M5A78L in asus_atk0110 driver." * tag 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging: hwmon: (asus_atk0110) Add quirk for Asus M5A78L
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-29 18:24:18 +0100