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* Merge tag 'upstream-5.2-rc1' of ↵Linus Torvalds2019-05-131-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/rw/ubifs Pull UBI/UBIFS updates from Richard Weinberger: - fscrypt framework usage updates - One huge fix for xattr unlink - Cleanup of fscrypt ifdefs - Fix for our new UBIFS auth feature * tag 'upstream-5.2-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/rw/ubifs: ubi: wl: Fix uninitialized variable ubifs: Drop unnecessary setting of zbr->znode ubifs: Remove ifdefs around CONFIG_UBIFS_ATIME_SUPPORT ubifs: Remove #ifdef around CONFIG_FS_ENCRYPTION ubifs: Limit number of xattrs per inode ubifs: orphan: Handle xattrs like files ubifs: journal: Handle xattrs like files ubifs: find.c: replace swap function with built-in one ubifs: Do not skip hash checking in data nodes ubifs: work around high stack usage with clang ubifs: remove unused function __ubifs_shash_final ubifs: remove unnecessary #ifdef around fscrypt_ioctl_get_policy() ubifs: remove unnecessary calls to set up directory key
| * ubi: wl: Fix uninitialized variableGustavo A. R. Silva2019-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | There is a potential execution path in which variable *err* is compared against UBI_IO_BITFLIPS without being properly initialized previously. Fix this by initializing variable *err* to 0. Addresses-Coverity-ID: 1477298 "(Uninitialized scalar variable") Fixes: 663586c0a892 ("ubi: Expose the bitrot interface") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Richard Weinberger <richard@nod.at>
* | Merge tag 'mtd/for-5.2' of ↵Linus Torvalds2019-05-1287-2544/+4132
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Richard Weinberger: "MTD core changes: - New AFS partition parser - Update MAINTAINERS entry - Use of fall-throughs markers NAND core changes: - Support having the bad block markers in either the first, second or last page of a block. The combination of all three location is now possible. - Constification of NAND_OP_PARSER(_PATTERN) elements. - Generic NAND DT bindings changed to yaml format (can be used to check the proposed bindings. First platform to be fully supported: sunxi. - Stopped using several legacy hooks. - Preparation to use the generic NAND layer with the addition of several helpers and the removal of the struct nand_chip from generic functions. - Kconfig cleanup to prepare the introduction of external ECC engines support. - Fallthrough comments. - Introduction of the SPI-mem dirmap API for SPI-NAND devices. Raw NAND controller drivers changes: - nandsim: - Switch to ->exec-op(). - meson: - Misc cleanups and fixes. - New OOB layout. - Sunxi: - A23/A33 NAND DMA support. - Ingenic: - Full reorganization and cleanup. - Clear separation between NAND controller and ECC engine. - Support JZ4740 an JZ4725B. - Denali: - Clear controller/chip separation. - ->exec_op() migration. - Various cleanups. - fsl_elbc: - Enable software ECC support. - Atmel: - Sam9x60 support. - GPMI: - Introduce the GPMI_IS_MXS() macro. - Various trivial/spelling/coding style fixes. SPI NOR core changes: - Print all JEDEC ID bytes on error - Fix comment of spi_nor_find_best_erase_type() - Add region locking flags for s25fl512s SPI NOR controller drivers changes: - intel-spi: - Avoid crossing 4K address boundary on read/write - Add support for Intel Comet Lake SPI serial flash" * tag 'mtd/for-5.2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (120 commits) mtd: part: fix incorrect format specifier for an unsigned long long mtd: lpddr_cmds: Mark expected switch fall-through mtd: phram: Mark expected switch fall-throughs mtd: cfi_cmdset_0002: Mark expected switch fall-throughs mtd: cfi_util: mark expected switch fall-throughs MAINTAINERS: MTD Git repository is hosted on kernel.org MAINTAINERS: Update jffs2 entry mtd: afs: add v2 partition parsing mtd: afs: factor the IIS read into partition parser mtd: afs: factor footer parsing into the v1 part parsing mtd: factor out v1 partition parsing mtd: afs: simplify partition detection mtd: afs: simplify partition parsing mtd: partitions: Add OF support to AFS partitions mtd: partitions: Add AFS partitions DT bindings mtd: afs: Move AFS partition parser to parsers subdir mtd: maps: Make uclinux_ram_map static mtd: maps: Allow MTD_PHYSMAP with MTD_RAM MAINTAINERS: Add myself as MTD maintainer MAINTAINERS: Remove my name from the MTD and NAND entries ...
| * | mtd: part: fix incorrect format specifier for an unsigned long longColin Ian King2019-05-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An unsigned long long is being formatted with %lld instead of the unsigned version %llu. Fix this. Clean up cppcheck warning: %lld in format string (no. 1) requires 'long long' but the argument type is 'unsigned long long'. Fixes: a62c24d75529 ("mtd: part: Add sysfs variable for offset of partition") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: lpddr_cmds: Mark expected switch fall-throughGustavo A. R. Silva2019-05-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/mtd/lpddr/lpddr_cmds.c: In function ‘chip_ready’: drivers/mtd/lpddr/lpddr_cmds.c:319:6: warning: this statement may fall through [-Wimplicit-fallthrough=] if (mode == FL_READY && chip->oldstate == FL_READY) ^ drivers/mtd/lpddr/lpddr_cmds.c:322:2: note: here default: ^~~~~~~ Warning level 3 was used: -Wimplicit-fallthrough=3 This patch is part of the ongoing efforts to enabling -Wimplicit-fallthrough. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: phram: Mark expected switch fall-throughsGustavo A. R. Silva2019-05-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/mtd/devices/phram.c: In function ‘parse_num64’: drivers/mtd/devices/phram.c:149:11: warning: this statement may fall through [-Wimplicit-fallthrough=] shift += 10; ~~~~~~^~~~~ drivers/mtd/devices/phram.c:150:4: note: here case 'M': ^~~~ drivers/mtd/devices/phram.c:151:11: warning: this statement may fall through [-Wimplicit-fallthrough=] shift += 10; ~~~~~~^~~~~ drivers/mtd/devices/phram.c:152:4: note: here case 'k': ^~~~ Warning level 3 was used: -Wimplicit-fallthrough=3 This patch is part of the ongoing efforts to enabling -Wimplicit-fallthrough. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: cfi_cmdset_0002: Mark expected switch fall-throughsGustavo A. R. Silva2019-05-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/mtd/chips/cfi_cmdset_0002.c: In function ‘get_chip’: drivers/mtd/chips/cfi_cmdset_0002.c:870:6: warning: this statement may fall through [-Wimplicit-fallthrough=] if (mode == FL_READY && chip->oldstate == FL_READY) ^ drivers/mtd/chips/cfi_cmdset_0002.c:873:2: note: here default: ^~~~~~~ drivers/mtd/chips/cfi_cmdset_0002.c: In function ‘cfi_amdstd_sync’: drivers/mtd/chips/cfi_cmdset_0002.c:2745:16: warning: this statement may fall through [-Wimplicit-fallthrough=] chip->state = FL_SYNCING; ~~~~~~~~~~~~^~~~~~~~~~~~ drivers/mtd/chips/cfi_cmdset_0002.c:2750:3: note: here case FL_SYNCING: ^~~~ Warning level 3 was used: -Wimplicit-fallthrough=3 This patch is part of the ongoing efforts to enabling -Wimplicit-fallthrough. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by: Tokunori Ikegami <ikegami.t@gmail.com> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: cfi_util: mark expected switch fall-throughsGustavo A. R. Silva2019-05-061-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/mtd/chips/cfi_util.c: In function ‘cfi_build_cmd’: drivers/mtd/chips/cfi_util.c:110:10: warning: this statement may fall through [-Wimplicit-fallthrough=] onecmd |= (onecmd << (chip_mode * 32)); ~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/chips/cfi_util.c:112:2: note: here case 4: ^~~~ drivers/mtd/chips/cfi_util.c:113:10: warning: this statement may fall through [-Wimplicit-fallthrough=] onecmd |= (onecmd << (chip_mode * 16)); ~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/chips/cfi_util.c:114:2: note: here case 2: ^~~~ drivers/mtd/chips/cfi_util.c: In function ‘cfi_merge_status’: drivers/mtd/chips/cfi_util.c:163:7: warning: this statement may fall through [-Wimplicit-fallthrough=] res |= (onestat >> (chip_mode * 32)); ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/chips/cfi_util.c:165:2: note: here case 4: ^~~~ drivers/mtd/chips/cfi_util.c:166:7: warning: this statement may fall through [-Wimplicit-fallthrough=] res |= (onestat >> (chip_mode * 16)); ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/chips/cfi_util.c:167:2: note: here case 2: ^~~~ Warning level 3 was used: -Wimplicit-fallthrough=3 This patch is part of the ongoing efforts to enabling -Wimplicit-fallthrough. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: afs: add v2 partition parsingLinus Walleij2019-05-061-1/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AFS v2 partition type appear in later ARM reference designs such as RealView, Versatile Express and the 64bit Juno Development Platform. The image informations is padded with a 32bit word (4 bytes) on the 32bit platforms and a 64bit word (8 bytes) on the 64bit platforms. The boot monitor source code gives at hand that this is because the first entry in the struct mapped over the image information is a "next" pointer for a linked list, filled in by firmware after reading in the info block, and always zero in the flash. We adjust padding by checking what padding gives the right checksum. This was tested on: - Integrator/AP (v1 partitions) - RealView PB11MPCore (v2 32bit partitions) - Juno Development System (v2 64bit partitions) All systems display the images in flash very nicely as separate partitions, e.g on Juno: 4 afs partitions found on MTD device 8000000.flash Creating 4 MTD partitions on "8000000.flash": 0x000000040000-0x0000000c0000 : "fip" 0x000000ec0000-0x0000018c0000 : "Image" 0x000000f00000-0x000000f40000 : "juno" 0x000003ec0000-0x000003f00000 : "bl1" Cc: Ryan Harkin <ryan.harkin@linaro.org> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: afs: factor the IIS read into partition parserLinus Walleij2019-05-061-39/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Factor the IIS (Image Information Structure) reading into the partition parser, giving us a single, clean partition parser function. Cc: Ryan Harkin <ryan.harkin@linaro.org> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: afs: factor footer parsing into the v1 part parsingLinus Walleij2019-05-061-59/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This simplifies the code by factoring in the image footer parsing into the single function parsing the AFSv1 partitions. Cc: Ryan Harkin <ryan.harkin@linaro.org> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: factor out v1 partition parsingLinus Walleij2019-05-061-38/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This breaks out the parsing of v1 partitions so we can later add a v2 partition parser. Cc: Ryan Harkin <ryan.harkin@linaro.org> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: afs: simplify partition detectionLinus Walleij2019-05-061-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of reading out the AFS footers twice, create a separate function to just check if there is a footer or not. Rids a few local variables and prepare us to join the actual parser into one function. Cc: Ryan Harkin <ryan.harkin@linaro.org> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: afs: simplify partition parsingLinus Walleij2019-05-061-35/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This simplifies the AFS partition parsing to make the code more straight-forward and readable. Before this patch the code tried to calculate the memory required to hold the partition info by adding up the sizes of the strings of the names and adding that to a single memory allocation, indexing the name pointers in front of the struct mtd_partition allocations so all allocated data was in one chunk. This is overzealous. Instead use kstrdup and bail out, kfree():ing the memory used for MTD partitions and names alike on the errorpath. In the process rename the index variable from idx to i. Cc: Ryan Harkin <ryan.harkin@linaro.org> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: partitions: Add OF support to AFS partitionsLinus Walleij2019-05-061-0/+7
| | | | | | | | | | | | | | | | | | | | | This adds device tree support for AFS partitioning. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: afs: Move AFS partition parser to parsers subdirLinus Walleij2019-05-065-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | This moves the AFS (ARM Firmware Suite) partition parser for NOR flash down into the parsers subdirectory. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: maps: Make uclinux_ram_map staticThomas Huth2019-05-061-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | The blackfin architecture has been removed a while ago, so there is no more need to declare uclinux_ram_map as a global structure. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: maps: Allow MTD_PHYSMAP with MTD_RAMChris Packham2019-05-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the physmap_of_core.c code was merged into physmap-core.c the ability to use MTD_PHYSMAP_OF with only MTD_RAM selected was lost. Restore this by adding MTD_RAM to the dependencies of MTD_PHYSMAP. Fixes: commit 642b1e8dbed7 ("mtd: maps: Merge physmap_of.c into physmap-core.c") Cc: <stable@vger.kernel.org> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: maps: physmap: Store gpio_values correctlyChris Packham2019-05-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the gpio-addr-flash.c driver was merged with physmap-core.c the code to store the current gpio_values was lost. This meant that once a gpio was asserted it was never de-asserted. Fix this by storing the current offset in gpio_values like the old driver used to. Fixes: commit ba32ce95cbd9 ("mtd: maps: Merge gpio-addr-flash.c into physmap-core.c") Cc: <stable@vger.kernel.org> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: parser_imagetag: add of_match_table supportJonas Gorski2019-05-061-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow matching the imagetag parser for fixed partitions defined in the device tree. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: bcm63xxpart: move imagetag parsing to its own parserJonas Gorski2019-05-065-147/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the bcm963xx Image Tag parsing into its own partition parser. This Allows reusing the parser with different full flash parsers. While moving it, rename it to bcm963* to better reflect it isn't chip, but reference implementation specific. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: bcm63xxpart: add of_match_table supportJonas Gorski2019-05-061-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add of_match_table support to allow using bcm63xxpart as a full flash layout parser from device tree. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: physmap_of_gemini: remove extranous __xipram annotationArnd Bergmann2019-05-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marking a local variable as __xipram causes a warning because of the noinline attribute: drivers/mtd/maps/physmap-gemini.c:89:11: error: '__noinline__' attribute only applies to functions [-Werror,-Wignored-attributes] map_word __xipram ret; ^ include/linux/mtd/xip.h:34:18: note: expanded from macro '__xipram' #define __xipram noinline __attribute__ ((__section__ (".xiptext"))) I can't see any reason for the anotation anyway, so just remove it here. Fixes: 9d3b5086f6d4 ("mtd: physmap_of_gemini: Handle pin control") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | Merge tag 'spi-nor/for-5.2' of ↵Richard Weinberger2019-05-063-4/+15
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next SPI NOR core changes: - Print all JEDEC ID bytes on error - Fix comment of spi_nor_find_best_erase_type() - Add region locking flags for s25fl512s SPI NOR controller drivers changes: - intel-spi: * Avoid crossing 4K address boundary on read/write * Add support for Intel Comet Lake SPI serial flash
| | * | spi-nor: intel-spi: Add support for Intel Comet Lake SPI serial flashMika Westerberg2019-05-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Comet Lake has the same SPI serial flash controller as Ice Lake. Add Comet Lake PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * | spi-nor: s25fl512s supports region lockingJonas Bonn2019-04-011-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both the BP[0-2] bits and the TBPROT bit are supported on this chip. Tested and verified on a Cypress s25fl512s. Signed-off-by: Jonas Bonn <jonas@norrbonn.se> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: spi-nor: intel-spi: Avoid crossing 4K address boundary on read/writeAlexander Sverdlin2019-04-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It was observed that reads crossing 4K address boundary are failing. This limitation is mentioned in Intel documents: Intel(R) 9 Series Chipset Family Platform Controller Hub (PCH) Datasheet: "5.26.3 Flash Access Program Register Access: * Program Register Accesses are not allowed to cross a 4 KB boundary..." Enhanced Serial Peripheral Interface (eSPI) Interface Base Specification (for Client and Server Platforms): "5.1.4 Address For other memory transactions, the address may start or end at any byte boundary. However, the address and payload length combination must not cross the naturally aligned address boundary of the corresponding Maximum Payload Size. It must not cross a 4 KB address boundary." Avoid this by splitting an operation crossing the boundary into two operations. Fixes: 8afda8b26d01 ("spi-nor: Add support for Intel SPI serial flash controller") Cc: stable@vger.kernel.org Reported-by: Romain Porte <romain.porte@nokia.com> Tested-by: Pascal Fabreges <pascal.fabreges@nokia.com> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: spi-nor: Fix comment of spi_nor_find_best_erase_type()Alexander Sverdlin2019-03-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erase types are sorted *smallest* type first, refer to spi_nor_sort_erase_mask(). Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: spi-nor: Print all JEDEC ID bytes on errorGeert Uytterhoeven2019-03-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If identification of an SPI NOR FLASH fails, the JEDEC ID is printed, which is stored in the first 3 bytes of the ID read from the FLASH. However, the extended JEDEC ID, which is stored in the remaining bytes, also matters, as it is used for identification of some FLASH types. Print all (currently 6) ID bytes read to ease failure analysis and debugging. Suggested-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * | | Merge tag 'nand/for-5.2' of ↵Richard Weinberger2019-05-0568-2100/+3422
| |\ \ \ | | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next NAND core changes: - Support having the bad block markers in either the first, second or last page of a block. The combination of all three location is now possible. - Constification of NAND_OP_PARSER(_PATTERN) elements. - Generic NAND DT bindings changed to yaml format (can be used to check the proposed bindings. First platform to be fully supported: sunxi. - Stopped using several legacy hooks. - Preparation to use the generic NAND layer with the addition of several helpers and the removal of the struct nand_chip from generic functions. - Kconfig cleanup to prepare the introduction of external ECC engines support. - Fallthrough comments. - Introduction of the SPI-mem dirmap API for SPI-NAND devices. Raw NAND controller drivers changes: - nandsim: * Switch to ->exec-op(). - meson: * Misc cleanups and fixes. * New OOB layout. - Sunxi: * A23/A33 NAND DMA support. - Ingenic: * Full reorganization and cleanup. * Clear separation between NAND controller and ECC engine. * Support JZ4740 an JZ4725B. - Denali: * Clear controller/chip separation. * ->exec_op() migration. * Various cleanups. - fsl_elbc: * Enable software ECC support. - Atmel: * Sam9x60 support. - GPMI: * Introduce the GPMI_IS_MXS() macro. - Various trivial/spelling/coding style fixes.
| | * | mtd: nandsim: switch to exec_op interfaceRichard Weinberger2019-04-181-31/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stop using the legacy interface. Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: nandsim: Embed struct nand_chip in struct nandsimRichard Weinberger2019-04-181-25/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We will need struct nand_controller soon, so more stuff need to be parts of struct nandsim. While we are here, rename "nand" to "ns" to use the same naming scheme everywhere in nandsim. Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: AMD: Also use the last page for bad block markersFrieder Schrempf2019-04-181-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheet of some Cypress SLC NANDs, the bad block markers can be in the first, second or last page of a block. So let's check all three locations. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: ESMT: Also use the last page for bad block markersFrieder Schrempf2019-04-181-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is known that some ESMT SLC NANDs have been shipped with the factory bad block markers in the first or last page of the block, instead of the first or second page. To be on the safe side, let's check all three locations. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: Support bad block markers in first, second or last pageFrieder Schrempf2019-04-183-37/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently supported bad block marker positions within the block are: * in first page only * in last page only * in first or second page Some ESMT NANDs are known to have been shipped by the manufacturer with bad block markers in the first or last page, instead of the first or second page. Also the datasheets for Cypress/Spansion/AMD NANDs claim that the first, second *and* last page needs to be checked. Therefore we make it possible to set NAND_BBM_FIRSTPAGE, NAND_BBM_SECONDPAGE and NAND_BBM_LASTPAGE independently in any combination. To simplify the code, the logic to evaluate the flags is moved to a a new function nand_bbm_get_next_page(). Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: nand: Make flags for bad block marker position more granularFrieder Schrempf2019-04-1810-11/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To be able to check and set bad block markers in the first and second page of a block independently of each other, we create separate flags for both cases. Previously NAND_BBM_SECONDPAGE meant, that both, the first and the second page were used. With this patch NAND_BBM_FIRSTPAGE stands for using the first page and NAND_BBM_SECONDPAGE for using the second page. This patch is only for preparation of subsequent changes and does not implement the logic to actually handle both flags separately. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: onenand: Store bad block marker position in chip structFrieder Schrempf2019-04-182-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The information about where the manufacturer puts the bad block markers inside the bad block and in the OOB data is stored in different places. Let's move this information to the chip struct, as we did it for rawnand. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: Always store info about bad block markers in chip structFrieder Schrempf2019-04-1810-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The information about where the manufacturer puts the bad block markers inside the bad block and in the OOB data is stored in different places. Let's move this information to nand_chip.options and nand_chip.badblockpos. As this chip-specific information is not directly related to the bad block table (BBT), we also rename the flags to NAND_BBM_*. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: meson: only initialize the RB completion onceMartin Blumenstingl2019-04-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Documentation/scheduler/completion.txt states: Calling init_completion() on the same completion object twice is most likely a bug as it re-initializes the queue to an empty queue and enqueued tasks could get "lost" - use reinit_completion() in that case, but be aware of other races. Initialize nfc->completion in meson_nfc_probe using init_completion and change the call in meson_nfc_queue_rb to reinit_completion so the logic matches what the documentation suggests. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: meson: use a void pointer for meson_nfc_dma_buffer_setupMartin Blumenstingl2019-04-181-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This simplifies the code because it gets rid of the casts to an u8-pointer when passing "info_buf" from struct meson_nfc_nand_chip. Also it gets rid of the cast of the u8 databuf pointer to a void pointer. The logic inside meson_nfc_dma_buffer_setup() doesn't care about the pointer types themselves because it only passes them to dma_map_single which accepts a void pointer. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: meson: use of_property_count_elems_of_size helperMartin Blumenstingl2019-04-181-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the of_property_count_elems_of_size() helper instead of open-coding it's logic. As a bonus this will now error out if the "reg" property values use an incorrect size (anything other than sizeof(u32)). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: meson: use struct_size macroMartin Blumenstingl2019-04-181-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the recently introduced struct_size macro instead of open-coding it's logic. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: marvell: Fix helper name in commentMiquel Raynal2019-04-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the migration of the driver to stop using the legacy ->select_chip() hook, the marvell_nfc_select_chip() helper has been 'renamed' to marvell_nfc_select_target(). Update a left-over reference to this helper in a comment in the ->resume() path. Fixes: b25251414f6e00 ("mtd: rawnand: marvell: Stop implementing ->select_chip()") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| | * | mtd: rawnand: sunxi: Add A23/A33 DMA supportMiquel Raynal2019-04-181-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner NAND controllers can make use of DMA to enhance the I/O throughput thanks to ECC pipelining. DMA handling with A23/A33 NAND IP is a bit different than with the older SoCs, hence the introduction of a new compatible to handle: * the differences between register offsets, * the burst length change from 4 to minimum 8, * drive SRAM accesses through the AHB bus instead of the MBUS. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: sunxi: Add a platform data structureMiquel Raynal2019-04-181-5/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before the introduction of A33 NAND DMA support, let's use a platform data structure for parameters that will differ. Right now, there is only one compatible with one data structure. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: ingenic: Make jz4725b_ooblayout_ops staticYueHaibing2019-04-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix sparse warning: drivers/mtd/nand/raw/ingenic/ingenic_nand.c:140:32: warning: symbol 'jz4725b_ooblayout_ops' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: ingenic: Add missing MODULE_* informationYueHaibing2019-04-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc warning this: WARNING: modpost: missing MODULE_LICENSE() in drivers/mtd/nand/raw/ingenic/ingenic_ecc.o Add MODULE_LICENSE,MODULE_AUTHOR and MODULE_DESCRIPTION. Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 9df5741a577e ("mtd: rawnand: ingenic: Separate top-level and SoC specific code") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: denali: clean up coding styleMasahiro Yamada2019-04-181-28/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Eliminate the following reports from 'scripts/checkpatch.pl --strict'. CHECK: Prefer kernel type 'u8' over 'uint8_t' CHECK: Prefer kernel type 'u32' over 'uint32_t' CHECK: Alignment should match open parenthesis I slightly changed denali_check_erased_page() to shorten it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: denali: remove DENALI_NR_BANKS macroMasahiro Yamada2019-04-181-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the runtime-detected denali->nbanks instead of hard-coded DENALI_NR_BANKS (=4). The actual number of banks depends on the IP configuration, and can be less than DENALI_NR_BANKS. It is pointless to touch registers of unsupported banks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: denali: decouple controller and NAND chipsMasahiro Yamada2019-04-184-217/+455
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, this driver sticks to the legacy NAND model because it was upstreamed before commit 2d472aba15ff ("mtd: nand: document the NAND controller/NAND chip DT representation"). However, relying on the dummy_controller is already deprecated. Switch over to the new controller/chip representation. The struct denali_nand_info has been split into denali_controller and denali_chip, to contain the controller data, per-chip data, respectively. One problem is, this commit changes the DT binding. So, as always, the backward compatibility must be taken into consideration. In the new binding, the controller node expects #address-cells = <1>; #size-cells = <0>; ... since the child nodes represent NAND chips. In the old binding, the controller node may have subnodes, but they are MTD partitions. The denali_dt_is_legacy_binding() exploits it to distinguish old/new platforms. Going forward, the old binding is only allowed for existing DT files. I updated the binding document. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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