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2017-07-11MIPS: generic: Support MIPS Boston development boardsPaul Burton6-0/+313
2017-07-11MIPS: DTS: img: Don't attempt to build-in all .dtb filesPaul Burton1-2/+1
2017-07-11clk: boston: Add a driver for MIPS Boston board clocksPaul Burton6-0/+116
2017-07-11dt-bindings: Document img,boston-clock bindingPaul Burton3-0/+52
2017-07-11MIPS: Traced negative syscalls should return -ENOSYSJames Hogan1-0/+7
2017-07-11MIPS: Correct forced syscall errorsJames Hogan1-1/+1
2017-07-11MIPS: Negate error syscall return in traceJames Hogan1-1/+1
2017-07-11MIPS: Drop duplicate HAVE_SYSCALL_TRACEPOINTS selectJames Hogan1-1/+0
2017-07-11MIPS16e2: Provide feature overrides for non-MIPS16 systemsMaciej W. Rozycki16-0/+16
2017-07-11MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfoMaciej W. Rozycki1-0/+1
2017-07-05MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructionsMaciej W. Rozycki1-2/+37
2017-07-05MIPS: MIPS16e2: Identify ASE presenceMaciej W. Rozycki4-0/+7
2017-06-29MIPS: VDSO: Fix a mismatch between comment and preprocessor constantAleksandar Markovic1-1/+1
2017-06-29MIPS: VDSO: Add implementation of gettimeofday() fallbackGoran Ferenc1-1/+23
2017-06-29MIPS: VDSO: Add implementation of clock_gettime() fallbackGoran Ferenc1-3/+22
2017-06-29MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse()Goran Ferenc2-6/+6
2017-06-29MIPS: Use current_cpu_type() in m4kc_tlbp_war()Paul Burton1-2/+1
2017-06-29MIPS: Allow storing pgd in C0_CONTEXT for MIPSr6Paul Burton1-1/+1
2017-06-29MIPS: Handle tlbex-tlbp race conditionPaul Burton1-1/+37
2017-06-29MIPS: Add CPU shared FTLB feature detectionPaul Burton3-0/+56
2017-06-29MIPS: CPS: Handle spurious VP starts more gracefullyPaul Burton1-1/+6
2017-06-29MIPS: CPS: Handle cores not powering down more gracefullyPaul Burton1-3/+24
2017-06-29MIPS: CPS: Prevent multi-core with dcache aliasingPaul Burton1-3/+5
2017-06-29MIPS: CPS: Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6Paul Burton1-0/+1
2017-06-29MIPS: CM: WARN on attempt to lock invalid VP, not BUGPaul Burton1-1/+1
2017-06-29MIPS: CM: Avoid per-core locking with CM3 & higherPaul Burton1-6/+32
2017-06-29MIPS: Skip IPI setup if we only have 1 CPUPaul Burton1-0/+3
2017-06-29MIPS: Use `pr_debug' for messages from `__compute_return_epc_for_insn'Maciej W. Rozycki1-6/+6
2017-06-29MIPS: math-emu: For MFHC1/MTHC1 also return SIGILL right awayMaciej W. Rozycki1-3/+2
2017-06-29MIPS: Fix a typo: s/preset/present/ in r2-to-r6 emulation error messageMaciej W. Rozycki1-1/+1
2017-06-29MIPS: Send SIGILL for R6 branches in `__compute_return_epc_for_insn'Maciej W. Rozycki1-20/+15
2017-06-29MIPS: Send SIGILL for linked branches in `__compute_return_epc_for_insn'Maciej W. Rozycki1-8/+4
2017-06-29MIPS: Rename `sigill_r6' to `sigill_r2r6' in `__compute_return_epc_for_insn'Maciej W. Rozycki1-8/+8
2017-06-29MIPS: Send SIGILL for BPOSGE32 in `__compute_return_epc_for_insn'Maciej W. Rozycki1-3/+4
2017-06-29MIPS: Fix unaligned PC interpretation in `compute_return_epc'Maciej W. Rozycki1-4/+1
2017-06-29MIPS: Actually decode JALX in `__compute_return_epc_for_insn'Maciej W. Rozycki1-0/+1
2017-06-29MIPS: math-emu: Prevent wrong ISA mode instruction emulationMaciej W. Rozycki1-0/+38
2017-06-29MIPS: Use queued spinlocks (qspinlock)Paul Burton4-232/+4
2017-06-29MIPS: Use queued read/write locks (qrwlock)Paul Burton4-224/+4
2017-06-29MIPS: cmpxchg: Rearrange __xchg() arguments to match xchg()Paul Burton1-2/+3
2017-06-29MIPS: cmpxchg: Implement 1 byte & 2 byte cmpxchg()Paul Burton2-0/+64
2017-06-29MIPS: cmpxchg: Implement 1 byte & 2 byte xchg()Paul Burton3-3/+60
2017-06-29MIPS: cmpxchg: Implement __cmpxchg() as a functionPaul Burton1-27/+32
2017-06-29MIPS: cmpxchg: Drop __xchg_u{32,64} functionsPaul Burton1-31/+17
2017-06-29MIPS: cmpxchg: Error out on unsupported xchg() callsPaul Burton1-15/+17
2017-06-29MIPS: cmpxchg: Use __compiletime_error() for bad cmpxchg() pointersPaul Burton1-3/+10
2017-06-29MIPS: cmpxchg: Pull xchg() asm into a macroPaul Burton1-48/+33
2017-06-29MIPS: cmpxchg: Unify R10000_LLSC_WAR & non-R10000_LLSC_WAR casesPaul Burton1-58/+22
2017-06-29MIPS: unaligned: Add DSP lwx & lhx missaligned access supportMiodrag Dinic2-74/+111
2017-06-29MIPS: R6: Fix PREF instruction usage by memcpy for MIPS R6Leonid Yegoshin1-0/+3