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2018-01-27clk: aspeed: Fix return value check in aspeed_cc_init()Wei Yongjun1-1/+1
2018-01-27clk: aspeed: Add reset controllerJoel Stanley1-1/+81
2018-01-27clk: aspeed: Register gated clocksJoel Stanley1-0/+130
2018-01-27clk: aspeed: Add platform driver and register PLLsJoel Stanley1-0/+130
2018-01-27clk: aspeed: Register core clocksJoel Stanley1-0/+177
2018-01-27clk: Add clock driver for ASPEED BMC SoCsJoel Stanley3-0/+154
2018-01-10clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being builtSean Wang3-9/+2
2018-01-10clk: fix reentrancy of clk_enable() on UP systemsDavid Lechner1-1/+9
2018-01-10clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()weiyongjun (A)1-0/+2
2018-01-10clk: Simplify debugfs registrationStephen Boyd1-6/+2
2018-01-10clk: Fix debugfs_create_*() usageGeert Uytterhoeven1-19/+17
2018-01-10clk: Show symbolic clock flags in debugfsGeert Uytterhoeven2-2/+57
2018-01-05clk: renesas: r8a7796: Add FDP clockABE Hiroshige1-0/+1
2018-01-05clk: Move __clk_{get,put}() into private clk.h APIStephen Boyd2-8/+4
2018-01-05clk: sunxi: Use CLK_IS_CRITICAL flag for critical clksStephen Boyd6-47/+44
2018-01-04clk: Improve flags doc for of_clk_detect_critical()Geert Uytterhoeven1-1/+1
2018-01-03arch: Remove clkdev.h asm-generic from KbuildStephen Boyd32-61/+0
2018-01-03clk: sunxi-ng: a83t: Add M divider to TCON1 clockJernej Škrabec1-2/+2
2018-01-03clk: Prepare to remove asm-generic/clkdev.hStephen Boyd2-2/+5
2018-01-03blackfin: Use generic clkdev.h headerStephen Boyd2-17/+1
2018-01-02clk: qcom: Add APCS clock controller supportGeorgi Djakov3-0/+150
2018-01-02clk: qcom: Add regmap mux-div clocks supportGeorgi Djakov3-0/+276
2018-01-02clk: qcom: Add A53 PLL supportGeorgi Djakov4-0/+140
2017-12-29clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCUIcenowy Zheng1-3/+3
2017-12-29clk: sunxi-ng: add support for Allwinner H3 DE2 CCUIcenowy Zheng1-0/+47
2017-12-29dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3Icenowy Zheng1-2/+3
2017-12-29clk: divider: fix incorrect usage of container_ofJerome Brunet8-12/+13
2017-12-28clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO()Gomonovych, Vasyl1-4/+1
2017-12-28clk: iproc: Minor tidy up of iproc pll data structuresLori Hikichi1-47/+36
2017-12-28clk: iproc: Allow plls to do minor rate changes without resetLori Hikichi1-0/+47
2017-12-28clk: iproc: Fix error in the pll post divider rate calculationLori Hikichi1-16/+17
2017-12-28clk: iproc: Allow iproc pll to runtime calculate vco parametersLori Hikichi3-35/+92
2017-12-28clk: si5351: _si5351_clkout_reset_pll() can be staticWu Fengguang1-1/+1
2017-12-28clk: pxa: unbreak lookup of CLK_POUTIgor Grinberg1-1/+5
2017-12-28clk: meson-axg: make local symbol axg_gp0_params_table staticweiyongjun (A)1-1/+1
2017-12-28clk: meson-axg: fix return value check in axg_clkc_probe()weiyongjun (A)1-1/+1
2017-12-27clk: mediatek: Fix all warnings for missing struct clk_onecell_dataSean Wang1-0/+1
2017-12-23clk: meson: mpll: use 64-bit maths in params_from_rateMartin Blumenstingl1-1/+1
2017-12-22clk: si5351: Do not enable parent clocks on probeSergej Sawazki1-26/+9
2017-12-22clk: si5351: Rename internal plls to avoid name collisionsSergej Sawazki1-1/+1
2017-12-22clk: si5351: Apply PLL soft reset before enabling the outputsSergej Sawazki1-0/+29
2017-12-22clk: si5351: Add DT property to enable PLL resetSergej Sawazki3-0/+6
2017-12-22clk: si5351: implement remove handlerAlexey Khoroshilov1-0/+13
2017-12-22clk: axi-clkgen: Round closest in round_rate() and recalc_rate()Lars-Peter Clausen1-3/+7
2017-12-22clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()Lars-Peter Clausen1-5/+24
2017-12-22clk: Don't touch hardware when reparenting during registrationStephen Boyd1-2/+5
2017-12-22clk: mediatek: fixup test-building of MediaTek clock driversSean Wang1-1/+1
2017-12-22clk: mediatek: group drivers under indpendent menuSean Wang1-46/+50
2017-12-22clk: at91: pmc: Support backup for programmable clocksRomain Izard3-0/+39
2017-12-22clk: at91: pmc: Save SCSR during suspendRomain Izard1-2/+2