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* [MIPS] Add support for MIPS CMP platform.Ralf Baechle2008-04-281-3/+4
| | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: Au1210/Au1250 CPU supportManuel Lauss2008-01-291-2/+2
| | | | | | | | | | This patch adds IDs for new Au1200 variants: Au1210 and Au1250. They are essentially identical to the Au1200 except for the Au1210 which has a different SoC-ID in the PRId register [bits 31:24]. The Au1250 is a "Au1200 V0.2". Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Convert list of CPU types from #define to enum.Ralf Baechle2007-10-121-70/+49
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle2007-10-121-18/+17
| | | | | | | | | | | It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add support for BCM47XX CPUs.Aurelien Jarno2007-10-121-2/+10
| | | | | | | | | | | | | | Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] PMC MSP71xx mips commonMarc St-Jean2007-07-101-0/+2
| | | | | | | Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-101-1/+6
| | | | | Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Enable support for the userlocal hardware registerRalf Baechle2007-07-101-0/+1
| | | | | | | | Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add macros to encode processor revisions.Ralf Baechle2007-07-061-0/+11
| | | | | | | | | Older processors used to encode processor version and revision in two 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores have switched to use the 8-bits as 3:3:2 bitfield with the last field as the patch number. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle2006-07-131-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Treat R14000 like R10000.Kumba2006-06-011-1/+3
| | | | | Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix detection and handling of the 74K processor.Chris Dearman2006-06-011-1/+3
| | | | | | | | Nothing exciting; Linux just didn't know it yet so this is most adding a value to a case statement. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix CPU type bitmasks for MIPS III, IV and V.Maciej W. Rozycki2006-02-141-3/+3
| | | | | Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Reorganize ISA constants strictly as bitmasks.Ralf Baechle2006-01-101-7/+10
| | | | Signed-off-by: Ralf Baechle <ralf@ongar.mips.com>
* MIPS: Introduce machinery for testing for MIPSxxR1/2.Ralf Baechle2006-01-101-1/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle2006-01-101-10/+7
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Add support for SB1A CPU.Andrew Isaacson2005-10-291-1/+3
| | | | | Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Cleanup the mess in cpu_cache_init.Ralf Baechle2005-10-291-19/+21
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Move MIPS Technologies processor IDs to where they belong.Maciej W. Rozycki2005-10-291-2/+7
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov2005-10-291-1/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Detect the MIPS R2 vectored interrupt, external interrupt controllerRalf Baechle2005-10-291-0/+4
| | | | | | options and the precense of the MT ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Detect the 34K.Ralf Baechle2005-10-291-1/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Support the MIPS32 / MIPS64 DSP ASE.Ralf Baechle2005-10-291-0/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Cleanup decoding of MIPSxx config registers.Ralf Baechle2005-10-291-1/+9
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Base Au1200 2.6 support.Pete Popov2005-10-291-1/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Add a few more PrId vendor IDs.Ralf Baechle2005-10-291-6/+11
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-171-0/+222
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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