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* [MIPS] Make timer interrupt frequency configurable from kconfig.Atsushi Nemoto2006-06-196-74/+1
| | | | | | | | | | Make HZ configurable. DECSTATION can select 128/256/1024 HZ, JAZZ can only select 100 HZ, others can select 100/128/250/256/1000/1024 HZ if not explicitly specified). Also remove all mach-xxx/param.h files and update all defconfigs according to current HZ value. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix R4K cache macro namesKumba2006-06-194-6/+6
| | | | | | | | Several machines have the R4K cache macro name spelled incorrectly. Namely, they have cpu_has_4kcache defined instead of cpu_has_4k_cache. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add Missing R4K Cache Macros to IP27 & IP32Kumba2006-06-192-0/+5
| | | | | | | | | Keeping in accordance with other machines, IP27 and IP32 lack a few macros. IP27 lacks cpu_has_4kex & cpu_has_4k_cache macros while IP32 lacks just the cpu_has_4k_cache macro. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Support for the RM9000-based Basler eXcite smart camera platform.Ralf Baechle2006-06-199-2/+313
| | | | | Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Support for the R5500-based NEC EMMA2RH Mark-eins boarddmitry pervushin2006-06-194-0/+425
| | | | | Signed-off-by: dmitry pervushin <dpervushin@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Support SNI RM200C SNI in big endian mode and R5000 processors.Thomas Bogendoerfer2006-06-192-7/+2
| | | | | | | | | Added support for RM200C machines with big endian firmware Added support for RM200-C40 (R5000 support) Signed-off-by: Florian Lohoff <flo@rfc822.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SN: include asm/sn/types.h for nasid_t.Ralf Baechle2006-06-191-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove support for NEC DDB5476.Ralf Baechle2006-06-192-160/+1
| | | | | | As warned several times before. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove support for NEC DDB5074.Ralf Baechle2006-06-194-88/+1
| | | | | | As warned several times before. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cleanup memory managment initialization.Ralf Baechle2006-06-191-0/+6
| | | | | | | | | | Historically plat_mem_setup did the entire platform initialization. This was rather impractical because it meant plat_mem_setup had to get away without any kind of memory allocator. To keep old code from breaking plat_setup was just renamed to plat_setup and a second platform initialization hook for anything else was introduced. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SN: Declare bridge_pci_ops.Ralf Baechle2006-06-191-0/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP27: Cleanup N/M mode configuration.Ralf Baechle2006-06-191-2/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP27: Throw away old unused hacks.Ralf Baechle2006-06-191-8/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Drop 0 definition for kern_addr_validRalf Baechle2006-06-192-5/+0
| | | | | | | | | | | | | | kern_addr_valid is currently only being used in kmem_ptr_validate which is making some vague attempt at verfying the validity of an address. Only IA-64, PARISC and x86-64 actually make some actual effort to verify the validity of the pointer. Most architecture definitions of kern_addr_valid() just define it as 1; the Alpha and CONFIG_DISCONTIGMEM on i386 and MIPS even as 0; the 0-definition will result in kmem_ptr_validate always failing which in turn will cause d_validate to always fail. d_validate's only two users are smbfs and ncpfs, so the 0 definition ended breaking those ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Consolidate definitions of pfn_valid in one file.Ralf Baechle2006-06-192-8/+19
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] APM emu supportRodolfo Giometti2006-06-191-0/+65
| | | | | Signed-off-by: Rodolfo Giometti <giometti@linux.it> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SN: Rename SGI_SN0_N_MODE -> SGI_SN_N_MODE.Ralf Baechle2006-06-193-6/+6
| | | | | | It's not SN0-specific. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SN: Move FRU header one level up; it is not SN0-specific.Ralf Baechle2006-06-192-5/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP27: Remove #if 0'ed code.Ralf Baechle2006-06-193-57/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP27: Nuke leftovers of _STANDALONERalf Baechle2006-06-192-95/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP27: Remove leftovers of sable support.Ralf Baechle2006-06-194-22/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP27: Nuke last leftovers from FRUTESTRalf Baechle2006-06-191-14/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP27: Nuke last leftovers of CONFIG_SGI_IO.Ralf Baechle2006-06-193-83/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cleanup __emt() a bit.Ralf Baechle2006-06-191-3/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove unused definitions from addrspace.h.Yoichi Yuasa2006-06-191-35/+0
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Qemu system shutdown supportThiemo Seufer2006-06-191-0/+6
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Unify mips_fpu_soft_struct and mips_fpu_hard_structs.Atsushi Nemoto2006-06-193-17/+6
| | | | | | | | | The struct mips_fpu_soft_struct and mips_fpu_hard_struct are completely same now and the kernel fpu emulator assumes that. This patch unifies them to mips_fpu_struct and get rid of mips_fpu_union. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Wind River 4KC PPMC Eval Board SupportMark.Zhan2006-06-191-0/+84
| | | | | | | Support for the GT-64120-based Wind River 4KC PPMC Evaluation board. Signed-off-by: Rongkai.Zhan <Rongkai.zhan@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix futex_atomic_op_inuser.Atsushi Nemoto2006-06-191-15/+17
| | | | | | | | | | | | | | I found that NPTL's pthread_cond_signal() does not work properly on kernels compiled by gcc 4.1.x. I suppose inline asm for __futex_atomic_op() was wrong. I suppose: 1. "=&r" constraint should be used for oldval. 2. Instead of "r" (uaddr), "=R" (*uaddr) for output and "R" (*uaddr) for input should be used. 3. "memory" should be added to the clobber list. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix fpu_save_double on 64-bit.Atsushi Nemoto2006-06-192-12/+11
| | | | | | | | | | | | | | | | | | > Without this fix, _save_fp() in 64-bit kernel is seriously broken. > > ffffffff8010bec0 <_save_fp>: > ffffffff8010bec0: 400d6000 mfc0 t1,c0_status > ffffffff8010bec4: 000c7140 sll t2,t0,0x5 > ffffffff8010bec8: 05c10011 bgez t2,ffffffff8010bf10 <_save_fp+0x50> > ffffffff8010becc: 00000000 nop > ffffffff8010bed0: f4810328 sdc1 $f1,808(a0) > ... Fix register usage in fpu_save_double() and make fpu_restore_double() more symmetric with fpu_save_double(). Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix sparsemem support.Chad Reese2006-06-062-0/+16
| | | | | | | | | | | | Move memory_present() in arch/mips/kernel/setup.c. When using sparsemem extreme, this function does an allocate for bootmem. This would always fail since init_bootmem hasn't been called yet. Move memory_present after free_bootmem. This only marks actual memory ranges as present instead of the entire address space. Signed-off-by: Chad Reese <creese@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix 64-bit build for RM7000.Ralf Baechle2006-06-061-0/+1
| | | | | | RM7000 has 40-bit virtual / 36-bit physical address space. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix non-linear memory mapping on MIPSSergei Shtylyov2006-06-062-27/+31
| | | | | | | | | | | Fix the non-linear memory mapping done via remap_file_pages() -- it didn't work on any MIPS CPU because the page offset clashing with _PAGE_FILE and some other page protection bits which should have been left zeros for this kind of pages. Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix swap entry for MIPS32 36-bit physical addressSergei Shtylyov2006-06-061-2/+14
| | | | | | | | | | | With 64-bit physical address enabled, 'swapon' was causing kernel oops on Alchemy CPUs (MIPS32) because of the swap entry type field corrupting the _PAGE_FILE bit in 'pte_low' field. So, switch to storing the swap entry in 'pte_high' field using all its bits except _PAGE_GLOBAL and _PAGE_VALID which gives 25 bits for the swap entry offset. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix mprotect() syscall for MIPS32 w/36-bit physical address supportSergei Shtylyov2006-06-061-2/+3
| | | | | | | | | Fix mprotect() syscall for MIPS32 CPUs with 36-bit physical address support: pte_modify() macro didn't clear the hardware page protection bits before modifying... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix declaration of smp_prepare_cpus() platform hook.Ralf Baechle2006-06-061-2/+2
| | | | | | | A while ago prom_prepare_cpus was replaced by plat_prepare_cpus but the declaration has stayed unchanged. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix instable BogoMIPS on multi-issue processors.Ralf Baechle2006-06-061-10/+12
| | | | | | | Increase alignment of BogoMIPS loop to 8 bytes. Having the delay loop overlap cache line boundaries may cause instable delays. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove duplicate declaration of cpu_online_map.Ralf Baechle2006-06-061-1/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6Linus Torvalds2006-06-031-1/+9
|\ | | | | | | | | | | * master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [SPARC64]: Fix D-cache corruption in mremap [SPARC64]: Make smp_processor_id() functional before start_kernel()
| * [SPARC64]: Fix D-cache corruption in mremapDavid S. Miller2006-06-021-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | If we move a mapping from one virtual address to another, and this changes the virtual color of the mapping to those pages, we can see corrupt data due to D-cache aliasing. Check for and deal with this by overriding the move_pte() macro. Set things up so that other platforms can cleanly override the move_pte() macro too. Signed-off-by: David S. Miller <davem@davemloft.net>
* | [MIPS] Treat R14000 like R10000.Kumba2006-06-011-1/+3
| | | | | | | | | | Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | [MIPS] Update/Fix instruction definitionsThiemo Seufer2006-06-011-5/+28
| | | | | | | | | | | | | | | | A small bugfix for up to now unused instruction definitions, and a somewhat larger update to cover MIPS32R2 instructions. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | [MIPS] DSP and MDMX share the same config flag bit.Thiemo Seufer2006-06-011-1/+1
| | | | | | | | | | | | | | Clarify comment. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | [MIPS] Update struct sigcontext member namesDaniel Jacobowitz2006-06-011-2/+8
| | | | | | | | | | | | | | | | Rename the 64-bit sc_hi and sc_lo arrays to use the same names as the 32-bit struct sigcontext (sc_mdhi, sc_hi1, et cetera). Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | [MIPS] Update/fix futex assemblyRalf Baechle2006-06-011-25/+116
| | | | | | | | | | | | | | | | | | o Implement futex_atomic_op_inuser() operation o Don't use the R10000-ll/sc bug workaround version for every processor. branch likely is deprecated and some historic ll/sc processors don't implement it. In any case it's slow. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | [MIPS] Fix detection and handling of the 74K processor.Chris Dearman2006-06-011-1/+3
| | | | | | | | | | | | | | | | Nothing exciting; Linux just didn't know it yet so this is most adding a value to a case statement. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | [MIPS] Fix marking buddy of pte global for MIPS32 w/36-bit physical addressSergei Shtylyov2006-06-011-39/+49
|/ | | | | | | | | | | | | | | | | | In case of CONFIG_64BIT_PHYS_ADDR, set_pte() and pte_clear() functions only set _PAGE_GLOBAL bit in the pte_low field of the buddy PTEs, forgetting to propagate ito to pte_high. Thus, the both pages might not really be made global for the CPU (since it AND's the G-bit of the odd / even PTEs together to decide whether they're global or not). Thus, if only a single page is allocated via vmalloc() or ioremap(), it's not really global for CPU (and it must be, since this is kernel mapping), and thus its ASID is compared against the current process' one -- so, we'll get into trouble sooner or later... Also, pte_none() will fail on global pages because _PAGE_GLOBAL bit is set in both pte_low and pte_high, and pte_val() will return u64 value consisting of those fields concateneted. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] 24K LV: Add core card id.Chris Dearman2006-04-271-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix bitops for MIPS32/MIPS64 CPUs.Atsushi Nemoto2006-04-271-32/+24
| | | | | | | | | | With recent rewrite for generic bitops, fls() for 32bit kernel with MIPS64_CPU is broken. Also, ffs(), fls() should be defined the same way as the libc and compiler built-in routines (returns int instead of unsigned long). Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Handle IDE PIO cache aliases on SMP.Ralf Baechle2006-04-192-2/+45
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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