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* [SPARC64]: Fix sparse warnings in arch/sparc64/kernel/irq.cDavid S. Miller2008-03-261-0/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: __inline__ --> inlineDavid S. Miller2007-10-271-6/+5
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: virt_irq --> bucket mapping no longer necessaryDavid S. Miller2007-10-141-2/+1
| | | | | | | We used to need this to compute virt_irq --> ino, but that is no longer necessary. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill ugly __irq_ino() macro.David S. Miller2007-10-141-1/+3
| | | | | | | | We have a place to stick INO information in the virt_to_real_irq_table[], which is currently only used for VIRQs. And that is readily accessible from the one __irq_ino() call site. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Make IVEC pointers 64-bit.David S. Miller2007-10-141-1/+1
| | | | | | | | | | | | | | | Currently we chain IVEC entries using 32-bit "pointers" because we know that the ivector_table is in the main kernel image, thus below 4GB. This uses proper 64-bit pointers instead. Whilst this bloats up the kernel image size, this sets the infrastructure necessary to significantly shrink the kernel size by using physical addresses and dynamically allocating the ivector table. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Consolidate MSI support code.David S. Miller2007-10-141-2/+4
| | | | | | | | | | | | | | | | This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Enable MSI on sun4u Fire PCI-E controllers.David S. Miller2007-10-141-0/+6
| | | | | | | | The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix several bugs in MSI handling.David S. Miller2007-08-311-0/+3
| | | | | | | | | | | | | | | | | | | | | 1) sun4{u,v}_build_msi() have improper return value handling. We should always return negative error codes, instead of using the magic value "0" which could in fact be a valid MSI number. 2) sun4{u,v}_build_msi() should return -ENOMEM instead of calling prom_prom() halt with kzalloc() of the interrupt data fails. 3) We 'remembered' the MSI number using a singleton in the struct device archdata area, this doesn't work for MSI-X which can cause multiple MSIs assosciated with one device. Delete that archdata member, and instead store the MSI number in the IRQ chip data area. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix type and constant sizes wrt. sun4u IMAP/ICLR handling.David S. Miller2007-08-311-11/+11
| | | | | | | | Sometimes we were using 32-bit values and the top bits were getting inadvertantly chopped off. This will matter for the forthcoming Fire controller MSI support. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: dr-cpu unconfigure support.David S. Miller2007-07-161-0/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Wire up cookie based sun4v interrupt registry.David S. Miller2007-06-131-0/+1
| | | | | | This will be used for logical domain channel interrupts. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add PCI MSI support on Niagara.David S. Miller2007-02-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is kind of hokey, we could use the hardware provided facilities much better. MSIs are assosciated with MSI Queues. MSI Queues generate interrupts when any MSI assosciated with it is signalled. This suggests a two-tiered IRQ dispatch scheme: MSI Queue interrupt --> queue interrupt handler MSI dispatch --> driver interrupt handler But we just get one-level under Linux currently. What I'd like to do is possibly stick the IRQ actions into a per-MSI-Queue data structure, and dispatch them form there, but the generic IRQ layer doesn't provide a way to do that right now. So, the current kludge is to "ACK" the interrupt by processing the MSI Queue data structures and ACK'ing them, then we run the actual handler like normal. We are wasting a lot of useful information, for example the MSI data and address are provided with ever MSI, as well as a system tick if available. If we could pass this into the IRQ handler it could help with certain things, in particular for PCI-Express error messages. The MSI entries on sparc64 also tell you exactly which bus/device/fn sent the MSI, which would be great for error handling when no registered IRQ handler can service the interrupt. We override the disable/enable IRQ chip methods in sun4v_msi, so we have to call {mask,unmask}_msi_irq() directly from there. This is another ugly wart. Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6Linus Torvalds2006-06-211-84/+12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [SPARC64]: Update defconfig. [SPARC64]: Don't double-export synchronize_irq. [SPARC64]: Move over to GENERIC_HARDIRQS. [SPARC64]: Virtualize IRQ numbers. [SPARC64]: Kill ino_bucket->pil [SPARC]: Kill __irq_itoa(). [SPARC64]: bp->pil can never be zero [SPARC64]: Send all device interrupts via one PIL. [SPARC]: Fix iommu_flush_iotlb end address [SPARC]: Mark smp init functions as cpuinit [SPARC]: Add missing rw can_lock macros [SPARC]: Setup cpu_possible_map [SPARC]: Add topology_init()
| * [SPARC64]: Move over to GENERIC_HARDIRQS.David S. Miller2006-06-201-75/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the long overdue conversion of sparc64 over to the generic IRQ layer. The kernel image is slightly larger, but the BSS is ~60K smaller due to the reduced size of struct ino_bucket. A lot of IRQ implementation details, including ino_bucket, were moved out of asm-sparc64/irq.h and are now private to arch/sparc64/kernel/irq.c, and most of the code in irq.c totally disappeared. One thing that's different at the moment is IRQ distribution, we do it at enable_irq() time. If the cpu mask is ALL then we round-robin using a global rotating cpu counter, else we pick the first cpu in the mask to support single cpu targetting. This is similar to what powerpc's XICS IRQ support code does. This works fine on my UP SB1000, and the SMP build goes fine and runs on that machine, but lots of testing on different setups is needed. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Virtualize IRQ numbers.David S. Miller2006-06-201-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Inspired by PowerPC XICS interrupt support code. All IRQs are virtualized in order to keep NR_IRQS from needing to be too large. Interrupts on sparc64 are arbitrary 11-bit values, but we don't need to define NR_IRQS to 2048 if we virtualize the IRQs. As PCI and SBUS controller drivers build device IRQs, we divy out virtual IRQ numbers incrementally starting at 1. Zero is a special virtual IRQ used for the timer interrupt. So device drivers all see virtual IRQs, and all the normal interfaces such as request_irq(), enable_irq(), etc. translate that into a real IRQ number in order to configure the IRQ. At this point knowledge of the struct ino_bucket is almost entirely contained within arch/sparc64/kernel/irq.c There are a few small bits in the PCI controller drivers that need to be swept away before we can remove ino_bucket's definition out of asm-sparc64/irq.h and privately into kernel/irq.c Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Kill ino_bucket->pilDavid S. Miller2006-06-201-6/+5
| | | | | | | | | | | | | | | | | | | | | | And reuse that struct member for virt_irq, which will be used in future changesets for the implementation of mapping between real and virtual IRQ numbers. This nicely kills off a ton of SBUS and PCI controller PIL assignment code which is no longer necessary. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC]: Kill __irq_itoa().David S. Miller2006-06-201-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This ugly hack was long overdue to die. It was a way to print out Sparc interrupts in a more freindly format, since IRQ numbers were arbitrary opaque 32-bit integers which vectored into PIL levels. These 32-bit integers were not necessarily in the 0-->NR_IRQS range, but the PILs they vectored to were. The idea now is that we will increase NR_IRQS a little bit and use a virtual<-->real IRQ number mapping scheme similar to PowerPC. That makes this IRQ printing hack irrelevant, and furthermore only a handful of drivers actually used __irq_itoa() making it even less useful. Signed-off-by: David S. Miller <davem@davemloft.net>
* | Don't include linux/config.h from anywhere else in include/David Woodhouse2006-04-261-1/+0
|/ | | | Signed-off-by: David Woodhouse <dwmw2@infradead.org>
* [SPARC64]: Fix uniprocessor IRQ targetting on SUN4V.David S. Miller2006-03-201-0/+3
| | | | | | | | | | | We need to use the real hardware processor ID when targetting interrupts, not the "define to 0" thing the uniprocessor build gives us. Also, fill in the Node-ID and Agent-ID fields properly on sun4u/Safari. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Generic sun4v_build_irq().David S. Miller2006-03-201-0/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add support for IRQ pre-handlers.David S. Miller2005-07-041-29/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows a PCI controller to shim into IRQ delivery so that DMA queues can be drained, if necessary. If some bus specific code needs to run before an IRQ handler is invoked, the bus driver simply needs to setup the function pointer in bucket->irq_info->pre_handler and the two args bucket->irq_info->pre_handler_arg[12]. The Schizo PCI driver is converted over to use a pre-handler for the DMA write-sync processing it needs when a device is behind a PCI->PCI bus deeper than the top-level APB bridges. While we're here, clean up all of the action allocation and handling. Now, we allocate the irqaction as part of the bucket->irq_info area. There is an array of 4 irqaction (for PCI irq sharing) and a bitmask saying which entries are active. The bucket->irq_info is allocated at build_irq() time, not at request_irq() time. This simplifies request_irq() and free_irq() tremendously. The SMP dynamic IRQ retargetting code got removed in this change too. It was disabled for a few months now, and we can resurrect it in the future if we want. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Get rid of fast IRQ feature.David S. Miller2005-06-281-6/+1
| | | | | | | | | | | The only real user was the assembler floppy interrupt handler, which does not need to be in assembly. This makes it so that there are less pieces of code which know about the internal layout of ivector_table[] and friends. Signed-off-by: David S. Miller <davem@davemloft.net>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-171-0/+157
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!