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path: root/include/drm/i915_pciids.h (unfollow)
Commit message (Expand)AuthorFilesLines
2023-02-06drm/i915: Add another EHL pci idJonathan Gray1-0/+1
2023-02-06drm/i915/hwmon: Enable PL1 power limitAshutosh Dixit1-0/+5
2023-02-03drm/i915/dsb: Introduce intel_dsb_finish()Ville Syrjälä3-4/+9
2023-02-03drm/i915/dsb: Split intel_dsb_wait() from intel_dsb_commit()Ville Syrjälä3-3/+13
2023-02-03drm/i915/dsb: Pimp debug/error printsVille Syrjälä1-4/+8
2023-02-03drm/i915/fbdev: Implement fb_dirty for intel custom fb helperJouni Högander1-0/+12
2023-02-02drm/i915/dmc: check incoming dmc id validityJani Nikula1-2/+6
2023-02-02drm/i915/dmc: add is_valid_dmc_id() and use itJani Nikula1-1/+6
2023-02-02drm/i915/dmc: remove unnecessary dmc_id validity checkJani Nikula1-5/+0
2023-02-02drm/i915/dmc: add for_each_dmc_id() and use itJani Nikula1-6/+9
2023-02-02drm/i915/dmc: add proper name to dmc id enum and use itJani Nikula2-40/+39
2023-02-01drm/i915: Expose SAGV state via debugfsVille Syrjälä3-7/+28
2023-02-01drm/i915: Keep sagv status updated on icl+Ville Syrjälä1-20/+29
2023-02-01drm/i915: Introduce HAS_SAGV()Ville Syrjälä2-4/+5
2023-02-01drm/i915: Don't do the WM0->WM1 copy w/a if WM1 is already enabledVille Syrjälä1-1/+2
2023-01-31drm/i915/lvds: s/pipe_config/crtc_state/Ville Syrjälä1-23/+23
2023-01-31drm/i915/lvds: s/intel_encoder/encoder/ etc.Ville Syrjälä1-70/+64
2023-01-31drm/i915/lvds: s/dev_priv/i915/Ville Syrjälä1-57/+54
2023-01-31drm/i915/lvds: Fix whitespaceVille Syrjälä1-14/+14
2023-01-31drm/i915/lvds: Extract intel_lvds_regs.hVille Syrjälä8-54/+71
2023-01-31drm/i915/lvds: Use REG_BIT() & co.Ville Syrjälä2-26/+24
2023-01-31drm/i915/lvds: Use intel_de_rmw()Ville Syrjälä1-8/+4
2023-01-31drm/i915/lvds: Split long linesVille Syrjälä1-3/+7
2023-01-31drm/i915: Implement workaround for CDCLK PLL disable/enableStanislav Lisovskiy1-2/+13
2023-01-31drm/i915/hdmi: Go for scrambling only if platform supports TMDS clock > 340MHzAnkit Nautiyal1-1/+20
2023-01-30drm/i915/dg1: Drop final use of IS_DG1_GRAPHICS_STEPMatt Roper2-4/+1
2023-01-30drm/i915/dg1: Drop support for pre-production steppingsMatt Roper5-59/+5
2023-01-30drm/i915/tgl: Drop support for pre-production steppingsMatt Roper7-83/+7
2023-01-30drm/i915: implement async_flip mode per plane trackingAndrzej Hajda5-4/+19
2023-01-30drm/i915/psr: Split sel fetch plane configuration into arm and noarmJouni Högander4-23/+42
2023-01-30drm/i915/display/dsi: use intel_de_rmw if possibleAndrzej Hajda1-174/+82
2023-01-30drm/i915/display/vlv: use intel_de_rmw if possibleAndrzej Hajda2-109/+41
2023-01-30drm/i915/display/vlv: fix pixel overlap register updateAndrzej Hajda1-15/+9
2023-01-30drm/i915/display/fdi: use intel_de_rmw if possibleAndrzej Hajda1-104/+44
2023-01-30drm/i915/adlp: Fix typo for reference clockChaitanya Kumar Borah1-1/+1
2023-01-27drm/i915/pxp: Pxp hw init should be in resume_completeAlan Previn3-6/+22
2023-01-27drm/i915/pxp: Trigger the global teardown for before suspendingAlan Previn5-13/+66
2023-01-27drm/i915/pxp: Invalidate all PXP fw sessions during teardownAlan Previn5-0/+56
2023-01-27mei: clean pending read with vtag on busAlexander Usyskin1-1/+3
2023-01-27drm/i915/pxp: add device link between i915 and mei_pxpAlexander Usyskin2-0/+14
2023-01-27mei: mei-me: resume device in prepareAlexander Usyskin1-1/+19
2023-01-27drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()Lucas De Marchi1-4/+5
2023-01-27drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()Lucas De Marchi1-3/+5
2023-01-27drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()Lucas De Marchi1-1/+3
2023-01-27drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()Lucas De Marchi1-3/+3
2023-01-27drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()Lucas De Marchi2-10/+9
2023-01-27drm/i915: Convert pll macros to _PICK_EVEN_2RANGESLucas De Marchi2-31/+29
2023-01-27drm/i915: Fix coding style on DPLL*_ENABLE definesLucas De Marchi1-10/+10
2023-01-27drm/i915: Add _PICK_EVEN_2RANGES()Lucas De Marchi1-0/+29
2023-01-26drm/i915/mtl: Apply Wa_14013475917 for all MTL steppingsJouni Högander1-3/+1
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