| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: socfpga: stratix10: add additional clocks needed for the NAND IP | Dinh Nguyen | 2019-06-25 | 1 | -1/+3 |
| * | dt-bindings: documentation: add clock bindings information for Stratix10 | Dinh Nguyen | 2018-04-06 | 1 | -0/+84 |
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