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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: dts: Add dra7 iodelay configurationTony Lindgren2017-08-101-0/+3
| | | | | | | | Add dra7 iodelay configuration. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* pinctrl: Move am4372 and dra7 macros to the the SoC header filesJavier Martinez Canillas2015-11-301-0/+6
| | | | | | | | | | | | | | | | | The <dt-bindings/pinctrl/omap.h> header file defines a set of macros for different SoCs families that falls under the OMAP sub-arch, that allow to define the padconf register physical address instead of the register offset from the padconf base. But the am43xx and dra7xx SoCs families have their own pinctrl header file so the DTS using these SoCs aren't able to use the AM4372_IOPAD() and DRA7XX_CORE_IOPAD() macros since <dt-bindings/pinctrl/omap.h> is not included. Move the macros to the correct header files so can be used by the DTS. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* pinctrl: dra: dt-bindings: Add virtual mode configuration optionNishanth Menon2015-07-141-0/+20
| | | | | | | | | | | | | | | | | | In addition to the regular mux configuration such as mux mode 1, 2 etc, certain pins of DRA7 require to have "virtual mode" also programmed. This allows for predefined delay characteristics to be used by the SoC to meet timing characterstics needed for the interface. Provide easy to use macro to do the same. It is important to note that the official TI guidelines recommend to do as minimal pin reconfiguration beyond the bootloader given the design of the hardware involved which can result in substantial glitches which may impair functionality of certain peripherals. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* pinctrl: dra: dt-bindings: Fix output pull up/downRoger Quadros2014-11-101-2/+2
| | | | | | | | | | | | | | For PIN_OUTPUT_PULLUP and PIN_OUTPUT_PULLDOWN we must not set the PULL_DIS bit which disables the PULLs. PULL_ENA is a 0 and using it in an OR operation is a NOP, so don't use it in the PIN_OUTPUT_PULLUP/DOWN macros. Fixes: 23d9cec07c58 ("pinctrl: dra: dt-bindings: Fix pull enable/disable") Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* pinctrl: dra: dt-bindings: Fix pull enable/disableNishanth Menon2014-07-231-3/+4
| | | | | | | | | | | | | | | | | | | | | The DRA74/72 control module pins have a weak pull up and pull down. This is configured by bit offset 17. if BIT(17) is 1, a pull up is selected, else a pull down is selected. However, this pull resisstor is applied based on BIT(16) - PULLUDENABLE - if BIT(18) is *0*, then pull as defined in BIT(17) is applied, else no weak pulls are applied. We defined this in reverse. Reference: Table 18-5 (Description of the pad configuration register bits) in Technical Reference Manual Revision (DRA74x revision Q: SPRUHI2Q Revised June 2014 and DRA72x revision F: SPRUHP2F - Revised June 2014) Fixes: 6e58b8f1daaf1a ("ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board") Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Felipe Balbi <balbi@ti.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm boardR Sricharan2013-10-081-0/+50
Add minimal device tree source needed for DRA7 based SoCs. Also add a board dts file for the dra7-evm (based on dra752) which contains 1.5G of memory with 1G interleaved and 512MB non-interleaved. Also added in the board file are pin configuration details for i2c, mcspi and uart devices on board. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Benoit Cousson <bcousson@baylibre.com>