summaryrefslogtreecommitdiffstats
path: root/include/dt-bindings (follow)
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'soc-drivers-6.7' of ↵Linus Torvalds2023-11-021-0/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "The highlights for the driver support this time are - Qualcomm platforms gain support for the Qualcomm Secure Execution Environment firmware interface to access EFI variables on certain devices, and new features for multiple platform and firmware drivers. - Arm FF-A firmware support gains support for v1.1 specification features, in particular notification and memory transaction descriptor changes. - SCMI firmware support now support v3.2 features for clock and DVFS configuration and a new transport for Qualcomm platforms. - Minor cleanups and bugfixes are added to pretty much all the active platforms: qualcomm, broadcom, dove, ti-k3, rockchip, sifive, amlogic, atmel, tegra, aspeed, vexpress, mediatek, samsung and more. In particular, this contains portions of the treewide conversion to use __counted_by annotations and the device_get_match_data helper" * tag 'soc-drivers-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (156 commits) soc: qcom: pmic_glink_altmode: Print return value on error firmware: qcom: scm: remove unneeded 'extern' specifiers firmware: qcom: scm: add a missing forward declaration for struct device firmware: qcom: move Qualcomm code into its own directory soc: samsung: exynos-chipid: Convert to platform remove callback returning void soc: qcom: apr: Add __counted_by for struct apr_rx_buf and use struct_size() soc: qcom: pmic_glink: fix connector type to be DisplayPort soc: ti: k3-socinfo: Avoid overriding return value soc: ti: k3-socinfo: Fix typo in bitfield documentation soc: ti: knav_qmss_queue: Use device_get_match_data() firmware: ti_sci: Use device_get_match_data() firmware: qcom: qseecom: add missing include guards soc/pxa: ssp: Convert to platform remove callback returning void soc/mediatek: mtk-mmsys: Convert to platform remove callback returning void soc/mediatek: mtk-devapc: Convert to platform remove callback returning void soc/loongson: loongson2_guts: Convert to platform remove callback returning void soc/litex: litex_soc_ctrl: Convert to platform remove callback returning void soc/ixp4xx: ixp4xx-qmgr: Convert to platform remove callback returning void soc/ixp4xx: ixp4xx-npe: Convert to platform remove callback returning void soc/hisilicon: kunpeng_hccs: Convert to platform remove callback returning void ...
| * dt-bindings: arm: qcom,ids: Add IDs for IPQ8174 familyRobert Marko2023-09-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | IPQ8174 (Oak) family is part of the IPQ8074 family, but the ID-s for it are missing so lets add them. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Kathiravan T <quic_kathirav@quicinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230901181041.1538999-1-robimarko@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * dt-bindings: arm: qcom,ids: Add SoC ID for QCM6490Luca Weiss2023-09-131-0/+1
| | | | | | | | | | | | | | | | | | | | Add the ID for the Qualcomm QCM6490 SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230830-fp5-initial-v1-7-5a954519bbad@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * dt-bindings: arm: qcom,ids: Add Soc ID for SM7150PDanila Tikhonov2023-09-131-0/+1
| | | | | | | | | | | | | | | | | | Add the ID for the Qualcomm SM7150P SoC. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230913181722.13917-2-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | Merge tag 'pmdomain-v6.7' of ↵Linus Torvalds2023-11-025-1/+110
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm Pull pmdomain updates from Ulf Hansson: - Move Kconfig files into the pmdomain subsystem - Drop use of genpd's redundant ->opp_to_performance_state() callback - amlogic: - Add support for the T7 power-domains controller - Fix mask for the second NNA mem power-domain - bcm: Fixup ASB register read and comparison for bcm2835-power - imx: Fix device link problem for consumers of the pgc power-domain - mediatek: Add support for the MT8365 power domains - qcom: - Add support for the rpmhpds for SC8380XP power-domains - Add support for the rpmhpds for SM8650 power-domains - Add support for the rpmhpd clocks for SM7150 - Add support for the rpmpds for MSM8917 (families) power-domains - starfive: Add support for the JH7110 AON PMU * tag 'pmdomain-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (56 commits) pmdomain: amlogic: Fix mask for the second NNA mem PD domain pmdomain: qcom: rpmhpd: Add SC8380XP power domains pmdomain: qcom: rpmhpd: Add SM8650 RPMh Power Domains dt-bindings: power: rpmpd: Add SC8380XP support dt-bindings: power: qcom,rpmhpd: Add GMXC PD index dt-bindings: power: qcom,rpmpd: document the SM8650 RPMh Power Domains pmdomain: imx: Make imx pgc power domain also set the fwnode pmdomain: qcom: rpmpd: Add QM215 power domains pmdomain: qcom: rpmpd: Add MSM8917 power domains dt-bindings: power: rpmpd: Add MSM8917, MSM8937 and QM215 pmdomain: bcm: bcm2835-power: check if the ASB register is equal to enable pmdomain: qcom: rpmhpd: Drop the ->opp_to_performance_state() callback pmdomain: qcom: rpmpd: Drop the ->opp_to_performance_state() callback pmdomain: qcom: cpr: Drop the ->opp_to_performance_state() callback pmdomain: Use device_get_match_data() pmdomain: ti: add missing of_node_put pmdomain: mediatek: Add support for MT8365 pmdomain: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap pmdomain: mediatek: Add support for WAY_EN operations pmdomain: mediatek: Unify configuration for infracfg and smi ...
| * \ pmdomain: Merge branch genpd_dt into nextUlf Hansson2023-10-261-0/+2
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | Merge the immutable branch genpd_dt into next, to allow the DT bindings to be tested together with new pmdomain changes that are targeted for v6.7. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| | * | dt-bindings: power: qcom,rpmhpd: Add GMXC PD indexSibi Sankar2023-10-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document GMXC (Graphics MXC) power domain index which will be used on SC8380XP SoCs. Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Link: https://lore.kernel.org/r/20231025135943.13854-2-quic_sibis@quicinc.com [Ulf: Re-based to step up the index number] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| | * | dt-bindings: power: qcom,rpmpd: document the SM8650 RPMh Power DomainsNeil Armstrong2023-10-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document the RPMh Power Domains on the SM8650 Platform. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-rpmpd-v1-1-f25d313104c6@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | pmdomain: Merge branch genpd_dt into nextUlf Hansson2023-10-241-0/+21
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | Merge the immutable branch genpd_dt into next, to allow the DT bindings to be tested together with new pmdomain changes that are targeted for v6.7. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| | * | dt-bindings: power: rpmpd: Add MSM8917, MSM8937 and QM215Otto Pflüger2023-10-241-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MSM8917, MSM8937 and QM215 SoCs have VDDCX and VDDMX power domains controlled in voltage level mode. Define the MSM8937 and QM215 power domains as aliases because these SoCs are similar to MSM8917 and may share some parts of the device tree. Also add the compatibles for these SoCs to the documentation, with qcom,msm8937-rpmpd using qcom,msm8917-rpmpd as a fallback compatible because there are no known differences. QM215 is not compatible with these because it uses different regulators. Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231014133823.14088-2-otto.pflueger@abscue.de Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | pmdomain: Merge branch genpd_dt into nextUlf Hansson2023-10-171-0/+19
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | Merge the immutable branch genpd_dt into next, to allow the DT bindings to be tested together with new pmdomain changes that are targeted for v6.7. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| | * | dt-bindings: power: Add MT8365 power domainsFabien Parent2023-10-171-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add power domains dt-bindings for MT8365. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-2-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | dt-bindings: power: Update prefixes for AON power domainChanghuang Liang2023-10-041-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use "JH7110_AON_PD_" prefix for AON power domain for JH7110 SoC. Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230927130734.9921-2-changhuang.liang@starfivetech.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | dt-bindings: power: Add power-domain header for JH7110Changhuang Liang2023-09-141-1/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Add power-domain header for JH7110 SoC, it can use to operate dphy power. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230913-grumbly-rewrite-34c85539f2ed@spud Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * / dt-bindings: power: add Amlogic T7 power domainsxianwei.zhao2023-09-111-0/+63
| |/ | | | | | | | | | | | | | | | | | | | | Add devicetree binding document and related header file for Amlogic T7 secure power domains. Signed-off-by: xianwei.zhao <xianwei.zhao@amlogic.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Lucas Tanure <tanure@linux.com> Link: https://lore.kernel.org/r/20230911025223.3433776-5-xianwei.zhao@amlogic.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | Merge tag 'clk-for-linus' of ↵Linus Torvalds2023-11-017-2/+905
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk driver updates from Stephen Boyd: "Herein lies a smallish collection of clk driver updates and some core clk framework changes for the merge window. The core framework changes are only improving the debugfs interface to allow phase adjustments and report which consumers of a clk there are. These are most likely only of interest to kernel developers. On the clk driver side, it's a ghastly amount of updates with only a handful of new clk drivers. We have a couple new clk drivers for Qualcomm, per usual, and a driver for Renesas, Amlogic, and TI respectively. The updates are spread throughout the clk drivers. Some highlights are fixing kunit tests for different configurations like lockdep and big-endian, avoiding integer overflow in rate settable clks, moving clk_hw_onecell_data to the end of allocations so that drivers don't corrupt their private data, and migrating clk drivers to the regmap maple tree. Otherwise it's the usual fixes to clk drivers that only come along with testing the drivers on real hardware. New Drivers: - Add clock driver for TWL6032 - Initial support for the Qualcomm SM4450 Global Clock Controller and SM4450 RPMh clock controllers - Add Camera Clock Controller on Qualcomm SM8550 - Add support for the Renesas RZ/G3S (R9A08G045) SoC - Add Amlogic s4 main clock controller support Updates: - Make clk kunit tests work with lockdep - Fix clk gate kunit test for big-endian - Convert more than a handful of clk drivers to use regmap maple tree - Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk implementation - Add consumer info to clk debugfs - Fix various clk drivers that have clk_hw_onecell_data not at the end of an allocation - Drop CLK_SET_RATE_PARENT for clocks with fixed-rate GPLLs across a variety of Qualcomm IPQ platforms - Add missing parent of APCS PLL on Qualcomm IPQ6018 - Add I2C QUP6 clk on Qualcomm IPQ6018 but mark it critical to avoid problems with RPM - Implement safe source switching for a53pll and use on Qualcomm IPQ5332 - Add support for Stromer Plus PLLs to Qualcomm clk driver - Switch Qualcomm SM8550 Video and GPU clock controllers to use OLE PLL configure method - Non critical fixes to halt bit checks in Qualcomm clk drivers - Add SMMU GDSC for Qualcomm MSM8998 - Fix possible integer overflow in Qualcomm RCG frequency calculation code - Remove RPM managed clks from Qualcomm MSM8996 GCC driver - Add HFPLL configuration for the three HFPLLs in Qualcomm MSM8976 - Switch Qualcomm MSM8996 CBF clock driver's remove function to return void - Fix missing dependency for s4 clock controllers - Select MXC_CLK when building in the CLK_IMX8QXP - Fixes for error handling paths in i.MX8 ACM driver - Move the clocks check in i.MX8 ACM driver in order to log any error - Drop the unused return value of clk_imx_acm_detach_pm_domains - Drop non-existant IMX8MP_CLK_AUDIOMIX_PDM_ROOT clock - Fix error handling in i.MX8MQ clock driver - Allow a different LCDIF1 clock parent if DT describes it for i.MX6SX - Keep the SCU resource table sorted in the i.MX8DXL rsrc driver - Move the elcdif PLL clock registration above lcd_clk, as it is its parent - Correct some ENET specific clocks for i.MX8DXL platform - Drop the VPU_UART and VPUCORE from i.MX8QM as latest HW revision doesn't have them - Remove "de-featured" MLB support from i.MX8QM/QXP/DXL platforms - Skip registering clocks owned by Cortex-A partition SCU-based platforms - Add CAN_1/2 to i.MX8QM and M4_0, PI_0_PWM_0 and PI_0_I2C_0 to i.MX8QXP resources" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (128 commits) clk: Fix clk gate kunit test on big-endian CPUs clk: si521xx: Increase stack based print buffer size in probe clk: mediatek: fix double free in mtk_clk_register_pllfh() clk: socfpga: agilex: Add bounds-checking coverage for struct stratix10_clock_data clk: socfpga: Fix undefined behavior bug in struct stratix10_clock_data clk: sifive: Allow building the driver as a module clk: analogbits: Allow building the library as a module clk: sprd: Composite driver support offset config clk: Allow phase adjustment from debugfs clk: Show active consumers of clocks in debugfs clk: Use device_get_match_data() clk: visconti: Add bounds-checking coverage for struct visconti_pll_provider clk: visconti: Fix undefined behavior bug in struct visconti_pll_provider clk: cdce925: Extend match support for OF tables clk: si570: Simplify probe clk: si5351: Simplify probe clk: rs9: Use i2c_get_match_data() instead of device_get_match_data() clk: clk-si544: Simplify probe() and is_valid_frequency() clk: si521xx: Use i2c_get_match_data() instead of device_get_match_data() clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILS ...
| | \
| | \
| *-. | Merge branches 'clk-renesas', 'clk-kunit', 'clk-regmap' and ↵Stephen Boyd2023-10-301-0/+242
| |\ \| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-frac-divider' into clk-next - Make clk kunit tests work with lockdep - Fix clk gate kunit test for big-endian - Convert more than a handful of clk drivers to use regmap maple tree - Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk implementation * clk-renesas: (23 commits) clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R() clk: renesas: Add minimal boot support for RZ/G3S SoC clk: renesas: rzg2l: Add divider clock for RZ/G3S clk: renesas: rzg2l: Refactor SD mux driver clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header clk: renesas: rzg2l: Add struct clk_hw_data clk: renesas: rzg2l: Add support for RZ/G3S PLL clk: renesas: rzg2l: Remove critical area clk: renesas: rzg2l: Fix computation formula clk: renesas: rzg2l: Trust value returned by hardware clk: renesas: rzg2l: Lock around writes to mux register clk: renesas: rzg2l: Wait for status bit of SD mux before continuing clk: renesas: rcar-gen3: Extend SDnH divider table dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC clk: renesas: r8a7795: Constify r8a7795_*_clks clk: renesas: r9a06g032: Name anonymous structs clk: renesas: r9a06g032: Fix kerneldoc warning clk: renesas: rzg2l: Use u32 for flag and mux_flags clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields ... * clk-kunit: clk: Fix clk gate kunit test on big-endian CPUs clk: Parameterize clk_leaf_mux_set_rate_parent clk: Drive clk_leaf_mux_set_rate_parent test from clk_ops * clk-regmap: clk: versaclock7: Convert to use maple tree register cache clk: versaclock5: Convert to use maple tree register cache clk: versaclock3: Convert to use maple tree register cache clk: versaclock3: Remove redundant _is_writeable() clk: si570: Convert to use maple tree register cache clk: si544: Convert to use maple tree register cache clk: si5351: Convert to use maple tree register cache clk: si5341: Convert to use maple tree register cache clk: si514: Convert to use maple tree register cache clk: cdce925: Convert to use maple tree register cache * clk-frac-divider: clk: fractional-divider: tests: Add test suite for edge cases clk: fractional-divider: Improve approximation when zero based and export
| | * | dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoCClaudiu Beznea2023-10-051-0/+242
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add documentation for the RZ/G3S CPG. The RZ/G3S CPG module is almost identical to the one available in RZ/G2{L,UL}, the exception being some core clocks as follows: - The SD clock is composed of a mux and a divider, and the divider has some limitations (div = 1 cannot be set if mux rate is 800MHz), - There are 3 SD clocks, - The OCTA and TSU clocks are specific to RZ/G3S, - PLL1/4/6 are specific to RZ/G3S with its own computation formula. Even with this RZ/G3S could use the same bindings as RZ/G2L. Along with documentation bindings for the RZ/G3S (R9A08G045) Clock Pulse Generator (CPG) core clocks, module clocks and resets were added. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-13-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | |
| | \
| *-. \ Merge branches 'clk-debugfs', 'clk-spreadtrum', 'clk-sifive', 'clk-counted' ↵Stephen Boyd2023-10-303-1/+384
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and 'clk-qcom' into clk-next - Add consumer info to clk debugfs - Fix various clk drivers that have clk_hw_onecell_data not at the end of an allocation * clk-debugfs: clk: Allow phase adjustment from debugfs clk: Show active consumers of clocks in debugfs * clk-spreadtrum: clk: sprd: Composite driver support offset config * clk-sifive: clk: sifive: Allow building the driver as a module clk: analogbits: Allow building the library as a module * clk-counted: clk: socfpga: agilex: Add bounds-checking coverage for struct stratix10_clock_data clk: socfpga: Fix undefined behavior bug in struct stratix10_clock_data clk: visconti: Add bounds-checking coverage for struct visconti_pll_provider clk: visconti: Fix undefined behavior bug in struct visconti_pll_provider * clk-qcom: (36 commits) clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks clk: qcom: gcc-ipq6018: add QUP6 I2C clock clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pll clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_config clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pll clk: qcom: clk-alpha-pll: introduce stromer plus ops clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM clk: qcom: videocc-sm8550: switch to clk_lucid_ole_pll_configure clk: qcom: gpucc-sm8550: switch to clk_lucid_ole_pll_configure clk: qcom: Replace of_device.h with explicit includes clk: qcom: smd-rpm: Move CPUSS_GNoC clock to interconnect clk: qcom: cbf-msm8996: Convert to platform remove callback returning void clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src clk: qcom: Add GCC driver support for SM4450 dt-bindings: clock: qcom: Add GCC clocks for SM4450 ...
| | | * Merge branch '20230909123431.1725728-1-quic_ajipan@quicinc.com' into clk-for-6.7Bjorn Andersson2023-09-201-0/+197
| | | |\ | | | | | | | | | | | | | | | | | | | | Merge the SM4450 RPMHCC and GCC through a topic branch, to allow reuse of the defines from the DeviceTree binding in the DeviceTree source.
| | | | * dt-bindings: clock: qcom: Add GCC clocks for SM4450Ajit Pandey2023-09-201-0/+197
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for qcom global clock controller bindings for SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230909123431.1725728-4-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| | | * clk: qcom: mmcc-msm8974: remove ocmemcx_ahb_clkLuca Weiss2023-09-201-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to a commit in the 3.4 vendor kernel sources[0] the ocmemcx_ahb_clk clock "is controlled by RPM and should not be touched by APPS.". [0] https://git.codelinaro.org/clo/la/kernel/msm/-/commit/37df5f2d91b4d5768b37fcaacaeea958dd683ebc And indeed, when using MDSS+GPU+OCMEM on MSM8226 and not using clk_ignore_unused, when Linux tries to disable the clock the device crashes and reboots. And since there's also no evidence of this clock in msm8974 vendor kernel sources, remove the clock for msm8226 and msm8974. Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230902-msm8226-ocmemcx_ahb_clk-remove-v1-1-8124dbde83b9@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| | | * dt-bindings: clock: qcom: Add SM8550 camera clock controllerJagadeesh Kona2023-09-191-0/+187
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree bindings for the camera clock controller on Qualcomm SM8550 platform. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230707035744.22245-2-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| | |
| | \
| *-. \ Merge branches 'clk-doc', 'clk-amlogic', 'clk-mediatek', 'clk-twl' and ↵Stephen Boyd2023-10-303-1/+279
| |\ \ \ | | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-imx' into clk-next - Add clock driver for TWL6032 * clk-doc: clk: linux/clk-provider.h: fix kernel-doc warnings and typos * clk-amlogic: clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILS clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver dt-bindings: clock: document Amlogic S4 SoC peripherals clock controller dt-bindings: clock: document Amlogic S4 SoC PLL clock controller * clk-mediatek: clk: mediatek: fix double free in mtk_clk_register_pllfh() clk: mediatek: clk-mt2701: Add check for mtk_alloc_clk_data clk: mediatek: clk-mt7629: Add check for mtk_alloc_clk_data clk: mediatek: clk-mt7629-eth: Add check for mtk_alloc_clk_data clk: mediatek: clk-mt6797: Add check for mtk_alloc_clk_data clk: mediatek: clk-mt6779: Add check for mtk_alloc_clk_data clk: mediatek: clk-mt6765: Add check for mtk_alloc_clk_data * clk-twl: clk: twl: add clock driver for TWL6032 * clk-imx: clk: imx: imx8qm/qxp: add more resources to whitelist clk: imx: scu: ignore clks not owned by Cortex-A partition clk: imx8: remove MLB support clk: imx: imx8qm-rsrc: drop VPU_UART/VPUCORE clk: imx: imx8qxp: correct the enet clocks for i.MX8DXL clk: imx: imx8qxp: Fix elcdif_pll clock clk: imx: imx8dxl-rsrc: keep sorted in the ascending order clk: imx: imx6sx: Allow a different LCDIF1 clock parent clk: imx: imx8mq: correct error handling path clk: imx8mp: Remove non-existent IMX8MP_CLK_AUDIOMIX_PDM_ROOT clk: imx: imx8: Simplify clk_imx_acm_detach_pm_domains() clk: imx: imx8: Add a message in case of devm_clk_hw_register_mux_parent_data_table() error clk: imx: imx8: Fix an error handling path in imx8_acm_clk_probe() clk: imx: imx8: Fix an error handling path if devm_clk_hw_register_mux_parent_data_table() fails clk: imx: imx8: Fix an error handling path in clk_imx_acm_attach_pm_domains() clk: imx: Select MXC_CLK for CLK_IMX8QXP
| | | * clk: imx8mp: Remove non-existent IMX8MP_CLK_AUDIOMIX_PDM_ROOTAdam Ford2023-10-041-1/+0
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TRM shows there is only one AUDIOMIX PDM Root Clock Select register, and it's called IMX8MP_CLK_AUDIOMIX_PDM_SEL. That selector doesn't appear to have any more children and the MICFIL driver can reference IMX8MP_CLK_AUDIOMIX_PDM_SEL directly without the need for any other. Remove this errant clock, since it doesn't really exist. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230831044431.250338-3-aford173@gmail.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * dt-bindings: clock: document Amlogic S4 SoC peripherals clock controllerYu Tu2023-09-271-0/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the S4 peripherals clock controller dt-bindings in the S4 SoC family. Signed-off-by: Yu Tu <yu.tu@amlogic.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230904075504.23263-3-yu.tu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * dt-bindings: clock: document Amlogic S4 SoC PLL clock controllerYu Tu2023-09-271-0/+43
| |/ | | | | | | | | | | | | | | | | Add the S4 PLL clock controller dt-bindings in the S4 SoC family. Signed-off-by: Yu Tu <yu.tu@amlogic.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230904075504.23263-2-yu.tu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* | dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for ↵Balsam CHIHI2023-10-191-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mt8192 Add LVTS thermal controller definition for MT8192. Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20231017190545.157282-2-bero@baylibre.com
* | dt-bindings: thermal: mediatek: Add LVTS thermal sensors for mt7988Frank Wunderlich2023-10-151-0/+9
|/ | | | | | | | | | Add sensor constants for MT7988. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20230922055020.6436-3-linux@fw-web.de
* Merge tag 'iommu-updates-v6.6' of ↵Linus Torvalds2023-09-021-0/+489
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu updates from Joerg Roedel: "Core changes: - Consolidate probe_device path - Make the PCI-SAC IOVA allocation trick PCI-only AMD IOMMU: - Consolidate PPR log handling - Interrupt handling improvements - Refcount fixes for amd_iommu_v2 driver Intel VT-d driver: - Enable idxd device DMA with pasid through iommu dma ops - Lift RESV_DIRECT check from VT-d driver to core - Miscellaneous cleanups and fixes ARM-SMMU drivers: - Device-tree binding updates: - Add additional compatible strings for Qualcomm SoCs - Allow ASIDs to be configured in the DT to work around Qualcomm's broken hypervisor - Fix clocks for Qualcomm's MSM8998 SoC - SMMUv2: - Support for Qualcomm's legacy firmware implementation featured on at least MSM8956 and MSM8976 - Match compatible strings for Qualcomm SM6350 and SM6375 SoC variants - SMMUv3: - Use 'ida' instead of a bitmap for VMID allocation - Rockchip IOMMU: - Lift page-table allocation restrictions on newer hardware - Mediatek IOMMU: - Add MT8188 IOMMU Support - Renesas IOMMU: - Allow PCIe devices .. and the usual set of cleanups an smaller fixes" * tag 'iommu-updates-v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (64 commits) iommu: Explicitly include correct DT includes iommu/amd: Remove unused declarations iommu/arm-smmu-qcom: Add SM6375 SMMUv2 iommu/arm-smmu-qcom: Add SM6350 DPU compatible iommu/arm-smmu-qcom: Add SM6375 DPU compatible iommu/arm-smmu-qcom: Sort the compatible list alphabetically dt-bindings: arm-smmu: Fix MSM8998 clocks description iommu/vt-d: Remove unused extern declaration dmar_parse_dev_scope() iommu/vt-d: Fix to convert mm pfn to dma pfn iommu/vt-d: Fix to flush cache of PASID directory table iommu/vt-d: Remove rmrr check in domain attaching device path iommu: Prevent RESV_DIRECT devices from blocking domains dmaengine/idxd: Re-enable kernel workqueue under DMA API iommu/vt-d: Add set_dev_pasid callback for dma domain iommu/vt-d: Prepare for set_dev_pasid callback iommu/vt-d: Make prq draining code generic iommu/vt-d: Remove pasid_mutex iommu/vt-d: Add domain_flush_pasid_iotlb() iommu: Move global PASID allocation from SVA to core iommu: Generalize PASID 0 for normal DMA w/o PASID ...
| * dt-bindings: mediatek: mt8188: Add binding for MM & INFRA IOMMUChengci.Xu2023-08-071-0/+489
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add descriptions for mt8188 IOMMU which also use ARM Short-Descriptor translation table format. In mt8188, there are two smi-common HW and IOMMU, one is for vdo(video output), the other is for vpp(video processing pipe). They connects with different smi-larbs, then some setting(larbid_remap) is different. Differentiate them with the compatible string. Something like this: IOMMU(VDO) IOMMU(VPP) | | SMI_COMMON_VDO SMI_COMMON_VPP --------------- ---------------- | | ... | | ... larb0 larb2 ... larb1 larb3 ... We also have an IOMMU that is for infra master like PCIe. And infra master don't have the larb and ports. Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com> Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230602090227.7264-2-yong.wu@mediatek.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
* | Merge tag 'char-misc-6.6-rc1' of ↵Linus Torvalds2023-09-016-148/+165
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc driver updates from Greg KH: "Here is the big set of char/misc and other small driver subsystem changes for 6.6-rc1. Stuff all over the place here, lots of driver updates and changes and new additions. Short summary is: - new IIO drivers and updates - Interconnect driver updates - fpga driver updates and additions - fsi driver updates - mei driver updates - coresight driver updates - nvmem driver updates - counter driver updates - lots of smaller misc and char driver updates and additions All of these have been in linux-next for a long time with no reported problems" * tag 'char-misc-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (267 commits) nvmem: core: Notify when a new layout is registered nvmem: core: Do not open-code existing functions nvmem: core: Return NULL when no nvmem layout is found nvmem: core: Create all cells before adding the nvmem device nvmem: u-boot-env:: Replace zero-length array with DECLARE_FLEX_ARRAY() helper nvmem: sec-qfprom: Add Qualcomm secure QFPROM support dt-bindings: nvmem: sec-qfprom: Add bindings for secure qfprom dt-bindings: nvmem: Add compatible for QCM2290 nvmem: Kconfig: Fix typo "drive" -> "driver" nvmem: Explicitly include correct DT includes nvmem: add new NXP QorIQ eFuse driver dt-bindings: nvmem: Add t1023-sfp efuse support dt-bindings: nvmem: qfprom: Add compatible for MSM8226 nvmem: uniphier: Use devm_platform_get_and_ioremap_resource() nvmem: qfprom: do some cleanup nvmem: stm32-romem: Use devm_platform_get_and_ioremap_resource() nvmem: rockchip-efuse: Use devm_platform_get_and_ioremap_resource() nvmem: meson-mx-efuse: Convert to devm_platform_ioremap_resource() nvmem: lpc18xx_otp: Convert to devm_platform_ioremap_resource() nvmem: brcm_nvram: Use devm_platform_get_and_ioremap_resource() ...
| * \ Merge tag 'icc-6.6-rc1' of ↵Greg Kroah-Hartman2023-08-242-0/+20
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next Georgi writes: interconnect changes for 6.6 This pull request contains the interconnect changes for the 6.6-rc1 merge window which is a mix of core and driver changes with the following highlights: Core changes: - New generic test client driver that allows issuing bandwidth requests between endpoints via debugfs. - Annotate all structs with flexible array members with the __counted_by attribute. - Introduce new icc_bw_lock for cases where we need to serialize bandwidth aggregation and update to decouple that from paths that require memory allocation. Driver changes: - Move the Qualcomm SMD RPM bus-clocks from CCF to interconnect framework where they actually belong. This brings power management improvements and reduces the overhead and layering. These changes are in immutable branch that is being pulled also into the qcom tree. - Fixes for QUP nodes on SM8250. - Enable sync_state and keepalive for QCM2290. - Enable sync_state for SM8450. - Improve enable_mask-based BCMs handling and fix some bugs. - Add compatible string for the OSM-L3 on SDM670. - Add compatible strings for SC7180, SM8250 and SM6350 bandwidth monitors. - Expand and retire the DEFINE_QNODE and DEFINE_QBCM macros, which have become ugly beasts with many different arguments. Signed-off-by: Georgi Djakov <djakov@kernel.org> * tag 'icc-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc: (64 commits) interconnect: Add debugfs test client interconnect: Reintroduce icc_get() debugfs: Add write support to debugfs_create_str() interconnect: qcom: icc-rpmh: Retire DEFINE_QBCM interconnect: qcom: sm8350: Retire DEFINE_QBCM interconnect: qcom: sm8250: Retire DEFINE_QBCM interconnect: qcom: sm8150: Retire DEFINE_QBCM interconnect: qcom: sm6350: Retire DEFINE_QBCM interconnect: qcom: sdx65: Retire DEFINE_QBCM interconnect: qcom: sdx55: Retire DEFINE_QBCM interconnect: qcom: sdm845: Retire DEFINE_QBCM interconnect: qcom: sdm670: Retire DEFINE_QBCM interconnect: qcom: sc7180: Retire DEFINE_QBCM interconnect: qcom: icc-rpmh: Retire DEFINE_QNODE interconnect: qcom: sm8350: Retire DEFINE_QNODE interconnect: qcom: sm8250: Retire DEFINE_QNODE interconnect: qcom: sm8150: Retire DEFINE_QNODE interconnect: qcom: sm6350: Retire DEFINE_QNODE interconnect: qcom: sdx65: Retire DEFINE_QNODE interconnect: qcom: sdx55: Retire DEFINE_QNODE ...
| | * \ Merge branch 'icc-sm8250-qup' into icc-nextGeorgi Djakov2023-07-181-0/+7
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SM8250 (like SM8150 but unlike all other QUP-equipped SoCs) doesn't provide a qup-core path. Adjust the bindings and drivers as necessary, and then describe the icc paths in the device tree. This makes it possible for interconnect sync_state succeed so long as you don't use UFS. * icc-sm8250-qup dt-bindings: interconnect: qcom,rpmh: Add SM8250 QUP virt dt-bindings: interconnect: qcom,sm8250: Add QUP virt interconnect: qcom: sm8250: Fix QUP0 nodes Link: https://lore.kernel.org/r/20230703-topic-8250_qup_icc-v2-0-9ba0a9460be2@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
| | | * | dt-bindings: interconnect: qcom,sm8250: Add QUP virtKonrad Dybcio2023-07-161-0/+7
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the required defines for QUP_virt nodes. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230703-topic-8250_qup_icc-v2-2-9ba0a9460be2@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
| * | / dt-bindings: iio: adc: qcom,spmi-adc7: use predefined channel idsDmitry Baryshkov2023-07-205-148/+158
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each of qcom,spmi-adc7-pm*.h headers define a set of ADC channels that can be used for monitoring on thie particular chip. Switch them to use channel IDs defined in the dt-bindings/iio/qcom,spmi-vadc.h header instead of specifying the numeric IDs. Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230707123027.1510723-2-dmitry.baryshkov@linaro.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* | | Merge tag 'clk-for-linus' of ↵Linus Torvalds2023-08-3132-184/+536
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk subsystem updates from Stephen Boyd: "This pull request is full of clk driver changes. In fact, there aren't any changes to the clk framework this time around. That's probably because everyone was on vacation (yours truly included). We did lose a couple clk drivers this time around because nobody was using those devices. That skews the diffstat a bit, but either way, nothing looks out of the ordinary here. The usual suspects are chugging along adding support for more SoCs and fixing bugs. If I had to choose, I'd say the theme for the past few months has been "polish". There's quite a few patches that migrate to devm_platform_ioremap_resource() in here. And there's more than a handful of patches that move the NR_CLKS define from the DT binding header to the driver. There's even patches that migrate drivers to use clk_parent_data and clk_hw to describe clk tree topology. It seems that the spring (summer?) cleaning bug got some folks, or the semiconductor shortage finally hit the software side. New Drivers: - StarFive JH7110 SoC clock drivers - Qualcomm IPQ5018 Global Clock Controller driver - Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK Removed Drivers: - Remove non-OF mmp clk drivers - Remove OXNAS clk driver Updates: - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Move defines for numbers of clks (NR_CLKS) from DT headers to drivers - Introduce kstrdup_and_replace() and use it - Add PLL rates for Rockchip rk3568 - Add the display clock tree for Rockchip rv1126 - Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and RZ/G2 SoCs - Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource() - Fix function name in a comment in ccu_mmc_timing.c - Parameter name correction for ccu_nkm_round_rate() - Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e. consider alternative parent rates when determining clock rates - Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi - Support finding closest (as opposed to closest but not higher) clock rate for NM, NKM, mux and div type clocks, as use it for Allwinner A64 pll-video0 - Prefer current parent rate if able to generate ideal clock rate for Allwinner NKM clocks - Clean up Qualcomm SMD RPM driver, with interconnect bus clocks moved out to the interconnect drivers - Fix various PM runtime bugs across many Qualcomm clk drivers - Migrate Qualcomm MDM9615 is to parent_hw and parent_data - Add network related resets on Qualcomm IPQ4019 - Add a couple missing USB related clocks to Qualcomm IPQ9574 - Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock controller - In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs, and GPLL1 are added, while PCIe pipe clock, SDCC rcg ops are corrected - Add missing GDSCs to and correct GDSCs for the SC8280XP global clock controller driver - Support retention for the Qualcomm SC8280XP display clock controller GDSCs. - Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE to fix issues with missing parent clocks across sc7180, sm7150, sm6350 and sm8250, while sm8450 is corrected to use floor ops - Correct Qualcomm SM6350 GPU clock controller's clock supplies - Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver - Add missing OXILICX GDSC to Qualcomm MSM8226 GCC - Change the delay in the Qualcomm reset controller to fsleep() for correctness - Extend the Qualcomm SM83550 Video clock controller to support SC8280XP - Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and R-Car H3, M3-W, and M3-N SoCs - Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M - Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five - Add the PDM IPC clock for i.MX93 - Add 519.75MHz frequency support for i.MX9 PLL - Simplify the .determine_rate() implementation for i.MX GPR mux - Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource() - Add the audio mux clock to i.MX8 - Fix the SPLL2 MULT range for PLLv4 - Update the SPLL2 type in i.MX8ULP - Fix the SAI4 clock on i.MX8MP - Add silicon revision print for i.MX25 on clocks init - Drop the return value from __mx25_clocks_init() - Fix the clock pauses on no-op set_rate for i.MX8M composite clock - Drop restrictions for i.MX PLL14xx and fix its max prediv value - Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to allow glitch free switching" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (207 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source ...
| * \ \ Merge branch 'clk-qcom' into clk-nextStephen Boyd2023-08-3010-45/+343
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-qcom: (87 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags clk: qcom: gcc-ipq5018: change some variable static clk: qcom: gcc-ipq4019: add missing networking resets dt-bindings: clock: qcom: ipq4019: add missing networking resets clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC clk: qcom: gcc-qdu1000: Update the RCGs ops clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops clk: qcom: gcc-qdu1000: Add support for GDSCs clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock clk: qcom: gcc-qdu1000: Fix clkref clocks handling clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock clk: qcom: ipq5332: drop the mem noc clocks clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks ...
| | * | | dt-bindings: clock: qcom: ipq4019: add missing networking resetsRobert Marko2023-08-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add bindings for the missing networking resets found in IPQ4019 GCC. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230814104119.96858-1-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| | * | | dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRCOtto Pflüger2023-08-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the missing #define for GPLL0_SLEEP_CLK_SRC, the parent clock of GPLL0_EARLY. Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230802170317.205112-2-otto.pflueger@abscue.de Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| | * | | dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCsImran Shaik2023-08-141-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock bindings for QDU1000 and QRU1000 SoCs. While at it, update the maintainers list. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230803105741.2292309-2-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| | * | | Merge branch '20230622-topic-8998clk-v2-1-6222fbc2916b@linaro.org' into ↵Bjorn Andersson2023-08-141-0/+3
| | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-for-6.6 Merge additional MSM8998 GCC DeviceTree binding constants through a topic branch to make them available to the DeviceTree source tree as well.
| | * \ \ \ Merge branch '1690533192-22220-2-git-send-email-quic_srichara@quicinc.com' ↵Bjorn Andersson2023-08-112-0/+305
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into clk-for-6.6 Merge the IPQ5018 GCC Devicetree binding through a topic branch, in order to the the clock defines.
| | * | | | | dt-bindings: clock: drop qcom,lcc-mdm9615 header fileDmitry Baryshkov2023-07-311-44/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same (as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of qcom,lcc-msm8960.h Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230512211727.3445575-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| | * | | | | Merge branch '20230526-topic-smd_icc-v7-0-09c78c175546@linaro.org' into ↵Bjorn Andersson2023-07-151-0/+13
| | |\ \ \ \ \ | | | | |_|_|/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-for-6.6 This series reshuffles things around, moving the management of SMD RPM bus clocks to the interconnect framework where they belong. This helps us solve a couple of issues: 1. We can work towards unused clk cleanup of RPMCC without worrying about it killing some NoC bus, resulting in the SoC dying. Deasserting actually unused RPM clocks (among other things) will let us achieve "true SoC-wide power collapse states", also known as VDD_LOW and VDD_MIN. 2. We no longer have to keep tons of quirky bus clock ifs in the icc driver. You either have a RPM clock and call "rpm set rate" or you have a single non-RPM clock (like AHB_CLK_SRC) or you don't have any. 3. There's less overhead - instead of going through layers and layers of the CCF, ratesetting comes down to calling max() and sending a single RPM message. ICC is very very dynamic so that's a big plus. The clocks still need to be vaguely described in the clk-smd-rpm driver, as it gives them an initial kickoff, before actually telling RPM to enable DVFS scaling. After RPM receives that command, all clocks that have not been assigned a rate are considered unused and are shut down in hardware, leading to the same issue as described in point 1. We can consider marking them __initconst in the future, but this series is very fat even without that.. Apart from that, it squashes a couple of bugs that really need fixing.. The series is merged through a topic branch to manage the dependencies between interconnect, Qualcomm clocks and Qualcomm SoC.
| | | * | | | dt-bindings: interconnect: Add Qcom RPM ICC bindingsKonrad Dybcio2023-07-151-0/+13
| | | | |_|/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SMD RPM interconnect driver requires different icc tags to the RPMh driver. Add bindings to reflect that. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Georgi Djakov <djakov@kernel.org> Link: https://lore.kernel.org/r/20230526-topic-smd_icc-v7-1-09c78c175546@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| | * | | | Merge branch '20230620-topic-sc8280_gccgdsc-v2-2-562c1428c10d@linaro.org' ↵Bjorn Andersson2023-07-101-0/+10
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into clk-for-6.6 Merge a set of new SC8280XP GCC GDSC constants through a topic branch, to allow them being introduce into the DeviceTree source as well.
| | | \ \ \ \
| | \ \ \ \ \
| | \ \ \ \ \
| | \ \ \ \ \
| | \ \ \ \ \
| | \ \ \ \ \
| *-----. \ \ \ \ \ Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and ↵Stephen Boyd2023-08-3018-139/+31
| |\ \ \ \ \ \ \ \ \ | | | | | |_|_|/ / / | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-lmk' into clk-next - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Remove non-OF mmp clk drivers - Move number of clks from DT headers to drivers * clk-imx: clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz clk: imx: pll14xx: align pdiv with reference manual clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op clk: imx25: make __mx25_clocks_init return void clk: imx25: print silicon revision during init dt-bindings: clocks: imx8mp: make sai4 a dummy clock clk: imx8mp: fix sai4 clock clk: imx: imx8ulp: update SPLL2 type clk: imx: pllv4: Fix SPLL2 MULT range clk: imx: imx8: add audio clock mux driver dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource() clk: imx: clk-gpr-mux: Simplify .determine_rate() clk: imx: Add 519.75MHz frequency support for imx9 pll clk: imx93: Add PDM IPG clk dt-bindings: clock: imx93: Add PDM IPG clk * clk-samsung: dt-bindings: clock: samsung: remove define with number of clocks clk: samsung: exynoautov9: do not define number of clocks in bindings clk: samsung: exynos850: do not define number of clocks in bindings clk: samsung: exynos7885: do not define number of clocks in bindings clk: samsung: exynos5433: do not define number of clocks in bindings clk: samsung: exynos5420: do not define number of clocks in bindings clk: samsung: exynos5410: do not define number of clocks in bindings clk: samsung: exynos5260: do not define number of clocks in bindings clk: samsung: exynos5250: do not define number of clocks in bindings clk: samsung: exynos4: do not define number of clocks in bindings clk: samsung: exynos3250: do not define number of clocks in bindings * clk-annotate: clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by clk: Annotate struct clk_hw_onecell_data with __counted_by * clk-marvell: clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source clk: mmp: Remove old non-OF clock drivers * clk-lmk: clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks
| | | | | * | | | | clk: pxa910: Move number of clocks to driver sourceDuje Mihanović2023-08-221-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr> Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-4-f9271bd7eaa5@skole.hr Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | * | | | | clk: pxa1928: Move number of clocks to driver sourceDuje Mihanović2023-08-221-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr> Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-3-f9271bd7eaa5@skole.hr Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 06:26:54 +0100