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* Merge tag 'pinctrl-v6.1-1' of ↵Linus Torvalds2022-10-113-3/+1290
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "There is nothing exciting going on, no core changes, just a few drivers and cleanups. New drivers: - Cypress CY8C95x0 chip pin control support, along with an immediate cleanup - Mediatek MT8188 SoC pin control support - Qualcomm SM8450 and SC8280XP LPASS (low power audio subsystem) pin control support - Qualcomm PM7250, PM8450 - Rockchip RV1126 SoC pin control support Improvements: - Fix some missing pins in the Armada 37xx driver - Convert Broadcom and Nomadik drivers to use PINCTRL_PINGROUP() macro - Fix some GPIO irq_chips to be immutable - Massive Qualcomm device tree binding cleanup, with more to come" * tag 'pinctrl-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (119 commits) MAINTAINERS: adjust STARFIVE JH7100 PINCTRL DRIVER after file movement pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100" pinctrl: Create subdirectory for StarFive drivers dt-bindings: pinctrl: st,stm32: Document interrupt-controller property dt-bindings: pinctrl: st,stm32: Document gpio-hog pattern property dt-bindings: pinctrl: st,stm32: Document gpio-line-names pinctrl: st: stop abusing of_get_named_gpio() pinctrl: wpcm450: Correct the fwnode_irq_get() return value check pinctrl: bcm: Remove unused struct bcm6328_pingroup pinctrl: qcom: restrict drivers per ARM/ARM64 pinctrl: bcm: ns: Remove redundant dev_err call gpio: rockchip: request GPIO mux to pinctrl when setting direction pinctrl: rockchip: add pinmux_ops.gpio_set_direction callback pinctrl: cy8c95x0: Align function names in cy8c95x0_pmxops pinctrl: cy8c95x0: Drop atomicity on operations on push_pull pinctrl: cy8c95x0: Lock register accesses in cy8c95x0_set_mux() pinctrl: sunxi: sun50i-h5: Switch to use dev_err_probe() helper pinctrl: stm32: Switch to use dev_err_probe() helper dt-bindings: qcom-pmic-gpio: Add PM7250B and PM8450 bindings pinctrl: qcom: spmi-gpio: Add compatible for PM7250B ...
| * pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"Jianlong Huang2022-10-041-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Add the SoC name to make it more clear. Also the next generation StarFive SoCs will use "pinctrl-starfive" as the core of StarFive pinctrl driver. No functional change. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220930061404.5418-1-hal.feng@linux.starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'samsung-pinctrl-6.1' of ↵Linus Walleij2022-09-141-0/+7
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.1 1. Minor fix in order of initializing pinctrl driver - GPIOs should be configured before registering gpiolib. 2. Final steps to deprecated bindings headers with register constants. The constants were moved to include files in DTS directories, because these are not suitable for bindings. Remove final references and mark binding header as deprecated to warn any users.
| | * dt-bindings: pinctrl: samsung: deprecate header with register constantsKrzysztof Kozlowski2022-08-191-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For convenience (less code duplication, some meaning added to raw number), the pin controller pin configuration register values were defined in the bindings header. These are not some IDs or other abstraction layer but raw numbers used in the registers These constants do not fit the purpose of bindings. They do not provide any abstraction, any hardware and driver independent ID. With minor exceptions, the Linux drivers actually do not use the bindings header at all. All of the constants were moved already to headers local to DTS (residing in DTS directory) and to Samsung pinctrl driver (where applicable), so remove any references to the bindings header and add a warning tha tit is deprecated. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220816133016.77553-3-krzysztof.kozlowski@linaro.org
| * | dt-bindings: pinctrl: mediatek: add support for mt8188Hui.Liu2022-08-251-0/+1280
| |/ | | | | | | | | | | | | | | | | | | | | Add the pinctrl header file on MediaTek mt8188. Add the new binding document for pinctrl on MediaTek mt8188. Signed-off-by: Hui.Liu <hui.liu@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220818075012.20880-2-hui.liu@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'iommu-updates-v6.1' of ↵Linus Torvalds2022-10-101-0/+95
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu updates from Joerg Roedel: - remove the bus_set_iommu() interface which became unnecesary because of IOMMU per-device probing - make the dma-iommu.h header private - Intel VT-d changes from Lu Baolu: - Decouple PASID and PRI from SVA - Add ESRTPS & ESIRTPS capability check - Cleanups - Apple DART support for the M1 Pro/MAX SOCs - support for AMD IOMMUv2 page-tables for the DMA-API layer. The v2 page-tables are compatible with the x86 CPU page-tables. Using them for DMA-API prepares support for hardware-assisted IOMMU virtualization - support for MT6795 Helio X10 M4Us in the Mediatek IOMMU driver - some smaller fixes and cleanups * tag 'iommu-updates-v6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (59 commits) iommu/vt-d: Avoid unnecessary global DMA cache invalidation iommu/vt-d: Avoid unnecessary global IRTE cache invalidation iommu/vt-d: Rename cap_5lp_support to cap_fl5lp_support iommu/vt-d: Remove pasid_set_eafe() iommu/vt-d: Decouple PASID & PRI enabling from SVA iommu/vt-d: Remove unnecessary SVA data accesses in page fault path dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names iommu: dart: Support t6000 variant iommu/io-pgtable-dart: Add DART PTE support for t6000 iommu/io-pgtable: Add DART subpage protection support iommu/io-pgtable: Move Apple DART support to its own file iommu/mediatek: Add support for MT6795 Helio X10 M4Us iommu/mediatek: Introduce new flag TF_PORT_TO_ADDR_MT8173 dt-bindings: mediatek: Add bindings for MT6795 M4U iommu/iova: Fix module config properly iommu/amd: Fix sparse warning iommu/amd: Remove outdated comment iommu/amd: Free domain ID after domain_flush_pages iommu/amd: Free domain id in error path iommu/virtio: Fix compile error with viommu_capable() ...
| * | dt-bindings: mediatek: Add bindings for MT6795 M4UAngeloGioacchino Del Regno2022-09-261-0/+95
| |/ | | | | | | | | | | | | | | | | | | | | Add bindings for the MediaTek Helio X10 (MT6795) IOMMU/M4U. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20220913151148.412312-2-angelogioacchino.delregno@collabora.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
* | Merge tag 'devicetree-for-6.1' of ↵Linus Torvalds2022-10-101-1/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "DT core: - Fix node refcounting in of_find_last_cache_level() - Constify device_node in of_device_compatible_match() - Fix 'dma-ranges' handling in bus controller nodes - Fix handling of initrd start > end - Improve error reporting in of_irq_init() - Taint kernel on DT unittest running - Use strscpy instead of strlcpy - Add a build target, dt_compatible_check, to check for compatible strings used in kernel sources against compatible strings in DT schemas. - Handle DT_SCHEMA_FILES changes when rebuilding DT bindings: - LED bindings for MT6370 PMIC - Convert Mediatek mtk-gce mailbox, MIPS CPU interrupt controller, mt7621 I2C, virtio,pci-iommu, nxp,tda998x, QCom fastrpc, qcom,pdc, and arm,versatile-sysreg to DT schema format - Add nvmem cells to u-boot,env schema - Add more LED_COLOR_ID definitions - Require 'opp-table' uses to be a node - Various schema fixes to match QEMU 'virt' DT usage - Tree wide dropping of redundant 'Device Tree Binding' in schema titles - More (unevaluated|additional)Properties fixes in schema child nodes - Drop various redundant minItems equal to maxItems" * tag 'devicetree-for-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (62 commits) of: base: Shift refcount decrement in of_find_last_cache_level() dt-bindings: leds: Add MediaTek MT6370 flashlight dt-bindings: leds: mt6370: Add MediaTek MT6370 current sink type LED indicator dt-bindings: mailbox: Convert mtk-gce to DT schema of: base: make of_device_compatible_match() accept const device node of: Fix "dma-ranges" handling for bus controllers of: fdt: Remove unused struct fdt_scan_status dt-bindings: display: st,stm32-dsi: Handle data-lanes in DSI port node dt-bindings: timer: Add power-domains for TI timer-dm on K3 dt: Add a check for undocumented compatible strings in kernel kbuild: take into account DT_SCHEMA_FILES changes while checking dtbs dt-bindings: interrupt-controller: migrate MIPS CPU interrupt controller text bindings to YAML dt-bindings: i2c: migrate mt7621 text bindings to YAML dt-bindings: power: gpcv2: correct patternProperties dt-bindings: virtio: Convert virtio,pci-iommu to DT schema dt-bindings: timer: arm,arch_timer: Allow dual compatible string dt-bindings: arm: cpus: Add kryo240 compatible dt-bindings: display: bridge: nxp,tda998x: Convert to json-schema dt-bindings: nvmem: u-boot,env: add basic NVMEM cells dt-bindings: remoteproc: qcom,adsp: enforce smd-edge schema ...
| * | dt-bindings: leds: Expand LED_COLOR_ID definitionsOlliver Schinagl2022-09-081-1/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 853a78a7d6c7 (dt-bindings: leds: Add LED_COLOR_ID definitions, Sun Jun 9 20:19:04 2019 +0200) the most basic color definitions where added. However, there's a little more very common LED colors. While the documentation states 'add what is missing', engineers tend to be lazy and will just use what currently exists. So this patch will take (a) list from online retailers [0], [1], [2] and use the common LED colors from there, this being reasonable as this is what is currently available to purchase. Note, that LIME seems to be the modern take to 'Yellow-green' or 'Yellowish-green' from some older datasheets. [0]: https://www.digikey.com/en/products/filter/led-lighting-color/125 [1]: https://eu.mouser.com/c/optoelectronics/led-lighting/led-emitters/standard-leds-smd [2]: https://nl.farnell.com/en-NL/c/optoelectronics-displays/led-products/standard-single-colour-leds-under-75ma Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Alexander Dahl <ada@thorsis.com> Acked-by: Jacek Anaszewski <jacek.anaszewski@gmail.com> Link: https://lore.kernel.org/r/20220830134613.1564059-1-oliver@schinagl.nl Signed-off-by: Rob Herring <robh@kernel.org>
* | Merge tag 'v6.1-p1' of ↵Linus Torvalds2022-10-102-0/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 Pull crypto updates from Herbert Xu: "API: - Feed untrusted RNGs into /dev/random - Allow HWRNG sleeping to be more interruptible - Create lib/utils module - Setting private keys no longer required for akcipher - Remove tcrypt mode=1000 - Reorganised Kconfig entries Algorithms: - Load x86/sha512 based on CPU features - Add AES-NI/AVX/x86_64/GFNI assembler implementation of aria cipher Drivers: - Add HACE crypto driver aspeed" * tag 'v6.1-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (124 commits) crypto: aspeed - Remove redundant dev_err call crypto: scatterwalk - Remove unused inline function scatterwalk_aligned() crypto: aead - Remove unused inline functions from aead crypto: bcm - Simplify obtain the name for cipher crypto: marvell/octeontx - use sysfs_emit() to instead of scnprintf() hwrng: core - start hwrng kthread also for untrusted sources crypto: zip - remove the unneeded result variable crypto: qat - add limit to linked list parsing crypto: octeontx2 - Remove the unneeded result variable crypto: ccp - Remove the unneeded result variable crypto: aspeed - Fix check for platform_get_irq() errors crypto: virtio - fix memory-leak crypto: cavium - prevent integer overflow loading firmware crypto: marvell/octeontx - prevent integer overflows crypto: aspeed - fix build error when only CRYPTO_DEV_ASPEED is enabled crypto: hisilicon/qm - fix the qos value initialization crypto: sun4i-ss - use DEFINE_SHOW_ATTRIBUTE to simplify sun4i_ss_debugfs crypto: tcrypt - add async speed test for aria cipher crypto: aria-avx - add AES-NI/AVX/x86_64/GFNI assembler implementation of aria cipher crypto: aria - prepare generic module for optimized implementations ...
| * | dt-bindings: clock: Add AST2500/AST2600 HACE reset definitionNeal Liu2022-08-262-0/+2
| |/ | | | | | | | | | | | | | | | | Add HACE reset bit definition for AST2500/AST2600. Signed-off-by: Neal Liu <neal_liu@aspeedtech.com> Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* | Merge tag 'clk-for-linus' of ↵Linus Torvalds2022-10-0820-2/+2015
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have some late breaking reports that a patch series to rework clk rate range support broke boot on some devices, so I've left that branch out of this. Hopefully we can get to that next week, or punt on it and let it bake another cycle. That means we don't really have any changes to the core framework this time around besides a few typo fixes. Instead this is all clk driver updates and fixes. The usual suspects are here (again), with Qualcomm dominating the diffstat. We look to have gained support for quite a few new Qualcomm SoCs and Dmitry worked on updating many of the existing Qualcomm drivers to use clk_parent_data. After that we have MediaTek drivers getting some much needed updates, in particular to support GPU DVFS. There are also quite a few Samsung clk driver patches, but that's mostly because there was a maintainer change and so last release we missed some of those patches. Overall things look normal, but I'm slowly reviewing core framework code nowadays and that shows given the rate range patches had to be yanked last minute. Let's hope this situation changes soon. New Drivers: - Support for Renesas VersaClock7 clock generator family - Add Spreadtrum UMS512 SoC clk support - New clock drivers for MediaTek Helio X10 MT6795 - Display clks for Qualcomm SM6115, SM8450 - GPU clks for Qualcomm SC8280XP - Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers Deleted Drivers: - Remove DaVinci DM644x and DM646x clk driver support Updates: - Convert Baikal-T1 CCU driver to platform driver - Split reset support out of primary Baikal-T1 CCU driver - Add some missing clks required for RPiVid Video Decoder on RaspberryPi - Mark PLLC critical on bcm2835 - More devm helpers for fixed rate registration - Various PXA168 clk driver fixes - Add resets for MediaTek MT8195 PCIe and USB - Miscellaneous of_node_put() fixes - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock - Convert gpio-clk-gate binding to YAML - Various fixes to AMD/Xilinx Zynqmp clk driver - Graduate AMD/Xilinx "clocking wizard" driver from staging - Add missing DPI1_HDMI clock in MT8195 VDOSYS1 - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195 - Fix GPU clock topology on MT8195 - Propogate rate changes from GPU clock gate up the tree - Clock mux notifiers for GPU-related PLLs - Conversion of more "simple" drivers to mtk_clk_simple_probe() - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers - Fixes to previous |struct clk| to |struct clk_hw| conversion on MediaTek - Shrink MT8192 clock driver by deduplicating clock parent lists - Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk' clocks for i.MX8MP - Drop unnecessary newline in i.MX8MM dt-bindings - Add more MU1 and SAI clocks dt-bindings Ids - Introduce slice busy bit check for i.MX93 composite clock - Introduce white list bit check for i.MX93 composite clock - Add new i.MX93 clock gate - Add MU1 and MU2 clocks to i.MX93 clock provider - Add SAI IPG clocks to i.MX93 clock provider - add generic clocks for U(S)ART available on SAMA5D2 SoCs - reset controller support for Polarfire clocks - .round_rate and .set rate support for clk-mpfs - code cleanup for clk-mpfs - PLL support for PolarFire SoC's Clock Conditioning Circuitry - Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car V4H - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8 - Add I2C clocks and resets on RZ/V2M - Document clock support for the RZ/Five SoC - mux-variant clock using the table variant to select parents - clock controller for the rv1126 soc - conversion of rk3128 to yaml and relicensing of the yaml bindings to gpl2+MIT (following dt-binding guildelines) - Exynos7885: add FSYS, TREX and MFC clock controllers - Exynos850: add IS and AUD (audio) clock controllers with bindings - ExynosAutov9: add FSYS clock controllers with bindings - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock controllers, due to duplicated entries. This is an acceptable ABI break: recently developed/added platform so without legacies, acked by known users/developers - ExynosAutov9: add few missing Peric 0/1 gates - ExynosAutov9: correct register offsets of few Peric 0/1 clocks - Minor code improvements (use of_device_get_match_data() helper, code style) - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he already maintainers that architecture/platform - Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving retention issues during suspend of USB on Qualcomm sc7180/sc7280 and SC8280XP - Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration - Qualcomm SDM660 SDCC1 moved to floor clk ops - Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018 was added/fixed - The Qualcomm MSM8996 CPU clocks are updated with support for ACD - Support for Qualcomm SDM670 GCC and RPMh clks was added - Transition to parent_data, parent_hws and use of ARRAY_SIZE() for num_parents was done for many Qualcomm SoCs - Support for per-reset defined delay on Qualcomm was introduced" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits) clk: qcom: gcc-sm6375: Ensure unsigned long type clk: qcom: gcc-sm6375: Remove unused variables clk: qcom: kpss-xcc: convert to parent data API clk: introduce (devm_)hw_register_mux_parent_data_table API clk: allow building lan966x as a module clk: clk-xgene: simplify if-if to if-else clk: ast2600: BCLK comes from EPLL clk: clocking-wizard: Depend on HAS_IOMEM clk: clocking-wizard: Use dev_err_probe() helper clk: nxp: fix typo in comment clk: pxa: add a check for the return value of kzalloc() clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975 dt-bindings: clock: vc5: Add 5P49V6975 clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe clk: Renesas versaclock7 ccf device driver dt-bindings: Renesas versaclock7 device tree bindings clk: ti: Balance of_node_get() calls for of_find_node_by_name() clk: imx: scu: fix memleak on platform_device_add() fails clk: vc5: Use regmap_{set,clear}_bits() where appropriate ...
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| *-. | Merge branches 'clk-baikal', 'clk-broadcom', 'clk-vc5' and 'clk-versaclock' ↵Stephen Boyd2022-10-041-0/+9
| |\ \| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into clk-next - Convert Baikal-T1 CCU driver to platform driver - Split reset support out of primary Baikal-T1 CCU driver - Add some missing clks required for RPiVid Video Decoder on RaspberryPi - Mark PLLC critical on bcm2835 - Support for Renesas VersaClock7 clock generator family * clk-baikal: clk: baikal-t1: Convert to platform device driver clk: baikal-t1: Add DDR/PCIe directly controlled resets support dt-bindings: clk: baikal-t1: Add DDR/PCIe reset IDs clk: baikal-t1: Move reset-controls code into a dedicated module clk: baikal-t1: Add SATA internal ref clock buffer clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parent clk: baikal-t1: Fix invalid xGMAC PTP clock divider clk: vc5: Fix 5P49V6901 outputs disabling when enabling FOD * clk-broadcom: clk: bcm: rpi: Add support for VEC clock clk: bcm: rpi: Handle pixel clock in firmware clk: bcm: rpi: Add support HEVC clock clk: bcm2835: fix bcm2835_clock_rate_from_divisor declaration clk: bcm2835: Round UART input clock up clk: bcm2835: Make peripheral PLLC critical * clk-vc5: clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975 dt-bindings: clock: vc5: Add 5P49V6975 clk: vc5: Use regmap_{set,clear}_bits() where appropriate clk: vc5: Check IO access results * clk-versaclock: clk: Renesas versaclock7 ccf device driver dt-bindings: Renesas versaclock7 device tree bindings
| | * | dt-bindings: clk: baikal-t1: Add DDR/PCIe reset IDsSerge Semin2022-09-301-0/+9
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aside with a set of the trigger-like resets Baikal-T1 CCU provides additional directly controlled reset signals for the DDR and PCIe controllers. As a preparation before adding these resets support to the kernel let's extent the Baikal-T1 CCU IDs list with the new IDs, which will be used to access the corresponding reset controls. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220929225402.9696-7-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| *-. \ Merge branches 'clk-fixed-rate', 'clk-spreadtrum', 'clk-pxa' and 'clk-ti' ↵Stephen Boyd2022-10-041-0/+6
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into clk-next - More devm helpers for fixed rate registration - Add Spreadtrum UMS512 SoC clk support - Various PXA168 clk driver fixes * clk-fixed-rate: clk: fixed-rate: add devm_clk_hw_register_fixed_rate clk: asm9260: use parent index to link the reference clock * clk-spreadtrum: clk: sprd: Add clocks support for UMS512 * clk-pxa: clk: pxa: add a check for the return value of kzalloc() clk: mmp: pxa168: control shared SDH bits with separate clock dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocks clk: mmp: pxa168: add clocks for SDH2 and SDH3 dt-bindings: marvell,pxa168: add clock id for SDH3 clk: mmp: pxa168: fix GPIO clock enable bits clk: mmp: pxa168: add muxes for more peripherals clk: mmp: pxa168: fix incorrect parent clocks clk: mmp: pxa168: fix const-correctness clk: mmp: pxa168: add new clocks for peripherals dt-bindings: marvell,pxa168: add clock ids for additional dividers clk: mmp: pxa168: fix incorrect dividers clk: mmp: pxa168: add additional register defines * clk-ti: clk: davinci: cfgchip: Use dev_err_probe() helper clk: davinci: pll: fix spelling typo in comment MAINTAINERS: add header file to TI DAVINCI SERIES CLOCK DRIVER
| | | * dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocksDoug Brown2022-09-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are clocks shared by SDH0/1 and SDH2/3, respectively. Signed-off-by: Doug Brown <doug@schmorgal.com> Link: https://lore.kernel.org/r/20220612192937.162952-12-doug@schmorgal.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * dt-bindings: marvell,pxa168: add clock id for SDH3Doug Brown2022-09-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are four SDHC peripherals on the PXA168, but only three of them were present in the DT bindings. This commit adds the fourth. Signed-off-by: Doug Brown <doug@schmorgal.com> Link: https://lore.kernel.org/r/20220612192937.162952-10-doug@schmorgal.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * dt-bindings: marvell,pxa168: add clock ids for additional dividersDoug Brown2022-09-301-0/+3
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a few new clocks divided from PLL1 and CLK32 that are potentially used by a few peripherals with muxed clocks. Signed-off-by: Doug Brown <doug@schmorgal.com> Link: https://lore.kernel.org/r/20220612192937.162952-4-doug@schmorgal.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| *-----. \ Merge branches 'clk-rockchip', 'clk-renesas', 'clk-microchip', ↵Stephen Boyd2022-10-044-2/+663
| |\ \ \ \ \ | | | | |_|/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-allwinner' and 'clk-imx' into clk-next * clk-rockchip: dt-bindings: clock: rockchip: change SPDX-License-Identifier dt-bindings: clock: convert rockchip,rk3128-cru.txt to YAML clk: rockchip: Add clock controller support for RV1126 SoC dt-bindings: clock: rockchip: Document RV1126 CRU clk: rockchip: Add dt-binding header for RV1126 clk: rockchip: Add MUXTBL variant * clk-renesas: clk: renesas: r8a779g0: Add EtherAVB clocks clk: renesas: r8a779g0: Add PFC/GPIO clocks clk: renesas: r8a779g0: Add I2C clocks clk: renesas: r8a779g0: Add watchdog clock dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC clk: renesas: r8a779f0: Add MSIOF clocks clk: renesas: r9a09g011: Add IIC clock and reset entries clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks clk: renesas: r8a779f0: Add CMT clocks clk: renesas: r8a779f0: Add SDH0 clock * clk-microchip: clk: at91: sama5d2: Add Generic Clocks for UART/USART clk: microchip: add PolarFire SoC fabric clock support dt-bindings: clk: add PolarFire SoC fabric clock ids dt-bindings: clk: document PolarFire SoC fabric clocks dt-bindings: clk: rename mpfs-clkcfg binding clk: microchip: mpfs: update module authorship & licencing clk: microchip: mpfs: convert periph_clk to clk_gate clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: add MSS pll's set & round rate MAINTAINERS: add polarfire soc reset controller reset: add polarfire soc reset support clk: microchip: mpfs: add reset controller dt-bindings: clk: microchip: mpfs: add reset controller support clk: microchip: mpfs: make the rtc's ahb clock critical clk: microchip: mpfs: fix clk_cfg array bounds violation * clk-allwinner: clk: sunxi-ng: ccu-sun9i-a80-usb: Use dev_err_probe() helper clk: sunxi-ng: ccu-sun9i-a80-de: Use dev_err_probe() helper clk: sunxi-ng: sun8i-de2: Use dev_err_probe() helper clk: sunxi-ng: d1: Limit PLL rates to stable ranges * clk-imx: clk: imx: scu: fix memleak on platform_device_add() fails clk: imx93: add SAI IPG clk clk: imx93: add MU1/2 clock clk: imx93: switch to use new clk gate API clk: imx: add i.MX93 clk gate clk: imx: clk-composite-93: check white_list clk: imx: clk-composite-93: check slice busy dt-bindings: clock: imx93-clock: add more MU/SAI clocks dt-bindings: clock: imx8mm: don't use multiple blank lines clk: imx8mp: tune the order of enet_qos_root_clk
| | | | | * dt-bindings: clock: imx93-clock: add more MU/SAI clocksPeng Fan2022-09-191-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MU[1,2]_[A,B] clock entries. Add SAI IPG clock entries. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220830033137.4149542-2-peng.fan@oss.nxp.com
| | | | | * dt-bindings: clock: imx8mm: don't use multiple blank linesMarcel Ziswiler2022-09-191-1/+0
| | | | |/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid the following checkpatch warning: include/dt-bindings/clock/imx8mm-clock.h:284: check: Please don't use multiple blank lines Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220722215445.3548530-13-marcel@ziswiler.com
| | | | * dt-bindings: clk: add PolarFire SoC fabric clock idsConor Dooley2022-09-141-0/+23
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each Clock Conditioning Circuitry block contains 2 PLLs and 2 DLLs. The PLLs have 4 outputs each and the DLLs 2. Add 16 new IDs covering these clocks. For more information on the CCC hardware, see the "PolarFire SoC FPGA Clocking Resources" document at the link below. Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220908143651.1252601-4-conor.dooley@microchip.com
| | * / clk: rockchip: Add dt-binding header for RV1126Jagan Teki2022-09-171-0/+632
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the dt-bindings header for the Rockchip RV1126, that gets shared between the clock controller and the clock references in the dts. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20220915163947.1922183-3-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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| *-----. \ Merge branches 'clk-samsung', 'clk-mtk', 'clk-rm', 'clk-ast' and 'clk-qcom' ↵Stephen Boyd2022-10-0417-32/+1577
| |\ \ \ \ \ | | | | | |/ | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into clk-next - Add resets for MediaTek MT8195 PCIe and USB - Remove DaVinci DM644x and DM646x clk driver support * clk-samsung: clk: samsung: MAINTAINERS: add Krzysztof Kozlowski clk: samsung: exynos850: Implement CMU_MFCMSCL domain clk: samsung: exynos850: Implement CMU_IS domain clk: samsung: exynos850: Implement CMU_AUD domain clk: samsung: exynos850: Style fixes clk: samsung: exynosautov9: add fsys1 clock support clk: samsung: exynosautov9: add fsys0 clock support clk: samsung: exynosautov9: correct register offsets of peric0/c1 clk: samsung: exynosautov9: add missing gate clks for peric0/c1 dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL dt-bindings: clock: exynos850: Add Exynos850 CMU_IS dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1 dt-bindings: clock: exynosautov9: add fsys1 clock definitions dt-bindings: clock: exynosautov9: add fys0 clock definitions clk: samsung: exynos7885: Add TREX clocks clk: samsung: exynos7885: Implement CMU_FSYS domain dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 clk: samsung: exynos-clkout: Use of_device_get_match_data() * clk-mtk: (42 commits) clk: mediatek: add driver for MT8365 SoC clk: mediatek: Export required common code symbols clk: mediatek: Provide mtk_devm_alloc_clk_data dt-bindings: clock: mediatek: add bindings for MT8365 SoC clk: mediatek: mt8192: deduplicate parent clock lists clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*() clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes clk: mediatek: mt8183: Add clk mux notifier for MFG mux clk: mediatek: mux: add clk notifier functions clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe clk: mediatek: gate: Export mtk_clk_register_gates_with_dev clk: mediatek: add VDOSYS1 clock dt-bindings: clk: mediatek: Add MT8195 DPI clocks ... * clk-rm: clk: davinci: remove PLL and PSC clocks for DaVinci DM644x and DM646x * clk-ast: clk: ast2600: BCLK comes from EPLL * clk-qcom: (97 commits) clk: qcom: gcc-sm6375: Ensure unsigned long type clk: qcom: gcc-sm6375: Remove unused variables clk: qcom: kpss-xcc: convert to parent data API clk: introduce (devm_)hw_register_mux_parent_data_table API clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-msm8939: use parent_hws where possible dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc8280xp: use retention for USB power domains clk: qcom: gdsc: add missing error handling dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos clk: qcom: Add global clock controller driver for SM6375 dt-bindings: clock: add SM6375 QCOM global clock bindings clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc clk: qcom: gdsc: Fix the handling of PWRSTS_RET support clk: qcom: Add SC8280XP GPU clock controller dt-bindings: clock: Add Qualcomm SC8280XP GPU binding clk: qcom: smd: Add SM6375 clocks ...
| | | | | * dt-bindings: clock: add SM6375 QCOM global clock bindingsKonrad Dybcio2022-09-281-0/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree bindings for global clock controller for SM6375 SoCs. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921001303.56151-2-konrad.dybcio@somainline.org
| | | | | * dt-bindings: clock: Add Qualcomm SC8280XP GPU bindingBjorn Andersson2022-09-271-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add compatible for the Qualcomm SC8280XP GPU. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220926173025.4747-2-quic_bjorande@quicinc.com
| | | | | * dt-bindings: clock: qcom: rpmcc: Add BIMC_FREQ_LOGKonrad Dybcio2022-09-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the missing definition for the aforementioned clock. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921004458.151842-2-konrad.dybcio@somainline.org
| | | | | * dt-bindings: clock: qcom: add bindings for dispcc on SM8450Dmitry Baryshkov2022-09-271-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree bindings for the display clock controller on Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908222850.3552050-2-dmitry.baryshkov@linaro.org
| | | | | * dt-bindings: clock: add QCOM SM6115 display clock bindingsAdam Skladowski2022-09-271-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6115 SoC. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> [bjorn: Minor fix of binding description] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220911164635.182973-2-a39.skl@gmail.com
| | | | | * dt-bindings: clock: add pcm reset for ipq806x lccChristian Marangi2022-09-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pcm reset define for ipq806x lcc. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724182329.9891-1-ansuelsmth@gmail.com
| | | | | * dt-bindings: clock: Add schema for MSM8909 GCCStephan Gerhold2022-09-141-0/+218
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Global Clock Controller (GCC) in the MSM8909 SoC provides clocks, resets and power domains for the various hardware blocks in the SoC. Add a DT schema to describe it, similar to other Qualcomm SoCs. Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220706134132.3623415-2-stephan.gerhold@kernkonzept.com
| | | | | * dt-bindings: clock: gcc-sdm845: add sdm670 global clocksRichard Acayan2022-09-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Snapdragon 670 clocks will be added into the sdm845 gcc driver. Most of the new clocks, GDSCs, and resets already have reserved IDs but there are some resources that don't. Add the new clock from Snapdragon 670 and document the differences between the SoC parent clocks. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220914013922.198778-2-mailingradian@gmail.com
| | | | | * dt-bindings: clock: Add support for external MCLKs for LPASS on SC7280Taniya Das2022-09-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support external mclk to interface external MI2S clocks for SC7280. Fixes: 4185b27b3bef ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280") Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1662005846-4838-5-git-send-email-quic_c_skakit@quicinc.com
| | | | | * dt-bindings: clock: Add resets for LPASS audio clock controller for SC7280Taniya Das2022-09-131-0/+5
| | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks for SC7280. Update reg property min/max items in YAML schema. Fixes: 4185b27b3bef ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280") Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1662005846-4838-4-git-send-email-quic_c_skakit@quicinc.com
| | | * | dt-bindings: clock: mediatek: add bindings for MT8365 SoCFabien Parent2022-10-011-0/+373
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the clock bindings for the MediaTek MT8365 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220822152652.3499972-2-msp@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * | dt-bindings: clk: mediatek: Add MT8195 DPI clocksPablo Sun2022-09-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expand dt-bindings slot for VDOSYS1 of MT8195. This clock is required by the DPI1 hardware and is a downstream of the HDMI pixel clock. Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220919-v1-1-4844816c9808@baylibre.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
| | | * | dt-bindings: reset: Add bindings for MT6795 Helio X10 reset controllersAngeloGioacchino Del Regno2022-09-261-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the reset controller bindings for MT6795. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220921091455.41327-4-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
| | | * | dt-bindings: clock: Add MediaTek Helio X10 MT6795 clock bindingsAngeloGioacchino Del Regno2022-09-261-0/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the bindings for MT6795's clock controller. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220921091455.41327-3-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
| | | * | dt-bindings: reset: mt8195: Add resets for USB/PCIe t-phy port 1AngeloGioacchino Del Regno2022-09-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the reset index for USBSIF P1 (T-PHY port 1), used as either USB or PCI-Express PHY reset. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220720102817.237483-2-angelogioacchino.delregno@collabora.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * | dt-bindings: reset: mt8195: Add resets for PCIE controllersAngeloGioacchino Del Regno2022-09-011-0/+2
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the reset index for PCIe P0 and P1 (PCIe0, PCIe1) on MT8195. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220629105205.173471-2-angelogioacchino.delregno@collabora.com Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | dt-bindings: clock: Move versaclock.h to dt-bindings/clockLukas Bulwahn2022-08-231-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the clock related dt-binding header files are located in dt-bindings/clock folder. It would be good to keep all the similar header files at a single location. This was discovered while investigating the state of ownership of the files in include/dt-bindings/ according to the MAINTAINERS file. This change here is similar to commit 8e28918a85a0 ("dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock") and commit 35d35aae8177 ("dt-bindings: clock: Move at91.h to dt-bindigs/clock"). Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220613081632.2159-3-lukas.bulwahn@gmail.com Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | | dt-bindings: clock: Move lochnagar.h to dt-bindings/clockLukas Bulwahn2022-08-231-0/+0
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the clock-related dt-binding header files are located in include/dt-bindings/clock. It would be good to keep all the similar header files at a single location. This was discovered while investigating the state of ownership of the files in include/dt-bindings/ according to the MAINTAINERS file. This change here is similar to commit 8e28918a85a0 ("dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock") and commit 35d35aae8177 ("dt-bindings: clock: Move at91.h to dt-bindigs/clock"). Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220613081632.2159-2-lukas.bulwahn@gmail.com Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | | Merge tag 'char-misc-6.1-rc1' of ↵Linus Torvalds2022-10-081-0/+3
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc and other driver updates from Greg KH: "Here is the large set of char/misc and other small driver subsystem changes for 6.1-rc1. Loads of different things in here: - IIO driver updates, additions, and changes. Probably the largest part of the diffstat - habanalabs driver update with support for new hardware and features, the second largest part of the diff. - fpga subsystem driver updates and additions - mhi subsystem updates - Coresight driver updates - gnss subsystem updates - extcon driver updates - icc subsystem updates - fsi subsystem updates - nvmem subsystem and driver updates - misc driver updates - speakup driver additions for new features - lots of tiny driver updates and cleanups All of these have been in the linux-next tree for a while with no reported issues" * tag 'char-misc-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (411 commits) w1: Split memcpy() of struct cn_msg flexible array spmi: pmic-arb: increase SPMI transaction timeout delay spmi: pmic-arb: block access for invalid PMIC arbiter v5 SPMI writes spmi: pmic-arb: correct duplicate APID to PPID mapping logic spmi: pmic-arb: add support to dispatch interrupt based on IRQ status spmi: pmic-arb: check apid against limits before calling irq handler spmi: pmic-arb: do not ack and clear peripheral interrupts in cleanup_irq spmi: pmic-arb: handle spurious interrupt spmi: pmic-arb: add a print in cleanup_irq drivers: spmi: Directly use ida_alloc()/free() MAINTAINERS: add TI ECAP driver info counter: ti-ecap-capture: capture driver support for ECAP Documentation: ABI: sysfs-bus-counter: add frequency & num_overflows items dt-bindings: counter: add ti,am62-ecap-capture.yaml counter: Introduce the COUNTER_COMP_ARRAY component type counter: Consolidate Counter extension sysfs attribute creation counter: Introduce the Count capture component counter: 104-quad-8: Add Signal polarity component counter: Introduce the Signal polarity component counter: interrupt-cnt: Implement watch_validate callback ...
| * | | dt-bindings: iio: adc: at91-sama5d2_adc: add id for temperature channelClaudiu Beznea2022-08-151-0/+3
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Add ID for temperature channel of AT91 SAMA5D2 ADC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220803102855.2191070-17-claudiu.beznea@microchip.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* | | Merge tag 'phy-for-6.1' of ↵Linus Torvalds2022-10-081-0/+1
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "This contains bunch of new device support and one new Sunplus driver along with updates which include another big round of qmp phy conversion. New support: - Qualcomm SC8280XP eDP & DP and USB3 UNI phy (Bjorn Andersson) - Rockchip rk3568 inno dsidphy (Chris Morgan) - ocelot-serdes phy yaml binding (Colin Foster) - Renesas gen2-usb phy yaml binding (Geert Uytterhoeven) - RGMII suport in lan966x driver (Horatiu Vultur) - Qualcomm SM6375 usb snps-femto-v2 bindings (Konrad Dybcio) - Rockchip rk356x csi-dphya (Michael Riesch) - Qualcomm sdm670 usb2 bindings (Richard Acayan) - Sunplus USB2 PHY (Vincent Shih) Updates: - Mediatek hdmi, ufs, tphy and xsphy updates to use bitfield helpers (Chunfeng Yun) - Continued Qualcomm qmp phy driver split and cleanup. More patches are under review and expected that next cycle might see completion of this activity (Dmitry Baryshkov & Johan Hovold) - TI wiz driver support for j7200 10g (Roger Quadros) - Qualcomm femto phy driver support for override params to help with tuning (Sandeep Maheswaram) - SGMII support in TI wiz driver (Siddharth Vadapalli) - dev_err_probe simplification (Yuan Can)" * tag 'phy-for-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (170 commits) phy: phy-mtk-dp: make array driving_params static const dt-bindings: phy: qcom,qusb2: document sdm670 compatible phy: qcom-qmp-pcie: fix resource mapping for SDM845 QHP PHY phy: rockchip-snps-pcie3: only look for rockchip,pipe-grf on rk3588 phy: tegra: xusb: Enable usb role switch attribute phy: mediatek: fix build warning of FIELD_PREP() phy: qcom-qmp-usb: Use dev_err_probe() to simplify code phy: qcom-qmp-ufs: Use dev_err_probe() to simplify code phy: qcom-qmp-pcie-msm8996: Use dev_err_probe() to simplify code phy: qcom-qmp-combo: Use dev_err_probe() to simplify code phy: qualcomm: call clk_disable_unprepare in the error handling phy: intel: Use dev_err_probe() to simplify code phy: tegra: xusb: Use dev_err_probe() to simplify code phy: qcom-snps: Use dev_err_probe() to simplify code phy: qcom-qusb2: Use dev_err_probe() to simplify code phy: qcom-qmp-pcie: Use dev_err_probe() to simplify code phy: ti: phy-j721e-wiz: fix reference leaks in wiz_probe() phy: mediatek: mipi: remove register access helpers phy: mediatek: mipi: mt8183: use common helper to access registers phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask ...
| * | | dt-bindings: phy: Add PHY_TYPE_USXGMII definitionSwapnil Jakhade2022-08-301-0/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add definition for USXGMII phy type. Cc: Rob Herring <robh@kernel.org> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Roger Quadros <rogerq@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220628122255.24265-3-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | | Merge tag 'mfd-next-6.1' of ↵Linus Torvalds2022-10-071-0/+18
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "Core Frameworks: - Fix 'mfd_of_node_list' OF node entry resource leak New Drivers: - Add support for Ocelot VSC7512 Networking Chip - Add support for MediaTek MT6370 subPMIC - Add support for Richtek RT5120 (I2C) PMIC New Device Support: - Add support for Rockchip RV1126 and RK3588 to Syscon - Add support for Rockchip RK817 Battery Charger to RK808 - Add support for Silergy SY7636a Voltage Regulator to Simple MFD - Add support for Qualcomm PMP8074 PMIC to QCOM SPMI - Add support for Secure Update to Intel M10 BMC New Functionality: - Provide SSP type to Intel's LPSS (PCI) SPI driver Fix-ups: - Remove legacy / unused code; stmpe, intel_soc_pmic_crc, syscon - Unify / simplify; intel_soc_pmic_crc - Trivial reordering / spelling, etc; Makefile, twl-core - Convert to managed resources; intel_soc_pmic_crc - Use appropriate APIs; intel_soc_pmic_crc - strscpy() conversion; htc-i2cpld, lpc_ich, mfd-core - GPIOD conversion; htc-i2cpld, stmpe - Add missing header file includes; twl4030-irq - DT goodies; stmpe, mediatek,mt6370, x-powers,axp152, aspeed,ast2x00-scu, mediatek,mt8195-scpsys, qcom,spmi-pmic, syscon, qcom,tcsr, rockchip,rk817, sprd,ums512-glbreg, dlg,da9063 Bug Fixes: - Properly check return values; sm501, htc-i2cpld - Repair Two-Wire Bus Mode; da9062-core - Fix error handling; intel_soc_pmic_core, fsl-imx25-tsadc, lp8788, lp8788-irq" * tag 'mfd-next-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (60 commits) mfd: syscon: Remove repetition of the regmap_get_val_endian() mfd: ocelot-spi: Add missing MODULE_DEVICE_TABLE power: supply: Add charger driver for Rockchip RK817 dt-bindings: mfd: mt6370: Fix the indentation in the example mfd: da9061: Fix Failed to set Two-Wire Bus Mode. mfd: htc-i2cpld: Fix an IS_ERR() vs NULL bug in htcpld_core_probe() dt-bindings: mfd: qcom,tcsr: Drop simple-mfd from IPQ6018 mfd: sm501: Add check for platform_driver_register() dt-bindings: mfd: mediatek: Add scpsys compatible for mt8186 mfd: twl4030: Add missed linux/device.h header dt-bindings: mfd: dlg,da9063: Add missing regulator patterns dt-bindings: mfd: sprd: Add bindings for ums512 global registers mfd: intel_soc_pmic_chtdc_ti: Switch from __maybe_unused to pm_sleep_ptr() etc dt-bindings: mfd: syscon: Add rk3588 QoS register compatible mfd: stmpe: Switch to using gpiod API mfd: qcom-spmi-pmic: Add pm7250b compatible dt-bindings: mfd: Add missing (unevaluated|additional)Properties on child nodes mfd/omap1: htc-i2cpld: Convert to a pure GPIO driver mfd: intel-m10-bmc: Add d5005 bmc secure update driver dt-bindings: mfd: syscon: Drop ref from reg-io-width ...
| * | | dt-bindings: mfd: Add MediaTek MT6370ChiYuan Huang2022-09-281-0/+18
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MediaTek MT6370 binding documentation. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: ChiYuan Huang <cy_huang@richtek.com> Signed-off-by: ChiaEn Wu <chiaen_wu@richtek.com> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20220805070610.3516-7-peterwu.pub@gmail.com
* | | Merge tag 'ata-6.1-rc1' of ↵Linus Torvalds2022-10-071-0/+20
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/libata Pull ata updates from Damien Le Moal: - Print the timeout value for internal command failures due to a timeout (from Tomas) - Improve parameter names in ata_dev_set_feature() to clarify this function use (from Niklas) - Improve the ahci driver low power mode setting initialization to allow more flexibility for the user (from Rafael) - Several patches to remove redundant variables in libata-core, libata-eh and the pata_macio driver and to fix typos in comments (from Jinpeng, Shaomin, Ye) - Some code simplifications and macro renaming (for clarity) in various functions of libata-core (from me) - Add a missing check for a potential failure of sata_scr_read() in sata_print_link_status() (from Li) - Cleanup of libata Kconfig PATA_PLATFORM and PATA_OF_PLATFORM options (from Lukas) - Cleanups of ata dt-bindings and improvements of libahci_platform, ahci and libahci code (from Serge) - New driver for Synopsys AHCI SATA controllers, based of the generic ahci code (from Serge). One compilation warning fix is added for this driver (from me) - Several fixes to macros used to discover a drive capabilities to be consistent with the ACS specifications (from Niklas) - A couple of simplifcations to some libata functions, removing unnecessary arguments (from Niklas) - An improvements to libata-eh code to avoid unnecessary link reset when revalidating a drive after a failed command. In practice, this extra, unneeded reset, reset does not cause any arm beyond slightly slowing down error recovery (from Niklas) * tag 'ata-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/libata: (45 commits) ata: libata-eh: avoid needless hard reset when revalidating link ata: libata: drop superfluous ata_eh_analyze_tf() parameter ata: libata: drop superfluous ata_eh_request_sense() parameter ata: fix ata_id_has_dipm() ata: fix ata_id_has_ncq_autosense() ata: fix ata_id_has_devslp() ata: fix ata_id_sense_reporting_enabled() and ata_id_has_sense_reporting() ata: libata-eh: Remove the unneeded result variable ata: ahci_st: Enable compile test ata: ahci_st: Fix compilation warning MAINTAINERS: Add maintainers for DWC AHCI SATA driver ata: ahci-dwc: Add Baikal-T1 AHCI SATA interface support ata: ahci-dwc: Add platform-specific quirks support dt-bindings: ata: ahci: Add Baikal-T1 AHCI SATA controller DT schema ata: ahci: Add DWC AHCI SATA controller support ata: libahci_platform: Add function returning a clock-handle by id dt-bindings: ata: ahci: Add DWC AHCI SATA controller DT schema ata: ahci: Introduce firmware-specific caps initialization ata: ahci: Convert __ahci_port_base to accepting hpriv as arguments ata: libahci: Don't read AHCI version twice in the save-config method ...
| * | | dt-bindings: ata: ahci: Add platform capability propertiesSerge Semin2022-09-161-0/+20
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case if the platform doesn't have BIOS or a comprehensive firmware installed then the HBA capability flags will be left uninitialized. As a good alternative we suggest to define the DT-properties with the AHCI platform capabilities describing all the HW-init flags of the corresponding capability register. Luckily there aren't too many of them. SSS - Staggered Spin-up support and MPS - Mechanical Presence Switch support determine the corresponding feature availability for the whole HBA by means of the "hba-cap" property. Each port can have the "hba-port-cap" property initialized indicating that the port supports some of the next functionalities: HPCP - HotPlug capable port, MPSP - Mechanical Presence Switch attached to a port, CPD - Cold Plug detection, ESP - External SATA Port (eSATA), FBSCP - FIS-based switching capable port. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 07:46:52 +0100