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2014-11-15drm: Simplify return value handling in drm_crtc.cDaniel Vetter1-17/+9
2014-11-15drm/dp/mst: Handle invalid link bandwidth from DPCD gracefullyChris Wilson1-6/+22
2014-11-15drm/atomic: rip out unnecessary locking checksRob Clark1-4/+0
2014-11-15drm: flip-work: change drm_flip_work_init prototypeBoris BREZILLON6-55/+12
2014-11-15drm: rework flip-work helpers to avoid calling func when the FIFO is fullBoris BREZILLON2-32/+96
2014-11-14drm/i915: Use correct pipe config to update pll dividers. V2Bob Paauwe1-6/+6
2014-11-13drm/tegra: gem: Check before freeing CMA memoryThierry Reding1-1/+1
2014-11-13drm/tegra: fb: Add error codes to error messagesThierry Reding1-4/+7
2014-11-13drm/tegra: fb: Properly release GEM objects on failureThierry Reding1-1/+2
2014-11-13drm/tegra: Detach panel when a connector is removedThierry Reding1-0/+3
2014-11-13drm/tegra: Plug memory leakThierry Reding1-0/+2
2014-11-13drm/tegra: gem: Use more consistent data typesThierry Reding2-8/+8
2014-11-13drm/tegra: fb: Do not destroy framebufferThierry Reding1-1/+1
2014-11-13drm/tegra: gem: dumb: pitch and size are outputsThierry Reding1-7/+3
2014-11-13drm/tegra: Enable the hotplug interrupt only when necessaryThierry Reding1-1/+23
2014-11-13drm/tegra: dc: Universal plane supportThierry Reding1-157/+330
2014-11-13drm/tegra: dc: Registers are 32 bits wideThierry Reding2-7/+6
2014-11-13drm/tegra: dc: Factor out DC, window and cursor commitThierry Reding1-24/+28
2014-11-13drm/tegra: Add IOMMU supportThierry Reding6-34/+309
2014-11-13drm/tegra: Fix error handling cleanupThierry Reding3-7/+34
2014-11-13drm/tegra: gem: Use dma_mmap_writecombine()Thierry Reding1-4/+12
2014-11-13drm/tegra: gem: Remove redundant drm_gem_free_mmap_offset()Thierry Reding1-2/+0
2014-11-13drm/tegra: gem: Cleanup tegra_bo_create_with_handle()Thierry Reding1-8/+6
2014-11-13drm/tegra: gem: Extract tegra_bo_alloc_object()Thierry Reding1-39/+38
2014-11-13drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlierSean Paul1-4/+7
2014-11-13drm/tegra: dsi: Replace 1000000 by USEC_PER_SECThierry Reding1-1/+1
2014-11-13drm/tegra: dsi: Replace 1000000000UL by NSEC_PER_SECThierry Reding1-1/+1
2014-11-13drm/tegra: dsi: Implement host transfersThierry Reding2-1/+279
2014-11-13drm/tegra: dsi: Add ganged mode supportThierry Reding3-29/+195
2014-11-13drm/tegra: dsi: Split out tegra_dsi_set_timeout()Thierry Reding1-15/+23
2014-11-13drm/tegra: dsi: Add command mode supportThierry Reding1-19/+63
2014-11-13drm/tegra: dsi: Refactor in preparation for command modeThierry Reding1-19/+81
2014-11-13drm/tegra: dsi: Properly cleanup on probe failureThierry Reding1-15/+37
2014-11-13drm/tegra: dsi: Mark connector hotpluggableThierry Reding1-2/+4
2014-11-13drm/tegra: dsi: Leave parent clock aloneThierry Reding1-7/+0
2014-11-13drm/tegra: dsi: Do not manage clock on enable/disableThierry Reding1-15/+14
2014-11-13drm/tegra: dsi: Make FIFO depths host parametersThierry Reding1-4/+6
2014-11-13drm/tegra: DPMS off/on in encoder prepare/commitSean Paul1-0/+2
2014-11-13drm/tegra: Do not enable output on .mode_set()Thierry Reding1-6/+0
2014-11-13drm/tegra: dc: Add powergate supportThierry Reding2-3/+43
2014-11-13gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 registerSean Paul1-0/+4
2014-11-13gpu: host1x: mipi: Calibrate clock lanesSean Paul1-32/+92
2014-11-13gpu: host1x: mipi: Preserve the contents of MIPI_CAL_CTRLSean Paul1-1/+3
2014-11-13gpu: host1x: mipi: Registers are 32 bits wideThierry Reding1-8/+8
2014-11-13gpu: host1x: Make gather offsets unsignedThierry Reding1-1/+1
2014-11-13gpu: host1x: Print address/offset pairs consistentlyThierry Reding2-4/+4
2014-11-13gpu: host1x: Fix typo in commentThierry Reding1-1/+1
2014-11-13gpu: host1x: Make mapped field of push buffers void *Thierry Reding3-4/+4
2014-11-13gpu: host1x: Use struct host1x_bo pointers in tracesThierry Reding2-16/+23
2014-11-13drm/tegra: Depend on COMMON_CLKThierry Reding1-0/+1
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