Commit message (Expand) | Author | Files | Lines | |
---|---|---|---|---|
2022-01-19 | net: axienet: increase default TX ring size to 128 | Robert Hancock | 1 | -1/+1 |
2022-01-19 | net: axienet: fix for TX busy handling | Robert Hancock | 1 | -39/+47 |
2022-01-19 | net: axienet: fix number of TX ring slots for available check | Robert Hancock | 1 | -2/+2 |
2022-01-19 | net: axienet: Fix TX ring slot available check | Robert Hancock | 1 | -2/+2 |
2022-01-19 | net: axienet: limit minimum TX ring size | Robert Hancock | 1 | -1/+3 |
2022-01-19 | net: axienet: add missing memory barriers | Robert Hancock | 1 | -1/+10 |
2022-01-19 | net: axienet: reset core on initialization prior to MDIO access | Robert Hancock | 1 | -0/+5 |
2022-01-19 | net: axienet: Wait for PhyRstCmplt after core reset | Robert Hancock | 1 | -0/+10 |
2022-01-19 | net: axienet: increase reset timeout | Robert Hancock | 1 | -10/+9 |
2022-01-19 | bpf, selftests: Add ringbuf memory type confusion test | Daniel Borkmann | 4 | -2/+79 |