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2015-11-17drm/i915: rename intel_power_domains_resume to *_sync_hwImre Deak1-2/+2
2015-11-17drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequencesDamien Lespiau4-4/+35
2015-11-17drm/i915: fix lookup_power_well for power wells without any domainImre Deak1-2/+4
2015-11-17drm/i915: fix the power well ID for always on wellsImre Deak2-1/+5
2015-11-17drm/i915: get runtime PM reference around GEM set_tiling IOCTLImre Deak1-0/+4
2015-11-17drm/i915: Serialise updates to GGTT with access through GGTT on BraswellChris Wilson2-0/+25
2015-11-17drm/i915: force link training when requested by SinkShubhangi Shrivastava1-1/+3
2015-11-17drm/i915: Cleanup test data during long/short hotplugShubhangi Shrivastava1-8/+22
2015-11-17drm/i915/skl: Correct other-pipe watermark update condition check (v2)Kumar, Mahesh1-7/+5
2015-11-16drm/i915: Model PSR AUX register selection more like the normal AUX codeVille Syrjälä1-6/+21
2015-11-16drm/i915: Add dev_priv->psr_mmio_baseVille Syrjälä4-21/+27
2015-11-16drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]Ville Syrjälä2-10/+85
2015-11-16drm/i915: Remove the magic AUX_CTL is at DP + foo tricksVille Syrjälä2-76/+105
2015-11-16drm/i915: Parametrize AUX registersVille Syrjälä3-63/+62
2015-11-16drm/i915: Replace the aux ddc name switch statement with kasprintf()Ville Syrjälä1-29/+46
2015-11-16drm/i915: Replace aux_ch_ctl_reg check with port checkVille Syrjälä1-1/+1
2015-11-13drm/i915/skl: Update DDI translation tables for SKLjim.bride@linux.intel.com1-11/+11
2015-11-13drm/i915: Fix SKL i_boost levelAnder Conselvan de Oliveira1-3/+3
2015-11-12drm/i915/skl: Removed assert for csr-fw-loading check during disabling dc6Animesh Manna1-1/+0
2015-11-12drm/i915/gen9: flush DMC fw loading work during system suspendImre Deak1-0/+3
2015-11-12drm/i915/gen9: Use flush_work to synchronize with dmc loaderAnimesh Manna2-2/+2
2015-11-12drm/i915: Use request_firmware and our own async workDaniel Vetter2-13/+14
2015-11-12drm/i915/gen9: extract parse_csr_fwDaniel Vetter1-19/+31
2015-11-12drm/i915/gen9: Use dev_priv in csr functionsDaniel Vetter4-24/+18
2015-11-12drm/i915/gen9: Don't try to load garbage dmc firmware on resumeDaniel Vetter1-1/+1
2015-11-12drm/i915/gen9: Simplify csr loading failure printing.Daniel Vetter3-23/+4
2015-11-12drm/i915/gen9: Align line continuations in intel_csr.c.Daniel Vetter1-15/+15
2015-11-12drm/i915/gen9: Remove csr.state, csr_lock and related code.Daniel Vetter6-83/+5
2015-11-12drm/i915/gen9: move assert_csr_loaded into intel_rpm.cDaniel Vetter3-11/+8
2015-11-12drm/i915: use correct power domain for csr loadingDaniel Vetter1-2/+2
2015-11-12drm/i915/gen9: csr_init after runtime pm enableAnimesh Manna1-3/+2
2015-11-12drm/i915: refactor stepping info retrievalJani Nikula1-23/+23
2015-11-12drm/i915: constify bxt stepping infoJani Nikula1-1/+1
2015-11-12drm/i915: fix indentation on skl stepping infoJani Nikula1-3/+3
2015-11-12drm/i915: Remove redundant check in i915_gem_obj_to_vmaTvrtko Ursulin1-4/+2
2015-11-11drm/i915: Clean up LVDS register handling harderLukas Wunner1-2/+1
2015-11-11drm/i915: Move the fbdev async_schedule() into intel_fbdev.cVille Syrjälä3-5/+9
2015-11-11drm/i915: Do fbdev fini first during unloadVille Syrjälä1-2/+2
2015-11-11drm/i915: Kill intel_runtime_pm_disable()Ville Syrjälä1-17/+0
2015-11-10drm/i915: Setup DDI clk for MST on SKLVille Syrjälä3-27/+32
2015-11-10drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on()Ville Syrjälä1-26/+19
2015-11-10drm/i915: Use intel_dp->DP in eDP PLL setupVille Syrjälä1-27/+14
2015-11-10drm/i915: Clean up eDP PLL state assertsVille Syrjälä1-15/+39
2015-11-10drm/i915: Remove ILK-A eDP PLL workaround notesVille Syrjälä1-4/+0
2015-11-10drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/Ville Syrjälä2-6/+6
2015-11-10drm/i915: Hide underruns from eDP PLL and port enable on ILKVille Syrjälä1-3/+31
2015-11-10drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaroundVille Syrjälä4-0/+42
2015-11-10drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder()Ville Syrjälä1-1/+1
2015-11-10drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPTVille Syrjälä3-31/+103
2015-11-10drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabledVille Syrjälä1-0/+13
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