linux - linux

	Commit message (Expand)	Author	Files	Lines
2017-04-19	clk: vc5: Add bindings for IDT VersaClock 5P49V5935	Alexey Firago	1	-3/+13
2017-04-19	clk: vc5: Add structure to describe particular chip features	Alexey Firago	1	-18/+47
2017-04-13	clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change	Chen-Yu Tsai	1	-0/+11
2017-04-13	clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks	Chen-Yu Tsai	2	-0/+61
2017-04-13	clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver	Tobias Regnery	1	-0/+1
2017-04-13	clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER	Tobias Regnery	1	-0/+1
2017-04-12	clk: cs2000: use existing priv_to_dev() to getting struct device	Kuninori Morimoto	1	-5/+3
2017-04-12	clk: aggregate return codes of notify chains	Peter De Schrijver	1	-0/+2
2017-04-12	clk: add clk_possible_parents debugfs file	Peter De Schrijver	1	-0/+32
2017-04-12	clk: imx: correct uart4_serial clock name in driver for i.MX6UL	Robin van der Gracht	1	-1/+1
2017-04-12	clk: zte: Mark pll config tables as const	Stephen Boyd	1	-2/+2
2017-04-12	clk: zte: add pll_vga clock for zx296718	Shawn Guo	1	-0/+24
2017-04-12	clk: zte: pd_bit is not 0 on zx296718	Shawn Guo	2	-2/+16
2017-04-12	clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks	Shawn Guo	1	-3/+3
2017-04-12	clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock	Robin van der Gracht	1	-4/+5
2017-04-12	cs-2000-cp: keep Reserved bit on each register	Kuninori Morimoto	1	-3/+22
2017-04-12	clk: qcom: msm8996: Fix the vfe1 powerdomain name	Rajendra Nayak	1	-1/+1
2017-04-12	clk: stm32f4: fix timeout management for pll and ready gate	Gabriel Fernandez	1	-14/+29
2017-04-12	clk: iproc: Remove redundant check	Ray Jui	1	-1/+1
2017-04-12	clk: stm32f4: fix: exclude values 0 and 1 for PLLQ	Gabriel Fernandez	1	-3/+10
2017-04-12	clk: hi6220: add debug APB clock	Leo Yan	2	-1/+5
2017-04-07	clk: meson: mpll: use 64bit math in rate_from_params	Martin Blumenstingl	1	-1/+1
2017-04-07	clk: meson: mpll: fix division by zero in rate_from_params	Martin Blumenstingl	1	-11/+15
2017-04-07	clk: meson: gxbb: add cts_i958 clock	Jerome Brunet	2	-1/+23
2017-04-07	clk: meson: gxbb: add cts_mclk_i958	Jerome Brunet	2	-1/+56
2017-04-07	clk: meson: gxbb: add cts_amclk	Jerome Brunet	2	-1/+71
2017-04-07	clk: meson: add audio clock divider support	Jerome Brunet	3	-1/+155
2017-04-07	clk: meson: gxbb: protect against holes in the onecell_data array	Jerome Brunet	1	-0/+4
2017-04-07	MAINTAINERS: Add maintainers for the meson clock driver	Jerome Brunet	1	-0/+10
2017-04-06	clk: sunxi-ng: Display index when clock registration fails	Priit Laes	1	-2/+2
2017-04-05	clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor	Chen-Yu Tsai	1	-7/+11
2017-04-05	clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks	Chen-Yu Tsai	1	-18/+52
2017-04-05	clk: sunxi-ng: mult: Support PLL lock detection	Chen-Yu Tsai	2	-0/+4
2017-04-04	clk: meson-gxbb: Add GXL/GXM GP0 Variant	Neil Armstrong	2	-28/+275
2017-04-04	clk: meson-gxbb: Add GP0 PLL init parameters	Neil Armstrong	1	-0/+13
2017-04-04	clk: meson: Add support for parameters for specific PLLs	Neil Armstrong	2	-2/+74
2017-04-04	clk: meson-gxbb: Add MALI clocks	Neil Armstrong	1	-0/+139
2017-04-04	dt-bindings: clock: gxbb-clkc: Add GXL compatible variant	Neil Armstrong	1	-1/+2
2017-04-04	clk: meson-gxbb: Expose GP0 dt-bindings clock id	Neil Armstrong	2	-1/+2
2017-04-04	clk: meson-gxbb: Add MALI clock IDS	Neil Armstrong	2	-1/+13
2017-04-04	dt-bindings: clk: gxbb: expose i2s output clock gates	Jerome Brunet	2	-5/+10
2017-04-04	clk: sunxi-ng: add support for PRCM CCUs	Icenowy Zheng	6	-0/+359
2017-04-04	dt-bindings: update device tree binding for Allwinner PRCM CCUs	Icenowy Zheng	1	-1/+16
2017-04-04	clk: tegra: Don't reset PLL-CX if it is already enabled	Jon Hunter	1	-4/+4
2017-04-04	clk: tegra: Add missing Tegra210 clocks	Peter De Schrijver	4	-8/+27
2017-04-04	clk: tegra: Propagate clk_out_x rate to parent	Alex Frid	1	-2/+4
2017-04-04	clk: stm32f4: fix: exclude values 0 and 1 for PLLQ	Gabriel Fernandez	1	-3/+10
2017-03-30	clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0	Geert Uytterhoeven	1	-11/+27
2017-03-30	clk: renesas: r8a7795: Add support for R-Car H3 ES2.0	Geert Uytterhoeven	1	-50/+151
2017-03-30	clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions	Geert Uytterhoeven	1	-0/+7