summaryrefslogtreecommitdiffstats
path: root/mm/secretmem.c (unfollow)
Commit message (Expand)AuthorFilesLines
2023-02-15riscv: ftrace: Remove wasted nops for !RISCV_ISA_CGuo Ren1-0/+4
2023-02-15riscv: ftrace: Fixup panic by disabling preemptionAndy Chiu1-1/+1
2023-02-15RISC-V: remove toolchain version checks for ZicbomConor Dooley2-11/+0
2023-02-15RISC-V: replace cbom instructions with an insn-defConor Dooley2-1/+14
2023-02-15RISC-V: insn-def: Add I-type insn-defAndrew Jones1-0/+46
2023-02-15dt-bindings: riscv: add a capacity-dmips-mhz cpu propertyConor Dooley1-0/+6
2023-02-15dt-bindings: arm: move cpu-capacity to a shared loationConor Dooley4-5/+5
2023-02-15riscv: Fix Zbb alternative IDsSamuel Holland4-8/+3
2023-02-15riscv: Fix early alternative patchingSamuel Holland1-3/+1
2023-02-15RISC-V: re-order Kconfig selects alphanumericallyConor Dooley1-24/+24
2023-02-15Documentation: riscv: fix insufficient list item indentConor Dooley1-4/+4
2023-02-01riscv: remove riscv_isa_ext_keys[] array and related usageJisheng Zhang2-41/+0
2023-02-01riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely()Andrew Jones1-2/+1
2023-02-01riscv: cpu_relax: switch to riscv_has_extension_likely()Jisheng Zhang1-1/+1
2023-02-01riscv: alternative: patch alternatives in the vDSOJisheng Zhang4-5/+40
2023-02-01riscv: switch to relative alternative entriesJisheng Zhang5-23/+36
2023-02-01riscv: module: Add ADD16 and SUB16 rela typesAndrew Jones1-0/+16
2023-02-01riscv: module: move find_section to module.hJisheng Zhang2-15/+16
2023-02-01riscv: fpu: switch has_fpu() to riscv_has_extension_likely()Jisheng Zhang1-1/+2
2023-02-01riscv: introduce riscv_has_extension_[un]likely()Jisheng Zhang1-0/+37
2023-02-01riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensionsJisheng Zhang2-62/+11
2023-02-01riscv: hwcap: make ISA extension ids can be used in asmJisheng Zhang1-24/+21
2023-02-01riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlierJisheng Zhang1-0/+3
2023-02-01riscv: move riscv_noncoherent_supported() out of ZICBOM probeJisheng Zhang2-1/+3
2023-01-31RISC-V: add zbb support to string functionsHeiko Stuebner8-1/+334
2023-01-31RISC-V: add infrastructure to allow different str* implementationsHeiko Stuebner7-0/+134
2023-01-25riscv: Move call to init_cpu_topology() to later initialization stageLey Foon Tan1-1/+2
2023-01-25RISC-V: Fix do_notify_resume / do_work_pending prototypeHeiko Stuebner1-1/+1
2023-01-25riscv/kprobe: Fix instruction simulation of JALRLiao Chang1-2/+2
2023-01-25riscv: fix jal offsets in patched alternativesJisheng Zhang2-0/+54
2023-01-25RISC-V: Kconfig: Remove trailing whitespaceGeert Uytterhoeven1-1/+1
2023-01-25riscv: pgtable: Fixup comment for KERN_VIRT_SIZEGuo Ren1-1/+1
2023-01-20riscv: fix -Wundef warning for CONFIG_RISCV_BOOT_SPINWAITMasahiro Yamada1-1/+1
2023-01-20MAINTAINERS: add an IRC entry for RISC-VConor Dooley1-0/+1
2023-01-20RISC-V: fix compile error from deduplicated __ALTERNATIVE_CFG_2Heiko Stuebner1-1/+1
2023-01-18Documentation: riscv: add a section about ISA string ordering in /proc/cpuinfoConor Dooley1-0/+42
2023-01-18RISC-V: resort all extensions in consistent ordersConor Dooley3-9/+13
2023-01-18RISC-V: clarify ISA string ordering rules in cpu.cConor Dooley1-13/+36
2023-01-18RISC-V: fix incorrect type of ARCH_CANAAN_K210_DTB_SOURCEConor Dooley1-1/+2
2023-01-06dt-bindings: riscv: fix single letter canonical orderConor Dooley1-1/+1
2023-01-06dt-bindings: riscv: fix underscore requirement for multi-letter extensionsConor Dooley1-1/+1
2023-01-05riscv: uaccess: fix type of 0 variable on error in get_user()Ben Dooks1-1/+1
2023-01-05riscv, kprobes: Stricter c.jr/c.jalr decodingBjörn Töpel1-2/+2
2022-12-29RISC-V: fix auipc-jalr addresses in patched alternativesHeiko Stuebner3-1/+63
2022-12-29RISC-V: add helpers for handling immediates in U-type and I-type pairsHeiko Stuebner1-0/+48
2022-12-29RISC-V: add rd reg parsing to insn.h headerHeiko Stuebner1-0/+5
2022-12-29RISC-V: add U-type imm parsing to insn.h headerHeiko Stuebner1-0/+13
2022-12-29RISC-V: kprobes: use central defined funct3 constantsHeiko Stuebner1-13/+6
2022-12-29RISC-V: rename parse_asm.h to insn.hHeiko Stuebner3-2/+2
2022-12-29RISC-V: Move riscv_insn_is_* macros into a common headerHeiko Stuebner3-62/+55