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* ASoC: hdac_hdmi/nau8825/rt286/rt298/rt5663/da7219: replace codec to componentKuninori Morimoto2018-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we can replace Codec to Component. Let's do it. Because intal/rockchip boards are using multi-codecs in 1 driver, we need to update these all related drivers in same time. Otherwise compile error/warning happen Note: hdac_hdmi xxx_codec_xxx() -> xxx_component_xxx() .idle_bias_off = 1 -> .idle_bias_on = 0 .ignore_pmdown_time = 0 -> .use_pmdown_time = 1 - -> .endianness = 1 - -> .non_legacy_dai_naming = 1 nau8825 xxx_codec_xxx() -> xxx_component_xxx() .idle_bias_off = 0 -> .idle_bias_on = 1 .ignore_pmdown_time = 0 -> .use_pmdown_time = 1 - -> .endianness = 1 - -> .non_legacy_dai_naming = 1 rt286 xxx_codec_xxx() -> xxx_component_xxx() .idle_bias_off = 1 -> .idle_bias_on = 0 .ignore_pmdown_time = 0 -> .use_pmdown_time = 1 - -> .endianness = 1 - -> .non_legacy_dai_naming = 1 rt298 xxx_codec_xxx() -> xxx_component_xxx() .idle_bias_off = 1 -> .idle_bias_on = 0 .ignore_pmdown_time = 0 -> .use_pmdown_time = 1 - -> .endianness = 1 - -> .non_legacy_dai_naming = 1 rt5663 xxx_codec_xxx() -> xxx_component_xxx() .idle_bias_off = 1 -> .idle_bias_on = 0 .ignore_pmdown_time = 0 -> .use_pmdown_time = 1 - -> .endianness = 1 - -> .non_legacy_dai_naming = 1 da7219 xxx_codec_xxx() -> xxx_component_xxx() .idle_bias_off = 0 -> .idle_bias_on = 1 .ignore_pmdown_time = 0 -> .use_pmdown_time = 1 - -> .endianness = 1 - -> .non_legacy_dai_naming = 1 Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: improve crosstalk measurement protectionJohn Hsu2017-12-041-0/+1
| | | | | | | | | | | | | | | | | | | | | The sequence of crosstalk measurement is not robust. The driver add more protections to make it stronger. The improvements as follows: (1)Give backup table the default value. The values are the same with the default of hardware registers. The impact will decline once restoring the backup table in the wrong way. (2)Add xtalk_baktab_initialized flag. The flag can keep the initiation status of backup table. It helps to backup and restore the backup-table correctly. (3)Add cancel parameter in the restore function. The volume ramping should do in crosstalk DONE state only. Otherwise, the delay action is not allowed because the restore may happen during the jack eject interruption. (4)Add xtalk_protect condition check before scheduling work in ISR. It makes sure the semaphore hold during the crosstalk measurement. The sequence is still under protection from playback interference. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: disable crosstalk by defaultJohn Hsu2017-11-291-1/+1
| | | | | | | | | | | | | | The driver makes the crosstalk funciton disabled by default which can simplify the codec function. The platform may not need this funciton and reduce the potential risk. Therefore, We change the property "nuvoton,crosstalk-bypass" to "nuvoton,crosstalk-enable". The crosstalk measurement is enabled if the property is set. Otherwise, it is disabled. Besides, add more condition in the entry point of the crosstalk sequence to disable the function completely. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: make crosstalk function optionalJohn Hsu2017-06-231-0/+1
| | | | | | | | | | | | | | | | | | | | Make crosstalk functoin optional. The jack detection can speed up without crosstalk detection. Let the decision of function usage to platform design. The patch helps the issue concern as follows: Google issue 35574278: Chell_headphone pop back from S3 There is a concern as follows: cras getting blocked for 2 seconds (worst-case 3 seconds) As I understand, ChromeOS expects resume finishes in 1 seconds. Video/Audio playing after 3 seconds of resume seems against the spec. If we really have to make the choice I would choose pop noise instead of waiting for 3 seconds. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: John Hsu <supercraig0719@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: fix invalid configuration in Pre-Scalar of FLLJohn Hsu2016-12-311-1/+2
| | | | | | | | | The clk_ref_div is not configured in the correct position of the register. The patch fixes that clk_ref_div, Pre-Scalar, is assigned the wrong value. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: correct the function name of registerJohn Hsu2016-12-311-2/+2
| | | | | | | Change to correct name of the register function. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: disable sinc filter for high THD of ADCJohn Hsu2016-12-061-0/+2
| | | | | | | | | | | | | This bit will enable 4th order SINC filter. =1, filter will enable; but it consumes higher power. =0, the sinc filter is disable, and it should always keep 0 value to get high THD. Therefor, disable the filter when codec initiation for better performance when recording. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: FLL parameters finetuneJohn Hsu2016-11-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The driver fine-tune some parameters to improve FLL performance. Those items have description as follow. (1)ICTRL_LATCH: FLL DSP speed capability control When FLL running at high frequency with long decimal number, DSP needs to operate at high speed. FLL DSP can optimize between performance and power consumption by ICTRL_LATCH.(111 has highest power consumption.) The default setting can be used to reduce power. (2)CUTOFF500: loop filter cutoff frequency at 500Khz It will give the best FLL performance but highest power consumption to enable the cutoff frequency. FLL Loop Filter enable to reduce FLL output noise, especially,(DCO frequency)/(FLL input reference frequency) is not a integer. (3)GAIN_ERR: FLL gain error correction threshold setting The threshold is comparison between DCO and target frequency. The value 1111 has the most sensitive threshold, that is, 1111 can have the most accurate DCO to target frequency. However, the gain error setting conditionally and inversely depends on FLL input reference clock rate. Higher FLL reference input frequency can only set lower gain error, such as 0000 for input reference from MCLK=12.288Mhz. On the other side, if FLL reference input is from Frame Sync, 48KHz, higher error gain can apply such as 1111. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: AD/DA over sampling rate configurationJohn Hsu2016-11-111-0/+4
| | | | | | | | | | | | | | | | | | | | | Over Sampling Rate (OSR) is defined as CLK_ADC frequency divided by the audio sample rate (Fs). OSR = CLK_ADC / FS The available OSRs are 32, 64, 128 or 256. Note that the OSR and Fs values must be selected such that the maximum frequency of CLK_ADC is less than 6.144 MHz. It is recommended to match the relationship between OSR and clock SRC according to following Table. ADC_RATE: 00(OSR=32) | CLK_ADC_SRC: 11(CODEC 1/8) ADC_RATE: 01(OSR=64) | CLK_ADC_SRC: 10(CODEC1/4) ADC_RATE: 10(OSR=128) | CLK_ADC_SRC: 01(CODEC 1/2) ADC_RATE: 11(OSR=256) | CLK_ADC_SRC: 00(CODEC CLK) The over sampling rate about DAC follows the same rule with ADCs. The driver changes the OSR to 64 value when initiation for better FLL performance and applies the dynamic SRC change by different OSR. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: Disable short Frame Sync detection logicJohn Hsu2016-11-111-0/+5
| | | | | | | | | | | | | | | | If the short Frame Sync detection logic enabled, the logic will check the short frame sync threshold. If frame sync is less than the setting; for example, frame sync less than 252 MCLK, the short frame sync signal is flagged, digital filter temporary mute and skip that data. If the system was intended for sampling rate change which could create temporary short frame sync and not enough MIPS to run the digital filter. But the situation doesn't happen in ALSA architecure. Thus the Frame Sync is always stable, then no require to do the detection. Therefore, the dirver disables the function for better performance. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: cross talk suppression measurement functionJohn Hsu2016-06-131-1/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cross talk measurement function can reduce cross talk across the JKTIP HPL) and JKR1(HPR) outputs which measures the cross talk signal level to determine what is the cross talk reduction gain. This system works by sending a 23Hz -24dBV sine wave into the headset output DAC and through the PGA. The output of the PGA is then connected to an internal current sense which measures the attenuated 23Hz signal and passing the output to an ADC which converts the measurement to a binary code. With two separated measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data can be separated read in IMM_RMS_L for HSR and HSL after each measurement. Thus, the measurement function has four states to complete whole sequence. (1)Prepare state : Prepare the resource for detection and transfer to HPR IMM stat to make JKR1(HPR) impedance measure. (2)HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer to HPL IMM state to make JKTIP(HPL) impedance measure. (3)HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and transfer to IMM state to determine suppression sidetone gain. (4)IMM state : Computes cross talk suppression sidetone gain with orignal and cross talk signal level. Apply this gain and then restore codec con- figuration. Then transfer to Done state for ending. In order to get the cross talk suppression sidetone gain, we need the function to compute log10 value and the result is round off to 3 decimal. This function takes reference to dvb-math. The source code locates as the following. "Linux/drivers/media/dvb-core/dvb_math.c" Then, the orignal and cross talk signal vlues need to be characterized. The sidetone value can be converted to decibel with the equation below. sidetone = 20 * log (original signal level / crosstalk signal level) Besides, the state machine for cross talk process needs interruptions to trigger worked. We have the RMS intrruption enabled with the internal VCO clock when headset connected. In the interrupt handler, the driver will judge the headset is high impedance or not. If yes, the cross talk supp- ression shouldn't apply and do nothing but relieve the protection raised before. Otherwise, apply the cross talk suppression in the headset and start the process. Because the process spends a lot of time, there is an resource race issue easily between the application and interruption. They will control codec power and clock concurrently. In one situaiton, the jack is inserted when playback, and then the application changes to headset device. The applica- tion prepares the playback and interrupt handler raises work for cross talk process together. For this case, the solution is that driver delays soc jack report until cross talk process completes. The mechanism can avoid application to do playback preparation before cross talk detection is still working. In another situaiton, the system suspends when playback. After resume, the system restarts playback, and meanwhile jack detection restarts. The play- back preparation and cross talk process triggered by interruptions happens concurrently. For the case, the driver provides the semaphone to syn- chronize the playback and interrupt handler. In order to avoid the play- back interfered by cross talk process, the driver make the playback prepa- ration halted until cross talk process finish. After codec resume, the driver finds the codec dai is active, and then the driver raises the pro- tection for cross talk function to avoid the playback recovers before cross talk process finish. The driver also provides cancel method to forcely cancel the cross talk task and restores the configuration to original status. Before the codec remove, ejection, or suspend, the driver is obliged to cancel the cross talk detection process. It can reduce the risk of failure when quickly and continually doing jack insertion and ejection. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: non-clock jack detection for power saving at standbyJohn Hsu2016-05-311-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver changes jack type detection interruption to non-clock archi- tecture for less 1mW power saving. The architecture is called manual mode jack detection. It has no hardware debounce, no jack type detection, but only detecting jack insertion. After jack insertion, the driver will switch to auto mode jack detection with internal clock which can detect microphone, jack type and do hardware debounce. The manual architecture has these main changes including codec initiation, interruption, clock control, and power management. When codec initiation or system resume, the clock is closed as jack insertion detection at man- ual mode, and bypass debounce circuit. These configurations move to resume setup function when setup bias level after resume. When jack insertion detection happens, the manual mode turns off and make configuration about jack type detection interruption at auto mode in auto irq setup function which can detect microphone and jack type. The inter- ruption will switch to manual mode again with clock free until jack ejec- tion happens. The system clock configuration adds clock disable option which can disable internal VCO clock. Before the system clock change, there is an restric- tion added to make sure clock disabled and not config any clock when no headset connected. In power management, we involve the solution about races and jack detec- tion in resume from Ben Zhang in the following patch and list his comment. [PATCH] ASoC: nau8825: Fix jack detection across suspend "Jack plug status is rechecked at resume to handle plug/unplug in S3 when the chip has no power." "Suspend/resume callbacks are moved from the i2c dev_pm_ops to snd_soc_codec_driver. soc_resume_deferred is a delayed work which may trigger nau8825_set_bias_level. The bias change races against dev_pm_ops, causing jack detection issues. soc_resume_deferred ensures bias change and snd_soc_codec_driver suspend/resume are sequenced correctly." Change SAR widget to supply type which can prevent the codec keeping at SND_SOC_BIAS_ON during suspend. The codec suspend function can just invoke normally. Before the system suspends, the driver turns off all interruptions. Keep the interruption quiet before resume setup completes. The ADC channel will be disabled which is needed for interruptions at audo mode. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: add programmable biquad filter controlJohn Hsu2016-05-311-0/+8
| | | | | | | | | Add programmable biquad filter configuration control for user space. The filter is configurable for low pass filters, high pass filters, Notch filter, etc in the ADC and DAC path. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: assign DAC Ch to match headset L/RJohn Hsu2016-05-301-0/+6
| | | | | | | | The default value of DAC channel select is reverse in codec. For normal usage, switch the channel select when codec bootup. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: change output power for interruptJohn Hsu2016-05-301-0/+1
| | | | | | | | | | | The interrupt clock is gated by x1[10:8], one of them needs to be enabled all the time for interrupts to happen. We change codec to enable ADC because it's helpful to reduce playback pop noise. Don't use force enable pin to enable ADC instead of ADC widget event. That won't interfere DAPM operation and let bias work normally. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: improve FLL function for better performanceJohn Hsu2016-05-301-5/+8
| | | | | | | | | In FLL calculation, increase VCO/DCO frequency for better performance. Besides, have different register configuration according to fraction or not when apply FLL parameters. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: support different clock source for FLL functionJohn Hsu2016-05-301-0/+8
| | | | | | | Extend FLL clock source selection. The source can be from MCLK, BCLK or FS. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: fix issue that pop noise when start playbackJohn Hsu2016-03-121-1/+15
| | | | | | | | | | | Reduce pop noise in power up and down sequence when playback. The DAPM widgets graph is reconstructed to ensure the register write sequence at playback matches exactly to the v5 clickless sequence provided by Nuvoton. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Ben Zhang <benzh@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: Add FLL configurationBen Zhang2015-10-221-5/+23
| | | | | | | | | snd_soc_codec_driver.set_pll is implemented to configure the FLL. The codec internal SYSCLK can be from either the MCLK pin directly, or the FLL. This is configured by snd_soc_codec_driver.set_pll. Signed-off-by: Ben Zhang <benzh@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: nau8825: Add driver for headset chip Nuvoton 8825Anatol Pomozov2015-10-071-0/+323
Sponsored-by: Google Chromium project Signed-off-by: Anatol Pomozov <anatol.pomozov@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>