summaryrefslogtreecommitdiffstats
path: root/tools/scripts (unfollow)
Commit message (Expand)AuthorFilesLines
2014-05-30ARM: l2c: move way size calculation data into l2c_init_dataRussell King1-9/+20
2014-05-30ARM: l2c: add decode for L2C-220 cache waysRussell King1-0/+1
2014-05-30ARM: l2c: move type string into l2c_init_data structureRussell King1-7/+13
2014-05-30ARM: l2c: remove obsolete l2x0 ops for non-OF initRussell King1-206/+0
2014-05-30ARM: l2c: convert Broadcom L2C-310 to new codeRussell King1-16/+11
2014-05-30ARM: l2c: add L2C-220 specific handlersRussell King1-10/+157
2014-05-30ARM: l2c: use L2C-210 handlers for L2C-310 errata-less implementationsRussell King1-22/+36
2014-05-30ARM: l2c: implement L2C-310 erratum 588369 as a method overrideRussell King1-0/+69
2014-05-30ARM: l2c: implement L2C-310 erratum 727915 as a method overrideRussell King1-0/+20
2014-05-30ARM: l2c: add L2C-210 specific handlersRussell King1-1/+122
2014-05-30ARM: l2c: move pl310_set_debug() into l2c-310 codeRussell King1-8/+6
2014-05-30ARM: l2c: simplify l2x0 unlocking codeRussell King1-17/+8
2014-05-30ARM: l2c: clean up save/resume functionsRussell King1-57/+52
2014-05-30ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OFRussell King1-74/+77
2014-05-30ARM: l2c: clean up L2 cache initialisation messagesRussell King1-3/+4
2014-05-30ARM: l2c: implement fixups for L2 cache controller quirks/errataRussell King1-11/+101
2014-05-30ARM: l2c: move aurora broadcast setup to enable functionRussell King1-13/+15
2014-05-30ARM: l2c: only write the auxiliary control register if requiredRussell King1-1/+3
2014-05-30ARM: l2c: write auxctrl register before unlockingRussell King1-5/+5
2014-05-30ARM: l2c: provide enable methodRussell King1-18/+62
2014-05-30ARM: l2c: group implementation specific code togetherRussell King1-251/+251
2014-05-30ARM: l2c: move l2c save function to __l2c_init()Russell King1-3/+7
2014-05-30ARM: l2c: pass iomem address into data->save functionRussell King1-16/+16
2014-05-30ARM: l2c: clean up OF initialisation a bitRussell King1-26/+40
2014-05-30ARM: l2c: add and use L2C revision constantsRussell King2-11/+21
2014-05-30ARM: l2c: rename cache_wait_way()Russell King1-3/+3
2014-05-30ARM: l2c: provide generic helper for way-based operationsRussell King1-6/+9
2014-05-30ARM: l2c: split out cache unlock codeRussell King1-7/+16
2014-05-30ARM: l2c: provide generic function for calling set_debug methodRussell King1-1/+11
2014-05-30ARM: l2c: rename OF specific things, making l2x0_of_data available to allRussell King1-32/+32
2014-05-30ARM: l2c: tidy up l2x0_of_data declarationsRussell King1-16/+14
2014-05-30ARM: l2c: add helper for L2 cache controller DT IDsRussell King1-13/+10
2014-05-30ARM: outer cache: add WARN_ON() to outer_disable()Russell King3-5/+22
2014-05-22ARM: outer cache: add documentation of outer cache functionsRussell King1-1/+47
2014-05-22ARM: l2c: remove unnecessary UL-suffix to mask valuesRussell King7-7/+7
2014-05-22ARM: l2c: omap2: remove ES1.0 supportRussell King1-17/+8
2014-05-22ARM: l2c: avoid calling outer_flush_all() unnecessarily (Spear)Russell King1-5/+14
2014-05-22ARM: l2c: remove unnecessary call to outer_flush_all()Russell King1-1/+0
2014-05-22ARM: l2c: remove outer_inv_all() methodRussell King3-14/+0
2014-05-21Linux 3.15-rc6v3.15-rc6Linus Torvalds1-1/+1
2014-05-20Btrfs: send, fix incorrect ref access when using extrefsFilipe Manana1-1/+1
2014-05-20Btrfs: fix EIO on reading file after ioctl clone works on itLiu Bo1-1/+5
2014-05-20scripts/checksyscalls.sh: Make renameat optionalJames Hogan1-1/+4
2014-05-20asm-generic: Add renameat2 syscallJames Hogan1-1/+3
2014-05-20ia64: add renameat2 syscallMiklos Szeredi3-1/+3
2014-05-20parisc: add renameat2 syscallMiklos Szeredi2-1/+3
2014-05-20m68k: add renameat2 syscallMiklos Szeredi3-1/+3
2014-05-20sysfs: make sure read buffer is zeroedTejun Heo1-1/+2
2014-05-19ahci: imx: PLL clock needs 100us to settle downShawn Guo1-0/+2
2014-05-19PCI: Wrong register used to check pending trafficGavin Shan1-2/+3
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-23 05:34:58 +0100