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2020-09-21PCI: layerscape: Add EP mode support for ls1088a and ls2088aXiaowei Bao1-19/+53
2020-09-21PCI: layerscape: Modify the MSIX to the doorbell modeXiaowei Bao1-1/+2
2020-09-21PCI: layerscape: Modify the way of getting capability with different PEXXiaowei Bao1-8/+23
2020-09-21PCI: layerscape: Fix some format issue of the codeXiaowei Bao1-2/+2
2020-09-21dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088aXiaowei Bao1-0/+2
2020-09-21PCI: designware-ep: Modify MSI and MSIX CAP way of findingXiaowei Bao2-21/+118
2020-09-21PCI: designware-ep: Move the function of getting MSI capability forwardXiaowei Bao1-4/+4
2020-09-21PCI: designware-ep: Add the doorbell mode of MSI-X in EP modeXiaowei Bao2-0/+31
2020-09-21PCI: designware-ep: Add multiple PFs support for DWCXiaowei Bao3-59/+143
2020-09-10PCI: dwc: Use DBI accessorsRob Herring2-10/+8
2020-09-10PCI: dwc: Move N_FTS setup to common setupRob Herring5-85/+35
2020-09-10PCI: dwc/intel-gw: Drop unused max_widthRob Herring1-4/+0
2020-09-10PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup()Rob Herring1-14/+1
2020-09-10PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' propertyRob Herring1-6/+0
2020-09-10PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup codeRob Herring2-4/+1
2020-09-10PCI: dwc: Centralize link gen settingRob Herring11-151/+40
2020-09-08PCI: dwc: Make ATU accessors privateRob Herring2-18/+6
2020-09-08PCI: dwc: Remove read_dbi2 codeRob Herring3-36/+0
2020-09-08PCI: dwc/tegra: Use common Designware port logic register definitionsRob Herring2-34/+28
2020-09-08PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offsetRob Herring3-12/+7
2020-09-08PCI: dwc/qcom: Use common PCI register definitionsRob Herring1-10/+8
2020-09-08PCI: dwc/imx6: Use common PCI register definitionsRob Herring1-23/+14
2020-09-08PCI: dwc/meson: Rework PCI config and DW port logic register accessesRob Herring1-51/+25
2020-09-08PCI: dwc/meson: Drop unnecessary RC config space initializationRob Herring1-20/+0
2020-09-08PCI: dwc/meson: Drop the duplicate number of lanes setupRob Herring1-28/+1
2020-09-08PCI: dwc: Ensure FAST_LINK_MODE is clearedRob Herring2-1/+5
2020-09-08PCI: dwc: Add a 'num_lanes' field to struct dw_pcieRob Herring2-8/+7
2020-09-08PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROLRob Herring1-2/+0
2020-09-08PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()Rob Herring9-34/+11
2020-09-08PCI: dwc/keystone: Drop duplicated 'num-viewport'Rob Herring1-10/+1
2020-09-08PCI: dwc: Simplify config space handlingRob Herring3-55/+20
2020-09-08PCI: dwc: Remove storing of PCI resourcesRob Herring4-29/+19
2020-09-08PCI: dwc: Remove root_bus pointerRob Herring3-5/+4
2020-09-08PCI: dwc: Convert to use pci_host_probe()Rob Herring2-19/+3
2020-09-08PCI: dwc: keystone: Convert .scan_bus() callback to use add_busRob Herring1-3/+9
2020-09-08PCI: Also call .add_bus() callback for root busRob Herring1-0/+6
2020-09-08PCI: dwc: Use generic config accessorsRob Herring1-82/+37
2020-09-08PCI: dwc: Remove dwc specific config accessor opsRob Herring2-20/+0
2020-09-08PCI: dwc: histb: Use pci_ops for root config space accessorsRob Herring1-18/+23
2020-09-08PCI: dwc: exynos: Use pci_ops for root config space accessorsRob Herring1-20/+25
2020-09-08PCI: dwc: kirin: Use pci_ops for root config space accessorsRob Herring1-18/+21
2020-09-08PCI: dwc: meson: Use pci_ops for root config space accessorsRob Herring1-13/+10
2020-09-08PCI: dwc: tegra: Use pci_ops for root config space accessorsRob Herring1-14/+16
2020-09-08PCI: dwc: keystone: Use pci_ops for config space accessorsRob Herring1-22/+18
2020-09-08PCI: dwc: al: Use pci_ops for child config space accessorsRob Herring1-50/+13
2020-09-08PCI: dwc: Add a default pci_ops.map_bus for root portRob Herring2-0/+20
2020-09-07PCI: dwc: Allow overriding bridge pci_opsRob Herring2-5/+11
2020-09-07PCI: dwc: Use DBI accessors instead of own config accessorsRob Herring1-36/+19
2020-09-07PCI: Allow root and child buses to have different pci_opsRob Herring2-1/+8
2020-09-07PCI: designware-ep: Fix the Header Type checkHou Zhiqiang2-1/+3
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