From f3b19aa5cab65f7e73613aa37f6851ce56b794d1 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 27 Feb 2015 17:54:14 +0200 Subject: ARM: OMAP2+: clock: export driver API to setup/get clock features As most of the clock driver support code is going to be moved under drivers/clk/ti, an API for setting / getting the SoC specific clock features is needed. This patch provides this API and changes the existing code to use it. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clkt_dpll.c | 14 +++++++------- arch/arm/mach-omap2/clock.c | 36 +++++++++++++++++------------------- arch/arm/mach-omap2/clock.h | 18 ------------------ arch/arm/mach-omap2/clock3xxx.c | 4 ++-- arch/arm/mach-omap2/dpll3xxx.c | 4 ++-- drivers/clk/ti/clk.c | 25 +++++++++++++++++++++++++ include/linux/clk/ti.h | 16 ++++++++++++++++ 7 files changed, 69 insertions(+), 48 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index f251a14cbf16..82f0600c35f4 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -80,8 +80,8 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n) fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN; fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX; } else { - fint_min = ti_clk_features.fint_min; - fint_max = ti_clk_features.fint_max; + fint_min = ti_clk_get_features()->fint_min; + fint_max = ti_clk_get_features()->fint_max; } if (!fint_min || !fint_max) { @@ -89,18 +89,18 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n) return DPLL_FINT_INVALID; } - if (fint < ti_clk_features.fint_min) { + if (fint < ti_clk_get_features()->fint_min) { pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", n); dd->max_divider = n; ret = DPLL_FINT_UNDERFLOW; - } else if (fint > ti_clk_features.fint_max) { + } else if (fint > ti_clk_get_features()->fint_max) { pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", n); dd->min_divider = n; ret = DPLL_FINT_INVALID; - } else if (fint > ti_clk_features.fint_band1_max && - fint < ti_clk_features.fint_band2_min) { + } else if (fint > ti_clk_get_features()->fint_band1_max && + fint < ti_clk_get_features()->fint_band2_min) { pr_debug("rejecting n=%d due to Fint failure\n", n); ret = DPLL_FINT_INVALID; } @@ -183,7 +183,7 @@ static int _omap2_dpll_is_in_bypass(u32 v) { u8 mask, val; - mask = ti_clk_features.dpll_bypass_vals; + mask = ti_clk_get_features()->dpll_bypass_vals; /* * Each set bit in the mask corresponds to a bypass value equal diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index a699d7169307..cbc65b3a3b62 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -48,11 +48,6 @@ u16 cpu_mask; -/* - * Clock features setup. Used instead of CPU type checks. - */ -struct ti_clk_features ti_clk_features; - /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 @@ -367,7 +362,7 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, * 34xx reverses this, just to keep us on our toes * AM35xx uses both, depending on the module. */ - *idlest_val = ti_clk_features.cm_idlest_val; + *idlest_val = ti_clk_get_features()->cm_idlest_val; } /** @@ -801,29 +796,30 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, */ void __init ti_clk_init_features(void) { + struct ti_clk_features features = { 0 }; /* Fint setup for DPLLs */ if (cpu_is_omap3430()) { - ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; - ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; - ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; - ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; + features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; + features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; + features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; + features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; } else { - ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; - ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; + features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; + features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; } /* Bypass value setup for DPLLs */ if (cpu_is_omap24xx()) { - ti_clk_features.dpll_bypass_vals |= + features.dpll_bypass_vals |= (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | (1 << OMAP2XXX_EN_DPLL_FRBYPASS); } else if (cpu_is_omap34xx()) { - ti_clk_features.dpll_bypass_vals |= + features.dpll_bypass_vals |= (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | (1 << OMAP3XXX_EN_DPLL_FRBYPASS); } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || soc_is_omap54xx() || soc_is_dra7xx()) { - ti_clk_features.dpll_bypass_vals |= + features.dpll_bypass_vals |= (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | (1 << OMAP4XXX_EN_DPLL_MNBYPASS); @@ -831,7 +827,7 @@ void __init ti_clk_init_features(void) /* Jitter correction only available on OMAP343X */ if (cpu_is_omap343x()) - ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL; + features.flags |= TI_CLK_DPLL_HAS_FREQSEL; /* Idlest value for interface clocks. * 24xx uses 0 to indicate not ready, and 1 to indicate ready. @@ -839,11 +835,13 @@ void __init ti_clk_init_features(void) * AM35xx uses both, depending on the module. */ if (cpu_is_omap24xx()) - ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; + features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; else if (cpu_is_omap34xx()) - ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; + features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */ if (omap_rev() == OMAP3430_REV_ES1_0) - ti_clk_features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; + features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; + + ti_clk_setup_features(&features); } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 652ed0ab86ec..ac21856d245d 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -225,24 +225,6 @@ void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg); extern u16 cpu_mask; -/* - * Clock features setup. Used instead of CPU type checks. - */ -struct ti_clk_features { - u32 flags; - long fint_min; - long fint_max; - long fint_band1_max; - long fint_band2_min; - u8 dpll_bypass_vals; - u8 cm_idlest_val; -}; - -#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0) -#define TI_CLK_DPLL4_DENY_REPROGRAM (1 << 1) - -extern struct ti_clk_features ti_clk_features; - extern const struct clkops clkops_omap2_dflt_wait; extern const struct clkops clkops_omap2_dflt; diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index a9e86db5daf9..8bede6aec44f 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -58,7 +58,7 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, * on 3430ES1 prevents us from changing DPLL multipliers or dividers * on DPLL4. */ - if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) { + if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) { pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); return -EINVAL; } @@ -81,7 +81,7 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index) { - if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) { + if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) { pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); return -EINVAL; } diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 44e57ec225d4..9a80f593ed15 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -307,7 +307,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) * Set jitter correction. Jitter correction applicable for OMAP343X * only since freqsel field is no longer present on other devices. */ - if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { + if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) { v = omap2_clk_readl(clk, dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); @@ -559,7 +559,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, return -EINVAL; /* Freqsel is available only on OMAP343X devices */ - if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { + if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) { freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); WARN_ON(!freqsel); } diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 0ebe5c51062b..e65ae4acff9c 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -30,6 +30,8 @@ struct ti_clk_ll_ops *ti_clk_ll_ops; static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS]; +struct ti_clk_features ti_clk_features; + /** * ti_dt_clocks_register - register DT alias clocks during boot * @oclks: list of clocks to register @@ -311,3 +313,26 @@ int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks) return 0; } #endif + +/** + * ti_clk_setup_features - setup clock features flags + * @features: features definition to use + * + * Initializes the clock driver features flags based on platform + * provided data. No return value. + */ +void __init ti_clk_setup_features(struct ti_clk_features *features) +{ + memcpy(&ti_clk_features, features, sizeof(*features)); +} + +/** + * ti_clk_get_features - get clock driver features flags + * + * Get TI clock driver features description. Returns a pointer + * to the current feature setup. + */ +const struct ti_clk_features *ti_clk_get_features(void) +{ + return &ti_clk_features; +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 79b76e13d904..1a7f86a68f62 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -338,6 +338,22 @@ int am43xx_dt_clk_init(void); int omap2420_dt_clk_init(void); int omap2430_dt_clk_init(void); +struct ti_clk_features { + u32 flags; + long fint_min; + long fint_max; + long fint_band1_max; + long fint_band2_min; + u8 dpll_bypass_vals; + u8 cm_idlest_val; +}; + +#define TI_CLK_DPLL_HAS_FREQSEL BIT(0) +#define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1) + +void ti_clk_setup_features(struct ti_clk_features *features); +const struct ti_clk_features *ti_clk_get_features(void); + #ifdef CONFIG_OF void of_ti_clk_allow_autoidle_all(void); void of_ti_clk_deny_autoidle_all(void); -- cgit v1.2.3 From b138b0283d35bed0cd3353d7e39add8ac493eb37 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 2 Mar 2015 09:57:28 +0200 Subject: clk: ti: move generic OMAP DPLL implementation under drivers/clk With the legacy clock data now gone, we can start moving OMAP clock type implementations under clock driver. Start this with moving the generic OMAP DPLL clock type under TI clock driver. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/clkt_dpll.c | 370 ---------------------------------------- drivers/clk/ti/Makefile | 3 +- drivers/clk/ti/clkt_dpll.c | 369 +++++++++++++++++++++++++++++++++++++++ drivers/clk/ti/clock.h | 2 + include/linux/clk/ti.h | 1 - 6 files changed, 374 insertions(+), 373 deletions(-) delete mode 100644 arch/arm/mach-omap2/clkt_dpll.c create mode 100644 drivers/clk/ti/clkt_dpll.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ec002bd4af77..fcb5d47f88ca 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -13,7 +13,7 @@ obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ omap_hwmod_common_data.o clock-common = clock.o clock_common_data.o \ - clkt_dpll.o clkt_clksel.o + clkt_clksel.o secure-common = omap-smc.o omap-secure.o obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c deleted file mode 100644 index 82f0600c35f4..000000000000 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * OMAP2/3/4 DPLL clock functions - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include -#include - -#include - -#include "clock.h" - -/* DPLL rate rounding: minimum DPLL multiplier, divider values */ -#define DPLL_MIN_MULTIPLIER 2 -#define DPLL_MIN_DIVIDER 1 - -/* Possible error results from _dpll_test_mult */ -#define DPLL_MULT_UNDERFLOW -1 - -/* - * Scale factor to mitigate roundoff errors in DPLL rate rounding. - * The higher the scale factor, the greater the risk of arithmetic overflow, - * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR - * must be a power of DPLL_SCALE_BASE. - */ -#define DPLL_SCALE_FACTOR 64 -#define DPLL_SCALE_BASE 2 -#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ - (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) - -/* - * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. - * From device data manual section 4.3 "DPLL and DLL Specifications". - */ -#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000 -#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000 - -/* _dpll_test_fint() return codes */ -#define DPLL_FINT_UNDERFLOW -1 -#define DPLL_FINT_INVALID -2 - -/* Private functions */ - -/* - * _dpll_test_fint - test whether an Fint value is valid for the DPLL - * @clk: DPLL struct clk to test - * @n: divider value (N) to test - * - * Tests whether a particular divider @n will result in a valid DPLL - * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter - * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate - * (assuming that it is counting N upwards), or -2 if the enclosing loop - * should skip to the next iteration (again assuming N is increasing). - */ -static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n) -{ - struct dpll_data *dd; - long fint, fint_min, fint_max; - int ret = 0; - - dd = clk->dpll_data; - - /* DPLL divider must result in a valid jitter correction val */ - fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; - - if (dd->flags & DPLL_J_TYPE) { - fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN; - fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX; - } else { - fint_min = ti_clk_get_features()->fint_min; - fint_max = ti_clk_get_features()->fint_max; - } - - if (!fint_min || !fint_max) { - WARN(1, "No fint limits available!\n"); - return DPLL_FINT_INVALID; - } - - if (fint < ti_clk_get_features()->fint_min) { - pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", - n); - dd->max_divider = n; - ret = DPLL_FINT_UNDERFLOW; - } else if (fint > ti_clk_get_features()->fint_max) { - pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", - n); - dd->min_divider = n; - ret = DPLL_FINT_INVALID; - } else if (fint > ti_clk_get_features()->fint_band1_max && - fint < ti_clk_get_features()->fint_band2_min) { - pr_debug("rejecting n=%d due to Fint failure\n", n); - ret = DPLL_FINT_INVALID; - } - - return ret; -} - -static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, - unsigned int m, unsigned int n) -{ - unsigned long long num; - - num = (unsigned long long)parent_rate * m; - do_div(num, n); - return num; -} - -/* - * _dpll_test_mult - test a DPLL multiplier value - * @m: pointer to the DPLL m (multiplier) value under test - * @n: current DPLL n (divider) value under test - * @new_rate: pointer to storage for the resulting rounded rate - * @target_rate: the desired DPLL rate - * @parent_rate: the DPLL's parent clock rate - * - * This code tests a DPLL multiplier value, ensuring that the - * resulting rate will not be higher than the target_rate, and that - * the multiplier value itself is valid for the DPLL. Initially, the - * integer pointed to by the m argument should be prescaled by - * multiplying by DPLL_SCALE_FACTOR. The code will replace this with - * a non-scaled m upon return. This non-scaled m will result in a - * new_rate as close as possible to target_rate (but not greater than - * target_rate) given the current (parent_rate, n, prescaled m) - * triple. Returns DPLL_MULT_UNDERFLOW in the event that the - * non-scaled m attempted to underflow, which can allow the calling - * function to bail out early; or 0 upon success. - */ -static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, - unsigned long target_rate, - unsigned long parent_rate) -{ - int r = 0, carry = 0; - - /* Unscale m and round if necessary */ - if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) - carry = 1; - *m = (*m / DPLL_SCALE_FACTOR) + carry; - - /* - * The new rate must be <= the target rate to avoid programming - * a rate that is impossible for the hardware to handle - */ - *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); - if (*new_rate > target_rate) { - (*m)--; - *new_rate = 0; - } - - /* Guard against m underflow */ - if (*m < DPLL_MIN_MULTIPLIER) { - *m = DPLL_MIN_MULTIPLIER; - *new_rate = 0; - r = DPLL_MULT_UNDERFLOW; - } - - if (*new_rate == 0) - *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); - - return r; -} - -/** - * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not - * @v: bitfield value of the DPLL enable - * - * Checks given DPLL enable bitfield to see whether the DPLL is in bypass - * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise. - */ -static int _omap2_dpll_is_in_bypass(u32 v) -{ - u8 mask, val; - - mask = ti_clk_get_features()->dpll_bypass_vals; - - /* - * Each set bit in the mask corresponds to a bypass value equal - * to the bitshift. Go through each set-bit in the mask and - * compare against the given register value. - */ - while (mask) { - val = __ffs(mask); - mask ^= (1 << val); - if (v == val) - return 1; - } - - return 0; -} - -/* Public functions */ -u8 omap2_init_dpll_parent(struct clk_hw *hw) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - u32 v; - struct dpll_data *dd; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - v = omap2_clk_readl(clk, dd->control_reg); - v &= dd->enable_mask; - v >>= __ffs(dd->enable_mask); - - /* Reparent the struct clk in case the dpll is in bypass */ - if (_omap2_dpll_is_in_bypass(v)) - return 1; - - return 0; -} - -/** - * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate - * @clk: struct clk * of a DPLL - * - * DPLLs can be locked or bypassed - basically, enabled or disabled. - * When locked, the DPLL output depends on the M and N values. When - * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock - * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and - * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively - * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. - * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is - * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 - * if the clock @clk is not a DPLL. - */ -unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) -{ - long long dpll_clk; - u32 dpll_mult, dpll_div, v; - struct dpll_data *dd; - - dd = clk->dpll_data; - if (!dd) - return 0; - - /* Return bypass rate if DPLL is bypassed */ - v = omap2_clk_readl(clk, dd->control_reg); - v &= dd->enable_mask; - v >>= __ffs(dd->enable_mask); - - if (_omap2_dpll_is_in_bypass(v)) - return __clk_get_rate(dd->clk_bypass); - - v = omap2_clk_readl(clk, dd->mult_div1_reg); - dpll_mult = v & dd->mult_mask; - dpll_mult >>= __ffs(dd->mult_mask); - dpll_div = v & dd->div1_mask; - dpll_div >>= __ffs(dd->div1_mask); - - dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult; - do_div(dpll_clk, dpll_div + 1); - - return dpll_clk; -} - -/* DPLL rate rounding code */ - -/** - * omap2_dpll_round_rate - round a target rate for an OMAP DPLL - * @clk: struct clk * for a DPLL - * @target_rate: desired DPLL clock rate - * - * Given a DPLL and a desired target rate, round the target rate to a - * possible, programmable rate for this DPLL. Attempts to select the - * minimum possible n. Stores the computed (m, n) in the DPLL's - * dpll_data structure so set_rate() will not need to call this - * (expensive) function again. Returns ~0 if the target rate cannot - * be rounded, or the rounded rate upon success. - */ -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, - unsigned long *parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - int m, n, r, scaled_max_m; - int min_delta_m = INT_MAX, min_delta_n = INT_MAX; - unsigned long scaled_rt_rp; - unsigned long new_rate = 0; - struct dpll_data *dd; - unsigned long ref_rate; - long delta; - long prev_min_delta = LONG_MAX; - const char *clk_name; - - if (!clk || !clk->dpll_data) - return ~0; - - dd = clk->dpll_data; - - ref_rate = __clk_get_rate(dd->clk_ref); - clk_name = __clk_get_name(hw->clk); - pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n", - clk_name, target_rate); - - scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR); - scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; - - dd->last_rounded_rate = 0; - - for (n = dd->min_divider; n <= dd->max_divider; n++) { - - /* Is the (input clk, divider) pair valid for the DPLL? */ - r = _dpll_test_fint(clk, n); - if (r == DPLL_FINT_UNDERFLOW) - break; - else if (r == DPLL_FINT_INVALID) - continue; - - /* Compute the scaled DPLL multiplier, based on the divider */ - m = scaled_rt_rp * n; - - /* - * Since we're counting n up, a m overflow means we - * can bail out completely (since as n increases in - * the next iteration, there's no way that m can - * increase beyond the current m) - */ - if (m > scaled_max_m) - break; - - r = _dpll_test_mult(&m, n, &new_rate, target_rate, - ref_rate); - - /* m can't be set low enough for this n - try with a larger n */ - if (r == DPLL_MULT_UNDERFLOW) - continue; - - /* skip rates above our target rate */ - delta = target_rate - new_rate; - if (delta < 0) - continue; - - if (delta < prev_min_delta) { - prev_min_delta = delta; - min_delta_m = m; - min_delta_n = n; - } - - pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n", - clk_name, m, n, new_rate); - - if (delta == 0) - break; - } - - if (prev_min_delta == LONG_MAX) { - pr_debug("clock: %s: cannot round to rate %lu\n", - clk_name, target_rate); - return ~0; - } - - dd->last_rounded_m = min_delta_m; - dd->last_rounded_n = min_delta_n; - dd->last_rounded_rate = target_rate - prev_min_delta; - - return dd->last_rounded_rate; -} - diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 105ffd0f5e79..62dae2ad3c69 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,6 +1,7 @@ obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ - fixed-factor.o mux.o apll.o + fixed-factor.o mux.o apll.o \ + clkt_dpll.o obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c new file mode 100644 index 000000000000..a01fc7f305c1 --- /dev/null +++ b/drivers/clk/ti/clkt_dpll.c @@ -0,0 +1,369 @@ +/* + * OMAP2/3/4 DPLL clock functions + * + * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2004-2010 Nokia Corporation + * + * Contacts: + * Richard Woodruff + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#undef DEBUG + +#include +#include +#include +#include +#include + +#include + +#include "clock.h" + +/* DPLL rate rounding: minimum DPLL multiplier, divider values */ +#define DPLL_MIN_MULTIPLIER 2 +#define DPLL_MIN_DIVIDER 1 + +/* Possible error results from _dpll_test_mult */ +#define DPLL_MULT_UNDERFLOW -1 + +/* + * Scale factor to mitigate roundoff errors in DPLL rate rounding. + * The higher the scale factor, the greater the risk of arithmetic overflow, + * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR + * must be a power of DPLL_SCALE_BASE. + */ +#define DPLL_SCALE_FACTOR 64 +#define DPLL_SCALE_BASE 2 +#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ + (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) + +/* + * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. + * From device data manual section 4.3 "DPLL and DLL Specifications". + */ +#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000 +#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000 + +/* _dpll_test_fint() return codes */ +#define DPLL_FINT_UNDERFLOW -1 +#define DPLL_FINT_INVALID -2 + +/* Private functions */ + +/* + * _dpll_test_fint - test whether an Fint value is valid for the DPLL + * @clk: DPLL struct clk to test + * @n: divider value (N) to test + * + * Tests whether a particular divider @n will result in a valid DPLL + * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter + * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate + * (assuming that it is counting N upwards), or -2 if the enclosing loop + * should skip to the next iteration (again assuming N is increasing). + */ +static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n) +{ + struct dpll_data *dd; + long fint, fint_min, fint_max; + int ret = 0; + + dd = clk->dpll_data; + + /* DPLL divider must result in a valid jitter correction val */ + fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; + + if (dd->flags & DPLL_J_TYPE) { + fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN; + fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX; + } else { + fint_min = ti_clk_get_features()->fint_min; + fint_max = ti_clk_get_features()->fint_max; + } + + if (!fint_min || !fint_max) { + WARN(1, "No fint limits available!\n"); + return DPLL_FINT_INVALID; + } + + if (fint < ti_clk_get_features()->fint_min) { + pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", + n); + dd->max_divider = n; + ret = DPLL_FINT_UNDERFLOW; + } else if (fint > ti_clk_get_features()->fint_max) { + pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", + n); + dd->min_divider = n; + ret = DPLL_FINT_INVALID; + } else if (fint > ti_clk_get_features()->fint_band1_max && + fint < ti_clk_get_features()->fint_band2_min) { + pr_debug("rejecting n=%d due to Fint failure\n", n); + ret = DPLL_FINT_INVALID; + } + + return ret; +} + +static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, + unsigned int m, unsigned int n) +{ + unsigned long long num; + + num = (unsigned long long)parent_rate * m; + do_div(num, n); + return num; +} + +/* + * _dpll_test_mult - test a DPLL multiplier value + * @m: pointer to the DPLL m (multiplier) value under test + * @n: current DPLL n (divider) value under test + * @new_rate: pointer to storage for the resulting rounded rate + * @target_rate: the desired DPLL rate + * @parent_rate: the DPLL's parent clock rate + * + * This code tests a DPLL multiplier value, ensuring that the + * resulting rate will not be higher than the target_rate, and that + * the multiplier value itself is valid for the DPLL. Initially, the + * integer pointed to by the m argument should be prescaled by + * multiplying by DPLL_SCALE_FACTOR. The code will replace this with + * a non-scaled m upon return. This non-scaled m will result in a + * new_rate as close as possible to target_rate (but not greater than + * target_rate) given the current (parent_rate, n, prescaled m) + * triple. Returns DPLL_MULT_UNDERFLOW in the event that the + * non-scaled m attempted to underflow, which can allow the calling + * function to bail out early; or 0 upon success. + */ +static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, + unsigned long target_rate, + unsigned long parent_rate) +{ + int r = 0, carry = 0; + + /* Unscale m and round if necessary */ + if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) + carry = 1; + *m = (*m / DPLL_SCALE_FACTOR) + carry; + + /* + * The new rate must be <= the target rate to avoid programming + * a rate that is impossible for the hardware to handle + */ + *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); + if (*new_rate > target_rate) { + (*m)--; + *new_rate = 0; + } + + /* Guard against m underflow */ + if (*m < DPLL_MIN_MULTIPLIER) { + *m = DPLL_MIN_MULTIPLIER; + *new_rate = 0; + r = DPLL_MULT_UNDERFLOW; + } + + if (*new_rate == 0) + *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); + + return r; +} + +/** + * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not + * @v: bitfield value of the DPLL enable + * + * Checks given DPLL enable bitfield to see whether the DPLL is in bypass + * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise. + */ +static int _omap2_dpll_is_in_bypass(u32 v) +{ + u8 mask, val; + + mask = ti_clk_get_features()->dpll_bypass_vals; + + /* + * Each set bit in the mask corresponds to a bypass value equal + * to the bitshift. Go through each set-bit in the mask and + * compare against the given register value. + */ + while (mask) { + val = __ffs(mask); + mask ^= (1 << val); + if (v == val) + return 1; + } + + return 0; +} + +/* Public functions */ +u8 omap2_init_dpll_parent(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 v; + struct dpll_data *dd; + + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + v = ti_clk_ll_ops->clk_readl(dd->control_reg); + v &= dd->enable_mask; + v >>= __ffs(dd->enable_mask); + + /* Reparent the struct clk in case the dpll is in bypass */ + if (_omap2_dpll_is_in_bypass(v)) + return 1; + + return 0; +} + +/** + * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate + * @clk: struct clk * of a DPLL + * + * DPLLs can be locked or bypassed - basically, enabled or disabled. + * When locked, the DPLL output depends on the M and N values. When + * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock + * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and + * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively + * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. + * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is + * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 + * if the clock @clk is not a DPLL. + */ +unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) +{ + long long dpll_clk; + u32 dpll_mult, dpll_div, v; + struct dpll_data *dd; + + dd = clk->dpll_data; + if (!dd) + return 0; + + /* Return bypass rate if DPLL is bypassed */ + v = ti_clk_ll_ops->clk_readl(dd->control_reg); + v &= dd->enable_mask; + v >>= __ffs(dd->enable_mask); + + if (_omap2_dpll_is_in_bypass(v)) + return __clk_get_rate(dd->clk_bypass); + + v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); + dpll_mult = v & dd->mult_mask; + dpll_mult >>= __ffs(dd->mult_mask); + dpll_div = v & dd->div1_mask; + dpll_div >>= __ffs(dd->div1_mask); + + dpll_clk = (long long)__clk_get_rate(dd->clk_ref) * dpll_mult; + do_div(dpll_clk, dpll_div + 1); + + return dpll_clk; +} + +/* DPLL rate rounding code */ + +/** + * omap2_dpll_round_rate - round a target rate for an OMAP DPLL + * @clk: struct clk * for a DPLL + * @target_rate: desired DPLL clock rate + * + * Given a DPLL and a desired target rate, round the target rate to a + * possible, programmable rate for this DPLL. Attempts to select the + * minimum possible n. Stores the computed (m, n) in the DPLL's + * dpll_data structure so set_rate() will not need to call this + * (expensive) function again. Returns ~0 if the target rate cannot + * be rounded, or the rounded rate upon success. + */ +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + int m, n, r, scaled_max_m; + int min_delta_m = INT_MAX, min_delta_n = INT_MAX; + unsigned long scaled_rt_rp; + unsigned long new_rate = 0; + struct dpll_data *dd; + unsigned long ref_rate; + long delta; + long prev_min_delta = LONG_MAX; + const char *clk_name; + + if (!clk || !clk->dpll_data) + return ~0; + + dd = clk->dpll_data; + + ref_rate = __clk_get_rate(dd->clk_ref); + clk_name = __clk_get_name(hw->clk); + pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n", + clk_name, target_rate); + + scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR); + scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; + + dd->last_rounded_rate = 0; + + for (n = dd->min_divider; n <= dd->max_divider; n++) { + /* Is the (input clk, divider) pair valid for the DPLL? */ + r = _dpll_test_fint(clk, n); + if (r == DPLL_FINT_UNDERFLOW) + break; + else if (r == DPLL_FINT_INVALID) + continue; + + /* Compute the scaled DPLL multiplier, based on the divider */ + m = scaled_rt_rp * n; + + /* + * Since we're counting n up, a m overflow means we + * can bail out completely (since as n increases in + * the next iteration, there's no way that m can + * increase beyond the current m) + */ + if (m > scaled_max_m) + break; + + r = _dpll_test_mult(&m, n, &new_rate, target_rate, + ref_rate); + + /* m can't be set low enough for this n - try with a larger n */ + if (r == DPLL_MULT_UNDERFLOW) + continue; + + /* skip rates above our target rate */ + delta = target_rate - new_rate; + if (delta < 0) + continue; + + if (delta < prev_min_delta) { + prev_min_delta = delta; + min_delta_m = m; + min_delta_n = n; + } + + pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n", + clk_name, m, n, new_rate); + + if (delta == 0) + break; + } + + if (prev_min_delta == LONG_MAX) { + pr_debug("clock: %s: cannot round to rate %lu\n", + clk_name, target_rate); + return ~0; + } + + dd->last_rounded_m = min_delta_m; + dd->last_rounded_n = min_delta_n; + dd->last_rounded_rate = target_rate - prev_min_delta; + + return dd->last_rounded_rate; +} diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 404158d2d7f8..05ed10a81ace 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -169,4 +169,6 @@ void ti_clk_patch_legacy_clks(struct ti_clk **patch); struct clk *ti_clk_register_clk(struct ti_clk *setup); int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); +u8 omap2_init_dpll_parent(struct clk_hw *hw); + #endif diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 1a7f86a68f62..886b2e9d2204 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -286,7 +286,6 @@ long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long max_rate, unsigned long *best_parent_rate, struct clk_hw **best_parent_clk); -u8 omap2_init_dpll_parent(struct clk_hw *hw); unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate); -- cgit v1.2.3 From 59245ce01a2e3ded836172266e3ac2e576a03333 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 2 Mar 2015 11:07:35 +0200 Subject: clk: ti: move OMAP4+ DPLL implementation under drivers/clk With the legacy clock support gone, the OMAP4 specific DPLL implementations can be moved under the clock driver. Change some of the function prototypes to be static at the same time, and remove some exports from the global TI clock driver header. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 6 +- arch/arm/mach-omap2/clock.h | 4 - arch/arm/mach-omap2/dpll44xx.c | 232 ---------------------------------------- drivers/clk/ti/Makefile | 6 +- drivers/clk/ti/clock.h | 14 +++ drivers/clk/ti/dpll44xx.c | 233 +++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 13 +-- 7 files changed, 254 insertions(+), 254 deletions(-) delete mode 100644 arch/arm/mach-omap2/dpll44xx.c create mode 100644 drivers/clk/ti/dpll44xx.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index fcb5d47f88ca..5bcd282f04b3 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -193,12 +193,12 @@ obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) -obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o +obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o obj-$(CONFIG_SOC_OMAP5) += $(clock-common) -obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o +obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o obj-$(CONFIG_SOC_DRA7XX) += $(clock-common) -obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o +obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o obj-$(CONFIG_SOC_AM43XX) += $(clock-common) dpll3xxx.o # OMAP2 clock rate set data (old "OPP" data) diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index ac21856d245d..d7ed2446057c 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -183,8 +183,6 @@ struct clksel { u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); void omap3_dpll_allow_idle(struct clk_hw_omap *clk); void omap3_dpll_deny_idle(struct clk_hw_omap *clk); -void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); -void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); void __init omap2_clk_disable_clkdm_control(void); @@ -204,8 +202,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); -unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); - void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, void __iomem **other_reg, u8 *other_bit); diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c deleted file mode 100644 index f231be05b9a6..000000000000 --- a/arch/arm/mach-omap2/dpll44xx.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * OMAP4-specific DPLL control functions - * - * Copyright (C) 2011 Texas Instruments, Inc. - * Rajendra Nayak - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include "clock.h" - -/* - * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that - * can supported when using the DPLL low-power mode. Frequencies are - * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control, - * Status, and Low-Power Operation Mode". - */ -#define OMAP4_DPLL_LP_FINT_MAX 1000000 -#define OMAP4_DPLL_LP_FOUT_MAX 100000000 - -/* - * Bitfield declarations - */ -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) -#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) - -/* Static rate multiplier for OMAP4 REGM4XEN clocks */ -#define OMAP4430_REGM4XEN_MULT 4 - -void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) -{ - u32 v; - u32 mask; - - if (!clk || !clk->clksel_reg) - return; - - mask = clk->flags & CLOCK_CLKOUTX2 ? - OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : - OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; - - v = omap2_clk_readl(clk, clk->clksel_reg); - /* Clear the bit to allow gatectrl */ - v &= ~mask; - omap2_clk_writel(v, clk, clk->clksel_reg); -} - -void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) -{ - u32 v; - u32 mask; - - if (!clk || !clk->clksel_reg) - return; - - mask = clk->flags & CLOCK_CLKOUTX2 ? - OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : - OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; - - v = omap2_clk_readl(clk, clk->clksel_reg); - /* Set the bit to deny gatectrl */ - v |= mask; - omap2_clk_writel(v, clk, clk->clksel_reg); -} - -const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { - .allow_idle = omap4_dpllmx_allow_gatectrl, - .deny_idle = omap4_dpllmx_deny_gatectrl, -}; - -/** - * omap4_dpll_lpmode_recalc - compute DPLL low-power setting - * @dd: pointer to the dpll data structure - * - * Calculates if low-power mode can be enabled based upon the last - * multiplier and divider values calculated. If low-power mode can be - * enabled, then the bit to enable low-power mode is stored in the - * last_rounded_lpmode variable. This implementation is based upon the - * criteria for enabling low-power mode as described in the OMAP4430/60 - * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power - * Operation Mode". - */ -static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) -{ - long fint, fout; - - fint = __clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1); - fout = fint * dd->last_rounded_m; - - if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX)) - dd->last_rounded_lpmode = 1; - else - dd->last_rounded_lpmode = 0; -} - -/** - * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit - * @clk: struct clk * of the DPLL to compute the rate for - * - * Compute the output rate for the OMAP4 DPLL represented by @clk. - * Takes the REGM4XEN bit into consideration, which is needed for the - * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) - * upon success, or 0 upon error. - */ -unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - u32 v; - unsigned long rate; - struct dpll_data *dd; - - if (!clk || !clk->dpll_data) - return 0; - - dd = clk->dpll_data; - - rate = omap2_get_dpll_rate(clk); - - /* regm4xen adds a multiplier of 4 to DPLL calculations */ - v = omap2_clk_readl(clk, dd->control_reg); - if (v & OMAP4430_DPLL_REGM4XEN_MASK) - rate *= OMAP4430_REGM4XEN_MULT; - - return rate; -} - -/** - * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit - * @clk: struct clk * of the DPLL to round a rate for - * @target_rate: the desired rate of the DPLL - * - * Compute the rate that would be programmed into the DPLL hardware - * for @clk if set_rate() were to be provided with the rate - * @target_rate. Takes the REGM4XEN bit into consideration, which is - * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before - * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or - * ~0 if an error occurred in omap2_dpll_round_rate(). - */ -long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, - unsigned long target_rate, - unsigned long *parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - struct dpll_data *dd; - long r; - - if (!clk || !clk->dpll_data) - return -EINVAL; - - dd = clk->dpll_data; - - dd->last_rounded_m4xen = 0; - - /* - * First try to compute the DPLL configuration for - * target rate without using the 4X multiplier. - */ - r = omap2_dpll_round_rate(hw, target_rate, NULL); - if (r != ~0) - goto out; - - /* - * If we did not find a valid DPLL configuration, try again, but - * this time see if using the 4X multiplier can help. Enabling the - * 4X multiplier is equivalent to dividing the target rate by 4. - */ - r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT, - NULL); - if (r == ~0) - return r; - - dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT; - dd->last_rounded_m4xen = 1; - -out: - omap4_dpll_lpmode_recalc(dd); - - return dd->last_rounded_rate; -} - -/** - * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL - * @hw: pointer to the clock to determine rate for - * @rate: target rate for the DPLL - * @best_parent_rate: pointer for returning best parent rate - * @best_parent_clk: pointer for returning best parent clock - * - * Determines which DPLL mode to use for reaching a desired rate. - * Checks whether the DPLL shall be in bypass or locked mode, and if - * locked, calculates the M,N values for the DPLL via round-rate. - * Returns a positive clock rate with success, negative error value - * in failure. - */ -long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long min_rate, - unsigned long max_rate, - unsigned long *best_parent_rate, - struct clk_hw **best_parent_clk) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - struct dpll_data *dd; - - if (!hw || !rate) - return -EINVAL; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - if (__clk_get_rate(dd->clk_bypass) == rate && - (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { - *best_parent_clk = __clk_get_hw(dd->clk_bypass); - } else { - rate = omap4_dpll_regm4xen_round_rate(hw, rate, - best_parent_rate); - *best_parent_clk = __clk_get_hw(dd->clk_ref); - } - - *best_parent_rate = rate; - - return rate; -} diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 62dae2ad3c69..c3ec3014fb2d 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -7,10 +7,10 @@ obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \ clk-3xxx.o -obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o -obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o dpll44xx.o +obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o dpll44xx.o obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \ - clk-dra7-atl.o + clk-dra7-atl.o dpll44xx.o obj-$(CONFIG_SOC_AM43XX) += $(clk-common) clk-43xx.o ifdef CONFIG_ATAGS diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 05ed10a81ace..c75d4b44cbef 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -169,6 +169,20 @@ void ti_clk_patch_legacy_clks(struct ti_clk **patch); struct clk *ti_clk_register_clk(struct ti_clk *setup); int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); +extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; + u8 omap2_init_dpll_parent(struct clk_hw *hw); +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, + unsigned long parent_rate); +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, + unsigned long target_rate, + unsigned long *parent_rate); +long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long min_rate, + unsigned long max_rate, + unsigned long *best_parent_rate, + struct clk_hw **best_parent_clk); + #endif diff --git a/drivers/clk/ti/dpll44xx.c b/drivers/clk/ti/dpll44xx.c new file mode 100644 index 000000000000..ef1a5b43d01f --- /dev/null +++ b/drivers/clk/ti/dpll44xx.c @@ -0,0 +1,233 @@ +/* + * OMAP4-specific DPLL control functions + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Rajendra Nayak + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include "clock.h" + +/* + * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that + * can supported when using the DPLL low-power mode. Frequencies are + * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control, + * Status, and Low-Power Operation Mode". + */ +#define OMAP4_DPLL_LP_FINT_MAX 1000000 +#define OMAP4_DPLL_LP_FOUT_MAX 100000000 + +/* + * Bitfield declarations + */ +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BIT(8) +#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BIT(10) +#define OMAP4430_DPLL_REGM4XEN_MASK BIT(11) + +/* Static rate multiplier for OMAP4 REGM4XEN clocks */ +#define OMAP4430_REGM4XEN_MULT 4 + +static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) +{ + u32 v; + u32 mask; + + if (!clk || !clk->clksel_reg) + return; + + mask = clk->flags & CLOCK_CLKOUTX2 ? + OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : + OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; + + v = ti_clk_ll_ops->clk_readl(clk->clksel_reg); + /* Clear the bit to allow gatectrl */ + v &= ~mask; + ti_clk_ll_ops->clk_writel(v, clk->clksel_reg); +} + +static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) +{ + u32 v; + u32 mask; + + if (!clk || !clk->clksel_reg) + return; + + mask = clk->flags & CLOCK_CLKOUTX2 ? + OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : + OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; + + v = ti_clk_ll_ops->clk_readl(clk->clksel_reg); + /* Set the bit to deny gatectrl */ + v |= mask; + ti_clk_ll_ops->clk_writel(v, clk->clksel_reg); +} + +const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { + .allow_idle = omap4_dpllmx_allow_gatectrl, + .deny_idle = omap4_dpllmx_deny_gatectrl, +}; + +/** + * omap4_dpll_lpmode_recalc - compute DPLL low-power setting + * @dd: pointer to the dpll data structure + * + * Calculates if low-power mode can be enabled based upon the last + * multiplier and divider values calculated. If low-power mode can be + * enabled, then the bit to enable low-power mode is stored in the + * last_rounded_lpmode variable. This implementation is based upon the + * criteria for enabling low-power mode as described in the OMAP4430/60 + * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power + * Operation Mode". + */ +static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) +{ + long fint, fout; + + fint = __clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1); + fout = fint * dd->last_rounded_m; + + if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX)) + dd->last_rounded_lpmode = 1; + else + dd->last_rounded_lpmode = 0; +} + +/** + * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit + * @clk: struct clk * of the DPLL to compute the rate for + * + * Compute the output rate for the OMAP4 DPLL represented by @clk. + * Takes the REGM4XEN bit into consideration, which is needed for the + * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) + * upon success, or 0 upon error. + */ +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 v; + unsigned long rate; + struct dpll_data *dd; + + if (!clk || !clk->dpll_data) + return 0; + + dd = clk->dpll_data; + + rate = omap2_get_dpll_rate(clk); + + /* regm4xen adds a multiplier of 4 to DPLL calculations */ + v = ti_clk_ll_ops->clk_readl(dd->control_reg); + if (v & OMAP4430_DPLL_REGM4XEN_MASK) + rate *= OMAP4430_REGM4XEN_MULT; + + return rate; +} + +/** + * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit + * @clk: struct clk * of the DPLL to round a rate for + * @target_rate: the desired rate of the DPLL + * + * Compute the rate that would be programmed into the DPLL hardware + * for @clk if set_rate() were to be provided with the rate + * @target_rate. Takes the REGM4XEN bit into consideration, which is + * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before + * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or + * ~0 if an error occurred in omap2_dpll_round_rate(). + */ +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, + unsigned long target_rate, + unsigned long *parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *dd; + long r; + + if (!clk || !clk->dpll_data) + return -EINVAL; + + dd = clk->dpll_data; + + dd->last_rounded_m4xen = 0; + + /* + * First try to compute the DPLL configuration for + * target rate without using the 4X multiplier. + */ + r = omap2_dpll_round_rate(hw, target_rate, NULL); + if (r != ~0) + goto out; + + /* + * If we did not find a valid DPLL configuration, try again, but + * this time see if using the 4X multiplier can help. Enabling the + * 4X multiplier is equivalent to dividing the target rate by 4. + */ + r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT, + NULL); + if (r == ~0) + return r; + + dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT; + dd->last_rounded_m4xen = 1; + +out: + omap4_dpll_lpmode_recalc(dd); + + return dd->last_rounded_rate; +} + +/** + * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL + * @hw: pointer to the clock to determine rate for + * @rate: target rate for the DPLL + * @best_parent_rate: pointer for returning best parent rate + * @best_parent_clk: pointer for returning best parent clock + * + * Determines which DPLL mode to use for reaching a desired rate. + * Checks whether the DPLL shall be in bypass or locked mode, and if + * locked, calculates the M,N values for the DPLL via round-rate. + * Returns a positive clock rate with success, negative error value + * in failure. + */ +long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate, + unsigned long min_rate, + unsigned long max_rate, + unsigned long *best_parent_rate, + struct clk_hw **best_parent_clk) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *dd; + + if (!hw || !rate) + return -EINVAL; + + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + if (__clk_get_rate(dd->clk_bypass) == rate && + (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { + *best_parent_clk = __clk_get_hw(dd->clk_bypass); + } else { + rate = omap4_dpll_regm4xen_round_rate(hw, rate, + best_parent_rate); + *best_parent_clk = __clk_get_hw(dd->clk_ref); + } + + *best_parent_rate = rate; + + return rate; +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 886b2e9d2204..ee59e076340f 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -275,17 +275,6 @@ long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long max_rate, unsigned long *best_parent_rate, struct clk_hw **best_parent_clk); -unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, - unsigned long parent_rate); -long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, - unsigned long target_rate, - unsigned long *parent_rate); -long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long min_rate, - unsigned long max_rate, - unsigned long *best_parent_rate, - struct clk_hw **best_parent_clk); unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate); @@ -314,6 +303,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); void omap2xxx_clkt_vps_init(void); +unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index); void ti_dt_clocks_register(struct ti_dt_clk *oclks); @@ -364,7 +354,6 @@ static inline void of_ti_clk_deny_autoidle_all(void) { } extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; -extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; extern const struct clk_hw_omap_ops clkhwops_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; -- cgit v1.2.3 From ef14db0977547b1982d4f6eaa305e1a22eb95778 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 2 Mar 2015 14:33:54 +0200 Subject: clk: ti: move interface clock implementation under drivers/clk With the legacy clock support gone, the OMAP interface clock implementation can be moved under the clock driver. Some temporary header file tweaks are also needed to make this change work properly. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 3 +- arch/arm/mach-omap2/clkt_iclk.c | 68 ----------------------------------------- arch/arm/mach-omap2/clock.h | 11 ------- drivers/clk/ti/Makefile | 2 +- drivers/clk/ti/clkt_iclk.c | 66 +++++++++++++++++++++++++++++++++++++++ drivers/clk/ti/clock.h | 2 ++ include/linux/clk/ti.h | 10 ++++-- 7 files changed, 78 insertions(+), 84 deletions(-) delete mode 100644 arch/arm/mach-omap2/clkt_iclk.c create mode 100644 drivers/clk/ti/clkt_iclk.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 5bcd282f04b3..a2f51564e8d4 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -185,13 +185,12 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c deleted file mode 100644 index 55eb579aeae1..000000000000 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * OMAP2/3 interface clock control - * - * Copyright (C) 2011 Nokia Corporation - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include - -#include "clock.h" - -/* Register offsets */ -#define CM_AUTOIDLE 0x30 -#define CM_ICLKEN 0x10 - -/* Private functions */ - -/* XXX */ -void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) -{ - u32 v; - void __iomem *r; - - r = (__force void __iomem *) - ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); - - v = omap2_clk_readl(clk, r); - v |= (1 << clk->enable_bit); - omap2_clk_writel(v, clk, r); -} - -/* XXX */ -void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) -{ - u32 v; - void __iomem *r; - - r = (__force void __iomem *) - ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); - - v = omap2_clk_readl(clk, r); - v &= ~(1 << clk->enable_bit); - omap2_clk_writel(v, clk, r); -} - -/* Public data */ - -const struct clk_hw_omap_ops clkhwops_iclk = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; - -const struct clk_hw_omap_ops clkhwops_iclk_wait = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, - .find_idlest = omap2_clk_dflt_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - - - diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index d7ed2446057c..ca8c42c70db5 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -198,16 +198,6 @@ int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); -/* clkt_iclk.c public functions */ -extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); -extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); - -void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, - void __iomem **other_reg, - u8 *other_bit); -void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val); int omap2_clk_enable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); int omap2_clk_deny_idle(struct clk *clk); @@ -231,7 +221,6 @@ extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; -extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index c3ec3014fb2d..23cd72638970 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,7 +1,7 @@ obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o \ - clkt_dpll.o + clkt_dpll.o clkt_iclk.o obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o diff --git a/drivers/clk/ti/clkt_iclk.c b/drivers/clk/ti/clkt_iclk.c new file mode 100644 index 000000000000..a03919df00ef --- /dev/null +++ b/drivers/clk/ti/clkt_iclk.c @@ -0,0 +1,66 @@ +/* + * OMAP2/3 interface clock control + * + * Copyright (C) 2011 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#undef DEBUG + +#include +#include +#include +#include + +#include "clock.h" + +/* Register offsets */ +#define CM_AUTOIDLE 0x30 +#define CM_ICLKEN 0x10 + +/* Private functions */ + +/* XXX */ +void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) +{ + u32 v; + void __iomem *r; + + r = (__force void __iomem *) + ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); + + v = ti_clk_ll_ops->clk_readl(r); + v |= (1 << clk->enable_bit); + ti_clk_ll_ops->clk_writel(v, r); +} + +/* XXX */ +void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) +{ + u32 v; + void __iomem *r; + + r = (__force void __iomem *) + ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); + + v = ti_clk_ll_ops->clk_readl(r); + v &= ~(1 << clk->enable_bit); + ti_clk_ll_ops->clk_writel(v, r); +} + +/* Public data */ + +const struct clk_hw_omap_ops clkhwops_iclk = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, +}; + +const struct clk_hw_omap_ops clkhwops_iclk_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap2_clk_dflt_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index c75d4b44cbef..a7256a98201d 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -170,6 +170,8 @@ struct clk *ti_clk_register_clk(struct ti_clk *setup); int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; +extern const struct clk_hw_omap_ops clkhwops_iclk; +extern const struct clk_hw_omap_ops clkhwops_iclk_wait; u8 omap2_init_dpll_parent(struct clk_hw *hw); diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index ee59e076340f..79e143dfc793 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -296,6 +296,14 @@ int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, int omap2_dflt_clk_enable(struct clk_hw *hw); void omap2_dflt_clk_disable(struct clk_hw *hw); int omap2_dflt_clk_is_enabled(struct clk_hw *hw); +void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); +void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); +void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, + void __iomem **other_reg, + u8 *other_bit); +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, + u8 *idlest_bit, u8 *idlest_val); void omap3_clk_lock_dpll5(void); unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, unsigned long parent_rate); @@ -358,8 +366,6 @@ extern const struct clk_hw_omap_ops clkhwops_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; -extern const struct clk_hw_omap_ops clkhwops_iclk; -extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; -- cgit v1.2.3 From afe2cf08401638fbf1bfaf7234be7eb3a5778b04 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 2 Mar 2015 16:24:26 +0200 Subject: ARM: OMAP3: dpll3-m2: get rid of obsolete clksel access Core DVFS support code is currently referencing clksel functionality, which is wrong. The m2 divisor has been implemented as a divider clock for a long time already, so replace the validrate check call with proper functionality. Core DVFS is currently not supported in the kernel so verifying this patch can be rather tricky, this should probably be fixed at some point. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index eb69acf21014..825e3dadb16b 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -60,7 +60,9 @@ int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate, if (!clk || !rate) return -EINVAL; - validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); + new_div = DIV_ROUND_UP(parent_rate, rate); + validrate = parent_rate / new_div; + if (validrate != rate) return -EINVAL; -- cgit v1.2.3 From 574c0116b910c7d47d7ead4f1dda21117c38723d Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 2 Mar 2015 16:30:52 +0200 Subject: ARM: OMAP2+: clk: remove obsolete clksel support code The clksel clock type is no longer used for anything, it is rather replaced with common clock divider code. Thus, remove the dead code from kernel. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 3 +- arch/arm/mach-omap2/clkt_clksel.c | 466 -------------------------------------- arch/arm/mach-omap2/clock.h | 12 - 3 files changed, 1 insertion(+), 480 deletions(-) delete mode 100644 arch/arm/mach-omap2/clkt_clksel.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index a2f51564e8d4..d03bc21d7db3 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -12,8 +12,7 @@ obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ omap_hwmod_common_data.o -clock-common = clock.o clock_common_data.o \ - clkt_clksel.o +clock-common = clock.o clock_common_data.o secure-common = omap-smc.o omap-secure.o obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c deleted file mode 100644 index 7ee26108ac0d..000000000000 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ /dev/null @@ -1,466 +0,0 @@ -/* - * clkt_clksel.c - OMAP2/3/4 clksel clock functions - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * - * clksel clocks are clocks that do not have a fixed parent, or that - * can divide their parent's rate, or possibly both at the same time, based - * on the contents of a hardware register bitfield. - * - * All of the various mux and divider settings can be encoded into - * struct clksel* data structures, and then these can be autogenerated - * from some hardware database for each new chip generation. This - * should avoid the need to write, review, and validate a lot of new - * clock code for each new chip, since it can be exported from the SoC - * design flow. This is now done on OMAP4. - * - * The fusion of mux and divider clocks is a software creation. In - * hardware reality, the multiplexer (parent selection) and the - * divider exist separately. XXX At some point these clksel clocks - * should be split into "divider" clocks and "mux" clocks to better - * match the hardware. - * - * (The name "clksel" comes from the name of the corresponding - * register field in the OMAP2/3 family of SoCs.) - * - * XXX Currently these clocks are only used in the OMAP2/3/4 code, but - * many of the OMAP1 clocks should be convertible to use this - * mechanism. - */ -#undef DEBUG - -#include -#include -#include -#include -#include - -#include "clock.h" - -/* Private functions */ - -/** - * _get_clksel_by_parent() - return clksel struct for a given clk & parent - * @clk: OMAP struct clk ptr to inspect - * @src_clk: OMAP struct clk ptr of the parent clk to search for - * - * Scan the struct clksel array associated with the clock to find - * the element associated with the supplied parent clock address. - * Returns a pointer to the struct clksel on success or NULL on error. - */ -static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, - struct clk *src_clk) -{ - const struct clksel *clks; - - if (!src_clk) - return NULL; - - for (clks = clk->clksel; clks->parent; clks++) - if (clks->parent == src_clk) - break; /* Found the requested parent */ - - if (!clks->parent) { - /* This indicates a data problem */ - WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", - __clk_get_name(clk->hw.clk), __clk_get_name(src_clk)); - return NULL; - } - - return clks; -} - -/** - * _write_clksel_reg() - program a clock's clksel register in hardware - * @clk: struct clk * to program - * @v: clksel bitfield value to program (with LSB at bit 0) - * - * Shift the clksel register bitfield value @v to its appropriate - * location in the clksel register and write it in. This function - * will ensure that the write to the clksel_reg reaches its - * destination before returning -- important since PRM and CM register - * accesses can be quite slow compared to ARM cycles -- but does not - * take into account any time the hardware might take to switch the - * clock source. - */ -static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) -{ - u32 v; - - v = omap2_clk_readl(clk, clk->clksel_reg); - v &= ~clk->clksel_mask; - v |= field_val << __ffs(clk->clksel_mask); - omap2_clk_writel(v, clk, clk->clksel_reg); - - v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */ -} - -/** - * _clksel_to_divisor() - turn clksel field value into integer divider - * @clk: OMAP struct clk to use - * @field_val: register field value to find - * - * Given a struct clk of a rate-selectable clksel clock, and a register field - * value to search for, find the corresponding clock divisor. The register - * field value should be pre-masked and shifted down so the LSB is at bit 0 - * before calling. Returns 0 on error or returns the actual integer divisor - * upon success. - */ -static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) -{ - const struct clksel *clks; - const struct clksel_rate *clkr; - struct clk *parent; - - parent = __clk_get_parent(clk->hw.clk); - - clks = _get_clksel_by_parent(clk, parent); - if (!clks) - return 0; - - for (clkr = clks->rates; clkr->div; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - if (clkr->val == field_val) - break; - } - - if (!clkr->div) { - /* This indicates a data error */ - WARN(1, "clock: %s: could not find fieldval %d for parent %s\n", - __clk_get_name(clk->hw.clk), field_val, - __clk_get_name(parent)); - return 0; - } - - return clkr->div; -} - -/** - * _divisor_to_clksel() - turn clksel integer divisor into a field value - * @clk: OMAP struct clk to use - * @div: integer divisor to search for - * - * Given a struct clk of a rate-selectable clksel clock, and a clock - * divisor, find the corresponding register field value. Returns the - * register field value _before_ left-shifting (i.e., LSB is at bit - * 0); or returns 0xFFFFFFFF (~0) upon error. - */ -static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) -{ - const struct clksel *clks; - const struct clksel_rate *clkr; - struct clk *parent; - - /* should never happen */ - WARN_ON(div == 0); - - parent = __clk_get_parent(clk->hw.clk); - clks = _get_clksel_by_parent(clk, parent); - if (!clks) - return ~0; - - for (clkr = clks->rates; clkr->div; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - if (clkr->div == div) - break; - } - - if (!clkr->div) { - pr_err("clock: %s: could not find divisor %d for parent %s\n", - __clk_get_name(clk->hw.clk), div, - __clk_get_name(parent)); - return ~0; - } - - return clkr->val; -} - -/** - * _read_divisor() - get current divisor applied to parent clock (from hdwr) - * @clk: OMAP struct clk to use. - * - * Read the current divisor register value for @clk that is programmed - * into the hardware, convert it into the actual divisor value, and - * return it; or return 0 on error. - */ -static u32 _read_divisor(struct clk_hw_omap *clk) -{ - u32 v; - - if (!clk->clksel || !clk->clksel_mask) - return 0; - - v = omap2_clk_readl(clk, clk->clksel_reg); - v &= clk->clksel_mask; - v >>= __ffs(clk->clksel_mask); - - return _clksel_to_divisor(clk, v); -} - -/* Public functions */ - -/** - * omap2_clksel_round_rate_div() - find divisor for the given clock and rate - * @clk: OMAP struct clk to use - * @target_rate: desired clock rate - * @new_div: ptr to where we should store the divisor - * - * Finds 'best' divider value in an array based on the source and target - * rates. The divider array must be sorted with smallest divider first. - * This function is also used by the DPLL3 M2 divider code. - * - * Returns the rounded clock rate or returns 0xffffffff on error. - */ -u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, - unsigned long target_rate, - u32 *new_div) -{ - unsigned long test_rate; - const struct clksel *clks; - const struct clksel_rate *clkr; - u32 last_div = 0; - struct clk *parent; - unsigned long parent_rate; - const char *clk_name; - - parent = __clk_get_parent(clk->hw.clk); - clk_name = __clk_get_name(clk->hw.clk); - parent_rate = __clk_get_rate(parent); - - if (!clk->clksel || !clk->clksel_mask) - return ~0; - - pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", - clk_name, target_rate); - - *new_div = 1; - - clks = _get_clksel_by_parent(clk, parent); - if (!clks) - return ~0; - - for (clkr = clks->rates; clkr->div; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - /* Sanity check */ - if (clkr->div <= last_div) - pr_err("clock: %s: clksel_rate table not sorted\n", - clk_name); - - last_div = clkr->div; - - test_rate = parent_rate / clkr->div; - - if (test_rate <= target_rate) - break; /* found it */ - } - - if (!clkr->div) { - pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n", - clk_name, target_rate, __clk_get_name(parent)); - return ~0; - } - - *new_div = clkr->div; - - pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, - (parent_rate / clkr->div)); - - return parent_rate / clkr->div; -} - -/* - * Clocktype interface functions to the OMAP clock code - * (i.e., those used in struct clk field function pointers, etc.) - */ - -/** - * omap2_clksel_find_parent_index() - return the array index of the current - * hardware parent of @hw - * @hw: struct clk_hw * to find the current hardware parent of - * - * Given a struct clk_hw pointer @hw to the 'hw' member of a struct - * clk_hw_omap record representing a source-selectable hardware clock, - * read the hardware register and determine what its parent is - * currently set to. Intended to be called only by the common clock - * framework struct clk_hw_ops.get_parent function pointer. Return - * the array index of this parent clock upon success -- there is no - * way to return an error, so if we encounter an error, just WARN() - * and pretend that we know that we're doing. - */ -u8 omap2_clksel_find_parent_index(struct clk_hw *hw) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - const struct clksel *clks; - const struct clksel_rate *clkr; - u32 r, found = 0; - struct clk *parent; - const char *clk_name; - int ret = 0, f = 0; - - parent = __clk_get_parent(hw->clk); - clk_name = __clk_get_name(hw->clk); - - /* XXX should be able to return an error */ - WARN((!clk->clksel || !clk->clksel_mask), - "clock: %s: attempt to call on a non-clksel clock", clk_name); - - r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask; - r >>= __ffs(clk->clksel_mask); - - for (clks = clk->clksel; clks->parent && !found; clks++) { - for (clkr = clks->rates; clkr->div && !found; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - if (clkr->val == r) { - found = 1; - ret = f; - } - } - f++; - } - - /* This indicates a data error */ - WARN(!found, "clock: %s: init parent: could not find regval %0x\n", - clk_name, r); - - return ret; -} - - -/** - * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field - * @clk: struct clk * - * - * This function is intended to be called only by the clock framework. - * Each clksel clock should have its struct clk .recalc field set to this - * function. Returns the clock's current rate, based on its parent's rate - * and its current divisor setting in the hardware. - */ -unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) -{ - unsigned long rate; - u32 div = 0; - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - - if (!parent_rate) - return 0; - - div = _read_divisor(clk); - if (!div) - rate = parent_rate; - else - rate = parent_rate / div; - - pr_debug("%s: recalc'd %s's rate to %lu (div %d)\n", __func__, - __clk_get_name(hw->clk), rate, div); - - return rate; -} - -/** - * omap2_clksel_round_rate() - find rounded rate for the given clock and rate - * @clk: OMAP struct clk to use - * @target_rate: desired clock rate - * - * This function is intended to be called only by the clock framework. - * Finds best target rate based on the source clock and possible dividers. - * rates. The divider array must be sorted with smallest divider first. - * - * Returns the rounded clock rate or returns 0xffffffff on error. - */ -long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, - unsigned long *parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - u32 new_div; - - return omap2_clksel_round_rate_div(clk, target_rate, &new_div); -} - -/** - * omap2_clksel_set_rate() - program clock rate in hardware - * @clk: struct clk * to program rate - * @rate: target rate to program - * - * This function is intended to be called only by the clock framework. - * Program @clk's rate to @rate in the hardware. The clock can be - * either enabled or disabled when this happens, although if the clock - * is enabled, some downstream devices may glitch or behave - * unpredictably when the clock rate is changed - this depends on the - * hardware. This function does not currently check the usecount of - * the clock, so if multiple drivers are using the clock, and the rate - * is changed, they will all be affected without any notification. - * Returns -EINVAL upon error, or 0 upon success. - */ -int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - u32 field_val, validrate, new_div = 0; - - if (!clk->clksel || !clk->clksel_mask) - return -EINVAL; - - validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); - if (validrate != rate) - return -EINVAL; - - field_val = _divisor_to_clksel(clk, new_div); - if (field_val == ~0) - return -EINVAL; - - _write_clksel_reg(clk, field_val); - - pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk), - __clk_get_rate(hw->clk)); - - return 0; -} - -/* - * Clksel parent setting function - not passed in struct clk function - * pointer - instead, the OMAP clock code currently assumes that any - * parent-setting clock is a clksel clock, and calls - * omap2_clksel_set_parent() by default - */ - -/** - * omap2_clksel_set_parent() - change a clock's parent clock - * @clk: struct clk * of the child clock - * @new_parent: struct clk * of the new parent clock - * - * This function is intended to be called only by the clock framework. - * Change the parent clock of clock @clk to @new_parent. This is - * intended to be used while @clk is disabled. This function does not - * currently check the usecount of the clock, so if multiple drivers - * are using the clock, and the parent is changed, they will all be - * affected without any notification. Returns -EINVAL upon error, or - * 0 upon success. - */ -int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - - if (!clk->clksel || !clk->clksel_mask) - return -EINVAL; - - _write_clksel_reg(clk, field_val); - return 0; -} diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index ca8c42c70db5..9efff4bb291b 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -186,18 +186,6 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk); void __init omap2_clk_disable_clkdm_control(void); -/* clkt_clksel.c public functions */ -u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, - unsigned long target_rate, - u32 *new_div); -u8 omap2_clksel_find_parent_index(struct clk_hw *hw); -unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate); -long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, - unsigned long *parent_rate); -int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate); -int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); - int omap2_clk_enable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); int omap2_clk_deny_idle(struct clk *clk); -- cgit v1.2.3 From c06bfbe75ef52ff548bffa3d89587aaaa92893bf Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 2 Mar 2015 17:06:59 +0200 Subject: ARM: OMAP2+: clock: remove clock_common_data.c file This only contains clksel tables that were used with the legacy clock data. Now that legacy clock data is completely gone, this file can be removed also. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/clock.h | 14 ---- arch/arm/mach-omap2/clock_common_data.c | 115 -------------------------------- 3 files changed, 1 insertion(+), 130 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock_common_data.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d03bc21d7db3..98d5030df137 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -12,7 +12,7 @@ obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ omap_hwmod_common_data.o -clock-common = clock.o clock_common_data.o +clock-common = clock.o secure-common = omap-smc.o omap-secure.o obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 9efff4bb291b..b71d43051c26 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -204,11 +204,6 @@ extern const struct clkops clkops_omap2_dflt; extern struct clk_functions omap2_clk_functions; -extern const struct clksel_rate gpt_32k_rates[]; -extern const struct clksel_rate gpt_sys_rates[]; -extern const struct clksel_rate gfx_l3_rates[]; -extern const struct clksel_rate dsp_ick_rates[]; - extern const struct clk_hw_omap_ops clkhwops_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; @@ -217,15 +212,6 @@ extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; extern const struct clk_hw_omap_ops clkhwops_apll54; extern const struct clk_hw_omap_ops clkhwops_apll96; -/* clksel_rate blocks shared between OMAP44xx and AM33xx */ -extern const struct clksel_rate div_1_0_rates[]; -extern const struct clksel_rate div3_1to4_rates[]; -extern const struct clksel_rate div_1_1_rates[]; -extern const struct clksel_rate div_1_2_rates[]; -extern const struct clksel_rate div_1_3_rates[]; -extern const struct clksel_rate div_1_4_rates[]; -extern const struct clksel_rate div31_1to31_rates[]; - extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c deleted file mode 100644 index 61b60dfb14ce..000000000000 --- a/arch/arm/mach-omap2/clock_common_data.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/clock_common_data.c - * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2009 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This file contains clock data that is common to both the OMAP2xxx and - * OMAP3xxx clock definition files. - */ - -#include "clock.h" - -/* clksel_rate data common to 24xx/343x */ -const struct clksel_rate gpt_32k_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX }, - { .div = 0 } -}; - -const struct clksel_rate gpt_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX }, - { .div = 0 } -}; - -const struct clksel_rate gfx_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX }, - { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX }, - { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX }, - { .div = 0 } -}; - -const struct clksel_rate dsp_ick_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_243X }, - { .div = 0 }, -}; - - -/* clksel_rate blocks shared between OMAP44xx and AM33xx */ - -const struct clksel_rate div_1_0_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 0 }, -}; - -const struct clksel_rate div3_1to4_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 4, .val = 2, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -const struct clksel_rate div_1_1_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 0 }, -}; - -const struct clksel_rate div_1_2_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 0 }, -}; - -const struct clksel_rate div_1_3_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 0 }, -}; - -const struct clksel_rate div_1_4_rates[] = { - { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 0 }, -}; - -const struct clksel_rate div31_1to31_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, - { .div = 0 }, -}; -- cgit v1.2.3 From 5100349b95bf238c6c83cb702a64a56a6ee58fc9 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 2 Mar 2015 17:10:39 +0200 Subject: ARM: OMAP36xx: remove clock36xx.c/.h files These files contain legacy clock implementations which are no longer used for anything, thus remove them completely. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/clock36xx.c | 69 ----------------------------------------- arch/arm/mach-omap2/clock36xx.h | 13 -------- 3 files changed, 1 insertion(+), 83 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock36xx.c delete mode 100644 arch/arm/mach-omap2/clock36xx.h diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 98d5030df137..f33d01105bf7 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -188,7 +188,7 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o -obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o +obj-$(CONFIG_ARCH_OMAP3) += clock3517.o obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c deleted file mode 100644 index 91ccb962e09e..000000000000 --- a/arch/arm/mach-omap2/clock36xx.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * OMAP36xx-specific clkops - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation - * - * Mike Turquette - * Vijaykumar GN - * Paul Walmsley - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, - * Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include -#include - -#include "clock.h" -#include "clock36xx.h" -#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) - -/** - * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering - * from HSDivider PWRDN problem Implements Errata ID: i556. - * @clk: DPLL output struct clk - * - * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, - * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset - * valueafter their respective PWRDN bits are set. Any dummy write - * (Any other value different from the Read value) to the - * corresponding CM_CLKSEL register will refresh the dividers. - */ -int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) -{ - struct clk_divider *parent; - struct clk_hw *parent_hw; - u32 dummy_v, orig_v; - struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk); - int ret; - - /* Clear PWRDN bit of HSDIVIDER */ - ret = omap2_dflt_clk_enable(clk); - - parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); - parent = to_clk_divider(parent_hw); - - /* Restore the dividers */ - if (!ret) { - orig_v = omap2_clk_readl(omap_clk, parent->reg); - dummy_v = orig_v; - - /* Write any other value different from the Read value */ - dummy_v ^= (1 << parent->shift); - omap2_clk_writel(dummy_v, omap_clk, parent->reg); - - /* Write the original divider */ - omap2_clk_writel(orig_v, omap_clk, parent->reg); - } - - return ret; -} diff --git a/arch/arm/mach-omap2/clock36xx.h b/arch/arm/mach-omap2/clock36xx.h deleted file mode 100644 index 945bb7f083e9..000000000000 --- a/arch/arm/mach-omap2/clock36xx.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * OMAP36xx clock function prototypes and macros - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H -#define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H - -extern int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *hw); - -#endif -- cgit v1.2.3 From bf22bae794d696e411acfcac39b415e160e93834 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 2 Mar 2015 19:06:54 +0200 Subject: clk: ti: autoidle: move generic autoidle handling code to clock driver This is no longer needed in platform directory, as the legacy clock data is gone, so move it under TI clock driver. Some static functions are renamed also. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c | 104 ------------------------------------ arch/arm/mach-omap2/clock.h | 3 -- drivers/clk/ti/autoidle.c | 119 +++++++++++++++++++++++++++++++++++++++--- drivers/clk/ti/clock.h | 3 ++ drivers/clk/ti/fixed-factor.c | 2 + include/linux/clk/ti.h | 13 ++--- 6 files changed, 119 insertions(+), 125 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index cbc65b3a3b62..42ce860e1d4c 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -69,8 +69,6 @@ u16 cpu_mask; */ static bool clkdm_control = true; -static LIST_HEAD(clk_hw_omap_clocks); - struct clk_iomap { struct regmap *regmap; void __iomem *mem; @@ -578,108 +576,6 @@ static int __init omap_clk_setup(char *str) } __setup("mpurate=", omap_clk_setup); -/** - * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock - * @clk: struct clk * to initialize - * - * Add an OMAP clock @clk to the internal list of OMAP clocks. Used - * temporarily for autoidle handling, until this support can be - * integrated into the common clock framework code in some way. No - * return value. - */ -void omap2_init_clk_hw_omap_clocks(struct clk *clk) -{ - struct clk_hw_omap *c; - - if (__clk_get_flags(clk) & CLK_IS_BASIC) - return; - - c = to_clk_hw_omap(__clk_get_hw(clk)); - list_add(&c->node, &clk_hw_omap_clocks); -} - -/** - * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that - * support it - * - * Enable clock autoidle on all OMAP clocks that have allow_idle - * function pointers associated with them. This function is intended - * to be temporary until support for this is added to the common clock - * code. Returns 0. - */ -int omap2_clk_enable_autoidle_all(void) -{ - struct clk_hw_omap *c; - - list_for_each_entry(c, &clk_hw_omap_clocks, node) - if (c->ops && c->ops->allow_idle) - c->ops->allow_idle(c); - - of_ti_clk_allow_autoidle_all(); - - return 0; -} - -/** - * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that - * support it - * - * Disable clock autoidle on all OMAP clocks that have allow_idle - * function pointers associated with them. This function is intended - * to be temporary until support for this is added to the common clock - * code. Returns 0. - */ -int omap2_clk_disable_autoidle_all(void) -{ - struct clk_hw_omap *c; - - list_for_each_entry(c, &clk_hw_omap_clocks, node) - if (c->ops && c->ops->deny_idle) - c->ops->deny_idle(c); - - of_ti_clk_deny_autoidle_all(); - - return 0; -} - -/** - * omap2_clk_deny_idle - disable autoidle on an OMAP clock - * @clk: struct clk * to disable autoidle for - * - * Disable autoidle on an OMAP clock. - */ -int omap2_clk_deny_idle(struct clk *clk) -{ - struct clk_hw_omap *c; - - if (__clk_get_flags(clk) & CLK_IS_BASIC) - return -EINVAL; - - c = to_clk_hw_omap(__clk_get_hw(clk)); - if (c->ops && c->ops->deny_idle) - c->ops->deny_idle(c); - return 0; -} - -/** - * omap2_clk_allow_idle - enable autoidle on an OMAP clock - * @clk: struct clk * to enable autoidle for - * - * Enable autoidle on an OMAP clock. - */ -int omap2_clk_allow_idle(struct clk *clk) -{ - struct clk_hw_omap *c; - - if (__clk_get_flags(clk) & CLK_IS_BASIC) - return -EINVAL; - - c = to_clk_hw_omap(__clk_get_hw(clk)); - if (c->ops && c->ops->allow_idle) - c->ops->allow_idle(c); - return 0; -} - /** * omap2_clk_enable_init_clocks - prepare & enable a list of clocks * @clk_names: ptr to an array of strings of clock names to enable diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index b71d43051c26..950a17ae4f36 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -186,9 +186,6 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk); void __init omap2_clk_disable_clkdm_control(void); -int omap2_clk_enable_autoidle_all(void); -int omap2_clk_allow_idle(struct clk *clk); -int omap2_clk_deny_idle(struct clk *clk); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c index e75c64c9e81c..3dbcc3681058 100644 --- a/drivers/clk/ti/autoidle.c +++ b/drivers/clk/ti/autoidle.c @@ -33,8 +33,47 @@ struct clk_ti_autoidle { #define AUTOIDLE_LOW 0x1 static LIST_HEAD(autoidle_clks); +static LIST_HEAD(clk_hw_omap_clocks); -static void ti_allow_autoidle(struct clk_ti_autoidle *clk) +/** + * omap2_clk_deny_idle - disable autoidle on an OMAP clock + * @clk: struct clk * to disable autoidle for + * + * Disable autoidle on an OMAP clock. + */ +int omap2_clk_deny_idle(struct clk *clk) +{ + struct clk_hw_omap *c; + + if (__clk_get_flags(clk) & CLK_IS_BASIC) + return -EINVAL; + + c = to_clk_hw_omap(__clk_get_hw(clk)); + if (c->ops && c->ops->deny_idle) + c->ops->deny_idle(c); + return 0; +} + +/** + * omap2_clk_allow_idle - enable autoidle on an OMAP clock + * @clk: struct clk * to enable autoidle for + * + * Enable autoidle on an OMAP clock. + */ +int omap2_clk_allow_idle(struct clk *clk) +{ + struct clk_hw_omap *c; + + if (__clk_get_flags(clk) & CLK_IS_BASIC) + return -EINVAL; + + c = to_clk_hw_omap(__clk_get_hw(clk)); + if (c->ops && c->ops->allow_idle) + c->ops->allow_idle(c); + return 0; +} + +static void _allow_autoidle(struct clk_ti_autoidle *clk) { u32 val; @@ -48,7 +87,7 @@ static void ti_allow_autoidle(struct clk_ti_autoidle *clk) ti_clk_ll_ops->clk_writel(val, clk->reg); } -static void ti_deny_autoidle(struct clk_ti_autoidle *clk) +static void _deny_autoidle(struct clk_ti_autoidle *clk) { u32 val; @@ -63,31 +102,31 @@ static void ti_deny_autoidle(struct clk_ti_autoidle *clk) } /** - * of_ti_clk_allow_autoidle_all - enable autoidle for all clocks + * _clk_generic_allow_autoidle_all - enable autoidle for all clocks * * Enables hardware autoidle for all registered DT clocks, which have * the feature. */ -void of_ti_clk_allow_autoidle_all(void) +static void _clk_generic_allow_autoidle_all(void) { struct clk_ti_autoidle *c; list_for_each_entry(c, &autoidle_clks, node) - ti_allow_autoidle(c); + _allow_autoidle(c); } /** - * of_ti_clk_deny_autoidle_all - disable autoidle for all clocks + * _clk_generic_deny_autoidle_all - disable autoidle for all clocks * * Disables hardware autoidle for all registered DT clocks, which have * the feature. */ -void of_ti_clk_deny_autoidle_all(void) +static void _clk_generic_deny_autoidle_all(void) { struct clk_ti_autoidle *c; list_for_each_entry(c, &autoidle_clks, node) - ti_deny_autoidle(c); + _deny_autoidle(c); } /** @@ -131,3 +170,67 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node) return 0; } + +/** + * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock + * @clk: struct clk * to initialize + * + * Add an OMAP clock @clk to the internal list of OMAP clocks. Used + * temporarily for autoidle handling, until this support can be + * integrated into the common clock framework code in some way. No + * return value. + */ +void omap2_init_clk_hw_omap_clocks(struct clk *clk) +{ + struct clk_hw_omap *c; + + if (__clk_get_flags(clk) & CLK_IS_BASIC) + return; + + c = to_clk_hw_omap(__clk_get_hw(clk)); + list_add(&c->node, &clk_hw_omap_clocks); +} + +/** + * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that + * support it + * + * Enable clock autoidle on all OMAP clocks that have allow_idle + * function pointers associated with them. This function is intended + * to be temporary until support for this is added to the common clock + * code. Returns 0. + */ +int omap2_clk_enable_autoidle_all(void) +{ + struct clk_hw_omap *c; + + list_for_each_entry(c, &clk_hw_omap_clocks, node) + if (c->ops && c->ops->allow_idle) + c->ops->allow_idle(c); + + _clk_generic_allow_autoidle_all(); + + return 0; +} + +/** + * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that + * support it + * + * Disable clock autoidle on all OMAP clocks that have allow_idle + * function pointers associated with them. This function is intended + * to be temporary until support for this is added to the common clock + * code. Returns 0. + */ +int omap2_clk_disable_autoidle_all(void) +{ + struct clk_hw_omap *c; + + list_for_each_entry(c, &clk_hw_omap_clocks, node) + if (c->ops && c->ops->deny_idle) + c->ops->deny_idle(c); + + _clk_generic_deny_autoidle_all(); + + return 0; +} diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index a7256a98201d..9b51021f509a 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -169,6 +169,9 @@ void ti_clk_patch_legacy_clks(struct ti_clk **patch); struct clk *ti_clk_register_clk(struct ti_clk *setup); int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); +void omap2_init_clk_hw_omap_clocks(struct clk *clk); +int of_ti_clk_autoidle_setup(struct device_node *node); + extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; extern const struct clk_hw_omap_ops clkhwops_iclk; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c index c2c8a287408c..3cd406768909 100644 --- a/drivers/clk/ti/fixed-factor.c +++ b/drivers/clk/ti/fixed-factor.c @@ -22,6 +22,8 @@ #include #include +#include "clock.h" + #undef pr_fmt #define pr_fmt(fmt) "%s: " fmt, __func__ diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 79e143dfc793..320e107f9a7a 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -259,7 +259,6 @@ extern const struct clk_ops ti_clk_mux_ops; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) -void omap2_init_clk_hw_omap_clocks(struct clk *clk); int omap3_noncore_dpll_enable(struct clk_hw *hw); void omap3_noncore_dpll_disable(struct clk_hw *hw); int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); @@ -288,6 +287,9 @@ long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate, int omap2_clkops_enable_clkdm(struct clk_hw *hw); void omap2_clkops_disable_clkdm(struct clk_hw *hw); int omap2_clk_disable_autoidle_all(void); +int omap2_clk_enable_autoidle_all(void); +int omap2_clk_allow_idle(struct clk *clk); +int omap2_clk_deny_idle(struct clk *clk); void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); @@ -320,7 +322,6 @@ void ti_dt_clk_init_retry_clks(void); void ti_dt_clockdomains_setup(void); int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, ti_of_clk_init_cb_t func); -int of_ti_clk_autoidle_setup(struct device_node *node); int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); int omap3430_dt_clk_init(void); @@ -351,14 +352,6 @@ struct ti_clk_features { void ti_clk_setup_features(struct ti_clk_features *features); const struct ti_clk_features *ti_clk_get_features(void); -#ifdef CONFIG_OF -void of_ti_clk_allow_autoidle_all(void); -void of_ti_clk_deny_autoidle_all(void); -#else -static inline void of_ti_clk_allow_autoidle_all(void) { } -static inline void of_ti_clk_deny_autoidle_all(void) { } -#endif - extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; -- cgit v1.2.3 From a5aa8a603efa25dd41220bff990da025c93b632b Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 3 Mar 2015 10:51:01 +0200 Subject: clk: ti: move omap2_clk_enable_init_clocks under clock driver This is no longer used outside clock driver, so move it under the driver and remove the export for it from the global header file. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c | 24 ------------------------ drivers/clk/ti/clk-2xxx.c | 2 ++ drivers/clk/ti/clk-33xx.c | 2 ++ drivers/clk/ti/clk-3xxx.c | 1 + drivers/clk/ti/clk-816x.c | 2 ++ drivers/clk/ti/clk.c | 24 ++++++++++++++++++++++++ drivers/clk/ti/clock.h | 1 + include/linux/clk/ti.h | 1 - 8 files changed, 32 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 42ce860e1d4c..234cedf8967d 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -576,30 +576,6 @@ static int __init omap_clk_setup(char *str) } __setup("mpurate=", omap_clk_setup); -/** - * omap2_clk_enable_init_clocks - prepare & enable a list of clocks - * @clk_names: ptr to an array of strings of clock names to enable - * @num_clocks: number of clock names in @clk_names - * - * Prepare and enable a list of clocks, named by @clk_names. No - * return value. XXX Deprecated; only needed until these clocks are - * properly claimed and enabled by the drivers or core code that uses - * them. XXX What code disables & calls clk_put on these clocks? - */ -void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) -{ - struct clk *init_clk; - int i; - - for (i = 0; i < num_clocks; i++) { - init_clk = clk_get(NULL, clk_names[i]); - if (WARN(IS_ERR(init_clk), "could not find init clock %s\n", - clk_names[i])) - continue; - clk_prepare_enable(init_clk); - } -} - const struct clk_hw_omap_ops clkhwops_wait = { .find_idlest = omap2_clk_dflt_find_idlest, .find_companion = omap2_clk_dflt_find_companion, diff --git a/drivers/clk/ti/clk-2xxx.c b/drivers/clk/ti/clk-2xxx.c index c808ab3d2bb2..bd8790be2ab1 100644 --- a/drivers/clk/ti/clk-2xxx.c +++ b/drivers/clk/ti/clk-2xxx.c @@ -19,6 +19,8 @@ #include #include +#include "clock.h" + static struct ti_dt_clk omap2xxx_clks[] = { DT_CLK(NULL, "func_32k_ck", "func_32k_ck"), DT_CLK(NULL, "secure_32k_ck", "secure_32k_ck"), diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c index 028b33783d38..733f9d374d0f 100644 --- a/drivers/clk/ti/clk-33xx.c +++ b/drivers/clk/ti/clk-33xx.c @@ -19,6 +19,8 @@ #include #include +#include "clock.h" + static struct ti_dt_clk am33xx_clks[] = { DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c index 757636d166cf..bb3b88359daf 100644 --- a/drivers/clk/ti/clk-3xxx.c +++ b/drivers/clk/ti/clk-3xxx.c @@ -19,6 +19,7 @@ #include #include +#include "clock.h" static struct ti_dt_clk omap3xxx_clks[] = { DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"), diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c index 9451e651a1ff..c69352b24dba 100644 --- a/drivers/clk/ti/clk-816x.c +++ b/drivers/clk/ti/clk-816x.c @@ -14,6 +14,8 @@ #include #include +#include "clock.h" + static struct ti_dt_clk dm816x_clks[] = { DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index e65ae4acff9c..5baea03cfc92 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -336,3 +336,27 @@ const struct ti_clk_features *ti_clk_get_features(void) { return &ti_clk_features; } + +/** + * omap2_clk_enable_init_clocks - prepare & enable a list of clocks + * @clk_names: ptr to an array of strings of clock names to enable + * @num_clocks: number of clock names in @clk_names + * + * Prepare and enable a list of clocks, named by @clk_names. No + * return value. XXX Deprecated; only needed until these clocks are + * properly claimed and enabled by the drivers or core code that uses + * them. XXX What code disables & calls clk_put on these clocks? + */ +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) +{ + struct clk *init_clk; + int i; + + for (i = 0; i < num_clocks; i++) { + init_clk = clk_get(NULL, clk_names[i]); + if (WARN(IS_ERR(init_clk), "could not find init clock %s\n", + clk_names[i])) + continue; + clk_prepare_enable(init_clk); + } +} diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 9b51021f509a..4b26af8a273d 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -171,6 +171,7 @@ int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); void omap2_init_clk_hw_omap_clocks(struct clk *clk); int of_ti_clk_autoidle_setup(struct device_node *node); +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; extern const struct clk_hw_omap_ops clkhwops_iclk; diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 320e107f9a7a..61deace552ec 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -290,7 +290,6 @@ int omap2_clk_disable_autoidle_all(void); int omap2_clk_enable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); int omap2_clk_deny_idle(struct clk *clk); -void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, -- cgit v1.2.3 From 846fdf2a3dd3343e5f461659f905c5ba43f325cc Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 3 Mar 2015 10:58:56 +0200 Subject: ARM: OMAP2+: clock: remove support for legacy mpurate command line param The legacy support is wrong and dangerous, as it doesn't take any OPPs into account and does not scale voltages. Switching mpurate should be handled through cpufreq. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/clock.c | 41 ----------------------------- arch/arm/mach-omap2/clock.h | 1 - arch/arm/mach-omap2/clock2xxx.c | 57 ----------------------------------------- arch/arm/mach-omap2/clock3xxx.c | 25 ------------------ 5 files changed, 1 insertion(+), 125 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock2xxx.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index f33d01105bf7..bf5d71d9fd2b 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -181,7 +181,7 @@ obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common) obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o # Clock framework -obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o +obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 234cedf8967d..94a4949be9b0 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -581,47 +581,6 @@ const struct clk_hw_omap_ops clkhwops_wait = { .find_companion = omap2_clk_dflt_find_companion, }; -/** - * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument - * @mpurate_ck_name: clk name of the clock to change rate - * - * Change the ARM MPU clock rate to the rate specified on the command - * line, if one was specified. @mpurate_ck_name should be - * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. - * XXX Does not handle voltage scaling - on OMAP2xxx this is currently - * handled by the virt_prcm_set clock, but this should be handled by - * the OPP layer. XXX This is intended to be handled by the OPP layer - * code in the near future and should be removed from the clock code. - * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects - * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name - * cannot be found, or 0 upon success. - */ -int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) -{ - struct clk *mpurate_ck; - int r; - - if (!mpurate) - return -EINVAL; - - mpurate_ck = clk_get(NULL, mpurate_ck_name); - if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) - return -ENOENT; - - r = clk_set_rate(mpurate_ck, mpurate); - if (r < 0) { - WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", - mpurate_ck_name, mpurate, r); - clk_put(mpurate_ck); - return -EINVAL; - } - - calibrate_delay(); - clk_put(mpurate_ck); - - return 0; -} - /** * omap2_clk_print_new_rates - print summary of current clock tree rates * @hfclkin_ck_name: clk name for the off-chip HF oscillator diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 950a17ae4f36..e2781b4aaeb4 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -186,7 +186,6 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk); void __init omap2_clk_disable_clkdm_control(void); -int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, const char *mpu_ck_name); diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c deleted file mode 100644 index b870f6a9e283..000000000000 --- a/arch/arm/mach-omap2/clock2xxx.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * clock2xxx.c - OMAP2xxx-specific clock integration code - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, - * Gordon McNutt and RidgeRun, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include -#include - -#include "soc.h" -#include "clock.h" -#include "clock2xxx.h" -#include "cm.h" -#include "cm-regbits-24xx.h" - -struct clk_hw *dclk_hw; -/* - * Omap24xx specific clock functions - */ - -/* - * Switch the MPU rate if specified on cmdline. We cannot do this - * early until cmdline is parsed. XXX This should be removed from the - * clock code and handled by the OPP layer code in the near future. - */ -static int __init omap2xxx_clk_arch_init(void) -{ - int ret; - - if (!cpu_is_omap24xx()) - return 0; - - ret = omap2_clk_switch_mpurate_at_boot("virt_prcm_set"); - if (!ret) - omap2_clk_print_new_rates("sys_ck", "dpll_ck", "mpu_ck"); - - return ret; -} - -omap_arch_initcall(omap2xxx_clk_arch_init); - - diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 8bede6aec44f..4bd61222aa33 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -108,28 +108,3 @@ void __init omap3_clk_lock_dpll5(void) clk_disable_unprepare(dpll5_clk); return; } - -/* Common clock code */ - -/* - * Switch the MPU rate if specified on cmdline. We cannot do this - * early until cmdline is parsed. XXX This should be removed from the - * clock code and handled by the OPP layer code in the near future. - */ -static int __init omap3xxx_clk_arch_init(void) -{ - int ret; - - if (!cpu_is_omap34xx()) - return 0; - - ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck"); - if (!ret) - omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck"); - - return ret; -} - -omap_arch_initcall(omap3xxx_clk_arch_init); - - -- cgit v1.2.3 From 9a356d622e8e559eff50b298e574bbc34e860aba Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 3 Mar 2015 11:14:31 +0200 Subject: ARM: OMAP2+: clock: add support for clkdm ops to the low level clk ops Clock driver requires access to certain clockdomain handling ops once the code is being moved over under clock driver. Example of this is clk_enable / clk_disable under omap3 DPLL code. The required clkdm APIs are now exported through the ti_clk_ll_ops struct. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c | 2 ++ include/linux/clk/ti.h | 16 +++++++++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 94a4949be9b0..d6afc1291fe9 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -120,6 +120,8 @@ u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) static struct ti_clk_ll_ops omap_clk_ll_ops = { .clk_readl = clk_memmap_readl, .clk_writel = clk_memmap_writel, + .clkdm_clk_enable = clkdm_clk_enable, + .clkdm_clk_disable = clkdm_clk_disable, }; /** diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 61deace552ec..fcf91844e94b 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -238,18 +238,24 @@ struct clk_omap_reg { }; /** - * struct ti_clk_ll_ops - low-level register access ops for a clock + * struct ti_clk_ll_ops - low-level ops for clocks * @clk_readl: pointer to register read function * @clk_writel: pointer to register write function + * @clkdm_clk_enable: pointer to clockdomain enable function + * @clkdm_clk_disable: pointer to clockdomain disable function * - * Low-level register access ops are generally used by the basic clock types - * (clk-gate, clk-mux, clk-divider etc.) to provide support for various - * low-level hardware interfaces (direct MMIO, regmap etc.), but can also be - * used by other hardware-specific clock drivers if needed. + * Low-level ops are generally used by the basic clock types (clk-gate, + * clk-mux, clk-divider etc.) to provide support for various low-level + * hadrware interfaces (direct MMIO, regmap etc.), and is initialized + * by board code. Low-level ops also contain some other platform specific + * operations not provided directly by clock drivers. */ struct ti_clk_ll_ops { u32 (*clk_readl)(void __iomem *reg); void (*clk_writel)(u32 val, void __iomem *reg); + int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk); + int (*clkdm_clk_disable)(struct clockdomain *clkdm, + struct clk *clk); }; extern struct ti_clk_ll_ops *ti_clk_ll_ops; -- cgit v1.2.3 From 192383d87b876ea9879d8b598af593809a25b7d2 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 3 Mar 2015 13:47:08 +0200 Subject: ARM: OMAP2+: clock: add support for specific CM ops to ti_clk_ll_ops Clock driver requires access to some CM API functions once the code is being moved under the clock driver from the platform directory. Gate type clock requires access to cm_wait_module_ready and cm_split_idlest_reg functions, which are both used for waiting until the module being clocked has been successfully activated. These CM APIs are now exported through the ti_clk_ll_ops struct. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c | 2 ++ include/linux/clk/ti.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index d6afc1291fe9..7a5713df54b3 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -122,6 +122,8 @@ static struct ti_clk_ll_ops omap_clk_ll_ops = { .clk_writel = clk_memmap_writel, .clkdm_clk_enable = clkdm_clk_enable, .clkdm_clk_disable = clkdm_clk_disable, + .cm_wait_module_ready = omap_cm_wait_module_ready, + .cm_split_idlest_reg = cm_split_idlest_reg, }; /** diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index fcf91844e94b..25eea896627a 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -243,6 +243,8 @@ struct clk_omap_reg { * @clk_writel: pointer to register write function * @clkdm_clk_enable: pointer to clockdomain enable function * @clkdm_clk_disable: pointer to clockdomain disable function + * @cm_wait_module_ready: pointer to CM module wait ready function + * @cm_split_idlest_reg: pointer to CM module function to split idlest reg * * Low-level ops are generally used by the basic clock types (clk-gate, * clk-mux, clk-divider etc.) to provide support for various low-level @@ -256,6 +258,10 @@ struct ti_clk_ll_ops { int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk); int (*clkdm_clk_disable)(struct clockdomain *clkdm, struct clk *clk); + int (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg, + u8 idlest_shift); + int (*cm_split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst, + u8 *idlest_reg_id); }; extern struct ti_clk_ll_ops *ti_clk_ll_ops; -- cgit v1.2.3 From 0565fb168d63f89591ce7dcb85438cb19d939a92 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 3 Mar 2015 13:27:48 +0200 Subject: clk: ti: dpll: move omap3 DPLL functionality to clock driver With the legacy clock support gone, OMAP3 generic DPLL code can now be moved over to the clock driver also. A few un-unused clkoutx2 functions are also removed at the same time. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 8 +- arch/arm/mach-omap2/clock.h | 4 - arch/arm/mach-omap2/clock3xxx.c | 77 ---- arch/arm/mach-omap2/dpll3xxx.c | 818 --------------------------------------- drivers/clk/ti/Makefile | 14 +- drivers/clk/ti/clk-3xxx.c | 31 ++ drivers/clk/ti/clock.h | 27 ++ drivers/clk/ti/dpll3xxx.c | 825 ++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 30 -- 9 files changed, 893 insertions(+), 941 deletions(-) delete mode 100644 arch/arm/mach-omap2/dpll3xxx.c create mode 100644 drivers/clk/ti/dpll3xxx.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index bf5d71d9fd2b..f9d4ccf39cea 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -189,15 +189,11 @@ obj-$(CONFIG_SOC_OMAP2430) += clock2430.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o -obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) -obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o -obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o +obj-$(CONFIG_SOC_AM33XX) += $(clock-common) obj-$(CONFIG_SOC_OMAP5) += $(clock-common) -obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o obj-$(CONFIG_SOC_DRA7XX) += $(clock-common) -obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o -obj-$(CONFIG_SOC_AM43XX) += $(clock-common) dpll3xxx.o +obj-$(CONFIG_SOC_AM43XX) += $(clock-common) # OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index e2781b4aaeb4..d60691d5626a 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -180,10 +180,6 @@ struct clksel { #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 #define OMAP4XXX_EN_DPLL_LOCKED 0x7 -u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); -void omap3_dpll_allow_idle(struct clk_hw_omap *clk); -void omap3_dpll_deny_idle(struct clk_hw_omap *clk); - void __init omap2_clk_disable_clkdm_control(void); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 4bd61222aa33..0b0e3a8777d3 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -29,82 +29,5 @@ #include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" -/* - * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks - * that are sourced by DPLL5, and both of these require this clock - * to be at 120 MHz for proper operation. - */ -#define DPLL5_FREQ_FOR_USBHOST 120000000 - /* needed by omap3_core_dpll_m2_set_rate() */ struct clk *sdrc_ick_p, *arm_fck_p; - -/** - * omap3_dpll4_set_rate - set rate for omap3 per-dpll - * @hw: clock to change - * @rate: target rate for clock - * @parent_rate: rate of the parent clock - * - * Check if the current SoC supports the per-dpll reprogram operation - * or not, and then do the rate change if supported. Returns -EINVAL - * if not supported, 0 for success, and potential error codes from the - * clock rate change. - */ -int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - /* - * According to the 12-5 CDP code from TI, "Limitation 2.5" - * on 3430ES1 prevents us from changing DPLL multipliers or dividers - * on DPLL4. - */ - if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) { - pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); - return -EINVAL; - } - - return omap3_noncore_dpll_set_rate(hw, rate, parent_rate); -} - -/** - * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll - * @hw: clock to change - * @rate: target rate for clock - * @parent_rate: rate of the parent clock - * @index: parent index, 0 - reference clock, 1 - bypass clock - * - * Check if the current SoC support the per-dpll reprogram operation - * or not, and then do the rate + parent change if supported. Returns - * -EINVAL if not supported, 0 for success, and potential error codes - * from the clock rate change. - */ -int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate, u8 index) -{ - if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) { - pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); - return -EINVAL; - } - - return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate, - index); -} - -void __init omap3_clk_lock_dpll5(void) -{ - struct clk *dpll5_clk; - struct clk *dpll5_m2_clk; - - dpll5_clk = clk_get(NULL, "dpll5_ck"); - clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); - clk_prepare_enable(dpll5_clk); - - /* Program dpll5_m2_clk divider for no division */ - dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); - clk_prepare_enable(dpll5_m2_clk); - clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); - - clk_disable_unprepare(dpll5_m2_clk); - clk_disable_unprepare(dpll5_clk); - return; -} diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c deleted file mode 100644 index 9a80f593ed15..000000000000 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ /dev/null @@ -1,818 +0,0 @@ -/* - * OMAP3/4 - specific DPLL control functions - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation - * - * Written by Paul Walmsley - * Testing and integration fixes by Jouni Högander - * - * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth - * Menon - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clockdomain.h" -#include "clock.h" - -/* CM_AUTOIDLE_PLL*.AUTO_* bit values */ -#define DPLL_AUTOIDLE_DISABLE 0x0 -#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 - -#define MAX_DPLL_WAIT_TRIES 1000000 - -/* Private functions */ - -/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ -static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) -{ - const struct dpll_data *dd; - u32 v; - - dd = clk->dpll_data; - - v = omap2_clk_readl(clk, dd->control_reg); - v &= ~dd->enable_mask; - v |= clken_bits << __ffs(dd->enable_mask); - omap2_clk_writel(v, clk, dd->control_reg); -} - -/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ -static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) -{ - const struct dpll_data *dd; - int i = 0; - int ret = -EINVAL; - const char *clk_name; - - dd = clk->dpll_data; - clk_name = __clk_get_name(clk->hw.clk); - - state <<= __ffs(dd->idlest_mask); - - while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) - != state) && i < MAX_DPLL_WAIT_TRIES) { - i++; - udelay(1); - } - - if (i == MAX_DPLL_WAIT_TRIES) { - printk(KERN_ERR "clock: %s failed transition to '%s'\n", - clk_name, (state) ? "locked" : "bypassed"); - } else { - pr_debug("clock: %s transition to '%s' in %d loops\n", - clk_name, (state) ? "locked" : "bypassed", i); - - ret = 0; - } - - return ret; -} - -/* From 3430 TRM ES2 4.7.6.2 */ -static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) -{ - unsigned long fint; - u16 f = 0; - - fint = __clk_get_rate(clk->dpll_data->clk_ref) / n; - - pr_debug("clock: fint is %lu\n", fint); - - if (fint >= 750000 && fint <= 1000000) - f = 0x3; - else if (fint > 1000000 && fint <= 1250000) - f = 0x4; - else if (fint > 1250000 && fint <= 1500000) - f = 0x5; - else if (fint > 1500000 && fint <= 1750000) - f = 0x6; - else if (fint > 1750000 && fint <= 2100000) - f = 0x7; - else if (fint > 7500000 && fint <= 10000000) - f = 0xB; - else if (fint > 10000000 && fint <= 12500000) - f = 0xC; - else if (fint > 12500000 && fint <= 15000000) - f = 0xD; - else if (fint > 15000000 && fint <= 17500000) - f = 0xE; - else if (fint > 17500000 && fint <= 21000000) - f = 0xF; - else - pr_debug("clock: unknown freqsel setting for %d\n", n); - - return f; -} - -/* - * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report - * readiness before returning. Will save and restore the DPLL's - * autoidle state across the enable, per the CDP code. If the DPLL - * locked successfully, return 0; if the DPLL did not lock in the time - * allotted, or DPLL3 was passed in, return -EINVAL. - */ -static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) -{ - const struct dpll_data *dd; - u8 ai; - u8 state = 1; - int r = 0; - - pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk)); - - dd = clk->dpll_data; - state <<= __ffs(dd->idlest_mask); - - /* Check if already locked */ - if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state) - goto done; - - ai = omap3_dpll_autoidle_read(clk); - - if (ai) - omap3_dpll_deny_idle(clk); - - _omap3_dpll_write_clken(clk, DPLL_LOCKED); - - r = _omap3_wait_dpll_status(clk, 1); - - if (ai) - omap3_dpll_allow_idle(clk); - -done: - return r; -} - -/* - * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to enter low-power bypass mode. In - * bypass mode, the DPLL's rate is set equal to its parent clock's - * rate. Waits for the DPLL to report readiness before returning. - * Will save and restore the DPLL's autoidle state across the enable, - * per the CDP code. If the DPLL entered bypass mode successfully, - * return 0; if the DPLL did not enter bypass in the time allotted, or - * DPLL3 was passed in, or the DPLL does not support low-power bypass, - * return -EINVAL. - */ -static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) -{ - int r; - u8 ai; - - if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) - return -EINVAL; - - pr_debug("clock: configuring DPLL %s for low-power bypass\n", - __clk_get_name(clk->hw.clk)); - - ai = omap3_dpll_autoidle_read(clk); - - _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); - - r = _omap3_wait_dpll_status(clk, 0); - - if (ai) - omap3_dpll_allow_idle(clk); - - return r; -} - -/* - * _omap3_noncore_dpll_stop - instruct a DPLL to stop - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to enter low-power stop. Will save and - * restore the DPLL's autoidle state across the stop, per the CDP - * code. If DPLL3 was passed in, or the DPLL does not support - * low-power stop, return -EINVAL; otherwise, return 0. - */ -static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) -{ - u8 ai; - - if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) - return -EINVAL; - - pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk)); - - ai = omap3_dpll_autoidle_read(clk); - - _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); - - if (ai) - omap3_dpll_allow_idle(clk); - - return 0; -} - -/** - * _lookup_dco - Lookup DCO used by j-type DPLL - * @clk: pointer to a DPLL struct clk - * @dco: digital control oscillator selector - * @m: DPLL multiplier to set - * @n: DPLL divider to set - * - * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" - * - * XXX This code is not needed for 3430/AM35xx; can it be optimized - * out in non-multi-OMAP builds for those chips? - */ -static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) -{ - unsigned long fint, clkinp; /* watch out for overflow */ - - clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); - fint = (clkinp / n) * m; - - if (fint < 1000000000) - *dco = 2; - else - *dco = 4; -} - -/** - * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL - * @clk: pointer to a DPLL struct clk - * @sd_div: target sigma-delta divider - * @m: DPLL multiplier to set - * @n: DPLL divider to set - * - * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" - * - * XXX This code is not needed for 3430/AM35xx; can it be optimized - * out in non-multi-OMAP builds for those chips? - */ -static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) -{ - unsigned long clkinp, sd; /* watch out for overflow */ - int mod1, mod2; - - clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); - - /* - * target sigma-delta to near 250MHz - * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] - */ - clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ - mod1 = (clkinp * m) % (250 * n); - sd = (clkinp * m) / (250 * n); - mod2 = sd % 10; - sd /= 10; - - if (mod1 || mod2) - sd++; - *sd_div = sd; -} - -/* - * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly - * @clk: struct clk * of DPLL to set - * @freqsel: FREQSEL value to set - * - * Program the DPLL with the last M, N values calculated, and wait for - * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success. - */ -static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) -{ - struct dpll_data *dd = clk->dpll_data; - u8 dco, sd_div; - u32 v; - - /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ - _omap3_noncore_dpll_bypass(clk); - - /* - * Set jitter correction. Jitter correction applicable for OMAP343X - * only since freqsel field is no longer present on other devices. - */ - if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) { - v = omap2_clk_readl(clk, dd->control_reg); - v &= ~dd->freqsel_mask; - v |= freqsel << __ffs(dd->freqsel_mask); - omap2_clk_writel(v, clk, dd->control_reg); - } - - /* Set DPLL multiplier, divider */ - v = omap2_clk_readl(clk, dd->mult_div1_reg); - - /* Handle Duty Cycle Correction */ - if (dd->dcc_mask) { - if (dd->last_rounded_rate >= dd->dcc_rate) - v |= dd->dcc_mask; /* Enable DCC */ - else - v &= ~dd->dcc_mask; /* Disable DCC */ - } - - v &= ~(dd->mult_mask | dd->div1_mask); - v |= dd->last_rounded_m << __ffs(dd->mult_mask); - v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); - - /* Configure dco and sd_div for dplls that have these fields */ - if (dd->dco_mask) { - _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n); - v &= ~(dd->dco_mask); - v |= dco << __ffs(dd->dco_mask); - } - if (dd->sddiv_mask) { - _lookup_sddiv(clk, &sd_div, dd->last_rounded_m, - dd->last_rounded_n); - v &= ~(dd->sddiv_mask); - v |= sd_div << __ffs(dd->sddiv_mask); - } - - omap2_clk_writel(v, clk, dd->mult_div1_reg); - - /* Set 4X multiplier and low-power mode */ - if (dd->m4xen_mask || dd->lpmode_mask) { - v = omap2_clk_readl(clk, dd->control_reg); - - if (dd->m4xen_mask) { - if (dd->last_rounded_m4xen) - v |= dd->m4xen_mask; - else - v &= ~dd->m4xen_mask; - } - - if (dd->lpmode_mask) { - if (dd->last_rounded_lpmode) - v |= dd->lpmode_mask; - else - v &= ~dd->lpmode_mask; - } - - omap2_clk_writel(v, clk, dd->control_reg); - } - - /* We let the clock framework set the other output dividers later */ - - /* REVISIT: Set ramp-up delay? */ - - _omap3_noncore_dpll_lock(clk); - - return 0; -} - -/* Public functions */ - -/** - * omap3_dpll_recalc - recalculate DPLL rate - * @clk: DPLL struct clk - * - * Recalculate and propagate the DPLL rate. - */ -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - - return omap2_get_dpll_rate(clk); -} - -/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ - -/** - * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. - * The choice of modes depends on the DPLL's programmed rate: if it is - * the same as the DPLL's parent clock, it will enter bypass; - * otherwise, it will enter lock. This code will wait for the DPLL to - * indicate readiness before returning, unless the DPLL takes too long - * to enter the target state. Intended to be used as the struct clk's - * enable function. If DPLL3 was passed in, or the DPLL does not - * support low-power stop, or if the DPLL took too long to enter - * bypass or lock, return -EINVAL; otherwise, return 0. - */ -int omap3_noncore_dpll_enable(struct clk_hw *hw) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - int r; - struct dpll_data *dd; - struct clk_hw *parent; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - if (clk->clkdm) { - r = clkdm_clk_enable(clk->clkdm, hw->clk); - if (r) { - WARN(1, - "%s: could not enable %s's clockdomain %s: %d\n", - __func__, __clk_get_name(hw->clk), - clk->clkdm->name, r); - return r; - } - } - - parent = __clk_get_hw(__clk_get_parent(hw->clk)); - - if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { - WARN_ON(parent != __clk_get_hw(dd->clk_bypass)); - r = _omap3_noncore_dpll_bypass(clk); - } else { - WARN_ON(parent != __clk_get_hw(dd->clk_ref)); - r = _omap3_noncore_dpll_lock(clk); - } - - return r; -} - -/** - * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop - * @clk: pointer to a DPLL struct clk - * - * Instructs a non-CORE DPLL to enter low-power stop. This function is - * intended for use in struct clkops. No return value. - */ -void omap3_noncore_dpll_disable(struct clk_hw *hw) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - - _omap3_noncore_dpll_stop(clk); - if (clk->clkdm) - clkdm_clk_disable(clk->clkdm, hw->clk); -} - - -/* Non-CORE DPLL rate set code */ - -/** - * omap3_noncore_dpll_determine_rate - determine rate for a DPLL - * @hw: pointer to the clock to determine rate for - * @rate: target rate for the DPLL - * @best_parent_rate: pointer for returning best parent rate - * @best_parent_clk: pointer for returning best parent clock - * - * Determines which DPLL mode to use for reaching a desired target rate. - * Checks whether the DPLL shall be in bypass or locked mode, and if - * locked, calculates the M,N values for the DPLL via round-rate. - * Returns a positive clock rate with success, negative error value - * in failure. - */ -long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long min_rate, - unsigned long max_rate, - unsigned long *best_parent_rate, - struct clk_hw **best_parent_clk) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - struct dpll_data *dd; - - if (!hw || !rate) - return -EINVAL; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - if (__clk_get_rate(dd->clk_bypass) == rate && - (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { - *best_parent_clk = __clk_get_hw(dd->clk_bypass); - } else { - rate = omap2_dpll_round_rate(hw, rate, best_parent_rate); - *best_parent_clk = __clk_get_hw(dd->clk_ref); - } - - *best_parent_rate = rate; - - return rate; -} - -/** - * omap3_noncore_dpll_set_parent - set parent for a DPLL clock - * @hw: pointer to the clock to set parent for - * @index: parent index to select - * - * Sets parent for a DPLL clock. This sets the DPLL into bypass or - * locked mode. Returns 0 with success, negative error value otherwise. - */ -int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - int ret; - - if (!hw) - return -EINVAL; - - if (index) - ret = _omap3_noncore_dpll_bypass(clk); - else - ret = _omap3_noncore_dpll_lock(clk); - - return ret; -} - -/** - * omap3_noncore_dpll_set_rate - set rate for a DPLL clock - * @hw: pointer to the clock to set parent for - * @rate: target rate for the clock - * @parent_rate: rate of the parent clock - * - * Sets rate for a DPLL clock. First checks if the clock parent is - * reference clock (in bypass mode, the rate of the clock can't be - * changed) and proceeds with the rate change operation. Returns 0 - * with success, negative error value otherwise. - */ -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - struct dpll_data *dd; - u16 freqsel = 0; - int ret; - - if (!hw || !rate) - return -EINVAL; - - dd = clk->dpll_data; - if (!dd) - return -EINVAL; - - if (__clk_get_hw(__clk_get_parent(hw->clk)) != - __clk_get_hw(dd->clk_ref)) - return -EINVAL; - - if (dd->last_rounded_rate == 0) - return -EINVAL; - - /* Freqsel is available only on OMAP343X devices */ - if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) { - freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); - WARN_ON(!freqsel); - } - - pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__, - __clk_get_name(hw->clk), rate); - - ret = omap3_noncore_dpll_program(clk, freqsel); - - return ret; -} - -/** - * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock - * @hw: pointer to the clock to set rate and parent for - * @rate: target rate for the DPLL - * @parent_rate: clock rate of the DPLL parent - * @index: new parent index for the DPLL, 0 - reference, 1 - bypass - * - * Sets rate and parent for a DPLL clock. If new parent is the bypass - * clock, only selects the parent. Otherwise proceeds with a rate - * change, as this will effectively also change the parent as the - * DPLL is put into locked mode. Returns 0 with success, negative error - * value otherwise. - */ -int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, - unsigned long rate, - unsigned long parent_rate, - u8 index) -{ - int ret; - - if (!hw || !rate) - return -EINVAL; - - /* - * clk-ref at index[0], in which case we only need to set rate, - * the parent will be changed automatically with the lock sequence. - * With clk-bypass case we only need to change parent. - */ - if (index) - ret = omap3_noncore_dpll_set_parent(hw, index); - else - ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate); - - return ret; -} - -/* DPLL autoidle read/set code */ - -/** - * omap3_dpll_autoidle_read - read a DPLL's autoidle bits - * @clk: struct clk * of the DPLL to read - * - * Return the DPLL's autoidle bits, shifted down to bit 0. Returns - * -EINVAL if passed a null pointer or if the struct clk does not - * appear to refer to a DPLL. - */ -u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) -{ - const struct dpll_data *dd; - u32 v; - - if (!clk || !clk->dpll_data) - return -EINVAL; - - dd = clk->dpll_data; - - if (!dd->autoidle_reg) - return -EINVAL; - - v = omap2_clk_readl(clk, dd->autoidle_reg); - v &= dd->autoidle_mask; - v >>= __ffs(dd->autoidle_mask); - - return v; -} - -/** - * omap3_dpll_allow_idle - enable DPLL autoidle bits - * @clk: struct clk * of the DPLL to operate on - * - * Enable DPLL automatic idle control. This automatic idle mode - * switching takes effect only when the DPLL is locked, at least on - * OMAP3430. The DPLL will enter low-power stop when its downstream - * clocks are gated. No return value. - */ -void omap3_dpll_allow_idle(struct clk_hw_omap *clk) -{ - const struct dpll_data *dd; - u32 v; - - if (!clk || !clk->dpll_data) - return; - - dd = clk->dpll_data; - - if (!dd->autoidle_reg) - return; - - /* - * REVISIT: CORE DPLL can optionally enter low-power bypass - * by writing 0x5 instead of 0x1. Add some mechanism to - * optionally enter this mode. - */ - v = omap2_clk_readl(clk, dd->autoidle_reg); - v &= ~dd->autoidle_mask; - v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); - omap2_clk_writel(v, clk, dd->autoidle_reg); - -} - -/** - * omap3_dpll_deny_idle - prevent DPLL from automatically idling - * @clk: struct clk * of the DPLL to operate on - * - * Disable DPLL automatic idle control. No return value. - */ -void omap3_dpll_deny_idle(struct clk_hw_omap *clk) -{ - const struct dpll_data *dd; - u32 v; - - if (!clk || !clk->dpll_data) - return; - - dd = clk->dpll_data; - - if (!dd->autoidle_reg) - return; - - v = omap2_clk_readl(clk, dd->autoidle_reg); - v &= ~dd->autoidle_mask; - v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); - omap2_clk_writel(v, clk, dd->autoidle_reg); - -} - -/* Clock control for DPLL outputs */ - -/* Find the parent DPLL for the given clkoutx2 clock */ -static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw) -{ - struct clk_hw_omap *pclk = NULL; - struct clk *parent; - - /* Walk up the parents of clk, looking for a DPLL */ - do { - do { - parent = __clk_get_parent(hw->clk); - hw = __clk_get_hw(parent); - } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC)); - if (!hw) - break; - pclk = to_clk_hw_omap(hw); - } while (pclk && !pclk->dpll_data); - - /* clk does not have a DPLL as a parent? error in the clock data */ - if (!pclk) { - WARN_ON(1); - return NULL; - } - - return pclk; -} - -/** - * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate - * @clk: DPLL output struct clk - * - * Using parent clock DPLL data, look up DPLL state. If locked, set our - * rate to the dpll_clk * 2; otherwise, just use dpll_clk. - */ -unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, - unsigned long parent_rate) -{ - const struct dpll_data *dd; - unsigned long rate; - u32 v; - struct clk_hw_omap *pclk = NULL; - - if (!parent_rate) - return 0; - - pclk = omap3_find_clkoutx2_dpll(hw); - - if (!pclk) - return 0; - - dd = pclk->dpll_data; - - WARN_ON(!dd->enable_mask); - - v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; - v >>= __ffs(dd->enable_mask); - if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) - rate = parent_rate; - else - rate = parent_rate * 2; - return rate; -} - -int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - return 0; -} - -long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - const struct dpll_data *dd; - u32 v; - struct clk_hw_omap *pclk = NULL; - - if (!*prate) - return 0; - - pclk = omap3_find_clkoutx2_dpll(hw); - - if (!pclk) - return 0; - - dd = pclk->dpll_data; - - /* TYPE J does not have a clkoutx2 */ - if (dd->flags & DPLL_J_TYPE) { - *prate = __clk_round_rate(__clk_get_parent(pclk->hw.clk), rate); - return *prate; - } - - WARN_ON(!dd->enable_mask); - - v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; - v >>= __ffs(dd->enable_mask); - - /* If in bypass, the rate is fixed to the bypass rate*/ - if (v != OMAP3XXX_EN_DPLL_LOCKED) - return *prate; - - if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { - unsigned long best_parent; - - best_parent = (rate / 2); - *prate = __clk_round_rate(__clk_get_parent(hw->clk), - best_parent); - } - - return *prate * 2; -} - -/* OMAP3/4 non-CORE DPLL clkops */ -const struct clk_hw_omap_ops clkhwops_omap3_dpll = { - .allow_idle = omap3_dpll_allow_idle, - .deny_idle = omap3_dpll_deny_idle, -}; diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 23cd72638970..05a0294aba10 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -2,16 +2,18 @@ obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o \ clkt_dpll.o clkt_iclk.o -obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o +obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \ - clk-3xxx.o -obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o dpll44xx.o -obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o dpll44xx.o + clk-3xxx.o dpll3xxx.o +obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o \ + dpll3xxx.o dpll44xx.o +obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \ + dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \ - clk-dra7-atl.o dpll44xx.o -obj-$(CONFIG_SOC_AM43XX) += $(clk-common) clk-43xx.o + clk-dra7-atl.o dpll3xxx.o dpll44xx.o +obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o ifdef CONFIG_ATAGS obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c index bb3b88359daf..5489ad8c07d4 100644 --- a/drivers/clk/ti/clk-3xxx.c +++ b/drivers/clk/ti/clk-3xxx.c @@ -21,6 +21,13 @@ #include "clock.h" +/* + * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks + * that are sourced by DPLL5, and both of these require this clock + * to be at 120 MHz for proper operation. + */ +#define DPLL5_FREQ_FOR_USBHOST 120000000 + static struct ti_dt_clk omap3xxx_clks[] = { DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"), DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"), @@ -325,6 +332,30 @@ enum { OMAP3_SOC_OMAP3630, }; +/** + * omap3_clk_lock_dpll5 - locks DPLL5 + * + * Locks DPLL5 to a pre-defined frequency. This is required for proper + * operation of USB. + */ +void __init omap3_clk_lock_dpll5(void) +{ + struct clk *dpll5_clk; + struct clk *dpll5_m2_clk; + + dpll5_clk = clk_get(NULL, "dpll5_ck"); + clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); + clk_prepare_enable(dpll5_clk); + + /* Program dpll5_m2_clk divider for no division */ + dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); + clk_prepare_enable(dpll5_m2_clk); + clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); + + clk_disable_unprepare(dpll5_m2_clk); + clk_disable_unprepare(dpll5_clk); +} + static int __init omap3xxx_dt_clk_init(int soc_type) { if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 || diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 4b26af8a273d..688d9e47b2c8 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -173,11 +173,38 @@ void omap2_init_clk_hw_omap_clocks(struct clk *clk); int of_ti_clk_autoidle_setup(struct device_node *node); void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); +extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; extern const struct clk_hw_omap_ops clkhwops_iclk; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; u8 omap2_init_dpll_parent(struct clk_hw *hw); +int omap3_noncore_dpll_enable(struct clk_hw *hw); +void omap3_noncore_dpll_disable(struct clk_hw *hw); +int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, + u8 index); +long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long min_rate, + unsigned long max_rate, + unsigned long *best_parent_rate, + struct clk_hw **best_parent_clk); +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate); +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, + unsigned long parent_rate); + +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); +int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, + unsigned long parent_rate); +int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate, u8 index); +void omap3_clk_lock_dpll5(void); unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, unsigned long parent_rate); diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c new file mode 100644 index 000000000000..22d77a331287 --- /dev/null +++ b/drivers/clk/ti/dpll3xxx.c @@ -0,0 +1,825 @@ +/* + * OMAP3/4 - specific DPLL control functions + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Written by Paul Walmsley + * Testing and integration fixes by Jouni Högander + * + * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth + * Menon + * + * Parts of this code are based on code written by + * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clock.h" + +/* CM_AUTOIDLE_PLL*.AUTO_* bit values */ +#define DPLL_AUTOIDLE_DISABLE 0x0 +#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 + +#define MAX_DPLL_WAIT_TRIES 1000000 + +#define OMAP3XXX_EN_DPLL_LOCKED 0x7 + +/* Forward declarations */ +static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); +static void omap3_dpll_deny_idle(struct clk_hw_omap *clk); +static void omap3_dpll_allow_idle(struct clk_hw_omap *clk); + +/* Private functions */ + +/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ +static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) +{ + const struct dpll_data *dd; + u32 v; + + dd = clk->dpll_data; + + v = ti_clk_ll_ops->clk_readl(dd->control_reg); + v &= ~dd->enable_mask; + v |= clken_bits << __ffs(dd->enable_mask); + ti_clk_ll_ops->clk_writel(v, dd->control_reg); +} + +/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ +static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) +{ + const struct dpll_data *dd; + int i = 0; + int ret = -EINVAL; + const char *clk_name; + + dd = clk->dpll_data; + clk_name = __clk_get_name(clk->hw.clk); + + state <<= __ffs(dd->idlest_mask); + + while (((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) + != state) && i < MAX_DPLL_WAIT_TRIES) { + i++; + udelay(1); + } + + if (i == MAX_DPLL_WAIT_TRIES) { + pr_err("clock: %s failed transition to '%s'\n", + clk_name, (state) ? "locked" : "bypassed"); + } else { + pr_debug("clock: %s transition to '%s' in %d loops\n", + clk_name, (state) ? "locked" : "bypassed", i); + + ret = 0; + } + + return ret; +} + +/* From 3430 TRM ES2 4.7.6.2 */ +static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) +{ + unsigned long fint; + u16 f = 0; + + fint = __clk_get_rate(clk->dpll_data->clk_ref) / n; + + pr_debug("clock: fint is %lu\n", fint); + + if (fint >= 750000 && fint <= 1000000) + f = 0x3; + else if (fint > 1000000 && fint <= 1250000) + f = 0x4; + else if (fint > 1250000 && fint <= 1500000) + f = 0x5; + else if (fint > 1500000 && fint <= 1750000) + f = 0x6; + else if (fint > 1750000 && fint <= 2100000) + f = 0x7; + else if (fint > 7500000 && fint <= 10000000) + f = 0xB; + else if (fint > 10000000 && fint <= 12500000) + f = 0xC; + else if (fint > 12500000 && fint <= 15000000) + f = 0xD; + else if (fint > 15000000 && fint <= 17500000) + f = 0xE; + else if (fint > 17500000 && fint <= 21000000) + f = 0xF; + else + pr_debug("clock: unknown freqsel setting for %d\n", n); + + return f; +} + +/* + * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness + * @clk: pointer to a DPLL struct clk + * + * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report + * readiness before returning. Will save and restore the DPLL's + * autoidle state across the enable, per the CDP code. If the DPLL + * locked successfully, return 0; if the DPLL did not lock in the time + * allotted, or DPLL3 was passed in, return -EINVAL. + */ +static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) +{ + const struct dpll_data *dd; + u8 ai; + u8 state = 1; + int r = 0; + + pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk)); + + dd = clk->dpll_data; + state <<= __ffs(dd->idlest_mask); + + /* Check if already locked */ + if ((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) == + state) + goto done; + + ai = omap3_dpll_autoidle_read(clk); + + if (ai) + omap3_dpll_deny_idle(clk); + + _omap3_dpll_write_clken(clk, DPLL_LOCKED); + + r = _omap3_wait_dpll_status(clk, 1); + + if (ai) + omap3_dpll_allow_idle(clk); + +done: + return r; +} + +/* + * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness + * @clk: pointer to a DPLL struct clk + * + * Instructs a non-CORE DPLL to enter low-power bypass mode. In + * bypass mode, the DPLL's rate is set equal to its parent clock's + * rate. Waits for the DPLL to report readiness before returning. + * Will save and restore the DPLL's autoidle state across the enable, + * per the CDP code. If the DPLL entered bypass mode successfully, + * return 0; if the DPLL did not enter bypass in the time allotted, or + * DPLL3 was passed in, or the DPLL does not support low-power bypass, + * return -EINVAL. + */ +static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) +{ + int r; + u8 ai; + + if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) + return -EINVAL; + + pr_debug("clock: configuring DPLL %s for low-power bypass\n", + __clk_get_name(clk->hw.clk)); + + ai = omap3_dpll_autoidle_read(clk); + + _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); + + r = _omap3_wait_dpll_status(clk, 0); + + if (ai) + omap3_dpll_allow_idle(clk); + + return r; +} + +/* + * _omap3_noncore_dpll_stop - instruct a DPLL to stop + * @clk: pointer to a DPLL struct clk + * + * Instructs a non-CORE DPLL to enter low-power stop. Will save and + * restore the DPLL's autoidle state across the stop, per the CDP + * code. If DPLL3 was passed in, or the DPLL does not support + * low-power stop, return -EINVAL; otherwise, return 0. + */ +static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) +{ + u8 ai; + + if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) + return -EINVAL; + + pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk)); + + ai = omap3_dpll_autoidle_read(clk); + + _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); + + if (ai) + omap3_dpll_allow_idle(clk); + + return 0; +} + +/** + * _lookup_dco - Lookup DCO used by j-type DPLL + * @clk: pointer to a DPLL struct clk + * @dco: digital control oscillator selector + * @m: DPLL multiplier to set + * @n: DPLL divider to set + * + * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" + * + * XXX This code is not needed for 3430/AM35xx; can it be optimized + * out in non-multi-OMAP builds for those chips? + */ +static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) +{ + unsigned long fint, clkinp; /* watch out for overflow */ + + clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); + fint = (clkinp / n) * m; + + if (fint < 1000000000) + *dco = 2; + else + *dco = 4; +} + +/** + * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL + * @clk: pointer to a DPLL struct clk + * @sd_div: target sigma-delta divider + * @m: DPLL multiplier to set + * @n: DPLL divider to set + * + * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" + * + * XXX This code is not needed for 3430/AM35xx; can it be optimized + * out in non-multi-OMAP builds for those chips? + */ +static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) +{ + unsigned long clkinp, sd; /* watch out for overflow */ + int mod1, mod2; + + clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); + + /* + * target sigma-delta to near 250MHz + * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] + */ + clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ + mod1 = (clkinp * m) % (250 * n); + sd = (clkinp * m) / (250 * n); + mod2 = sd % 10; + sd /= 10; + + if (mod1 || mod2) + sd++; + *sd_div = sd; +} + +/* + * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly + * @clk: struct clk * of DPLL to set + * @freqsel: FREQSEL value to set + * + * Program the DPLL with the last M, N values calculated, and wait for + * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success. + */ +static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) +{ + struct dpll_data *dd = clk->dpll_data; + u8 dco, sd_div; + u32 v; + + /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ + _omap3_noncore_dpll_bypass(clk); + + /* + * Set jitter correction. Jitter correction applicable for OMAP343X + * only since freqsel field is no longer present on other devices. + */ + if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) { + v = ti_clk_ll_ops->clk_readl(dd->control_reg); + v &= ~dd->freqsel_mask; + v |= freqsel << __ffs(dd->freqsel_mask); + ti_clk_ll_ops->clk_writel(v, dd->control_reg); + } + + /* Set DPLL multiplier, divider */ + v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); + + /* Handle Duty Cycle Correction */ + if (dd->dcc_mask) { + if (dd->last_rounded_rate >= dd->dcc_rate) + v |= dd->dcc_mask; /* Enable DCC */ + else + v &= ~dd->dcc_mask; /* Disable DCC */ + } + + v &= ~(dd->mult_mask | dd->div1_mask); + v |= dd->last_rounded_m << __ffs(dd->mult_mask); + v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); + + /* Configure dco and sd_div for dplls that have these fields */ + if (dd->dco_mask) { + _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n); + v &= ~(dd->dco_mask); + v |= dco << __ffs(dd->dco_mask); + } + if (dd->sddiv_mask) { + _lookup_sddiv(clk, &sd_div, dd->last_rounded_m, + dd->last_rounded_n); + v &= ~(dd->sddiv_mask); + v |= sd_div << __ffs(dd->sddiv_mask); + } + + ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg); + + /* Set 4X multiplier and low-power mode */ + if (dd->m4xen_mask || dd->lpmode_mask) { + v = ti_clk_ll_ops->clk_readl(dd->control_reg); + + if (dd->m4xen_mask) { + if (dd->last_rounded_m4xen) + v |= dd->m4xen_mask; + else + v &= ~dd->m4xen_mask; + } + + if (dd->lpmode_mask) { + if (dd->last_rounded_lpmode) + v |= dd->lpmode_mask; + else + v &= ~dd->lpmode_mask; + } + + ti_clk_ll_ops->clk_writel(v, dd->control_reg); + } + + /* We let the clock framework set the other output dividers later */ + + /* REVISIT: Set ramp-up delay? */ + + _omap3_noncore_dpll_lock(clk); + + return 0; +} + +/* Public functions */ + +/** + * omap3_dpll_recalc - recalculate DPLL rate + * @clk: DPLL struct clk + * + * Recalculate and propagate the DPLL rate. + */ +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + + return omap2_get_dpll_rate(clk); +} + +/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ + +/** + * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode + * @clk: pointer to a DPLL struct clk + * + * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. + * The choice of modes depends on the DPLL's programmed rate: if it is + * the same as the DPLL's parent clock, it will enter bypass; + * otherwise, it will enter lock. This code will wait for the DPLL to + * indicate readiness before returning, unless the DPLL takes too long + * to enter the target state. Intended to be used as the struct clk's + * enable function. If DPLL3 was passed in, or the DPLL does not + * support low-power stop, or if the DPLL took too long to enter + * bypass or lock, return -EINVAL; otherwise, return 0. + */ +int omap3_noncore_dpll_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + int r; + struct dpll_data *dd; + struct clk_hw *parent; + + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + if (clk->clkdm) { + r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); + if (r) { + WARN(1, + "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), + clk->clkdm_name, r); + return r; + } + } + + parent = __clk_get_hw(__clk_get_parent(hw->clk)); + + if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { + WARN_ON(parent != __clk_get_hw(dd->clk_bypass)); + r = _omap3_noncore_dpll_bypass(clk); + } else { + WARN_ON(parent != __clk_get_hw(dd->clk_ref)); + r = _omap3_noncore_dpll_lock(clk); + } + + return r; +} + +/** + * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop + * @clk: pointer to a DPLL struct clk + * + * Instructs a non-CORE DPLL to enter low-power stop. This function is + * intended for use in struct clkops. No return value. + */ +void omap3_noncore_dpll_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + + _omap3_noncore_dpll_stop(clk); + if (clk->clkdm) + ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); +} + +/* Non-CORE DPLL rate set code */ + +/** + * omap3_noncore_dpll_determine_rate - determine rate for a DPLL + * @hw: pointer to the clock to determine rate for + * @rate: target rate for the DPLL + * @best_parent_rate: pointer for returning best parent rate + * @best_parent_clk: pointer for returning best parent clock + * + * Determines which DPLL mode to use for reaching a desired target rate. + * Checks whether the DPLL shall be in bypass or locked mode, and if + * locked, calculates the M,N values for the DPLL via round-rate. + * Returns a positive clock rate with success, negative error value + * in failure. + */ +long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate, + unsigned long min_rate, + unsigned long max_rate, + unsigned long *best_parent_rate, + struct clk_hw **best_parent_clk) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *dd; + + if (!hw || !rate) + return -EINVAL; + + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + if (__clk_get_rate(dd->clk_bypass) == rate && + (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { + *best_parent_clk = __clk_get_hw(dd->clk_bypass); + } else { + rate = omap2_dpll_round_rate(hw, rate, best_parent_rate); + *best_parent_clk = __clk_get_hw(dd->clk_ref); + } + + *best_parent_rate = rate; + + return rate; +} + +/** + * omap3_noncore_dpll_set_parent - set parent for a DPLL clock + * @hw: pointer to the clock to set parent for + * @index: parent index to select + * + * Sets parent for a DPLL clock. This sets the DPLL into bypass or + * locked mode. Returns 0 with success, negative error value otherwise. + */ +int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + int ret; + + if (!hw) + return -EINVAL; + + if (index) + ret = _omap3_noncore_dpll_bypass(clk); + else + ret = _omap3_noncore_dpll_lock(clk); + + return ret; +} + +/** + * omap3_noncore_dpll_set_rate - set rate for a DPLL clock + * @hw: pointer to the clock to set parent for + * @rate: target rate for the clock + * @parent_rate: rate of the parent clock + * + * Sets rate for a DPLL clock. First checks if the clock parent is + * reference clock (in bypass mode, the rate of the clock can't be + * changed) and proceeds with the rate change operation. Returns 0 + * with success, negative error value otherwise. + */ +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *dd; + u16 freqsel = 0; + int ret; + + if (!hw || !rate) + return -EINVAL; + + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + if (__clk_get_hw(__clk_get_parent(hw->clk)) != + __clk_get_hw(dd->clk_ref)) + return -EINVAL; + + if (dd->last_rounded_rate == 0) + return -EINVAL; + + /* Freqsel is available only on OMAP343X devices */ + if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) { + freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); + WARN_ON(!freqsel); + } + + pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__, + __clk_get_name(hw->clk), rate); + + ret = omap3_noncore_dpll_program(clk, freqsel); + + return ret; +} + +/** + * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock + * @hw: pointer to the clock to set rate and parent for + * @rate: target rate for the DPLL + * @parent_rate: clock rate of the DPLL parent + * @index: new parent index for the DPLL, 0 - reference, 1 - bypass + * + * Sets rate and parent for a DPLL clock. If new parent is the bypass + * clock, only selects the parent. Otherwise proceeds with a rate + * change, as this will effectively also change the parent as the + * DPLL is put into locked mode. Returns 0 with success, negative error + * value otherwise. + */ +int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, + u8 index) +{ + int ret; + + if (!hw || !rate) + return -EINVAL; + + /* + * clk-ref at index[0], in which case we only need to set rate, + * the parent will be changed automatically with the lock sequence. + * With clk-bypass case we only need to change parent. + */ + if (index) + ret = omap3_noncore_dpll_set_parent(hw, index); + else + ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate); + + return ret; +} + +/* DPLL autoidle read/set code */ + +/** + * omap3_dpll_autoidle_read - read a DPLL's autoidle bits + * @clk: struct clk * of the DPLL to read + * + * Return the DPLL's autoidle bits, shifted down to bit 0. Returns + * -EINVAL if passed a null pointer or if the struct clk does not + * appear to refer to a DPLL. + */ +static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) +{ + const struct dpll_data *dd; + u32 v; + + if (!clk || !clk->dpll_data) + return -EINVAL; + + dd = clk->dpll_data; + + if (!dd->autoidle_reg) + return -EINVAL; + + v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg); + v &= dd->autoidle_mask; + v >>= __ffs(dd->autoidle_mask); + + return v; +} + +/** + * omap3_dpll_allow_idle - enable DPLL autoidle bits + * @clk: struct clk * of the DPLL to operate on + * + * Enable DPLL automatic idle control. This automatic idle mode + * switching takes effect only when the DPLL is locked, at least on + * OMAP3430. The DPLL will enter low-power stop when its downstream + * clocks are gated. No return value. + */ +static void omap3_dpll_allow_idle(struct clk_hw_omap *clk) +{ + const struct dpll_data *dd; + u32 v; + + if (!clk || !clk->dpll_data) + return; + + dd = clk->dpll_data; + + if (!dd->autoidle_reg) + return; + + /* + * REVISIT: CORE DPLL can optionally enter low-power bypass + * by writing 0x5 instead of 0x1. Add some mechanism to + * optionally enter this mode. + */ + v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg); + v &= ~dd->autoidle_mask; + v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); + ti_clk_ll_ops->clk_writel(v, dd->autoidle_reg); +} + +/** + * omap3_dpll_deny_idle - prevent DPLL from automatically idling + * @clk: struct clk * of the DPLL to operate on + * + * Disable DPLL automatic idle control. No return value. + */ +static void omap3_dpll_deny_idle(struct clk_hw_omap *clk) +{ + const struct dpll_data *dd; + u32 v; + + if (!clk || !clk->dpll_data) + return; + + dd = clk->dpll_data; + + if (!dd->autoidle_reg) + return; + + v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg); + v &= ~dd->autoidle_mask; + v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); + ti_clk_ll_ops->clk_writel(v, dd->autoidle_reg); +} + +/* Clock control for DPLL outputs */ + +/* Find the parent DPLL for the given clkoutx2 clock */ +static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw) +{ + struct clk_hw_omap *pclk = NULL; + struct clk *parent; + + /* Walk up the parents of clk, looking for a DPLL */ + do { + do { + parent = __clk_get_parent(hw->clk); + hw = __clk_get_hw(parent); + } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC)); + if (!hw) + break; + pclk = to_clk_hw_omap(hw); + } while (pclk && !pclk->dpll_data); + + /* clk does not have a DPLL as a parent? error in the clock data */ + if (!pclk) { + WARN_ON(1); + return NULL; + } + + return pclk; +} + +/** + * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate + * @clk: DPLL output struct clk + * + * Using parent clock DPLL data, look up DPLL state. If locked, set our + * rate to the dpll_clk * 2; otherwise, just use dpll_clk. + */ +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + const struct dpll_data *dd; + unsigned long rate; + u32 v; + struct clk_hw_omap *pclk = NULL; + + if (!parent_rate) + return 0; + + pclk = omap3_find_clkoutx2_dpll(hw); + + if (!pclk) + return 0; + + dd = pclk->dpll_data; + + WARN_ON(!dd->enable_mask); + + v = ti_clk_ll_ops->clk_readl(dd->control_reg) & dd->enable_mask; + v >>= __ffs(dd->enable_mask); + if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) + rate = parent_rate; + else + rate = parent_rate * 2; + return rate; +} + +/* OMAP3/4 non-CORE DPLL clkops */ +const struct clk_hw_omap_ops clkhwops_omap3_dpll = { + .allow_idle = omap3_dpll_allow_idle, + .deny_idle = omap3_dpll_deny_idle, +}; + +/** + * omap3_dpll4_set_rate - set rate for omap3 per-dpll + * @hw: clock to change + * @rate: target rate for clock + * @parent_rate: rate of the parent clock + * + * Check if the current SoC supports the per-dpll reprogram operation + * or not, and then do the rate change if supported. Returns -EINVAL + * if not supported, 0 for success, and potential error codes from the + * clock rate change. + */ +int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + /* + * According to the 12-5 CDP code from TI, "Limitation 2.5" + * on 3430ES1 prevents us from changing DPLL multipliers or dividers + * on DPLL4. + */ + if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) { + pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); + return -EINVAL; + } + + return omap3_noncore_dpll_set_rate(hw, rate, parent_rate); +} + +/** + * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll + * @hw: clock to change + * @rate: target rate for clock + * @parent_rate: rate of the parent clock + * @index: parent index, 0 - reference clock, 1 - bypass clock + * + * Check if the current SoC support the per-dpll reprogram operation + * or not, and then do the rate + parent change if supported. Returns + * -EINVAL if not supported, 0 for success, and potential error codes + * from the clock rate change. + */ +int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate, u8 index) +{ + if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) { + pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); + return -EINVAL; + } + + return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate, + index); +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 25eea896627a..f8e50271ec97 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -271,41 +271,13 @@ extern const struct clk_ops ti_clk_mux_ops; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) -int omap3_noncore_dpll_enable(struct clk_hw *hw); -void omap3_noncore_dpll_disable(struct clk_hw *hw); -int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate); -int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, - unsigned long rate, - unsigned long parent_rate, - u8 index); -long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long min_rate, - unsigned long max_rate, - unsigned long *best_parent_rate, - struct clk_hw **best_parent_clk); -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, - unsigned long *parent_rate); void omap2_init_clk_clkdm(struct clk_hw *clk); -unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, - unsigned long parent_rate); -int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate); -long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate); int omap2_clkops_enable_clkdm(struct clk_hw *hw); void omap2_clkops_disable_clkdm(struct clk_hw *hw); int omap2_clk_disable_autoidle_all(void); int omap2_clk_enable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); int omap2_clk_deny_idle(struct clk *clk); -int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, - unsigned long parent_rate); -int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate, u8 index); int omap2_dflt_clk_enable(struct clk_hw *hw); void omap2_dflt_clk_disable(struct clk_hw *hw); int omap2_dflt_clk_is_enabled(struct clk_hw *hw); @@ -317,7 +289,6 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); -void omap3_clk_lock_dpll5(void); unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, unsigned long parent_rate); int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, @@ -365,7 +336,6 @@ const struct ti_clk_features *ti_clk_get_features(void); extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; extern const struct clk_hw_omap_ops clkhwops_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; -- cgit v1.2.3 From 6f0051da4bb5b35014e1bb326d0a31fcad2369e5 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 4 Mar 2015 11:56:22 +0200 Subject: ARM: OMAP3: clock: remove clock3xxx.c file This now only has a couple of variables within it, which are used outside the file itself. Move these variables to where they are actually used, and remove the file completely as it is now empty. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 2 ++ arch/arm/mach-omap2/clock3xxx.c | 33 --------------------------------- 3 files changed, 3 insertions(+), 34 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock3xxx.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index f9d4ccf39cea..070526563698 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -186,7 +186,7 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o -obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index 825e3dadb16b..6cd2961069e9 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -29,6 +29,8 @@ #define CYCLES_PER_MHZ 1000000 +struct clk *sdrc_ick_p, *arm_fck_p; + /* * CORE DPLL (DPLL3) M2 divider rate programming functions * diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c deleted file mode 100644 index 0b0e3a8777d3..000000000000 --- a/arch/arm/mach-omap2/clock3xxx.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * OMAP3-specific clock framework functions - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2010 Nokia Corporation - * - * Paul Walmsley - * Jouni Högander - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include -#include - -#include "soc.h" -#include "clock.h" -#include "clock3xxx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-34xx.h" -#include "cm2xxx_3xxx.h" -#include "cm-regbits-34xx.h" - -/* needed by omap3_core_dpll_m2_set_rate() */ -struct clk *sdrc_ick_p, *arm_fck_p; -- cgit v1.2.3 From 046b7c31668311942a2e431e7983d8ab9874d845 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 3 Mar 2015 15:13:50 +0200 Subject: ARM: OMAP2+: clock: remove clkdm_control static boolean from code clkdm_control is used to determine, whether clocks should trigger a clockdomain transition when they are enabled/disabled. Keep this functionality intact, but replace this with a clk_features flag which can be initialized during boot if needed. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c | 34 ++++++++++------------------------ arch/arm/mach-omap2/clock.h | 2 -- include/linux/clk/ti.h | 1 + 3 files changed, 11 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 7a5713df54b3..6c17adf40e6f 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -61,14 +61,6 @@ u16 cpu_mask; #define OMAP3PLUS_DPLL_FINT_MIN 32000 #define OMAP3PLUS_DPLL_FINT_MAX 52000000 -/* - * clkdm_control: if true, then when a clock is enabled in the - * hardware, its clockdomain will first be enabled; and when a clock - * is disabled in the hardware, its clockdomain will be disabled - * afterwards. - */ -static bool clkdm_control = true; - struct clk_iomap { struct regmap *regmap; void __iomem *mem; @@ -287,19 +279,6 @@ void omap2_init_clk_clkdm(struct clk_hw *hw) } } -/** - * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable - * - * Prevent the OMAP clock code from calling into the clockdomain code - * when a hardware clock in that clockdomain is enabled or disabled. - * Intended to be called at init time from omap*_clk_init(). No - * return value. - */ -void __init omap2_clk_disable_clkdm_control(void) -{ - clkdm_control = false; -} - /** * omap2_clk_dflt_find_companion - find companion clock to @clk * @clk: struct clk * to find the companion clock of @@ -384,6 +363,12 @@ int omap2_dflt_clk_enable(struct clk_hw *hw) struct clk_hw_omap *clk; u32 v; int ret = 0; + bool clkdm_control; + + if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) + clkdm_control = false; + else + clkdm_control = true; clk = to_clk_hw_omap(hw); @@ -457,7 +442,8 @@ void omap2_dflt_clk_disable(struct clk_hw *hw) omap2_clk_writel(v, clk, clk->enable_reg); /* No OCP barrier needed here since it is a disable operation */ - if (clkdm_control && clk->clkdm) + if (!(ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) && + clk->clkdm) clkdm_clk_disable(clk->clkdm, hw->clk); } @@ -490,7 +476,7 @@ int omap2_clkops_enable_clkdm(struct clk_hw *hw) pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, __clk_get_name(hw->clk)); - if (!clkdm_control) { + if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) { pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", __func__, __clk_get_name(hw->clk)); return 0; @@ -528,7 +514,7 @@ void omap2_clkops_disable_clkdm(struct clk_hw *hw) pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, __clk_get_name(hw->clk)); - if (!clkdm_control) { + if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) { pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", __func__, __clk_get_name(hw->clk)); return; diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index d60691d5626a..948065497472 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -180,8 +180,6 @@ struct clksel { #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 #define OMAP4XXX_EN_DPLL_LOCKED 0x7 -void __init omap2_clk_disable_clkdm_control(void); - void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, const char *mpu_ck_name); diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index f8e50271ec97..fbb65e401d13 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -330,6 +330,7 @@ struct ti_clk_features { #define TI_CLK_DPLL_HAS_FREQSEL BIT(0) #define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1) +#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2) void ti_clk_setup_features(struct ti_clk_features *features); const struct ti_clk_features *ti_clk_get_features(void); -- cgit v1.2.3 From 9f37e90efaf0772b8f98bc347b9db77a3f0c27eb Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 3 Mar 2015 15:28:53 +0200 Subject: clk: ti: dflt: move support for default gate clock to clock driver With the legacy support gone, OMAP2+ default gate clock can be moved under clock driver. Create a new file for the purpose, and clean-up the header exports a bit as some clock APIs are no longer needed outside clock driver itself. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c | 273 -------------------------------------- drivers/clk/ti/Makefile | 2 +- drivers/clk/ti/clkt_dflt.c | 316 ++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/ti/clock.h | 5 + include/linux/clk/ti.h | 4 - 5 files changed, 322 insertions(+), 278 deletions(-) create mode 100644 drivers/clk/ti/clkt_dflt.c diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 6c17adf40e6f..38a336b4c42b 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -40,12 +40,6 @@ #include "cm-regbits-34xx.h" #include "common.h" -/* - * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait - * for a module to indicate that it is no longer in idle - */ -#define MAX_MODULE_ENABLE_WAIT 100000 - u16 cpu_mask; /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ @@ -176,77 +170,6 @@ void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem) /* Private functions */ - -/** - * _wait_idlest_generic - wait for a module to leave the idle state - * @clk: module clock to wait for (needed for register offsets) - * @reg: virtual address of module IDLEST register - * @mask: value to mask against to determine if the module is active - * @idlest: idle state indicator (0 or 1) for the clock - * @name: name of the clock (for printk) - * - * Wait for a module to leave idle, where its idle-status register is - * not inside the CM module. Returns 1 if the module left idle - * promptly, or 0 if the module did not leave idle before the timeout - * elapsed. XXX Deprecated - should be moved into drivers for the - * individual IP block that the IDLEST register exists in. - */ -static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, - u32 mask, u8 idlest, const char *name) -{ - int i = 0, ena = 0; - - ena = (idlest) ? 0 : mask; - - omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), - MAX_MODULE_ENABLE_WAIT, i); - - if (i < MAX_MODULE_ENABLE_WAIT) - pr_debug("omap clock: module associated with clock %s ready after %d loops\n", - name, i); - else - pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", - name, MAX_MODULE_ENABLE_WAIT); - - return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; -}; - -/** - * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE - * @clk: struct clk * belonging to the module - * - * If the necessary clocks for the OMAP hardware IP block that - * corresponds to clock @clk are enabled, then wait for the module to - * indicate readiness (i.e., to leave IDLE). This code does not - * belong in the clock code and will be moved in the medium term to - * module-dependent code. No return value. - */ -static void _omap2_module_wait_ready(struct clk_hw_omap *clk) -{ - void __iomem *companion_reg, *idlest_reg; - u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; - s16 prcm_mod; - int r; - - /* Not all modules have multiple clocks that their IDLEST depends on */ - if (clk->ops->find_companion) { - clk->ops->find_companion(clk, &companion_reg, &other_bit); - if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) - return; - } - - clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); - r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); - if (r) { - /* IDLEST register not in the CM module */ - _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), - idlest_val, __clk_get_name(clk->hw.clk)); - } else { - omap_cm_wait_module_ready(0, prcm_mod, idlest_reg_id, - idlest_bit); - }; -} - /* Public functions */ /** @@ -279,174 +202,6 @@ void omap2_init_clk_clkdm(struct clk_hw *hw) } } -/** - * omap2_clk_dflt_find_companion - find companion clock to @clk - * @clk: struct clk * to find the companion clock of - * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in - * @other_bit: u8 ** to return the companion clock bit shift in - * - * Note: We don't need special code here for INVERT_ENABLE for the - * time being since INVERT_ENABLE only applies to clocks enabled by - * CM_CLKEN_PLL - * - * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's - * just a matter of XORing the bits. - * - * Some clocks don't have companion clocks. For example, modules with - * only an interface clock (such as MAILBOXES) don't have a companion - * clock. Right now, this code relies on the hardware exporting a bit - * in the correct companion register that indicates that the - * nonexistent 'companion clock' is active. Future patches will - * associate this type of code with per-module data structures to - * avoid this issue, and remove the casts. No return value. - */ -void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, - void __iomem **other_reg, u8 *other_bit) -{ - u32 r; - - /* - * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes - * it's just a matter of XORing the bits. - */ - r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); - - *other_reg = (__force void __iomem *)r; - *other_bit = clk->enable_bit; -} - -/** - * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk - * @clk: struct clk * to find IDLEST info for - * @idlest_reg: void __iomem ** to return the CM_IDLEST va in - * @idlest_bit: u8 * to return the CM_IDLEST bit shift in - * @idlest_val: u8 * to return the idle status indicator - * - * Return the CM_IDLEST register address and bit shift corresponding - * to the module that "owns" this clock. This default code assumes - * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that - * the IDLEST register address ID corresponds to the CM_*CLKEN - * register address ID (e.g., that CM_FCLKEN2 corresponds to - * CM_IDLEST2). This is not true for all modules. No return value. - */ -void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) -{ - u32 r; - - r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); - *idlest_reg = (__force void __iomem *)r; - *idlest_bit = clk->enable_bit; - - /* - * 24xx uses 0 to indicate not ready, and 1 to indicate ready. - * 34xx reverses this, just to keep us on our toes - * AM35xx uses both, depending on the module. - */ - *idlest_val = ti_clk_get_features()->cm_idlest_val; -} - -/** - * omap2_dflt_clk_enable - enable a clock in the hardware - * @hw: struct clk_hw * of the clock to enable - * - * Enable the clock @hw in the hardware. We first call into the OMAP - * clockdomain code to "enable" the corresponding clockdomain if this - * is the first enabled user of the clockdomain. Then program the - * hardware to enable the clock. Then wait for the IP block that uses - * this clock to leave idle (if applicable). Returns the error value - * from clkdm_clk_enable() if it terminated with an error, or -EINVAL - * if @hw has a null clock enable_reg, or zero upon success. - */ -int omap2_dflt_clk_enable(struct clk_hw *hw) -{ - struct clk_hw_omap *clk; - u32 v; - int ret = 0; - bool clkdm_control; - - if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) - clkdm_control = false; - else - clkdm_control = true; - - clk = to_clk_hw_omap(hw); - - if (clkdm_control && clk->clkdm) { - ret = clkdm_clk_enable(clk->clkdm, hw->clk); - if (ret) { - WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", - __func__, __clk_get_name(hw->clk), - clk->clkdm->name, ret); - return ret; - } - } - - if (unlikely(clk->enable_reg == NULL)) { - pr_err("%s: %s missing enable_reg\n", __func__, - __clk_get_name(hw->clk)); - ret = -EINVAL; - goto err; - } - - /* FIXME should not have INVERT_ENABLE bit here */ - v = omap2_clk_readl(clk, clk->enable_reg); - if (clk->flags & INVERT_ENABLE) - v &= ~(1 << clk->enable_bit); - else - v |= (1 << clk->enable_bit); - omap2_clk_writel(v, clk, clk->enable_reg); - v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ - - if (clk->ops && clk->ops->find_idlest) - _omap2_module_wait_ready(clk); - - return 0; - -err: - if (clkdm_control && clk->clkdm) - clkdm_clk_disable(clk->clkdm, hw->clk); - return ret; -} - -/** - * omap2_dflt_clk_disable - disable a clock in the hardware - * @hw: struct clk_hw * of the clock to disable - * - * Disable the clock @hw in the hardware, and call into the OMAP - * clockdomain code to "disable" the corresponding clockdomain if all - * clocks/hwmods in that clockdomain are now disabled. No return - * value. - */ -void omap2_dflt_clk_disable(struct clk_hw *hw) -{ - struct clk_hw_omap *clk; - u32 v; - - clk = to_clk_hw_omap(hw); - if (!clk->enable_reg) { - /* - * 'independent' here refers to a clock which is not - * controlled by its parent. - */ - pr_err("%s: independent clock %s has no enable_reg\n", - __func__, __clk_get_name(hw->clk)); - return; - } - - v = omap2_clk_readl(clk, clk->enable_reg); - if (clk->flags & INVERT_ENABLE) - v |= (1 << clk->enable_bit); - else - v &= ~(1 << clk->enable_bit); - omap2_clk_writel(v, clk, clk->enable_reg); - /* No OCP barrier needed here since it is a disable operation */ - - if (!(ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) && - clk->clkdm) - clkdm_clk_disable(clk->clkdm, hw->clk); -} - /** * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw * @hw: struct clk_hw * of the clock being enabled @@ -523,29 +278,6 @@ void omap2_clkops_disable_clkdm(struct clk_hw *hw) clkdm_clk_disable(clk->clkdm, hw->clk); } -/** - * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? - * @hw: struct clk_hw * to check - * - * Return 1 if the clock represented by @hw is enabled in the - * hardware, or 0 otherwise. Intended for use in the struct - * clk_ops.is_enabled function pointer. - */ -int omap2_dflt_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_hw_omap *clk = to_clk_hw_omap(hw); - u32 v; - - v = omap2_clk_readl(clk, clk->enable_reg); - - if (clk->flags & INVERT_ENABLE) - v ^= BIT(clk->enable_bit); - - v &= BIT(clk->enable_bit); - - return v ? 1 : 0; -} - static int __initdata mpurate; /* @@ -566,11 +298,6 @@ static int __init omap_clk_setup(char *str) } __setup("mpurate=", omap_clk_setup); -const struct clk_hw_omap_ops clkhwops_wait = { - .find_idlest = omap2_clk_dflt_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - /** * omap2_clk_print_new_rates - print summary of current clock tree rates * @hfclkin_ck_name: clk name for the off-chip HF oscillator diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 05a0294aba10..9b93e6904359 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,7 +1,7 @@ obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o \ - clkt_dpll.o clkt_iclk.o + clkt_dpll.o clkt_iclk.o clkt_dflt.o obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o diff --git a/drivers/clk/ti/clkt_dflt.c b/drivers/clk/ti/clkt_dflt.c new file mode 100644 index 000000000000..a176b8ac8dd0 --- /dev/null +++ b/drivers/clk/ti/clkt_dflt.c @@ -0,0 +1,316 @@ +/* + * Default clock type + * + * Copyright (C) 2005-2008, 2015 Texas Instruments, Inc. + * Copyright (C) 2004-2010 Nokia Corporation + * + * Contacts: + * Richard Woodruff + * Paul Walmsley + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include "clock.h" + +/* + * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait + * for a module to indicate that it is no longer in idle + */ +#define MAX_MODULE_ENABLE_WAIT 100000 + +/* + * CM module register offsets, used for calculating the companion + * register addresses. + */ +#define CM_FCLKEN 0x0000 +#define CM_ICLKEN 0x0010 + +/** + * _wait_idlest_generic - wait for a module to leave the idle state + * @clk: module clock to wait for (needed for register offsets) + * @reg: virtual address of module IDLEST register + * @mask: value to mask against to determine if the module is active + * @idlest: idle state indicator (0 or 1) for the clock + * @name: name of the clock (for printk) + * + * Wait for a module to leave idle, where its idle-status register is + * not inside the CM module. Returns 1 if the module left idle + * promptly, or 0 if the module did not leave idle before the timeout + * elapsed. XXX Deprecated - should be moved into drivers for the + * individual IP block that the IDLEST register exists in. + */ +static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, + u32 mask, u8 idlest, const char *name) +{ + int i = 0, ena = 0; + + ena = (idlest) ? 0 : mask; + + /* Wait until module enters enabled state */ + for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) { + if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena) + break; + udelay(1); + } + + if (i < MAX_MODULE_ENABLE_WAIT) + pr_debug("omap clock: module associated with clock %s ready after %d loops\n", + name, i); + else + pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", + name, MAX_MODULE_ENABLE_WAIT); + + return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; +} + +/** + * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE + * @clk: struct clk * belonging to the module + * + * If the necessary clocks for the OMAP hardware IP block that + * corresponds to clock @clk are enabled, then wait for the module to + * indicate readiness (i.e., to leave IDLE). This code does not + * belong in the clock code and will be moved in the medium term to + * module-dependent code. No return value. + */ +static void _omap2_module_wait_ready(struct clk_hw_omap *clk) +{ + void __iomem *companion_reg, *idlest_reg; + u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; + s16 prcm_mod; + int r; + + /* Not all modules have multiple clocks that their IDLEST depends on */ + if (clk->ops->find_companion) { + clk->ops->find_companion(clk, &companion_reg, &other_bit); + if (!(ti_clk_ll_ops->clk_readl(companion_reg) & + (1 << other_bit))) + return; + } + + clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); + r = ti_clk_ll_ops->cm_split_idlest_reg(idlest_reg, &prcm_mod, + &idlest_reg_id); + if (r) { + /* IDLEST register not in the CM module */ + _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), + idlest_val, __clk_get_name(clk->hw.clk)); + } else { + ti_clk_ll_ops->cm_wait_module_ready(0, prcm_mod, idlest_reg_id, + idlest_bit); + } +} + +/** + * omap2_clk_dflt_find_companion - find companion clock to @clk + * @clk: struct clk * to find the companion clock of + * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in + * @other_bit: u8 ** to return the companion clock bit shift in + * + * Note: We don't need special code here for INVERT_ENABLE for the + * time being since INVERT_ENABLE only applies to clocks enabled by + * CM_CLKEN_PLL + * + * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's + * just a matter of XORing the bits. + * + * Some clocks don't have companion clocks. For example, modules with + * only an interface clock (such as MAILBOXES) don't have a companion + * clock. Right now, this code relies on the hardware exporting a bit + * in the correct companion register that indicates that the + * nonexistent 'companion clock' is active. Future patches will + * associate this type of code with per-module data structures to + * avoid this issue, and remove the casts. No return value. + */ +void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, + void __iomem **other_reg, u8 *other_bit) +{ + u32 r; + + /* + * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes + * it's just a matter of XORing the bits. + */ + r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); + + *other_reg = (__force void __iomem *)r; + *other_bit = clk->enable_bit; +} + +/** + * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk + * @clk: struct clk * to find IDLEST info for + * @idlest_reg: void __iomem ** to return the CM_IDLEST va in + * @idlest_bit: u8 * to return the CM_IDLEST bit shift in + * @idlest_val: u8 * to return the idle status indicator + * + * Return the CM_IDLEST register address and bit shift corresponding + * to the module that "owns" this clock. This default code assumes + * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that + * the IDLEST register address ID corresponds to the CM_*CLKEN + * register address ID (e.g., that CM_FCLKEN2 corresponds to + * CM_IDLEST2). This is not true for all modules. No return value. + */ +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, u8 *idlest_bit, + u8 *idlest_val) +{ + u32 r; + + r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); + *idlest_reg = (__force void __iomem *)r; + *idlest_bit = clk->enable_bit; + + /* + * 24xx uses 0 to indicate not ready, and 1 to indicate ready. + * 34xx reverses this, just to keep us on our toes + * AM35xx uses both, depending on the module. + */ + *idlest_val = ti_clk_get_features()->cm_idlest_val; +} + +/** + * omap2_dflt_clk_enable - enable a clock in the hardware + * @hw: struct clk_hw * of the clock to enable + * + * Enable the clock @hw in the hardware. We first call into the OMAP + * clockdomain code to "enable" the corresponding clockdomain if this + * is the first enabled user of the clockdomain. Then program the + * hardware to enable the clock. Then wait for the IP block that uses + * this clock to leave idle (if applicable). Returns the error value + * from clkdm_clk_enable() if it terminated with an error, or -EINVAL + * if @hw has a null clock enable_reg, or zero upon success. + */ +int omap2_dflt_clk_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + u32 v; + int ret = 0; + bool clkdm_control; + + if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) + clkdm_control = false; + else + clkdm_control = true; + + clk = to_clk_hw_omap(hw); + + if (clkdm_control && clk->clkdm) { + ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); + if (ret) { + WARN(1, + "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), + clk->clkdm_name, ret); + return ret; + } + } + + if (unlikely(!clk->enable_reg)) { + pr_err("%s: %s missing enable_reg\n", __func__, + __clk_get_name(hw->clk)); + ret = -EINVAL; + goto err; + } + + /* FIXME should not have INVERT_ENABLE bit here */ + v = ti_clk_ll_ops->clk_readl(clk->enable_reg); + if (clk->flags & INVERT_ENABLE) + v &= ~(1 << clk->enable_bit); + else + v |= (1 << clk->enable_bit); + ti_clk_ll_ops->clk_writel(v, clk->enable_reg); + v = ti_clk_ll_ops->clk_readl(clk->enable_reg); /* OCP barrier */ + + if (clk->ops && clk->ops->find_idlest) + _omap2_module_wait_ready(clk); + + return 0; + +err: + if (clkdm_control && clk->clkdm) + ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); + return ret; +} + +/** + * omap2_dflt_clk_disable - disable a clock in the hardware + * @hw: struct clk_hw * of the clock to disable + * + * Disable the clock @hw in the hardware, and call into the OMAP + * clockdomain code to "disable" the corresponding clockdomain if all + * clocks/hwmods in that clockdomain are now disabled. No return + * value. + */ +void omap2_dflt_clk_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + u32 v; + + clk = to_clk_hw_omap(hw); + if (!clk->enable_reg) { + /* + * 'independent' here refers to a clock which is not + * controlled by its parent. + */ + pr_err("%s: independent clock %s has no enable_reg\n", + __func__, __clk_get_name(hw->clk)); + return; + } + + v = ti_clk_ll_ops->clk_readl(clk->enable_reg); + if (clk->flags & INVERT_ENABLE) + v |= (1 << clk->enable_bit); + else + v &= ~(1 << clk->enable_bit); + ti_clk_ll_ops->clk_writel(v, clk->enable_reg); + /* No OCP barrier needed here since it is a disable operation */ + + if (!(ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) && + clk->clkdm) + ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); +} + +/** + * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? + * @hw: struct clk_hw * to check + * + * Return 1 if the clock represented by @hw is enabled in the + * hardware, or 0 otherwise. Intended for use in the struct + * clk_ops.is_enabled function pointer. + */ +int omap2_dflt_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 v; + + v = ti_clk_ll_ops->clk_readl(clk->enable_reg); + + if (clk->flags & INVERT_ENABLE) + v ^= BIT(clk->enable_bit); + + v &= BIT(clk->enable_bit); + + return v ? 1 : 0; +} + +const struct clk_hw_omap_ops clkhwops_wait = { + .find_idlest = omap2_clk_dflt_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 688d9e47b2c8..f21538364588 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -175,9 +175,14 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; +extern const struct clk_hw_omap_ops clkhwops_wait; extern const struct clk_hw_omap_ops clkhwops_iclk; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; +int omap2_dflt_clk_enable(struct clk_hw *hw); +void omap2_dflt_clk_disable(struct clk_hw *hw); +int omap2_dflt_clk_is_enabled(struct clk_hw *hw); + u8 omap2_init_dpll_parent(struct clk_hw *hw); int omap3_noncore_dpll_enable(struct clk_hw *hw); void omap3_noncore_dpll_disable(struct clk_hw *hw); diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index fbb65e401d13..81a913edffa7 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -278,9 +278,6 @@ int omap2_clk_disable_autoidle_all(void); int omap2_clk_enable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); int omap2_clk_deny_idle(struct clk *clk); -int omap2_dflt_clk_enable(struct clk_hw *hw); -void omap2_dflt_clk_disable(struct clk_hw *hw); -int omap2_dflt_clk_is_enabled(struct clk_hw *hw); void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, @@ -337,7 +334,6 @@ const struct ti_clk_features *ti_clk_get_features(void); extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; -extern const struct clk_hw_omap_ops clkhwops_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; -- cgit v1.2.3 From d5a04dddf51e234dc89f21e4e4b91e853cf49ff2 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 3 Mar 2015 16:08:42 +0200 Subject: clk: ti: omap2430: move clock support code under clock driver With the legacy clock support gone, this is no longer needed under platform code-base. Thus, move this under the TI clock driver, and remove the exported API from the public header. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 1 - arch/arm/mach-omap2/clock2430.c | 57 ----------------------------------------- drivers/clk/ti/clkt_iclk.c | 35 +++++++++++++++++++++++++ drivers/clk/ti/clock.h | 1 + include/linux/clk/ti.h | 1 - 5 files changed, 36 insertions(+), 59 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock2430.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 070526563698..695d58f81ff3 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -185,7 +185,6 @@ obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o -obj-$(CONFIG_SOC_OMAP2430) += clock2430.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c deleted file mode 100644 index cef0c8d1de52..000000000000 --- a/arch/arm/mach-omap2/clock2430.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * clock2430.c - OMAP2430-specific clock integration code - * - * Copyright (C) 2005-2008 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation - * - * Contacts: - * Richard Woodruff - * Paul Walmsley - * - * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, - * Gordon McNutt and RidgeRun, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock2xxx.h" -#include "cm2xxx.h" -#include "cm-regbits-24xx.h" - -/** - * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator - * - * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the - * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function - * passes back the correct CM_IDLEST register address for I2CHS - * modules. No return value. - */ -static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, - u8 *idlest_val) -{ - *idlest_reg = OMAP2430_CM_REGADDR(CORE_MOD, CM_IDLEST); - *idlest_bit = clk->enable_bit; - *idlest_val = OMAP24XX_CM_IDLEST_VAL; -} - -/* 2430 I2CHS has non-standard IDLEST register */ -const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = { - .find_idlest = omap2430_clk_i2chs_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; diff --git a/drivers/clk/ti/clkt_iclk.c b/drivers/clk/ti/clkt_iclk.c index a03919df00ef..38c36908cf88 100644 --- a/drivers/clk/ti/clkt_iclk.c +++ b/drivers/clk/ti/clkt_iclk.c @@ -18,8 +18,12 @@ #include "clock.h" /* Register offsets */ +#define OMAP24XX_CM_FCLKEN2 0x04 #define CM_AUTOIDLE 0x30 #define CM_ICLKEN 0x10 +#define CM_IDLEST 0x20 + +#define OMAP24XX_CM_IDLEST_VAL 0 /* Private functions */ @@ -51,6 +55,31 @@ void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) ti_clk_ll_ops->clk_writel(v, r); } +/** + * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS + * @clk: struct clk * being enabled + * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into + * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into + * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator + * + * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the + * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function + * passes back the correct CM_IDLEST register address for I2CHS + * modules. No return value. + */ +static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, + u8 *idlest_bit, + u8 *idlest_val) +{ + u32 r; + + r = ((__force u32)clk->enable_reg ^ (OMAP24XX_CM_FCLKEN2 ^ CM_IDLEST)); + *idlest_reg = (__force void __iomem *)r; + *idlest_bit = clk->enable_bit; + *idlest_val = OMAP24XX_CM_IDLEST_VAL; +} + /* Public data */ const struct clk_hw_omap_ops clkhwops_iclk = { @@ -64,3 +93,9 @@ const struct clk_hw_omap_ops clkhwops_iclk_wait = { .find_idlest = omap2_clk_dflt_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; + +/* 2430 I2CHS has non-standard IDLEST register */ +const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = { + .find_idlest = omap2430_clk_i2chs_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index f21538364588..3652c267cf81 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -178,6 +178,7 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; extern const struct clk_hw_omap_ops clkhwops_wait; extern const struct clk_hw_omap_ops clkhwops_iclk; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; +extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; int omap2_dflt_clk_enable(struct clk_hw *hw); void omap2_dflt_clk_disable(struct clk_hw *hw); diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 81a913edffa7..440ace33ea35 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -333,7 +333,6 @@ void ti_clk_setup_features(struct ti_clk_features *features); const struct ti_clk_features *ti_clk_get_features(void); extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; -extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; -- cgit v1.2.3 From bd86cfdcbd827216fd682d62ffba2667bbe6fbc3 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 3 Mar 2015 16:22:50 +0200 Subject: clk: ti: clkdm: move clkdm gate clock support code to clock driver With the legacy clock data gone, this is no longer needed under platform, so move it under the clock driver itself. Remove the exported clock driver APIs as well, as these are not needed outside clock driver anymore. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c | 76 -------------------------------------------- arch/arm/mach-omap2/clock.h | 3 -- drivers/clk/ti/clock.h | 3 ++ drivers/clk/ti/clockdomain.c | 76 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 2 -- 5 files changed, 79 insertions(+), 81 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 38a336b4c42b..99875dba803a 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -202,82 +202,6 @@ void omap2_init_clk_clkdm(struct clk_hw *hw) } } -/** - * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw - * @hw: struct clk_hw * of the clock being enabled - * - * Increment the usecount of the clockdomain of the clock pointed to - * by @hw; if the usecount is 1, the clockdomain will be "enabled." - * Only needed for clocks that don't use omap2_dflt_clk_enable() as - * their enable function pointer. Passes along the return value of - * clkdm_clk_enable(), -EINVAL if @hw is not associated with a - * clockdomain, or 0 if clock framework-based clockdomain control is - * not implemented. - */ -int omap2_clkops_enable_clkdm(struct clk_hw *hw) -{ - struct clk_hw_omap *clk; - int ret = 0; - - clk = to_clk_hw_omap(hw); - - if (unlikely(!clk->clkdm)) { - pr_err("%s: %s: no clkdm set ?!\n", __func__, - __clk_get_name(hw->clk)); - return -EINVAL; - } - - if (unlikely(clk->enable_reg)) - pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, - __clk_get_name(hw->clk)); - - if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) { - pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", - __func__, __clk_get_name(hw->clk)); - return 0; - } - - ret = clkdm_clk_enable(clk->clkdm, hw->clk); - WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", - __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); - - return ret; -} - -/** - * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw - * @hw: struct clk_hw * of the clock being disabled - * - * Decrement the usecount of the clockdomain of the clock pointed to - * by @hw; if the usecount is 0, the clockdomain will be "disabled." - * Only needed for clocks that don't use omap2_dflt_clk_disable() as their - * disable function pointer. No return value. - */ -void omap2_clkops_disable_clkdm(struct clk_hw *hw) -{ - struct clk_hw_omap *clk; - - clk = to_clk_hw_omap(hw); - - if (unlikely(!clk->clkdm)) { - pr_err("%s: %s: no clkdm set ?!\n", __func__, - __clk_get_name(hw->clk)); - return; - } - - if (unlikely(clk->enable_reg)) - pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, - __clk_get_name(hw->clk)); - - if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) { - pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", - __func__, __clk_get_name(hw->clk)); - return; - } - - clkdm_clk_disable(clk->clkdm, hw->clk); -} - static int __initdata mpurate; /* diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 948065497472..a7e951129ffb 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -202,9 +202,6 @@ extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; extern const struct clk_hw_omap_ops clkhwops_apll54; extern const struct clk_hw_omap_ops clkhwops_apll96; -extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); -extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); - struct regmap; int __init omap2_clk_provider_init(struct device_node *np, int index, diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 3652c267cf81..83476d12d561 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -180,6 +180,9 @@ extern const struct clk_hw_omap_ops clkhwops_iclk; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; +int omap2_clkops_enable_clkdm(struct clk_hw *hw); +void omap2_clkops_disable_clkdm(struct clk_hw *hw); + int omap2_dflt_clk_enable(struct clk_hw *hw); void omap2_dflt_clk_disable(struct clk_hw *hw); int omap2_dflt_clk_is_enabled(struct clk_hw *hw); diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c index 35fe1085480c..61ef87b1a688 100644 --- a/drivers/clk/ti/clockdomain.c +++ b/drivers/clk/ti/clockdomain.c @@ -24,6 +24,82 @@ #undef pr_fmt #define pr_fmt(fmt) "%s: " fmt, __func__ +/** + * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw + * @hw: struct clk_hw * of the clock being enabled + * + * Increment the usecount of the clockdomain of the clock pointed to + * by @hw; if the usecount is 1, the clockdomain will be "enabled." + * Only needed for clocks that don't use omap2_dflt_clk_enable() as + * their enable function pointer. Passes along the return value of + * clkdm_clk_enable(), -EINVAL if @hw is not associated with a + * clockdomain, or 0 if clock framework-based clockdomain control is + * not implemented. + */ +int omap2_clkops_enable_clkdm(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + int ret = 0; + + clk = to_clk_hw_omap(hw); + + if (unlikely(!clk->clkdm)) { + pr_err("%s: %s: no clkdm set ?!\n", __func__, + __clk_get_name(hw->clk)); + return -EINVAL; + } + + if (unlikely(clk->enable_reg)) + pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, + __clk_get_name(hw->clk)); + + if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) { + pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", + __func__, __clk_get_name(hw->clk)); + return 0; + } + + ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); + WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), clk->clkdm_name, ret); + + return ret; +} + +/** + * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw + * @hw: struct clk_hw * of the clock being disabled + * + * Decrement the usecount of the clockdomain of the clock pointed to + * by @hw; if the usecount is 0, the clockdomain will be "disabled." + * Only needed for clocks that don't use omap2_dflt_clk_disable() as their + * disable function pointer. No return value. + */ +void omap2_clkops_disable_clkdm(struct clk_hw *hw) +{ + struct clk_hw_omap *clk; + + clk = to_clk_hw_omap(hw); + + if (unlikely(!clk->clkdm)) { + pr_err("%s: %s: no clkdm set ?!\n", __func__, + __clk_get_name(hw->clk)); + return; + } + + if (unlikely(clk->enable_reg)) + pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, + __clk_get_name(hw->clk)); + + if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) { + pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", + __func__, __clk_get_name(hw->clk)); + return; + } + + ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); +} + static void __init of_ti_clockdomain_setup(struct device_node *node) { struct clk *clk; diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 440ace33ea35..27828422c9c5 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -272,8 +272,6 @@ extern const struct clk_ops ti_clk_mux_ops; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) void omap2_init_clk_clkdm(struct clk_hw *clk); -int omap2_clkops_enable_clkdm(struct clk_hw *hw); -void omap2_clkops_disable_clkdm(struct clk_hw *hw); int omap2_clk_disable_autoidle_all(void); int omap2_clk_enable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); -- cgit v1.2.3 From f2671d5c6cb4abe4636014cd66fd0eeb8190b2ca Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 3 Mar 2015 17:28:12 +0200 Subject: clk: ti: omap34xx: move omap34xx clock type support code to clock driver With the legacy clock data gone, this is no longer needed under platform, so move it under the clock driver itself. Remove unnecessary declarations from the TI clock header also. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/clock34xx.c | 138 ---------------------------------------- drivers/clk/ti/clk-3xxx.c | 118 ++++++++++++++++++++++++++++++++++ drivers/clk/ti/clock.h | 4 ++ include/linux/clk/ti.h | 4 -- 5 files changed, 123 insertions(+), 143 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock34xx.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 695d58f81ff3..22d2e48dcff5 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -186,7 +186,7 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) -obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o +obj-$(CONFIG_ARCH_OMAP3) += clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) obj-$(CONFIG_SOC_AM33XX) += $(clock-common) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c deleted file mode 100644 index 4596468e50ab..000000000000 --- a/arch/arm/mach-omap2/clock34xx.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * OMAP3-specific clock framework functions - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2011 Nokia Corporation - * - * Paul Walmsley - * Jouni Högander - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, - * Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include - -#include "clock.h" -#include "clock34xx.h" -#include "cm3xxx.h" -#include "cm-regbits-34xx.h" - -/** - * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator - * - * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift - * from the CM_{I,F}CLKEN bit. Pass back the correct info via - * @idlest_reg and @idlest_bit. No return value. - */ -static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, - u8 *idlest_val) -{ - u32 r; - - r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); - *idlest_reg = (__force void __iomem *)r; - *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; - *idlest_val = OMAP34XX_CM_IDLEST_VAL; -} -const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait = { - .find_idlest = omap3430es2_clk_ssi_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, - .find_idlest = omap3430es2_clk_ssi_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -/** - * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator - * - * Some OMAP modules on OMAP3 ES2+ chips have both initiator and - * target IDLEST bits. For our purposes, we are concerned with the - * target IDLEST bits, which exist at a different bit position than - * the *CLKEN bit position for these modules (DSS and USBHOST) (The - * default find_idlest code assumes that they are at the same - * position.) No return value. - */ -static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, - u8 *idlest_val) -{ - u32 r; - - r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); - *idlest_reg = (__force void __iomem *)r; - /* USBHOST_IDLE has same shift */ - *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; - *idlest_val = OMAP34XX_CM_IDLEST_VAL; -} - -const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = { - .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, - .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -/** - * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator - * - * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different - * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via - * @idlest_reg and @idlest_bit. No return value. - */ -static void omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, - u8 *idlest_val) -{ - u32 r; - - r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); - *idlest_reg = (__force void __iomem *)r; - *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; - *idlest_val = OMAP34XX_CM_IDLEST_VAL; -} - -const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, - .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; - -const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait = { - .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c index 5489ad8c07d4..58879f0b7949 100644 --- a/drivers/clk/ti/clk-3xxx.c +++ b/drivers/clk/ti/clk-3xxx.c @@ -28,6 +28,124 @@ */ #define DPLL5_FREQ_FOR_USBHOST 120000000 +#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 +#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 +#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 + +#define OMAP34XX_CM_IDLEST_VAL 1 + +/** + * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI + * @clk: struct clk * being enabled + * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into + * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into + * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator + * + * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift + * from the CM_{I,F}CLKEN bit. Pass back the correct info via + * @idlest_reg and @idlest_bit. No return value. + */ +static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, + u8 *idlest_bit, + u8 *idlest_val) +{ + u32 r; + + r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); + *idlest_reg = (__force void __iomem *)r; + *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; + *idlest_val = OMAP34XX_CM_IDLEST_VAL; +} + +const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait = { + .find_idlest = omap3430es2_clk_ssi_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; + +const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap3430es2_clk_ssi_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; + +/** + * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST + * @clk: struct clk * being enabled + * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into + * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into + * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator + * + * Some OMAP modules on OMAP3 ES2+ chips have both initiator and + * target IDLEST bits. For our purposes, we are concerned with the + * target IDLEST bits, which exist at a different bit position than + * the *CLKEN bit position for these modules (DSS and USBHOST) (The + * default find_idlest code assumes that they are at the same + * position.) No return value. + */ +static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, + u8 *idlest_bit, + u8 *idlest_val) +{ + u32 r; + + r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); + *idlest_reg = (__force void __iomem *)r; + /* USBHOST_IDLE has same shift */ + *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; + *idlest_val = OMAP34XX_CM_IDLEST_VAL; +} + +const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = { + .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; + +const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; + +/** + * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB + * @clk: struct clk * being enabled + * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into + * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into + * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator + * + * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different + * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via + * @idlest_reg and @idlest_bit. No return value. + */ +static void omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, + u8 *idlest_bit, + u8 *idlest_val) +{ + u32 r; + + r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); + *idlest_reg = (__force void __iomem *)r; + *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; + *idlest_val = OMAP34XX_CM_IDLEST_VAL; +} + +const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; + +const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait = { + .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; + static struct ti_dt_clk omap3xxx_clks[] = { DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"), DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"), diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 83476d12d561..c6fbd153b6d4 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -179,6 +179,10 @@ extern const struct clk_hw_omap_ops clkhwops_wait; extern const struct clk_hw_omap_ops clkhwops_iclk; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; int omap2_clkops_enable_clkdm(struct clk_hw *hw); void omap2_clkops_disable_clkdm(struct clk_hw *hw); diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 27828422c9c5..cd5b3eadc317 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -331,12 +331,8 @@ void ti_clk_setup_features(struct ti_clk_features *features); const struct ti_clk_features *ti_clk_get_features(void); extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; #ifdef CONFIG_ATAGS int omap3430_clk_legacy_init(void); -- cgit v1.2.3 From eb0572520db9322e47ab97e4aff4a7cbf0381387 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 3 Mar 2015 21:10:49 +0200 Subject: ARM: OMAP4: clock: remove clock44xx.h header This is not needed for anything anymore, so remove it completely. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock44xx.h | 20 -------------------- arch/arm/mach-omap2/io.c | 1 - 2 files changed, 21 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock44xx.h diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h deleted file mode 100644 index 287a46f78d97..000000000000 --- a/arch/arm/mach-omap2/clock44xx.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * OMAP4 clock function prototypes and macros - * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H -#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H - -/* - * OMAP4430_REGM4XEN_MULT: If the CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN bit is - * set, then the DPLL's lock frequency is multiplied by 4 (OMAP4430 TRM - * vV Section 3.6.3.3.1 "DPLLs Output Clocks Parameters") - */ -#define OMAP4430_REGM4XEN_MULT 4 - -int omap4xxx_clk_init(void); - -#endif diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 820dde8b5b04..74678565cd97 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -37,7 +37,6 @@ #include "clock.h" #include "clock2xxx.h" #include "clock3xxx.h" -#include "clock44xx.h" #include "omap-pm.h" #include "sdrc.h" #include "control.h" -- cgit v1.2.3 From c9a58b0a848e4b88d2dd4690ef19bae8696649eb Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 3 Mar 2015 21:19:25 +0200 Subject: clk: ti: am3517: move remaining am3517 clock support code to clock driver With legacy clock support gone, this is no longer needed under platform, so move it under the clock driver itself. Make some exports be driver internal definitions at the same time. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Makefile | 1 - arch/arm/mach-omap2/clock3517.c | 118 ---------------------------------------- arch/arm/mach-omap2/clock3517.h | 14 ----- drivers/clk/ti/clk-3xxx.c | 94 ++++++++++++++++++++++++++++++++ drivers/clk/ti/clock.h | 2 + include/linux/clk/ti.h | 2 - 6 files changed, 96 insertions(+), 135 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock3517.c delete mode 100644 arch/arm/mach-omap2/clock3517.h diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 22d2e48dcff5..d424920a5e1c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -187,7 +187,6 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) obj-$(CONFIG_ARCH_OMAP3) += clkt34xx_dpll3m2.o -obj-$(CONFIG_ARCH_OMAP3) += clock3517.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) obj-$(CONFIG_SOC_AM33XX) += $(clock-common) obj-$(CONFIG_SOC_OMAP5) += $(clock-common) diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c deleted file mode 100644 index 4d79ae2c0241..000000000000 --- a/arch/arm/mach-omap2/clock3517.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * OMAP3517/3505-specific clock framework functions - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2011 Nokia Corporation - * - * Ranjith Lohithakshan - * Paul Walmsley - * - * Parts of this code are based on code written by - * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, - * Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#undef DEBUG - -#include -#include -#include - -#include "clock.h" -#include "clock3517.h" -#include "cm3xxx.h" -#include "cm-regbits-34xx.h" - -/* - * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported - * in the same register at a bit offset of 0x8. The EN_ACK for ICK is - * at an offset of 4 from ICK enable bit. - */ -#define AM35XX_IPSS_ICK_MASK 0xF -#define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4 -#define AM35XX_IPSS_ICK_FCK_OFFSET 0x8 -#define AM35XX_IPSS_CLK_IDLEST_VAL 0 - -/** - * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator - * - * The interface clocks on AM35xx IPSS reflects the clock idle status - * in the enable register itsel at a bit offset of 4 from the enable - * bit. A value of 1 indicates that clock is enabled. - */ -static void am35xx_clk_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, - u8 *idlest_val) -{ - *idlest_reg = (__force void __iomem *)(clk->enable_reg); - *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; - *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL; -} - -/** - * am35xx_clk_find_companion - find companion clock to @clk - * @clk: struct clk * to find the companion clock of - * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in - * @other_bit: u8 ** to return the companion clock bit shift in - * - * Some clocks don't have companion clocks. For example, modules with - * only an interface clock (such as HECC) don't have a companion - * clock. Right now, this code relies on the hardware exporting a bit - * in the correct companion register that indicates that the - * nonexistent 'companion clock' is active. Future patches will - * associate this type of code with per-module data structures to - * avoid this issue, and remove the casts. No return value. - */ -static void am35xx_clk_find_companion(struct clk_hw_omap *clk, - void __iomem **other_reg, - u8 *other_bit) -{ - *other_reg = (__force void __iomem *)(clk->enable_reg); - if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) - *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; - else - *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; -} -const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = { - .find_idlest = am35xx_clk_find_idlest, - .find_companion = am35xx_clk_find_companion, -}; - -/** - * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS - * @clk: struct clk * being enabled - * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into - * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into - * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator - * - * The IPSS target CM_IDLEST bit is at a different shift from the - * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg - * and @idlest_bit. No return value. - */ -static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, - u8 *idlest_val) -{ - u32 r; - - r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); - *idlest_reg = (__force void __iomem *)r; - *idlest_bit = AM35XX_ST_IPSS_SHIFT; - *idlest_val = OMAP34XX_CM_IDLEST_VAL; -} - -const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, - .find_idlest = am35xx_clk_ipss_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; diff --git a/arch/arm/mach-omap2/clock3517.h b/arch/arm/mach-omap2/clock3517.h deleted file mode 100644 index ca5e5a64c2e2..000000000000 --- a/arch/arm/mach-omap2/clock3517.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * OMAP3517/3505 clock function prototypes and macros - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK3517_H -#define __ARCH_ARM_MACH_OMAP2_CLOCK3517_H - -extern const struct clkops clkops_am35xx_ipss_module_wait; -extern const struct clkops clkops_am35xx_ipss_wait; - -#endif diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c index 58879f0b7949..6e33332b6b34 100644 --- a/drivers/clk/ti/clk-3xxx.c +++ b/drivers/clk/ti/clk-3xxx.c @@ -34,6 +34,18 @@ #define OMAP34XX_CM_IDLEST_VAL 1 +/* + * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported + * in the same register at a bit offset of 0x8. The EN_ACK for ICK is + * at an offset of 4 from ICK enable bit. + */ +#define AM35XX_IPSS_ICK_MASK 0xF +#define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4 +#define AM35XX_IPSS_ICK_FCK_OFFSET 0x8 +#define AM35XX_IPSS_CLK_IDLEST_VAL 0 + +#define AM35XX_ST_IPSS_SHIFT 5 + /** * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI * @clk: struct clk * being enabled @@ -146,6 +158,88 @@ const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait = { .find_companion = omap2_clk_dflt_find_companion, }; +/** + * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS + * @clk: struct clk * being enabled + * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into + * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into + * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator + * + * The interface clocks on AM35xx IPSS reflects the clock idle status + * in the enable register itsel at a bit offset of 4 from the enable + * bit. A value of 1 indicates that clock is enabled. + */ +static void am35xx_clk_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, + u8 *idlest_bit, + u8 *idlest_val) +{ + *idlest_reg = (__force void __iomem *)(clk->enable_reg); + *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; + *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL; +} + +/** + * am35xx_clk_find_companion - find companion clock to @clk + * @clk: struct clk * to find the companion clock of + * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in + * @other_bit: u8 ** to return the companion clock bit shift in + * + * Some clocks don't have companion clocks. For example, modules with + * only an interface clock (such as HECC) don't have a companion + * clock. Right now, this code relies on the hardware exporting a bit + * in the correct companion register that indicates that the + * nonexistent 'companion clock' is active. Future patches will + * associate this type of code with per-module data structures to + * avoid this issue, and remove the casts. No return value. + */ +static void am35xx_clk_find_companion(struct clk_hw_omap *clk, + void __iomem **other_reg, + u8 *other_bit) +{ + *other_reg = (__force void __iomem *)(clk->enable_reg); + if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) + *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; + else + *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; +} + +const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = { + .find_idlest = am35xx_clk_find_idlest, + .find_companion = am35xx_clk_find_companion, +}; + +/** + * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS + * @clk: struct clk * being enabled + * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into + * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into + * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator + * + * The IPSS target CM_IDLEST bit is at a different shift from the + * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg + * and @idlest_bit. No return value. + */ +static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, + u8 *idlest_bit, + u8 *idlest_val) +{ + u32 r; + + r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); + *idlest_reg = (__force void __iomem *)r; + *idlest_bit = AM35XX_ST_IPSS_SHIFT; + *idlest_val = OMAP34XX_CM_IDLEST_VAL; +} + +const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = am35xx_clk_ipss_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; + static struct ti_dt_clk omap3xxx_clks[] = { DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"), DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"), diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index c6fbd153b6d4..0ca5a36da999 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -183,6 +183,8 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; +extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; +extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; int omap2_clkops_enable_clkdm(struct clk_hw *hw); void omap2_clkops_disable_clkdm(struct clk_hw *hw); diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index cd5b3eadc317..15f3c971ccab 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -331,8 +331,6 @@ void ti_clk_setup_features(struct ti_clk_features *features); const struct ti_clk_features *ti_clk_get_features(void); extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; -extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; -extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; #ifdef CONFIG_ATAGS int omap3430_clk_legacy_init(void); -- cgit v1.2.3 From a3314e9cf69c1d4052017e559ea69a042ccd83e2 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 4 Mar 2015 21:02:05 +0200 Subject: clk: ti: move some public definitions to private header Several exported TI clock driver features are no longer needed outside the clock driver itself, thus move all of these to the driver private header file. Also, update some of the driver files to actually include this header. Signed-off-by: Tero Kristo --- drivers/clk/ti/apll.c | 2 ++ drivers/clk/ti/autoidle.c | 2 ++ drivers/clk/ti/clk-43xx.c | 2 ++ drivers/clk/ti/clk-44xx.c | 2 ++ drivers/clk/ti/clk-54xx.c | 2 ++ drivers/clk/ti/clk-7xx.c | 3 ++- drivers/clk/ti/clock.h | 47 +++++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 45 --------------------------------------------- 8 files changed, 59 insertions(+), 46 deletions(-) diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c index 49baf3831546..594b759f02ee 100644 --- a/drivers/clk/ti/apll.c +++ b/drivers/clk/ti/apll.c @@ -27,6 +27,8 @@ #include #include +#include "clock.h" + #define APLL_FORCE_LOCK 0x1 #define APLL_AUTO_IDLE 0x2 #define MAX_APLL_WAIT_TRIES 1000000 diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c index 3dbcc3681058..94f0dcd94181 100644 --- a/drivers/clk/ti/autoidle.c +++ b/drivers/clk/ti/autoidle.c @@ -22,6 +22,8 @@ #include #include +#include "clock.h" + struct clk_ti_autoidle { void __iomem *reg; u8 shift; diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index 3795fce8a830..894316738459 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -19,6 +19,8 @@ #include #include +#include "clock.h" + static struct ti_dt_clk am43xx_clks[] = { DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c index 581db7711f51..7a8b51b35f9f 100644 --- a/drivers/clk/ti/clk-44xx.c +++ b/drivers/clk/ti/clk-44xx.c @@ -16,6 +16,8 @@ #include #include +#include "clock.h" + /* * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index 96c69a335975..59ce2fa2c104 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -17,6 +17,8 @@ #include #include +#include "clock.h" + #define OMAP5_DPLL_ABE_DEFFREQ 98304000 /* diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 5d2217ae4478..8b827219d454 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -16,11 +16,12 @@ #include #include +#include "clock.h" + #define DRA7_DPLL_ABE_DEFFREQ 180633600 #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 #define DRA7_DPLL_USB_DEFFREQ 960000000 - static struct ti_dt_clk dra7xx_clks[] = { DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"), DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"), diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 0ca5a36da999..3c43125b9cc9 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -154,6 +154,35 @@ struct ti_clk_dpll { u8 recal_st_bit; }; +/* Composite clock component types */ +enum { + CLK_COMPONENT_TYPE_GATE = 0, + CLK_COMPONENT_TYPE_DIVIDER, + CLK_COMPONENT_TYPE_MUX, + CLK_COMPONENT_TYPE_MAX, +}; + +/** + * struct ti_dt_clk - OMAP DT clock alias declarations + * @lk: clock lookup definition + * @node_name: clock DT node to map to + */ +struct ti_dt_clk { + struct clk_lookup lk; + char *node_name; +}; + +#define DT_CLK(dev, con, name) \ + { \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + }, \ + .node_name = name, \ + } + +typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); + struct clk *ti_clk_register_gate(struct ti_clk *setup); struct clk *ti_clk_register_interface(struct ti_clk *setup); struct clk *ti_clk_register_mux(struct ti_clk *setup); @@ -169,6 +198,12 @@ void ti_clk_patch_legacy_clks(struct ti_clk **patch); struct clk *ti_clk_register_clk(struct ti_clk *setup); int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); +void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index); +void ti_dt_clocks_register(struct ti_dt_clk *oclks); +int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, + ti_of_clk_init_cb_t func); +int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); + void omap2_init_clk_hw_omap_clocks(struct clk *clk); int of_ti_clk_autoidle_setup(struct device_node *node); void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); @@ -186,12 +221,24 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; +extern const struct clk_ops ti_clk_divider_ops; +extern const struct clk_ops ti_clk_mux_ops; + int omap2_clkops_enable_clkdm(struct clk_hw *hw); void omap2_clkops_disable_clkdm(struct clk_hw *hw); int omap2_dflt_clk_enable(struct clk_hw *hw); void omap2_dflt_clk_disable(struct clk_hw *hw); int omap2_dflt_clk_is_enabled(struct clk_hw *hw); +void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, + void __iomem **other_reg, + u8 *other_bit); +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, + u8 *idlest_bit, u8 *idlest_val); + +void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); +void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); u8 omap2_init_dpll_parent(struct clk_hw *hw); int omap3_noncore_dpll_enable(struct clk_hw *hw); diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 15f3c971ccab..5eccdf5c0e84 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -188,33 +188,6 @@ struct clk_hw_omap { /* DPLL Type and DCO Selection Flags */ #define DPLL_J_TYPE 0x1 -/* Composite clock component types */ -enum { - CLK_COMPONENT_TYPE_GATE = 0, - CLK_COMPONENT_TYPE_DIVIDER, - CLK_COMPONENT_TYPE_MUX, - CLK_COMPONENT_TYPE_MAX, -}; - -/** - * struct ti_dt_clk - OMAP DT clock alias declarations - * @lk: clock lookup definition - * @node_name: clock DT node to map to - */ -struct ti_dt_clk { - struct clk_lookup lk; - char *node_name; -}; - -#define DT_CLK(dev, con, name) \ - { \ - .lk = { \ - .dev_id = dev, \ - .con_id = con, \ - }, \ - .node_name = name, \ - } - /* Static memmap indices */ enum { TI_CLKM_CM = 0, @@ -225,8 +198,6 @@ enum { CLK_MAX_MEMMAPS }; -typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); - /** * struct clk_omap_reg - OMAP register declaration * @offset: offset from the master IP module base address @@ -266,9 +237,6 @@ struct ti_clk_ll_ops { extern struct ti_clk_ll_ops *ti_clk_ll_ops; -extern const struct clk_ops ti_clk_divider_ops; -extern const struct clk_ops ti_clk_mux_ops; - #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) void omap2_init_clk_clkdm(struct clk_hw *clk); @@ -276,14 +244,6 @@ int omap2_clk_disable_autoidle_all(void); int omap2_clk_enable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); int omap2_clk_deny_idle(struct clk *clk); -void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); -void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); -void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, - void __iomem **other_reg, - u8 *other_bit); -void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, - void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val); unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, unsigned long parent_rate); int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, @@ -292,14 +252,9 @@ void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); void omap2xxx_clkt_vps_init(void); unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); -void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index); -void ti_dt_clocks_register(struct ti_dt_clk *oclks); void ti_dt_clk_init_provider(struct device_node *np, int index); void ti_dt_clk_init_retry_clks(void); void ti_dt_clockdomains_setup(void); -int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, - ti_of_clk_init_cb_t func); -int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); int omap3430_dt_clk_init(void); int omap3630_dt_clk_init(void); -- cgit v1.2.3 From 9e11814ab8f08a0932c583b9e1504acac52ec7b3 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 4 Mar 2015 14:50:27 +0200 Subject: ARM: OMAP2+: clock: remove dead definitions from the clock header file Cleanup the mess in clock.h by removing all definitions that are no longer used for anything. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 1 - arch/arm/mach-omap2/clock.h | 124 --------------------------------- arch/arm/mach-omap2/clock34xx.h | 18 ----- 3 files changed, 143 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock34xx.h diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index 6cd2961069e9..07e1956a26ce 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -23,7 +23,6 @@ #include "clock.h" #include "clock3xxx.h" -#include "clock34xx.h" #include "sdrc.h" #include "sram.h" diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index a7e951129ffb..1986ab216b1a 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -23,90 +23,6 @@ #include #include -struct omap_clk { - u16 cpu; - struct clk_lookup lk; -}; - -#define CLK(dev, con, ck) \ - { \ - .lk = { \ - .dev_id = dev, \ - .con_id = con, \ - .clk = ck, \ - }, \ - } - -struct clockdomain; - -#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ - static struct clk_core _name##_core = { \ - .name = #_name, \ - .hw = &_name##_hw.hw, \ - .parent_names = _parent_array_name, \ - .num_parents = ARRAY_SIZE(_parent_array_name), \ - .ops = &_clkops_name, \ - }; \ - static struct clk _name = { \ - .core = &_name##_core, \ - }; - -#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \ - _clkops_name, _flags) \ - static struct clk_core _name##_core = { \ - .name = #_name, \ - .hw = &_name##_hw.hw, \ - .parent_names = _parent_array_name, \ - .num_parents = ARRAY_SIZE(_parent_array_name), \ - .ops = &_clkops_name, \ - .flags = _flags, \ - }; \ - static struct clk _name = { \ - .core = &_name##_core, \ - }; - -#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \ - static struct clk_hw_omap _name##_hw = { \ - .hw = { \ - .clk = &_name, \ - }, \ - .clkdm_name = _clkdm_name, \ - }; - -#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ - _clksel_reg, _clksel_mask, \ - _parent_names, _ops) \ - static struct clk _name; \ - static struct clk_hw_omap _name##_hw = { \ - .hw = { \ - .clk = &_name, \ - }, \ - .clksel = _clksel, \ - .clksel_reg = _clksel_reg, \ - .clksel_mask = _clksel_mask, \ - .clkdm_name = _clkdm_name, \ - }; \ - DEFINE_STRUCT_CLK(_name, _parent_names, _ops); - -#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \ - _clksel_reg, _clksel_mask, \ - _enable_reg, _enable_bit, \ - _hwops, _parent_names, _ops) \ - static struct clk _name; \ - static struct clk_hw_omap _name##_hw = { \ - .hw = { \ - .clk = &_name, \ - }, \ - .ops = _hwops, \ - .enable_reg = _enable_reg, \ - .enable_bit = _enable_bit, \ - .clksel = _clksel, \ - .clksel_reg = _clksel_reg, \ - .clksel_mask = _clksel_mask, \ - .clkdm_name = _clkdm_name, \ - }; \ - DEFINE_STRUCT_CLK(_name, _parent_names, _ops); - /* struct clksel_rate.flags possibilities */ #define RATE_IN_242X (1 << 0) #define RATE_IN_243X (1 << 1) @@ -127,38 +43,6 @@ struct clockdomain; /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) - -/** - * struct clksel_rate - register bitfield values corresponding to clk divisors - * @val: register bitfield value (shifted to bit 0) - * @div: clock divisor corresponding to @val - * @flags: (see "struct clksel_rate.flags possibilities" above) - * - * @val should match the value of a read from struct clk.clksel_reg - * AND'ed with struct clk.clksel_mask, shifted right to bit 0. - * - * @div is the divisor that should be applied to the parent clock's rate - * to produce the current clock's rate. - */ -struct clksel_rate { - u32 val; - u8 div; - u16 flags; -}; - -/** - * struct clksel - available parent clocks, and a pointer to their divisors - * @parent: struct clk * to a possible parent clock - * @rates: available divisors for this parent clock - * - * A struct clksel is always associated with one or more struct clks - * and one or more struct clksel_rates. - */ -struct clksel { - struct clk *parent; - const struct clksel_rate *rates; -}; - /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 #define CORE_CLK_SRC_DPLL 0x1 @@ -194,14 +78,6 @@ extern const struct clkops clkops_omap2_dflt; extern struct clk_functions omap2_clk_functions; -extern const struct clk_hw_omap_ops clkhwops_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; -extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; -extern const struct clk_hw_omap_ops clkhwops_apll54; -extern const struct clk_hw_omap_ops clkhwops_apll96; - struct regmap; int __init omap2_clk_provider_init(struct device_node *np, int index, diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h deleted file mode 100644 index 084ba71b2b31..000000000000 --- a/arch/arm/mach-omap2/clock34xx.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * OMAP34xx clock function prototypes and macros - * - * Copyright (C) 2007-2010 Texas Instruments, Inc. - * Copyright (C) 2007-2011 Nokia Corporation - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H -#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H - -extern const struct clkops clkops_omap3430es2_ssi_wait; -extern const struct clkops clkops_omap3430es2_iclk_ssi_wait; -extern const struct clkops clkops_omap3430es2_hsotgusb_wait; -extern const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait; -extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; -extern const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait; - -#endif -- cgit v1.2.3 From e9e63088e4f93cf4ed7999294c09905b7dcb4d32 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 27 Apr 2015 21:55:42 +0300 Subject: clk: ti: remove exported ll_ops struct, instead add an API for registration We should avoid exporting data from drivers, instead use an API for registering the clock low level operations. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c | 17 +++++++++++++---- arch/arm/mach-omap2/clock.h | 1 + arch/arm/mach-omap2/io.c | 2 ++ drivers/clk/ti/clk.c | 21 +++++++++++++++++++++ drivers/clk/ti/clock.h | 2 ++ drivers/clk/ti/clockdomain.c | 2 ++ include/linux/clk/ti.h | 3 +-- 7 files changed, 42 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 99875dba803a..40a88c2e4016 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -112,6 +112,19 @@ static struct ti_clk_ll_ops omap_clk_ll_ops = { .cm_split_idlest_reg = cm_split_idlest_reg, }; +/** + * omap2_clk_setup_ll_ops - setup clock driver low-level ops + * + * Sets up clock driver low-level platform ops. These are needed + * for register accesses and various other misc platform operations. + * Returns 0 on success, -EBUSY if low level ops have been registered + * already. + */ +int __init omap2_clk_setup_ll_ops(void) +{ + return ti_clk_setup_ll_ops(&omap_clk_ll_ops); +} + /** * omap2_clk_provider_init - initialize a clock provider * @match_table: DT device table to match for devices to init @@ -130,8 +143,6 @@ int __init omap2_clk_provider_init(struct device_node *np, int index, { struct clk_iomap *io; - ti_clk_ll_ops = &omap_clk_ll_ops; - io = kzalloc(sizeof(*io), GFP_KERNEL); io->regmap = syscon; @@ -155,8 +166,6 @@ void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem) { struct clk_iomap *io; - ti_clk_ll_ops = &omap_clk_ll_ops; - io = memblock_virt_alloc(sizeof(*io), 0); io->mem = mem; diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 1986ab216b1a..a7051d6a05e9 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -83,6 +83,7 @@ struct regmap; int __init omap2_clk_provider_init(struct device_node *np, int index, struct regmap *syscon, void __iomem *mem); void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem); +int __init omap2_clk_setup_ll_ops(void); void __init ti_clk_init_features(void); #endif diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 74678565cd97..a253aafbb9a2 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -722,6 +722,8 @@ int __init omap_clk_init(void) ti_clk_init_features(); + omap2_clk_setup_ll_ops(); + if (of_have_populated_dt()) { ret = omap_control_init(); if (ret) diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 5baea03cfc92..58b83e0af90f 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -32,6 +32,27 @@ static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS]; struct ti_clk_features ti_clk_features; +/** + * ti_clk_setup_ll_ops - setup low level clock operations + * @ops: low level clock ops descriptor + * + * Sets up low level clock operations for TI clock driver. This is used + * to provide various callbacks for the clock driver towards platform + * specific code. Returns 0 on success, -EBUSY if ll_ops have been + * registered already. + */ +int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops) +{ + if (ti_clk_ll_ops) { + pr_err("Attempt to register ll_ops multiple times.\n"); + return -EBUSY; + } + + ti_clk_ll_ops = ops; + + return 0; +} + /** * ti_dt_clocks_register - register DT alias clocks during boot * @oclks: list of clocks to register diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 3c43125b9cc9..d4d232fd89bc 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -280,4 +280,6 @@ long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long *best_parent_rate, struct clk_hw **best_parent_clk); +extern struct ti_clk_ll_ops *ti_clk_ll_ops; + #endif diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c index 61ef87b1a688..80a7b6944d10 100644 --- a/drivers/clk/ti/clockdomain.c +++ b/drivers/clk/ti/clockdomain.c @@ -21,6 +21,8 @@ #include #include +#include "clock.h" + #undef pr_fmt #define pr_fmt(fmt) "%s: " fmt, __func__ diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 5eccdf5c0e84..5b644313e38a 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -235,8 +235,6 @@ struct ti_clk_ll_ops { u8 *idlest_reg_id); }; -extern struct ti_clk_ll_ops *ti_clk_ll_ops; - #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) void omap2_init_clk_clkdm(struct clk_hw *clk); @@ -255,6 +253,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); void ti_dt_clk_init_provider(struct device_node *np, int index); void ti_dt_clk_init_retry_clks(void); void ti_dt_clockdomains_setup(void); +int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops); int omap3430_dt_clk_init(void); int omap3630_dt_clk_init(void); -- cgit v1.2.3 From e3aedf0234e7f12554c591bc37236f3469fed8fa Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 27 Apr 2015 22:20:57 +0300 Subject: ARM: OMAP2+: clock: remove legacy omap2_clk_readl/writel APIs As most of the clock driver code has migrated, these are no longer used for anything. Thus remove these APIs completely. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c | 16 ---------------- arch/arm/mach-omap2/clock.h | 3 --- 2 files changed, 19 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 40a88c2e4016..79cec5fbbe74 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -87,22 +87,6 @@ static u32 clk_memmap_readl(void __iomem *reg) return val; } -void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) -{ - if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) - writel_relaxed(val, reg); - else - clk_memmap_writel(val, reg); -} - -u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) -{ - if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) - return readl_relaxed(reg); - else - return clk_memmap_readl(reg); -} - static struct ti_clk_ll_ops omap_clk_ll_ops = { .clk_readl = clk_memmap_readl, .clk_writel = clk_memmap_writel, diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index a7051d6a05e9..f3dc04cd5538 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -68,9 +68,6 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, const char *mpu_ck_name); -u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg); -void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg); - extern u16 cpu_mask; extern const struct clkops clkops_omap2_dflt_wait; -- cgit v1.2.3 From 989feafb84118a840ff21250a1e5f516f43e3dbb Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 27 Apr 2015 22:23:06 +0300 Subject: clk: ti: move low-level access and init code under clock driver With most of the clock code under clock driver already, the low-level register access code, and the init code for the same, is no longer needed outside the clock driver. Thus, these can be moved under clock driver also. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c | 84 --------------------------------------------- arch/arm/mach-omap2/clock.h | 5 --- drivers/clk/ti/clk.c | 75 ++++++++++++++++++++++++++++++++++++++-- include/linux/clk/ti.h | 7 +++- 4 files changed, 78 insertions(+), 93 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 79cec5fbbe74..4340ba6524d1 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -23,9 +23,7 @@ #include #include #include -#include #include -#include #include #include @@ -55,41 +53,7 @@ u16 cpu_mask; #define OMAP3PLUS_DPLL_FINT_MIN 32000 #define OMAP3PLUS_DPLL_FINT_MAX 52000000 -struct clk_iomap { - struct regmap *regmap; - void __iomem *mem; -}; - -static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS]; - -static void clk_memmap_writel(u32 val, void __iomem *reg) -{ - struct clk_omap_reg *r = (struct clk_omap_reg *)® - struct clk_iomap *io = clk_memmaps[r->index]; - - if (io->regmap) - regmap_write(io->regmap, r->offset, val); - else - writel_relaxed(val, io->mem + r->offset); -} - -static u32 clk_memmap_readl(void __iomem *reg) -{ - u32 val; - struct clk_omap_reg *r = (struct clk_omap_reg *)® - struct clk_iomap *io = clk_memmaps[r->index]; - - if (io->regmap) - regmap_read(io->regmap, r->offset, &val); - else - val = readl_relaxed(io->mem + r->offset); - - return val; -} - static struct ti_clk_ll_ops omap_clk_ll_ops = { - .clk_readl = clk_memmap_readl, - .clk_writel = clk_memmap_writel, .clkdm_clk_enable = clkdm_clk_enable, .clkdm_clk_disable = clkdm_clk_disable, .cm_wait_module_ready = omap_cm_wait_module_ready, @@ -109,54 +73,6 @@ int __init omap2_clk_setup_ll_ops(void) return ti_clk_setup_ll_ops(&omap_clk_ll_ops); } -/** - * omap2_clk_provider_init - initialize a clock provider - * @match_table: DT device table to match for devices to init - * @np: device node pointer for the this clock provider - * @index: index for the clock provider - + @syscon: syscon regmap pointer - * @mem: iomem pointer for the clock provider memory area, only used if - * syscon is not provided - * - * Initializes a clock provider module (CM/PRM etc.), registering - * the memory mapping at specified index and initializing the - * low level driver infrastructure. Returns 0 in success. - */ -int __init omap2_clk_provider_init(struct device_node *np, int index, - struct regmap *syscon, void __iomem *mem) -{ - struct clk_iomap *io; - - io = kzalloc(sizeof(*io), GFP_KERNEL); - - io->regmap = syscon; - io->mem = mem; - - clk_memmaps[index] = io; - - ti_dt_clk_init_provider(np, index); - - return 0; -} - -/** - * omap2_clk_legacy_provider_init - initialize a legacy clock provider - * @index: index for the clock provider - * @mem: iomem pointer for the clock provider memory area - * - * Initializes a legacy clock provider memory mapping. - */ -void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem) -{ - struct clk_iomap *io; - - io = memblock_virt_alloc(sizeof(*io), 0); - - io->mem = mem; - - clk_memmaps[index] = io; -} - /* * OMAP2+ specific clock functions */ diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index f3dc04cd5538..67da640ba1c7 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -75,11 +75,6 @@ extern const struct clkops clkops_omap2_dflt; extern struct clk_functions omap2_clk_functions; -struct regmap; - -int __init omap2_clk_provider_init(struct device_node *np, int index, - struct regmap *syscon, void __iomem *mem); -void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem); int __init omap2_clk_setup_ll_ops(void); void __init ti_clk_init_features(void); diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 58b83e0af90f..07584e00677e 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -21,6 +21,8 @@ #include #include #include +#include +#include #include "clock.h" @@ -32,6 +34,38 @@ static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS]; struct ti_clk_features ti_clk_features; +struct clk_iomap { + struct regmap *regmap; + void __iomem *mem; +}; + +static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS]; + +static void clk_memmap_writel(u32 val, void __iomem *reg) +{ + struct clk_omap_reg *r = (struct clk_omap_reg *)® + struct clk_iomap *io = clk_memmaps[r->index]; + + if (io->regmap) + regmap_write(io->regmap, r->offset, val); + else + writel_relaxed(val, io->mem + r->offset); +} + +static u32 clk_memmap_readl(void __iomem *reg) +{ + u32 val; + struct clk_omap_reg *r = (struct clk_omap_reg *)® + struct clk_iomap *io = clk_memmaps[r->index]; + + if (io->regmap) + regmap_read(io->regmap, r->offset, &val); + else + val = readl_relaxed(io->mem + r->offset); + + return val; +} + /** * ti_clk_setup_ll_ops - setup low level clock operations * @ops: low level clock ops descriptor @@ -49,6 +83,8 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops) } ti_clk_ll_ops = ops; + ops->clk_readl = clk_memmap_readl; + ops->clk_writel = clk_memmap_writel; return 0; } @@ -161,28 +197,61 @@ void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index) } /** - * ti_dt_clk_init_provider - init master clock provider + * omap2_clk_provider_init - init master clock provider * @parent: master node * @index: internal index for clk_reg_ops + * @syscon: syscon regmap pointer for accessing clock registers + * @mem: iomem pointer for the clock provider memory area, only used if + * syscon is not provided * * Initializes a master clock IP block. This basically sets up the * mapping from clocks node to the memory map index. All the clocks * are then initialized through the common of_clk_init call, and the * clocks will access their memory maps based on the node layout. + * Returns 0 in success. */ -void ti_dt_clk_init_provider(struct device_node *parent, int index) +int __init omap2_clk_provider_init(struct device_node *parent, int index, + struct regmap *syscon, void __iomem *mem) { struct device_node *clocks; + struct clk_iomap *io; /* get clocks for this parent */ clocks = of_get_child_by_name(parent, "clocks"); if (!clocks) { pr_err("%s missing 'clocks' child node.\n", parent->name); - return; + return -EINVAL; } /* add clocks node info */ clocks_node_ptr[index] = clocks; + + io = kzalloc(sizeof(*io), GFP_KERNEL); + + io->regmap = syscon; + io->mem = mem; + + clk_memmaps[index] = io; + + return 0; +} + +/** + * omap2_clk_legacy_provider_init - initialize a legacy clock provider + * @index: index for the clock provider + * @mem: iomem pointer for the clock provider memory area + * + * Initializes a legacy clock provider memory mapping. + */ +void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem) +{ + struct clk_iomap *io; + + io = memblock_virt_alloc(sizeof(*io), 0); + + io->mem = mem; + + clk_memmaps[index] = io; } /** diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 5b644313e38a..9299222d680d 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -250,11 +250,16 @@ void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); void omap2xxx_clkt_vps_init(void); unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); -void ti_dt_clk_init_provider(struct device_node *np, int index); void ti_dt_clk_init_retry_clks(void); void ti_dt_clockdomains_setup(void); int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops); +struct regmap; + +int omap2_clk_provider_init(struct device_node *parent, int index, + struct regmap *syscon, void __iomem *mem); +void omap2_clk_legacy_provider_init(int index, void __iomem *mem); + int omap3430_dt_clk_init(void); int omap3630_dt_clk_init(void); int am35xx_dt_clk_init(void); -- cgit v1.2.3 From 7663a4aac625268674060d78ee00f97a36a03af7 Mon Sep 17 00:00:00 2001 From: Hartmut Knaack Date: Wed, 10 Jun 2015 21:51:20 +0200 Subject: tools:iio: adjust coding style Fix various coding style issues, including: * have spaces around operators * indentation * consolidate parameters in same line * required braces * adjust/drop comments * multiline comment style * delete unnecessary empty lines * add empty lines to visualize logial code blocks * typos Signed-off-by: Hartmut Knaack Signed-off-by: Jonathan Cameron --- tools/iio/generic_buffer.c | 46 +++++++++-------- tools/iio/iio_event_monitor.c | 13 +++-- tools/iio/iio_utils.c | 111 +++++++++++++++++++++++++----------------- tools/iio/iio_utils.h | 15 +++--- tools/iio/lsiio.c | 15 +++--- 5 files changed, 118 insertions(+), 82 deletions(-) diff --git a/tools/iio/generic_buffer.c b/tools/iio/generic_buffer.c index 4eebb6616e5c..fc362d2ff983 100644 --- a/tools/iio/generic_buffer.c +++ b/tools/iio/generic_buffer.c @@ -51,11 +51,13 @@ int size_from_channelarray(struct iio_channel_info *channels, int num_channels) if (bytes % channels[i].bytes == 0) channels[i].location = bytes; else - channels[i].location = bytes - bytes%channels[i].bytes - + channels[i].bytes; + channels[i].location = bytes - bytes % channels[i].bytes + + channels[i].bytes; + bytes = channels[i].location + channels[i].bytes; i++; } + return bytes; } @@ -136,9 +138,9 @@ void print8byte(uint64_t input, struct iio_channel_info *info) /** * process_scan() - print out the values in SI units * @data: pointer to the start of the scan - * @channels: information about the channels. Note - * size_from_channelarray must have been called first to fill the - * location offsets. + * @channels: information about the channels. + * Note: size_from_channelarray must have been called first + * to fill the location offsets. * @num_channels: number of channels **/ void process_scan(char *data, @@ -213,6 +215,7 @@ int main(int argc, char **argv) num_loops = strtoul(optarg, &dummy, 10); if (errno) return -errno; + break; case 'e': noevents = 1; @@ -225,6 +228,7 @@ int main(int argc, char **argv) buf_len = strtoul(optarg, &dummy, 10); if (errno) return -errno; + break; case 'n': device_name = optarg; @@ -257,6 +261,7 @@ int main(int argc, char **argv) printf("Failed to find the %s\n", device_name); return dev_num; } + printf("iio device number being used is %d\n", dev_num); ret = asprintf(&dev_dir_name, "%siio:device%d", iio_dir, dev_num); @@ -285,9 +290,11 @@ int main(int argc, char **argv) ret = trig_num; goto error_free_triggername; } + printf("iio trigger number being used is %d\n", trig_num); - } else + } else { printf("trigger-less mode selected\n"); + } /* * Parse the files in scan_elements to identify what channels are @@ -314,8 +321,10 @@ int main(int argc, char **argv) if (!notrigger) { printf("%s %s\n", dev_dir_name, trigger_name); - /* Set the device trigger to be the data ready trigger found - * above */ + /* + * Set the device trigger to be the data ready trigger found + * above + */ ret = write_sysfs_string_and_verify("trigger/current_trigger", dev_dir_name, trigger_name); @@ -334,8 +343,9 @@ int main(int argc, char **argv) ret = write_sysfs_int("enable", buf_dir_name, 1); if (ret < 0) goto error_free_buf_dir_name; + scan_size = size_from_channelarray(channels, num_channels); - data = malloc(scan_size*buf_len); + data = malloc(scan_size * buf_len); if (!data) { ret = -ENOMEM; goto error_free_buf_dir_name; @@ -349,13 +359,12 @@ int main(int argc, char **argv) /* Attempt to open non blocking the access dev */ fp = open(buffer_access, O_RDONLY | O_NONBLOCK); - if (fp == -1) { /* If it isn't there make the node */ + if (fp == -1) { /* TODO: If it isn't there make the node */ ret = -errno; printf("Failed to open %s\n", buffer_access); goto error_free_buffer_access; } - /* Wait for events 10 times */ for (j = 0; j < num_loops; j++) { if (!noevents) { struct pollfd pfd = { @@ -372,25 +381,22 @@ int main(int argc, char **argv) } toread = buf_len; - } else { usleep(timedelay); toread = 64; } - read_size = read(fp, - data, - toread*scan_size); + read_size = read(fp, data, toread * scan_size); if (read_size < 0) { if (errno == EAGAIN) { printf("nothing available\n"); continue; - } else + } else { break; + } } - for (i = 0; i < read_size/scan_size; i++) - process_scan(data + scan_size*i, - channels, + for (i = 0; i < read_size / scan_size; i++) + process_scan(data + scan_size * i, channels, num_channels); } @@ -409,6 +415,7 @@ int main(int argc, char **argv) error_close_buffer_access: if (close(fp) == -1) perror("Failed to close buffer"); + error_free_buffer_access: free(buffer_access); error_free_data: @@ -424,6 +431,7 @@ error_free_channels: error_free_triggername: if (datardytrigger) free(trigger_name); + error_free_dev_dir_name: free(dev_dir_name); diff --git a/tools/iio/iio_event_monitor.c b/tools/iio/iio_event_monitor.c index 016760e769c0..a4ab6bb8f872 100644 --- a/tools/iio/iio_event_monitor.c +++ b/tools/iio/iio_event_monitor.c @@ -13,7 +13,6 @@ * * Usage: * iio_event_monitor - * */ #include @@ -209,7 +208,8 @@ static void print_event(struct iio_event_data *event) if (!event_is_known(event)) { printf("Unknown event: time: %lld, id: %llx\n", - event->timestamp, event->id); + event->timestamp, event->id); + return; } @@ -229,6 +229,7 @@ static void print_event(struct iio_event_data *event) if (dir != IIO_EV_DIR_NONE) printf(", direction: %s", iio_ev_dir_text[dir]); + printf("\n"); } @@ -251,14 +252,16 @@ int main(int argc, char **argv) dev_num = find_type_by_name(device_name, "iio:device"); if (dev_num >= 0) { printf("Found IIO device with name %s with device number %d\n", - device_name, dev_num); + device_name, dev_num); ret = asprintf(&chrdev_name, "/dev/iio:device%d", dev_num); if (ret < 0) { return -ENOMEM; } } else { - /* If we can't find a IIO device by name assume device_name is a - IIO chrdev */ + /* + * If we can't find an IIO device by name assume device_name is + * an IIO chrdev + */ chrdev_name = strdup(device_name); if (!chrdev_name) return -ENOMEM; diff --git a/tools/iio/iio_utils.c b/tools/iio/iio_utils.c index ec9ab7f9ae4c..4eac11ad38c4 100644 --- a/tools/iio/iio_utils.c +++ b/tools/iio/iio_utils.c @@ -32,8 +32,7 @@ static char * const iio_direction[] = { * * Returns 0 on success, or a negative error code if string extraction failed. **/ -int iioutils_break_up_name(const char *full_name, - char **generic_name) +int iioutils_break_up_name(const char *full_name, char **generic_name) { char *current; char *w, *r; @@ -65,6 +64,7 @@ int iioutils_break_up_name(const char *full_name, *w = *r; w++; } + r++; } *w = '\0'; @@ -88,15 +88,10 @@ int iioutils_break_up_name(const char *full_name, * * Returns a value >= 0 on success, otherwise a negative error code. **/ -int iioutils_get_type(unsigned *is_signed, - unsigned *bytes, - unsigned *bits_used, - unsigned *shift, - uint64_t *mask, - unsigned *be, - const char *device_dir, - const char *name, - const char *generic_name) +int iioutils_get_type(unsigned *is_signed, unsigned *bytes, unsigned *bits_used, + unsigned *shift, uint64_t *mask, unsigned *be, + const char *device_dir, const char *name, + const char *generic_name) { FILE *sysfsfp; int ret; @@ -126,6 +121,7 @@ int iioutils_get_type(unsigned *is_signed, ret = -errno; goto error_free_builtname_generic; } + ret = -ENOENT; while (ent = readdir(dp), ent != NULL) /* @@ -140,6 +136,7 @@ int iioutils_get_type(unsigned *is_signed, ret = -ENOMEM; goto error_closedir; } + sysfsfp = fopen(filename, "r"); if (sysfsfp == NULL) { ret = -errno; @@ -162,12 +159,14 @@ int iioutils_get_type(unsigned *is_signed, printf("scan type description didn't match\n"); goto error_close_sysfsfp; } + *be = (endianchar == 'b'); *bytes = padint / 8; if (*bits_used == 64) *mask = ~0; else *mask = (1 << *bits_used) - 1; + *is_signed = (signchar == 's'); if (fclose(sysfsfp)) { ret = -errno; @@ -177,9 +176,9 @@ int iioutils_get_type(unsigned *is_signed, sysfsfp = 0; free(filename); - filename = 0; } + error_close_sysfsfp: if (sysfsfp) if (fclose(sysfsfp)) @@ -188,6 +187,7 @@ error_close_sysfsfp: error_free_filename: if (filename) free(filename); + error_closedir: if (closedir(dp) == -1) perror("iioutils_get_type(): Failed to close directory"); @@ -212,11 +212,9 @@ error_free_scan_el_dir: * * Returns a value >= 0 on success, otherwise a negative error code. **/ -int iioutils_get_param_float(float *output, - const char *param_name, - const char *device_dir, - const char *name, - const char *generic_name) +int iioutils_get_param_float(float *output, const char *param_name, + const char *device_dir, const char *name, + const char *generic_name) { FILE *sysfsfp; int ret; @@ -235,11 +233,13 @@ int iioutils_get_param_float(float *output, ret = -ENOMEM; goto error_free_builtname; } + dp = opendir(device_dir); if (dp == NULL) { ret = -errno; goto error_free_builtname_generic; } + ret = -ENOENT; while (ent = readdir(dp), ent != NULL) if ((strcmp(builtname, ent->d_name) == 0) || @@ -250,11 +250,13 @@ int iioutils_get_param_float(float *output, ret = -ENOMEM; goto error_closedir; } + sysfsfp = fopen(filename, "r"); if (!sysfsfp) { ret = -errno; goto error_free_filename; } + errno = 0; if (fscanf(sysfsfp, "%f", output) != 1) ret = errno ? -errno : -ENODATA; @@ -264,6 +266,7 @@ int iioutils_get_param_float(float *output, error_free_filename: if (filename) free(filename); + error_closedir: if (closedir(dp) == -1) perror("iioutils_get_param_float(): Failed to close directory"); @@ -282,16 +285,14 @@ error_free_builtname: * @cnt: the amount of array elements **/ -void bsort_channel_array_by_index(struct iio_channel_info **ci_array, - int cnt) +void bsort_channel_array_by_index(struct iio_channel_info **ci_array, int cnt) { - struct iio_channel_info temp; int x, y; for (x = 0; x < cnt; x++) for (y = 0; y < (cnt - 1); y++) - if ((*ci_array)[y].index > (*ci_array)[y+1].index) { + if ((*ci_array)[y].index > (*ci_array)[y + 1].index) { temp = (*ci_array)[y + 1]; (*ci_array)[y + 1] = (*ci_array)[y]; (*ci_array)[y] = temp; @@ -307,8 +308,7 @@ void bsort_channel_array_by_index(struct iio_channel_info **ci_array, * Returns 0 on success, otherwise a negative error code. **/ int build_channel_array(const char *device_dir, - struct iio_channel_info **ci_array, - int *counter) + struct iio_channel_info **ci_array, int *counter) { DIR *dp; FILE *sysfsfp; @@ -329,6 +329,7 @@ int build_channel_array(const char *device_dir, ret = -errno; goto error_free_name; } + while (ent = readdir(dp), ent != NULL) if (strcmp(ent->d_name + strlen(ent->d_name) - strlen("_en"), "_en") == 0) { @@ -338,12 +339,14 @@ int build_channel_array(const char *device_dir, ret = -ENOMEM; goto error_close_dir; } + sysfsfp = fopen(filename, "r"); if (sysfsfp == NULL) { ret = -errno; free(filename); goto error_close_dir; } + errno = 0; if (fscanf(sysfsfp, "%i", &ret) != 1) { ret = errno ? -errno : -ENODATA; @@ -353,9 +356,9 @@ int build_channel_array(const char *device_dir, free(filename); goto error_close_dir; } - if (ret == 1) (*counter)++; + if (fclose(sysfsfp)) { ret = -errno; free(filename); @@ -364,11 +367,13 @@ int build_channel_array(const char *device_dir, free(filename); } + *ci_array = malloc(sizeof(**ci_array) * (*counter)); if (*ci_array == NULL) { ret = -ENOMEM; goto error_close_dir; } + seekdir(dp, 0); while (ent = readdir(dp), ent != NULL) { if (strcmp(ent->d_name + strlen(ent->d_name) - strlen("_en"), @@ -384,6 +389,7 @@ int build_channel_array(const char *device_dir, count--; goto error_cleanup_array; } + sysfsfp = fopen(filename, "r"); if (sysfsfp == NULL) { ret = -errno; @@ -391,6 +397,7 @@ int build_channel_array(const char *device_dir, count--; goto error_cleanup_array; } + errno = 0; if (fscanf(sysfsfp, "%i", ¤t_enabled) != 1) { ret = errno ? -errno : -ENODATA; @@ -423,6 +430,7 @@ int build_channel_array(const char *device_dir, count--; goto error_cleanup_array; } + /* Get the generic and specific name elements */ ret = iioutils_break_up_name(current->name, ¤t->generic_name); @@ -432,6 +440,7 @@ int build_channel_array(const char *device_dir, count--; goto error_cleanup_array; } + ret = asprintf(&filename, "%s/%s_index", scan_el_dir, @@ -441,6 +450,7 @@ int build_channel_array(const char *device_dir, ret = -ENOMEM; goto error_cleanup_array; } + sysfsfp = fopen(filename, "r"); if (sysfsfp == NULL) { ret = -errno; @@ -474,6 +484,7 @@ int build_channel_array(const char *device_dir, current->generic_name); if (ret < 0) goto error_cleanup_array; + ret = iioutils_get_param_float(¤t->offset, "offset", device_dir, @@ -481,6 +492,7 @@ int build_channel_array(const char *device_dir, current->generic_name); if (ret < 0) goto error_cleanup_array; + ret = iioutils_get_type(¤t->is_signed, ¤t->bytes, ¤t->bits_used, @@ -562,9 +574,9 @@ int find_type_by_name(const char *name, const char *type) while (ent = readdir(dp), ent != NULL) { if (strcmp(ent->d_name, ".") != 0 && - strcmp(ent->d_name, "..") != 0 && - strlen(ent->d_name) > strlen(type) && - strncmp(ent->d_name, type, strlen(type)) == 0) { + strcmp(ent->d_name, "..") != 0 && + strlen(ent->d_name) > strlen(type) && + strncmp(ent->d_name, type, strlen(type)) == 0) { errno = 0; ret = sscanf(ent->d_name + strlen(type), "%d", &number); if (ret < 0) { @@ -580,12 +592,9 @@ int find_type_by_name(const char *name, const char *type) numstrlen = calc_digits(number); /* verify the next character is not a colon */ if (strncmp(ent->d_name + strlen(type) + numstrlen, - ":", - 1) != 0) { - filename = malloc(strlen(iio_dir) - + strlen(type) - + numstrlen - + 6); + ":", 1) != 0) { + filename = malloc(strlen(iio_dir) + strlen(type) + + numstrlen + 6); if (filename == NULL) { ret = -ENOMEM; goto error_close_dir; @@ -603,6 +612,7 @@ int find_type_by_name(const char *name, const char *type) free(filename); continue; } + free(filename); errno = 0; if (fscanf(nameFile, "%s", thisname) != 1) { @@ -618,6 +628,7 @@ int find_type_by_name(const char *name, const char *type) if (strcmp(name, thisname) == 0) { if (closedir(dp) == -1) return -errno; + return number; } } @@ -631,6 +642,7 @@ int find_type_by_name(const char *name, const char *type) error_close_dir: if (closedir(dp) == -1) perror("find_type_by_name(): Failed to close directory"); + return ret; } @@ -644,6 +656,7 @@ static int _write_sysfs_int(const char *filename, const char *basedir, int val, if (temp == NULL) return -ENOMEM; + ret = sprintf(temp, "%s/%s", basedir, filename); if (ret < 0) goto error_free; @@ -654,6 +667,7 @@ static int _write_sysfs_int(const char *filename, const char *basedir, int val, printf("failed to open %s\n", temp); goto error_free; } + ret = fprintf(sysfsfp, "%d", val); if (ret < 0) { if (fclose(sysfsfp)) @@ -674,6 +688,7 @@ static int _write_sysfs_int(const char *filename, const char *basedir, int val, printf("failed to open %s\n", temp); goto error_free; } + if (fscanf(sysfsfp, "%d", &test) != 1) { ret = errno ? -errno : -ENODATA; if (fclose(sysfsfp)) @@ -688,13 +703,12 @@ static int _write_sysfs_int(const char *filename, const char *basedir, int val, } if (test != val) { - printf("Possible failure in int write %d to %s%s\n", - val, - basedir, - filename); + printf("Possible failure in int write %d to %s/%s\n", + val, basedir, filename); ret = -1; } } + error_free: free(temp); return ret; @@ -739,6 +753,7 @@ static int _write_sysfs_string(const char *filename, const char *basedir, printf("Memory allocation failed\n"); return -ENOMEM; } + ret = sprintf(temp, "%s/%s", basedir, filename); if (ret < 0) goto error_free; @@ -749,6 +764,7 @@ static int _write_sysfs_string(const char *filename, const char *basedir, printf("Could not open %s\n", temp); goto error_free; } + ret = fprintf(sysfsfp, "%s", val); if (ret < 0) { if (fclose(sysfsfp)) @@ -766,9 +782,10 @@ static int _write_sysfs_string(const char *filename, const char *basedir, sysfsfp = fopen(temp, "r"); if (sysfsfp == NULL) { ret = -errno; - printf("could not open file to verify\n"); + printf("Could not open file to verify\n"); goto error_free; } + if (fscanf(sysfsfp, "%s", temp) != 1) { ret = errno ? -errno : -ENODATA; if (fclose(sysfsfp)) @@ -784,15 +801,12 @@ static int _write_sysfs_string(const char *filename, const char *basedir, if (strcmp(temp, val) != 0) { printf("Possible failure in string write of %s " - "Should be %s " - "written to %s\%s\n", - temp, - val, - basedir, - filename); + "Should be %s written to %s/%s\n", temp, val, + basedir, filename); ret = -1; } } + error_free: free(temp); @@ -845,6 +859,7 @@ int read_sysfs_posint(const char *filename, const char *basedir) printf("Memory allocation failed"); return -ENOMEM; } + ret = sprintf(temp, "%s/%s", basedir, filename); if (ret < 0) goto error_free; @@ -854,6 +869,7 @@ int read_sysfs_posint(const char *filename, const char *basedir) ret = -errno; goto error_free; } + errno = 0; if (fscanf(sysfsfp, "%d\n", &ret) != 1) { ret = errno ? -errno : -ENODATA; @@ -868,6 +884,7 @@ int read_sysfs_posint(const char *filename, const char *basedir) error_free: free(temp); + return ret; } @@ -889,6 +906,7 @@ int read_sysfs_float(const char *filename, const char *basedir, float *val) printf("Memory allocation failed"); return -ENOMEM; } + ret = sprintf(temp, "%s/%s", basedir, filename); if (ret < 0) goto error_free; @@ -898,6 +916,7 @@ int read_sysfs_float(const char *filename, const char *basedir, float *val) ret = -errno; goto error_free; } + errno = 0; if (fscanf(sysfsfp, "%f\n", val) != 1) { ret = errno ? -errno : -ENODATA; @@ -912,6 +931,7 @@ int read_sysfs_float(const char *filename, const char *basedir, float *val) error_free: free(temp); + return ret; } @@ -933,6 +953,7 @@ int read_sysfs_string(const char *filename, const char *basedir, char *str) printf("Memory allocation failed"); return -ENOMEM; } + ret = sprintf(temp, "%s/%s", basedir, filename); if (ret < 0) goto error_free; @@ -942,6 +963,7 @@ int read_sysfs_string(const char *filename, const char *basedir, char *str) ret = -errno; goto error_free; } + errno = 0; if (fscanf(sysfsfp, "%s\n", str) != 1) { ret = errno ? -errno : -ENODATA; @@ -956,6 +978,7 @@ int read_sysfs_string(const char *filename, const char *basedir, char *str) error_free: free(temp); + return ret; } diff --git a/tools/iio/iio_utils.h b/tools/iio/iio_utils.h index 379eed9deaea..086610139ade 100644 --- a/tools/iio/iio_utils.h +++ b/tools/iio/iio_utils.h @@ -51,17 +51,16 @@ struct iio_channel_info { }; int iioutils_break_up_name(const char *full_name, char **generic_name); -int iioutils_get_type(unsigned *is_signed, unsigned *bytes, - unsigned *bits_used, unsigned *shift, - uint64_t *mask, unsigned *be, - const char *device_dir, const char *name, - const char *generic_name); +int iioutils_get_type(unsigned *is_signed, unsigned *bytes, unsigned *bits_used, + unsigned *shift, uint64_t *mask, unsigned *be, + const char *device_dir, const char *name, + const char *generic_name); int iioutils_get_param_float(float *output, const char *param_name, - const char *device_dir, const char *name, - const char *generic_name); + const char *device_dir, const char *name, + const char *generic_name); void bsort_channel_array_by_index(struct iio_channel_info **ci_array, int cnt); int build_channel_array(const char *device_dir, - struct iio_channel_info **ci_array, int *counter); + struct iio_channel_info **ci_array, int *counter); int find_type_by_name(const char *name, const char *type); int write_sysfs_int(const char *filename, const char *basedir, int val); int write_sysfs_int_and_verify(const char *filename, const char *basedir, diff --git a/tools/iio/lsiio.c b/tools/iio/lsiio.c index b59ee1733924..f5b3bd0267d5 100644 --- a/tools/iio/lsiio.c +++ b/tools/iio/lsiio.c @@ -20,7 +20,6 @@ #include #include "iio_utils.h" - static enum verbosity { VERBLEVEL_DEFAULT, /* 0 gives lspci behaviour */ VERBLEVEL_SENSORS, /* 1 lists sensors */ @@ -29,17 +28,16 @@ static enum verbosity { const char *type_device = "iio:device"; const char *type_trigger = "trigger"; - static inline int check_prefix(const char *str, const char *prefix) { return strlen(str) > strlen(prefix) && - strncmp(str, prefix, strlen(prefix)) == 0; + strncmp(str, prefix, strlen(prefix)) == 0; } static inline int check_postfix(const char *str, const char *postfix) { return strlen(str) > strlen(postfix) && - strcmp(str + strlen(str) - strlen(postfix), postfix) == 0; + strcmp(str + strlen(str) - strlen(postfix), postfix) == 0; } static int dump_channels(const char *dev_dir_name) @@ -50,11 +48,11 @@ static int dump_channels(const char *dev_dir_name) dp = opendir(dev_dir_name); if (dp == NULL) return -errno; + while (ent = readdir(dp), ent != NULL) if (check_prefix(ent->d_name, "in_") && - check_postfix(ent->d_name, "_raw")) { + check_postfix(ent->d_name, "_raw")) printf(" %-10s\n", ent->d_name); - } return (closedir(dp) == -1) ? -errno : 0; } @@ -69,6 +67,7 @@ static int dump_one_device(const char *dev_dir_name) "%i", &dev_idx); if (retval != 1) return -EINVAL; + retval = read_sysfs_string("name", dev_dir_name, name); if (retval) return retval; @@ -77,6 +76,7 @@ static int dump_one_device(const char *dev_dir_name) if (verblevel >= VERBLEVEL_SENSORS) return dump_channels(dev_dir_name); + return 0; } @@ -90,11 +90,13 @@ static int dump_one_trigger(const char *dev_dir_name) "%i", &dev_idx); if (retval != 1) return -EINVAL; + retval = read_sysfs_string("name", dev_dir_name, name); if (retval) return retval; printf("Trigger %03d: %s\n", dev_idx, name); + return 0; } @@ -151,6 +153,7 @@ static int dump_devices(void) free(dev_dir_name); } } + return (closedir(dp) == -1) ? -errno : 0; error_close_dir: -- cgit v1.2.3 From a9d7acc8b0d52ae2f15f6280f63ac9d1e73cfb78 Mon Sep 17 00:00:00 2001 From: Hartmut Knaack Date: Wed, 10 Jun 2015 21:51:21 +0200 Subject: tools:iio: rename variables Use more appropriate/common variable names: * namepf instead of nameFile in iio_utils.c * ret instead of retval in lsiio.c Signed-off-by: Hartmut Knaack Signed-off-by: Jonathan Cameron --- tools/iio/iio_utils.c | 10 +++++----- tools/iio/lsiio.c | 28 ++++++++++++++-------------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/tools/iio/iio_utils.c b/tools/iio/iio_utils.c index 4eac11ad38c4..8fb3214c70f2 100644 --- a/tools/iio/iio_utils.c +++ b/tools/iio/iio_utils.c @@ -561,7 +561,7 @@ int find_type_by_name(const char *name, const char *type) const struct dirent *ent; int number, numstrlen, ret; - FILE *nameFile; + FILE *namefp; DIR *dp; char thisname[IIO_MAX_NAME_LENGTH]; char *filename; @@ -607,20 +607,20 @@ int find_type_by_name(const char *name, const char *type) goto error_close_dir; } - nameFile = fopen(filename, "r"); - if (!nameFile) { + namefp = fopen(filename, "r"); + if (!namefp) { free(filename); continue; } free(filename); errno = 0; - if (fscanf(nameFile, "%s", thisname) != 1) { + if (fscanf(namefp, "%s", thisname) != 1) { ret = errno ? -errno : -ENODATA; goto error_close_dir; } - if (fclose(nameFile)) { + if (fclose(namefp)) { ret = -errno; goto error_close_dir; } diff --git a/tools/iio/lsiio.c b/tools/iio/lsiio.c index f5b3bd0267d5..7f432a55a6c4 100644 --- a/tools/iio/lsiio.c +++ b/tools/iio/lsiio.c @@ -61,16 +61,16 @@ static int dump_one_device(const char *dev_dir_name) { char name[IIO_MAX_NAME_LENGTH]; int dev_idx; - int retval; + int ret; - retval = sscanf(dev_dir_name + strlen(iio_dir) + strlen(type_device), - "%i", &dev_idx); - if (retval != 1) + ret = sscanf(dev_dir_name + strlen(iio_dir) + strlen(type_device), "%i", + &dev_idx); + if (ret != 1) return -EINVAL; - retval = read_sysfs_string("name", dev_dir_name, name); - if (retval) - return retval; + ret = read_sysfs_string("name", dev_dir_name, name); + if (ret) + return ret; printf("Device %03d: %s\n", dev_idx, name); @@ -84,16 +84,16 @@ static int dump_one_trigger(const char *dev_dir_name) { char name[IIO_MAX_NAME_LENGTH]; int dev_idx; - int retval; + int ret; - retval = sscanf(dev_dir_name + strlen(iio_dir) + strlen(type_trigger), - "%i", &dev_idx); - if (retval != 1) + ret = sscanf(dev_dir_name + strlen(iio_dir) + strlen(type_trigger), + "%i", &dev_idx); + if (ret != 1) return -EINVAL; - retval = read_sysfs_string("name", dev_dir_name, name); - if (retval) - return retval; + ret = read_sysfs_string("name", dev_dir_name, name); + if (ret) + return ret; printf("Trigger %03d: %s\n", dev_idx, name); -- cgit v1.2.3 From ad37616e9048123ab664bf2064604888e25c539f Mon Sep 17 00:00:00 2001 From: Adriana Reus Date: Fri, 12 Jun 2015 19:01:07 +0300 Subject: iio: Documentation: Add additional *scale_available attributes Added some more *scale_available attributes to the list that are used in various drivers but were missiong from Documentation. Signed-off-by: Adriana Reus Signed-off-by: Jonathan Cameron --- Documentation/ABI/testing/sysfs-bus-iio | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index bbed111c31b4..666a341b01b8 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -413,6 +413,11 @@ Description: to compute the calories burnt by the user. What: /sys/bus/iio/devices/iio:deviceX/in_accel_scale_available +What: /sys/.../iio:deviceX/in_anglvel_scale_available +What: /sys/.../iio:deviceX/in_magn_scale_available +What: /sys/.../iio:deviceX/in_illuminance_scale_available +What: /sys/.../iio:deviceX/in_intensity_scale_available +What: /sys/.../iio:deviceX/in_proximity_scale_available What: /sys/.../iio:deviceX/in_voltageX_scale_available What: /sys/.../iio:deviceX/in_voltage-voltage_scale_available What: /sys/.../iio:deviceX/out_voltageX_scale_available -- cgit v1.2.3 From a858c7dab4b9b6a0b5742c39b10408780ca315c8 Mon Sep 17 00:00:00 2001 From: Adriana Reus Date: Fri, 12 Jun 2015 18:10:22 +0300 Subject: iio: inv-mpu: Export scale_available attributes Export the available scales for accel and gyro in order to hint the user-space as to what are the available valid values. Signed-off-by: Adriana Reus Signed-off-by: Jonathan Cameron --- drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c index 17d4bb15be4d..096e545538b8 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c @@ -673,6 +673,10 @@ static const struct iio_chan_spec inv_mpu_channels[] = { /* constant IIO attribute */ static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500"); +static IIO_CONST_ATTR(in_anglvel_scale_available, + "0.000133090 0.000266181 0.000532362 0.001064724"); +static IIO_CONST_ATTR(in_accel_scale_available, + "0.000598 0.001196 0.002392 0.004785"); static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show, inv_mpu6050_fifo_rate_store); static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL, @@ -685,6 +689,8 @@ static struct attribute *inv_attributes[] = { &iio_dev_attr_in_accel_matrix.dev_attr.attr, &iio_dev_attr_sampling_frequency.dev_attr.attr, &iio_const_attr_sampling_frequency_available.dev_attr.attr, + &iio_const_attr_in_accel_scale_available.dev_attr.attr, + &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, NULL, }; -- cgit v1.2.3 From 003f4880bd2eba68c6f9191607ce73787f3402bd Mon Sep 17 00:00:00 2001 From: Tiberiu Breana Date: Wed, 10 Jun 2015 18:07:29 +0300 Subject: iio: accel: STK8BA50: replace scale table with a struct Replaced the stk8ba50_scale_table with an identically named struct in order to make the code a bit more readable. Signed-off-by: Tiberiu Breana Signed-off-by: Jonathan Cameron --- drivers/iio/accel/stk8ba50.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/iio/accel/stk8ba50.c b/drivers/iio/accel/stk8ba50.c index 30950c6b36de..3302a3d1b4bf 100644 --- a/drivers/iio/accel/stk8ba50.c +++ b/drivers/iio/accel/stk8ba50.c @@ -50,7 +50,10 @@ * * Locally, the range is stored as a table index. */ -static const int stk8ba50_scale_table[][2] = { +static const struct { + u8 reg_val; + u32 scale_val; +} stk8ba50_scale_table[] = { {3, 38400}, {5, 76700}, {8, 153400}, {12, 306900} }; @@ -114,7 +117,7 @@ static int stk8ba50_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: *val = 0; - *val2 = stk8ba50_scale_table[data->range][1]; + *val2 = stk8ba50_scale_table[data->range].scale_val; return IIO_VAL_INT_PLUS_MICRO; } @@ -136,7 +139,7 @@ static int stk8ba50_write_raw(struct iio_dev *indio_dev, return -EINVAL; for (i = 0; i < ARRAY_SIZE(stk8ba50_scale_table); i++) - if (val2 == stk8ba50_scale_table[i][1]) { + if (val2 == stk8ba50_scale_table[i].scale_val) { index = i; break; } @@ -145,7 +148,7 @@ static int stk8ba50_write_raw(struct iio_dev *indio_dev, ret = i2c_smbus_write_byte_data(data->client, STK8BA50_REG_RANGE, - stk8ba50_scale_table[index][0]); + stk8ba50_scale_table[index].reg_val); if (ret < 0) dev_err(&data->client->dev, "failed to set measurement range\n"); -- cgit v1.2.3 From eb2c9ce2cc938d7d39fc06430519bf0fc5004566 Mon Sep 17 00:00:00 2001 From: Tiberiu Breana Date: Wed, 10 Jun 2015 18:07:30 +0300 Subject: iio: accel: Add sampling rate support for STK8BA50 Added support for setting the STK8BA50 accelerometer's sampling rate. Signed-off-by: Tiberiu Breana Signed-off-by: Jonathan Cameron --- drivers/iio/accel/stk8ba50.c | 57 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 50 insertions(+), 7 deletions(-) diff --git a/drivers/iio/accel/stk8ba50.c b/drivers/iio/accel/stk8ba50.c index 3302a3d1b4bf..92229bd8c82d 100644 --- a/drivers/iio/accel/stk8ba50.c +++ b/drivers/iio/accel/stk8ba50.c @@ -21,6 +21,7 @@ #define STK8BA50_REG_YOUT 0x04 #define STK8BA50_REG_ZOUT 0x06 #define STK8BA50_REG_RANGE 0x0F +#define STK8BA50_REG_BWSEL 0x10 #define STK8BA50_REG_POWMODE 0x11 #define STK8BA50_REG_SWRST 0x14 @@ -29,6 +30,7 @@ #define STK8BA50_MODE_POWERBIT BIT(7) #define STK8BA50_DATA_SHIFT 6 #define STK8BA50_RESET_CMD 0xB6 +#define STK8BA50_SR_1792HZ_IDX 7 #define STK8BA50_DRIVER_NAME "stk8ba50" @@ -57,19 +59,30 @@ static const struct { {3, 38400}, {5, 76700}, {8, 153400}, {12, 306900} }; +/* Sample rates are stored as { , } */ +static const struct { + u8 reg_val; + u16 samp_freq; +} stk8ba50_samp_freq_table[] = { + {0x08, 14}, {0x09, 25}, {0x0A, 56}, {0x0B, 112}, + {0x0C, 224}, {0x0D, 448}, {0x0E, 896}, {0x0F, 1792} +}; + struct stk8ba50_data { struct i2c_client *client; struct mutex lock; int range; + u8 sample_rate_idx; }; -#define STK8BA50_ACCEL_CHANNEL(reg, axis) { \ - .type = IIO_ACCEL, \ - .address = reg, \ - .modified = 1, \ - .channel2 = IIO_MOD_##axis, \ - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ +#define STK8BA50_ACCEL_CHANNEL(reg, axis) { \ + .type = IIO_ACCEL, \ + .address = reg, \ + .modified = 1, \ + .channel2 = IIO_MOD_##axis, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ } static const struct iio_chan_spec stk8ba50_channels[] = { @@ -80,8 +93,11 @@ static const struct iio_chan_spec stk8ba50_channels[] = { static IIO_CONST_ATTR(in_accel_scale_available, STK8BA50_SCALE_AVAIL); +static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("14 25 56 112 224 448 896 1792"); + static struct attribute *stk8ba50_attributes[] = { &iio_const_attr_in_accel_scale_available.dev_attr.attr, + &iio_const_attr_sampling_frequency_available.dev_attr.attr, NULL, }; @@ -119,6 +135,11 @@ static int stk8ba50_read_raw(struct iio_dev *indio_dev, *val = 0; *val2 = stk8ba50_scale_table[data->range].scale_val; return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_SAMP_FREQ: + *val = stk8ba50_samp_freq_table + [data->sample_rate_idx].samp_freq; + *val2 = 0; + return IIO_VAL_INT; } return -EINVAL; @@ -155,6 +176,25 @@ static int stk8ba50_write_raw(struct iio_dev *indio_dev, else data->range = index; + return ret; + case IIO_CHAN_INFO_SAMP_FREQ: + for (i = 0; i < ARRAY_SIZE(stk8ba50_samp_freq_table); i++) + if (val == stk8ba50_samp_freq_table[i].samp_freq) { + index = i; + break; + } + if (index < 0) + return -EINVAL; + + ret = i2c_smbus_write_byte_data(data->client, + STK8BA50_REG_BWSEL, + stk8ba50_samp_freq_table[index].reg_val); + if (ret < 0) + dev_err(&data->client->dev, + "failed to set sampling rate\n"); + else + data->sample_rate_idx = index; + return ret; } @@ -231,6 +271,9 @@ static int stk8ba50_probe(struct i2c_client *client, /* The default range is +/-2g */ data->range = 0; + /* The default sampling rate is 1792 Hz (maximum) */ + data->sample_rate_idx = STK8BA50_SR_1792HZ_IDX; + ret = iio_device_register(indio_dev); if (ret < 0) { dev_err(&client->dev, "device_register failed\n"); -- cgit v1.2.3 From ae35496230bc792fa76505ab7fcee694c7f7d523 Mon Sep 17 00:00:00 2001 From: Naidu Tellapati Date: Thu, 7 May 2015 18:24:02 -0300 Subject: iio: adc: cc10001: Power-up the ADC at probe time when used remotely The ADC is typically shared with remote CPUs not running Linux. However, there is only one register to power-up/power-down. Remote CPUs aren't able to power-up the ADC, and rely in Linux doing it instead. This commit uses the adc-reserved-channels devicetree property to distinguish shared usage. In this case, the ADC is powered up at probe time. If the ADC is used only by the CPU running Linux, power-up/down at runtime, only when neeeded. Signed-off-by: Naidu Tellapati Signed-off-by: Ezequiel Garcia Signed-off-by: Jonathan Cameron --- drivers/iio/adc/cc10001_adc.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/cc10001_adc.c b/drivers/iio/adc/cc10001_adc.c index 115f6e99a7fa..8254f529b2a9 100644 --- a/drivers/iio/adc/cc10001_adc.c +++ b/drivers/iio/adc/cc10001_adc.c @@ -62,6 +62,7 @@ struct cc10001_adc_device { struct regulator *reg; u16 *buf; + bool shared; struct mutex lock; unsigned int start_delay_ns; unsigned int eoc_delay_ns; @@ -153,7 +154,8 @@ static irqreturn_t cc10001_adc_trigger_h(int irq, void *p) mutex_lock(&adc_dev->lock); - cc10001_adc_power_up(adc_dev); + if (!adc_dev->shared) + cc10001_adc_power_up(adc_dev); /* Calculate delay step for eoc and sampled data */ delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT; @@ -177,7 +179,8 @@ static irqreturn_t cc10001_adc_trigger_h(int irq, void *p) } done: - cc10001_adc_power_down(adc_dev); + if (!adc_dev->shared) + cc10001_adc_power_down(adc_dev); mutex_unlock(&adc_dev->lock); @@ -196,7 +199,8 @@ static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev, unsigned int delay_ns; u16 val; - cc10001_adc_power_up(adc_dev); + if (!adc_dev->shared) + cc10001_adc_power_up(adc_dev); /* Calculate delay step for eoc and sampled data */ delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT; @@ -205,7 +209,8 @@ static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev, val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns); - cc10001_adc_power_down(adc_dev); + if (!adc_dev->shared) + cc10001_adc_power_down(adc_dev); return val; } @@ -322,8 +327,10 @@ static int cc10001_adc_probe(struct platform_device *pdev) adc_dev = iio_priv(indio_dev); channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0); - if (!of_property_read_u32(node, "adc-reserved-channels", &ret)) + if (!of_property_read_u32(node, "adc-reserved-channels", &ret)) { + adc_dev->shared = true; channel_map &= ~ret; + } adc_dev->reg = devm_regulator_get(&pdev->dev, "vref"); if (IS_ERR(adc_dev->reg)) @@ -368,6 +375,14 @@ static int cc10001_adc_probe(struct platform_device *pdev) adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate; adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES; + /* + * There is only one register to power-up/power-down the AUX ADC. + * If the ADC is shared among multiple CPUs, always power it up here. + * If the ADC is used only by the MIPS, power-up/power-down at runtime. + */ + if (adc_dev->shared) + cc10001_adc_power_up(adc_dev); + /* Setup the ADC channels available on the device */ ret = cc10001_adc_channel_init(indio_dev, channel_map); if (ret < 0) @@ -402,6 +417,7 @@ static int cc10001_adc_remove(struct platform_device *pdev) struct iio_dev *indio_dev = platform_get_drvdata(pdev); struct cc10001_adc_device *adc_dev = iio_priv(indio_dev); + cc10001_adc_power_down(adc_dev); iio_device_unregister(indio_dev); iio_triggered_buffer_cleanup(indio_dev); clk_disable_unprepare(adc_dev->adc_clk); -- cgit v1.2.3 From 1ca0259b18478b2bab6d5c81ca1de52dd519ae5e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 8 May 2015 15:54:00 -0300 Subject: iio: light: hid-sensor-prox: Fit assignment in one line There is no need to do the assignment to indio_dev->num_channels in two lines code. Put it in one line. Signed-off-by: Fabio Estevam Signed-off-by: Jonathan Cameron --- drivers/iio/light/hid-sensor-prox.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/iio/light/hid-sensor-prox.c b/drivers/iio/light/hid-sensor-prox.c index 0d248476f4c9..45ca056f019e 100644 --- a/drivers/iio/light/hid-sensor-prox.c +++ b/drivers/iio/light/hid-sensor-prox.c @@ -284,8 +284,7 @@ static int hid_prox_probe(struct platform_device *pdev) goto error_free_dev_mem; } - indio_dev->num_channels = - ARRAY_SIZE(prox_channels); + indio_dev->num_channels = ARRAY_SIZE(prox_channels); indio_dev->dev.parent = &pdev->dev; indio_dev->info = &prox_info; indio_dev->name = name; -- cgit v1.2.3 From c0d901cce736cb628d2e15f07ae00ea1029f64df Mon Sep 17 00:00:00 2001 From: Irina Tirdea Date: Mon, 13 Apr 2015 18:41:01 +0300 Subject: iio: accel: mma9551_core: use size in words for word buffers Change the prototype for the mma9551_read/write_*_words functions to receive the length of the buffer in words (instead of bytes) since we are using a word buffer. This will prevent users from sending an odd number of bytes for a word array. Signed-off-by: Irina Tirdea Signed-off-by: Jonathan Cameron --- drivers/iio/accel/mma9551_core.c | 27 ++++++++++++--------------- drivers/iio/accel/mma9553.c | 9 ++++++--- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/iio/accel/mma9551_core.c b/drivers/iio/accel/mma9551_core.c index 2fd2a995686b..583660b74f42 100644 --- a/drivers/iio/accel/mma9551_core.c +++ b/drivers/iio/accel/mma9551_core.c @@ -373,7 +373,7 @@ EXPORT_SYMBOL(mma9551_read_status_word); * @client: I2C client * @app_id: Application ID * @reg: Application register - * @len: Length of array to read in bytes + * @len: Length of array to read (in words) * @buf: Array of words to read * * Read multiple configuration registers (word-sized registers). @@ -388,20 +388,19 @@ int mma9551_read_config_words(struct i2c_client *client, u8 app_id, u16 reg, u8 len, u16 *buf) { int ret, i; - int len_words = len / sizeof(u16); __be16 be_buf[MMA9551_MAX_MAILBOX_DATA_REGS / 2]; - if (len_words > ARRAY_SIZE(be_buf)) { + if (len > ARRAY_SIZE(be_buf)) { dev_err(&client->dev, "Invalid buffer size %d\n", len); return -EINVAL; } ret = mma9551_transfer(client, app_id, MMA9551_CMD_READ_CONFIG, - reg, NULL, 0, (u8 *) be_buf, len); + reg, NULL, 0, (u8 *)be_buf, len * sizeof(u16)); if (ret < 0) return ret; - for (i = 0; i < len_words; i++) + for (i = 0; i < len; i++) buf[i] = be16_to_cpu(be_buf[i]); return 0; @@ -413,7 +412,7 @@ EXPORT_SYMBOL(mma9551_read_config_words); * @client: I2C client * @app_id: Application ID * @reg: Application register - * @len: Length of array to read in bytes + * @len: Length of array to read (in words) * @buf: Array of words to read * * Read multiple status registers (word-sized registers). @@ -428,20 +427,19 @@ int mma9551_read_status_words(struct i2c_client *client, u8 app_id, u16 reg, u8 len, u16 *buf) { int ret, i; - int len_words = len / sizeof(u16); __be16 be_buf[MMA9551_MAX_MAILBOX_DATA_REGS / 2]; - if (len_words > ARRAY_SIZE(be_buf)) { + if (len > ARRAY_SIZE(be_buf)) { dev_err(&client->dev, "Invalid buffer size %d\n", len); return -EINVAL; } ret = mma9551_transfer(client, app_id, MMA9551_CMD_READ_STATUS, - reg, NULL, 0, (u8 *) be_buf, len); + reg, NULL, 0, (u8 *)be_buf, len * sizeof(u16)); if (ret < 0) return ret; - for (i = 0; i < len_words; i++) + for (i = 0; i < len; i++) buf[i] = be16_to_cpu(be_buf[i]); return 0; @@ -453,7 +451,7 @@ EXPORT_SYMBOL(mma9551_read_status_words); * @client: I2C client * @app_id: Application ID * @reg: Application register - * @len: Length of array to write in bytes + * @len: Length of array to write (in words) * @buf: Array of words to write * * Write multiple configuration registers (word-sized registers). @@ -468,19 +466,18 @@ int mma9551_write_config_words(struct i2c_client *client, u8 app_id, u16 reg, u8 len, u16 *buf) { int i; - int len_words = len / sizeof(u16); __be16 be_buf[(MMA9551_MAX_MAILBOX_DATA_REGS - 1) / 2]; - if (len_words > ARRAY_SIZE(be_buf)) { + if (len > ARRAY_SIZE(be_buf)) { dev_err(&client->dev, "Invalid buffer size %d\n", len); return -EINVAL; } - for (i = 0; i < len_words; i++) + for (i = 0; i < len; i++) be_buf[i] = cpu_to_be16(buf[i]); return mma9551_transfer(client, app_id, MMA9551_CMD_WRITE_CONFIG, - reg, (u8 *) be_buf, len, NULL, 0); + reg, (u8 *)be_buf, len * sizeof(u16), NULL, 0); } EXPORT_SYMBOL(mma9551_write_config_words); diff --git a/drivers/iio/accel/mma9553.c b/drivers/iio/accel/mma9553.c index 8bfc61824fb2..06c870789383 100644 --- a/drivers/iio/accel/mma9553.c +++ b/drivers/iio/accel/mma9553.c @@ -322,7 +322,8 @@ static int mma9553_read_activity_stepcnt(struct mma9553_data *data, int ret; ret = mma9551_read_status_words(data->client, MMA9551_APPID_PEDOMETER, - MMA9553_REG_STATUS, sizeof(u32), buf); + MMA9553_REG_STATUS, ARRAY_SIZE(buf), + buf); if (ret < 0) { dev_err(&data->client->dev, "error reading status and stepcnt\n"); @@ -397,7 +398,8 @@ static int mma9553_init(struct mma9553_data *data) ret = mma9551_read_config_words(data->client, MMA9551_APPID_PEDOMETER, MMA9553_REG_CONF_SLEEPMIN, - sizeof(data->conf), (u16 *) &data->conf); + sizeof(data->conf) / sizeof(u16), + (u16 *)&data->conf); if (ret < 0) { dev_err(&data->client->dev, "failed to read configuration registers\n"); @@ -430,7 +432,8 @@ static int mma9553_init(struct mma9553_data *data) ret = mma9551_write_config_words(data->client, MMA9551_APPID_PEDOMETER, MMA9553_REG_CONF_SLEEPMIN, - sizeof(data->conf), (u16 *) &data->conf); + sizeof(data->conf) / sizeof(u16), + (u16 *)&data->conf); if (ret < 0) { dev_err(&data->client->dev, "failed to write configuration registers\n"); -- cgit v1.2.3 From b37c19903a64951f12ae213ce0be7ca3bd26cc12 Mon Sep 17 00:00:00 2001 From: Irina Tirdea Date: Mon, 13 Apr 2015 18:41:02 +0300 Subject: iio: accel: mma9553: fix alignment issues Fix code alignment and wrap parameters. Fix issues reported by checkpatch.pl --strict. Signed-off-by: Irina Tirdea Suggested-by: Hartmut Knaack Signed-off-by: Jonathan Cameron --- drivers/iio/accel/mma9551_core.c | 8 ++--- drivers/iio/accel/mma9551_core.h | 6 ++-- drivers/iio/accel/mma9553.c | 76 +++++++++++++++++++--------------------- 3 files changed, 43 insertions(+), 47 deletions(-) diff --git a/drivers/iio/accel/mma9551_core.c b/drivers/iio/accel/mma9551_core.c index 583660b74f42..c34c5ce8123b 100644 --- a/drivers/iio/accel/mma9551_core.c +++ b/drivers/iio/accel/mma9551_core.c @@ -297,7 +297,7 @@ EXPORT_SYMBOL(mma9551_read_status_byte); * Returns: 0 on success, negative value on failure. */ int mma9551_read_config_word(struct i2c_client *client, u8 app_id, - u16 reg, u16 *val) + u16 reg, u16 *val) { int ret; __be16 v; @@ -328,12 +328,12 @@ EXPORT_SYMBOL(mma9551_read_config_word); * Returns: 0 on success, negative value on failure. */ int mma9551_write_config_word(struct i2c_client *client, u8 app_id, - u16 reg, u16 val) + u16 reg, u16 val) { __be16 v = cpu_to_be16(val); return mma9551_transfer(client, app_id, MMA9551_CMD_WRITE_CONFIG, reg, - (u8 *) &v, 2, NULL, 0); + (u8 *)&v, 2, NULL, 0); } EXPORT_SYMBOL(mma9551_write_config_word); @@ -385,7 +385,7 @@ EXPORT_SYMBOL(mma9551_read_status_word); * Returns: 0 on success, negative value on failure. */ int mma9551_read_config_words(struct i2c_client *client, u8 app_id, - u16 reg, u8 len, u16 *buf) + u16 reg, u8 len, u16 *buf) { int ret, i; __be16 be_buf[MMA9551_MAX_MAILBOX_DATA_REGS / 2]; diff --git a/drivers/iio/accel/mma9551_core.h b/drivers/iio/accel/mma9551_core.h index 79939e40805a..5e88e6454dfd 100644 --- a/drivers/iio/accel/mma9551_core.h +++ b/drivers/iio/accel/mma9551_core.h @@ -53,13 +53,13 @@ int mma9551_write_config_byte(struct i2c_client *client, u8 app_id, int mma9551_read_status_byte(struct i2c_client *client, u8 app_id, u16 reg, u8 *val); int mma9551_read_config_word(struct i2c_client *client, u8 app_id, - u16 reg, u16 *val); + u16 reg, u16 *val); int mma9551_write_config_word(struct i2c_client *client, u8 app_id, - u16 reg, u16 val); + u16 reg, u16 val); int mma9551_read_status_word(struct i2c_client *client, u8 app_id, u16 reg, u16 *val); int mma9551_read_config_words(struct i2c_client *client, u8 app_id, - u16 reg, u8 len, u16 *buf); + u16 reg, u8 len, u16 *buf); int mma9551_read_status_words(struct i2c_client *client, u8 app_id, u16 reg, u8 len, u16 *buf); int mma9551_write_config_words(struct i2c_client *client, u8 app_id, diff --git a/drivers/iio/accel/mma9553.c b/drivers/iio/accel/mma9553.c index 06c870789383..08f28c3eb6cc 100644 --- a/drivers/iio/accel/mma9553.c +++ b/drivers/iio/accel/mma9553.c @@ -343,10 +343,10 @@ static int mma9553_conf_gpio(struct mma9553_data *data) struct mma9553_event *ev_step_detect; bool activity_enabled; - activity_enabled = - mma9553_is_any_event_enabled(data, true, IIO_ACTIVITY); - ev_step_detect = - mma9553_get_event(data, IIO_STEPS, IIO_NO_MOD, IIO_EV_DIR_NONE); + activity_enabled = mma9553_is_any_event_enabled(data, true, + IIO_ACTIVITY); + ev_step_detect = mma9553_get_event(data, IIO_STEPS, IIO_NO_MOD, + IIO_EV_DIR_NONE); /* * If both step detector and activity are enabled, use the MRGFL bit. @@ -372,9 +372,8 @@ static int mma9553_conf_gpio(struct mma9553_data *data) return ret; } - ret = mma9551_gpio_config(data->client, - MMA9553_DEFAULT_GPIO_PIN, - appid, bitnum, MMA9553_DEFAULT_GPIO_POLARITY); + ret = mma9551_gpio_config(data->client, MMA9553_DEFAULT_GPIO_PIN, appid, + bitnum, MMA9553_DEFAULT_GPIO_POLARITY); if (ret < 0) return ret; data->gpio_bitnum = bitnum; @@ -395,18 +394,16 @@ static int mma9553_init(struct mma9553_data *data) * a device identification command to differentiate the MMA9553L * from the MMA9550L. */ - ret = - mma9551_read_config_words(data->client, MMA9551_APPID_PEDOMETER, - MMA9553_REG_CONF_SLEEPMIN, - sizeof(data->conf) / sizeof(u16), - (u16 *)&data->conf); + ret = mma9551_read_config_words(data->client, MMA9551_APPID_PEDOMETER, + MMA9553_REG_CONF_SLEEPMIN, + sizeof(data->conf) / sizeof(u16), + (u16 *)&data->conf); if (ret < 0) { dev_err(&data->client->dev, "failed to read configuration registers\n"); return ret; } - /* Reset GPIO */ data->gpio_bitnum = MMA9553_MAX_BITNUM; ret = mma9553_conf_gpio(data); @@ -421,19 +418,18 @@ static int mma9553_init(struct mma9553_data *data) data->conf.sleepmin = MMA9553_DEFAULT_SLEEPMIN; data->conf.sleepmax = MMA9553_DEFAULT_SLEEPMAX; data->conf.sleepthd = MMA9553_DEFAULT_SLEEPTHD; - data->conf.config = - mma9553_set_bits(data->conf.config, 1, MMA9553_MASK_CONF_CONFIG); + data->conf.config = mma9553_set_bits(data->conf.config, 1, + MMA9553_MASK_CONF_CONFIG); /* * Clear the activity debounce counter when the activity level changes, * so that the confidence level applies for any activity level. */ data->conf.config = mma9553_set_bits(data->conf.config, 1, MMA9553_MASK_CONF_ACT_DBCNTM); - ret = - mma9551_write_config_words(data->client, MMA9551_APPID_PEDOMETER, - MMA9553_REG_CONF_SLEEPMIN, - sizeof(data->conf) / sizeof(u16), - (u16 *)&data->conf); + ret = mma9551_write_config_words(data->client, MMA9551_APPID_PEDOMETER, + MMA9553_REG_CONF_SLEEPMIN, + sizeof(data->conf) / sizeof(u16), + (u16 *)&data->conf); if (ret < 0) { dev_err(&data->client->dev, "failed to write configuration registers\n"); @@ -570,7 +566,7 @@ static int mma9553_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; case IIO_CHAN_INFO_CALIBHEIGHT: tmp = mma9553_get_bits(data->conf.height_weight, - MMA9553_MASK_CONF_HEIGHT); + MMA9553_MASK_CONF_HEIGHT); *val = tmp / 100; /* cm to m */ *val2 = (tmp % 100) * 10000; return IIO_VAL_INT_PLUS_MICRO; @@ -722,7 +718,6 @@ static int mma9553_read_event_config(struct iio_dev *indio_dev, enum iio_event_type type, enum iio_event_direction dir) { - struct mma9553_data *data = iio_priv(indio_dev); struct mma9553_event *event; @@ -1029,22 +1024,22 @@ static irqreturn_t mma9553_event_handler(int irq, void *private) return IRQ_HANDLED; } - ev_prev_activity = - mma9553_get_event(data, IIO_ACTIVITY, - mma9553_activity_to_mod(data->activity), - IIO_EV_DIR_FALLING); - ev_activity = - mma9553_get_event(data, IIO_ACTIVITY, - mma9553_activity_to_mod(activity), - IIO_EV_DIR_RISING); - ev_step_detect = - mma9553_get_event(data, IIO_STEPS, IIO_NO_MOD, IIO_EV_DIR_NONE); + ev_prev_activity = mma9553_get_event(data, IIO_ACTIVITY, + mma9553_activity_to_mod( + data->activity), + IIO_EV_DIR_FALLING); + ev_activity = mma9553_get_event(data, IIO_ACTIVITY, + mma9553_activity_to_mod(activity), + IIO_EV_DIR_RISING); + ev_step_detect = mma9553_get_event(data, IIO_STEPS, IIO_NO_MOD, + IIO_EV_DIR_NONE); if (ev_step_detect->enabled && (stepcnt != data->stepcnt)) { data->stepcnt = stepcnt; iio_push_event(indio_dev, IIO_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD, - IIO_EV_DIR_NONE, IIO_EV_TYPE_CHANGE, 0, 0, 0), + IIO_EV_DIR_NONE, + IIO_EV_TYPE_CHANGE, 0, 0, 0), data->timestamp); } @@ -1054,17 +1049,19 @@ static irqreturn_t mma9553_event_handler(int irq, void *private) if (ev_prev_activity && ev_prev_activity->enabled) iio_push_event(indio_dev, IIO_EVENT_CODE(IIO_ACTIVITY, 0, - ev_prev_activity->info->mod, - IIO_EV_DIR_FALLING, - IIO_EV_TYPE_THRESH, 0, 0, 0), + ev_prev_activity->info->mod, + IIO_EV_DIR_FALLING, + IIO_EV_TYPE_THRESH, 0, 0, + 0), data->timestamp); if (ev_activity && ev_activity->enabled) iio_push_event(indio_dev, IIO_EVENT_CODE(IIO_ACTIVITY, 0, - ev_activity->info->mod, - IIO_EV_DIR_RISING, - IIO_EV_TYPE_THRESH, 0, 0, 0), + ev_activity->info->mod, + IIO_EV_DIR_RISING, + IIO_EV_TYPE_THRESH, 0, 0, + 0), data->timestamp); } mutex_unlock(&data->mutex); @@ -1159,7 +1156,6 @@ static int mma9553_probe(struct i2c_client *client, client->irq); goto out_poweroff; } - } ret = iio_device_register(indio_dev); -- cgit v1.2.3 From 23f93cde93efed59ca82d2687a2fab6a93eaafcc Mon Sep 17 00:00:00 2001 From: Irina Tirdea Date: Mon, 13 Apr 2015 18:41:03 +0300 Subject: iio: accel: mma9553: document use of mutex Fix checkpatch.pl --strict check: CHECK: struct mutex definition without comment + struct mutex mutex; Signed-off-by: Irina Tirdea Signed-off-by: Jonathan Cameron --- drivers/iio/accel/mma9553.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/iio/accel/mma9553.c b/drivers/iio/accel/mma9553.c index 08f28c3eb6cc..a605280637e9 100644 --- a/drivers/iio/accel/mma9553.c +++ b/drivers/iio/accel/mma9553.c @@ -182,6 +182,10 @@ struct mma9553_conf_regs { struct mma9553_data { struct i2c_client *client; + /* + * 1. Serialize access to HW (requested by mma9551_core API). + * 2. Serialize sequences that power on/off the device and access HW. + */ struct mutex mutex; struct mma9553_conf_regs conf; struct mma9553_event events[MMA9553_EVENTS_INFO_SIZE]; -- cgit v1.2.3 From 4b8d80157e5d9074c5eac12aff8dad1742b52f1c Mon Sep 17 00:00:00 2001 From: Peter Meerwald Date: Sat, 20 Jun 2015 23:52:30 +0200 Subject: iio: Add missing modifier names to core some are documented, others are in iio_event_monitor.c which was recently moved from staging Signed-off-by: Peter Meerwald Signed-off-by: Jonathan Cameron --- drivers/iio/industrialio-core.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 3524b0de8721..d8051cdcbdc2 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -81,6 +81,14 @@ static const char * const iio_modifier_names[] = { [IIO_MOD_X] = "x", [IIO_MOD_Y] = "y", [IIO_MOD_Z] = "z", + [IIO_MOD_X_AND_Y] = "x&y", + [IIO_MOD_X_AND_Z] = "x&z", + [IIO_MOD_Y_AND_Z] = "y&z", + [IIO_MOD_X_AND_Y_AND_Z] = "x&y&z", + [IIO_MOD_X_OR_Y] = "x|y", + [IIO_MOD_X_OR_Z] = "x|z", + [IIO_MOD_Y_OR_Z] = "y|z", + [IIO_MOD_X_OR_Y_OR_Z] = "x|y|z", [IIO_MOD_ROOT_SUM_SQUARED_X_Y] = "sqrt(x^2+y^2)", [IIO_MOD_SUM_SQUARED_X_Y_Z] = "x^2+y^2+z^2", [IIO_MOD_LIGHT_BOTH] = "both", -- cgit v1.2.3 From 30e8326728fff4c66377bd3ba99266cf8489c915 Mon Sep 17 00:00:00 2001 From: Peter Meerwald Date: Sat, 20 Jun 2015 23:52:31 +0200 Subject: tools: iio: Add missing names to iio_event_monitor Signed-off-by: Peter Meerwald Signed-off-by: Jonathan Cameron --- tools/iio/iio_event_monitor.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tools/iio/iio_event_monitor.c b/tools/iio/iio_event_monitor.c index a4ab6bb8f872..1dba09062a64 100644 --- a/tools/iio/iio_event_monitor.c +++ b/tools/iio/iio_event_monitor.c @@ -50,6 +50,9 @@ static const char * const iio_chan_type_name_spec[] = { [IIO_HUMIDITYRELATIVE] = "humidityrelative", [IIO_ACTIVITY] = "activity", [IIO_STEPS] = "steps", + [IIO_ENERGY] = "energy", + [IIO_DISTANCE] = "distance", + [IIO_VELOCITY] = "velocity", }; static const char * const iio_ev_type_text[] = { @@ -98,6 +101,7 @@ static const char * const iio_modifier_names[] = { [IIO_MOD_JOGGING] = "jogging", [IIO_MOD_WALKING] = "walking", [IIO_MOD_STILL] = "still", + [IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z] = "sqrt(x^2+y^2+z^2)", }; static bool event_is_known(struct iio_event_data *event) @@ -129,6 +133,9 @@ static bool event_is_known(struct iio_event_data *event) case IIO_HUMIDITYRELATIVE: case IIO_ACTIVITY: case IIO_STEPS: + case IIO_ENERGY: + case IIO_DISTANCE: + case IIO_VELOCITY: break; default: return false; @@ -166,6 +173,7 @@ static bool event_is_known(struct iio_event_data *event) case IIO_MOD_JOGGING: case IIO_MOD_WALKING: case IIO_MOD_STILL: + case IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z: break; default: return false; -- cgit v1.2.3 From 208335138001015fd7c5c986b39e05fffad1c528 Mon Sep 17 00:00:00 2001 From: Peter Meerwald Date: Sat, 20 Jun 2015 23:51:38 +0200 Subject: iio: light: isl29125: Add scale_available information Signed-off-by: Peter Meerwald Signed-off-by: Jonathan Cameron --- drivers/iio/light/isl29125.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/iio/light/isl29125.c b/drivers/iio/light/isl29125.c index c82f4a6f8464..b3cbbe830141 100644 --- a/drivers/iio/light/isl29125.c +++ b/drivers/iio/light/isl29125.c @@ -197,9 +197,21 @@ done: return IRQ_HANDLED; } +static IIO_CONST_ATTR(scale_available, "0.005722 0.152590"); + +static struct attribute *isl29125_attributes[] = { + &iio_const_attr_scale_available.dev_attr.attr, + NULL +}; + +static const struct attribute_group isl29125_attribute_group = { + .attrs = isl29125_attributes, +}; + static const struct iio_info isl29125_info = { .read_raw = isl29125_read_raw, .write_raw = isl29125_write_raw, + .attrs = &isl29125_attribute_group, .driver_module = THIS_MODULE, }; -- cgit v1.2.3 From db42a9be9f05516255e749a5ee4c1e5d07e0a73b Mon Sep 17 00:00:00 2001 From: Tiberiu Breana Date: Fri, 19 Jun 2015 17:56:37 +0300 Subject: iio: accel: STK8BA50: suspend sensor on init errors Put chip in 'suspend' mode in case something goes wrong during probe. Signed-off-by: Tiberiu Breana Signed-off-by: Jonathan Cameron --- drivers/iio/accel/stk8ba50.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/iio/accel/stk8ba50.c b/drivers/iio/accel/stk8ba50.c index 92229bd8c82d..9836880cc2d1 100644 --- a/drivers/iio/accel/stk8ba50.c +++ b/drivers/iio/accel/stk8ba50.c @@ -265,7 +265,7 @@ static int stk8ba50_probe(struct i2c_client *client, STK8BA50_REG_SWRST, STK8BA50_RESET_CMD); if (ret < 0) { dev_err(&client->dev, "failed to reset sensor\n"); - return ret; + goto err_power_off; } /* The default range is +/-2g */ @@ -277,10 +277,14 @@ static int stk8ba50_probe(struct i2c_client *client, ret = iio_device_register(indio_dev); if (ret < 0) { dev_err(&client->dev, "device_register failed\n"); - stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND); + goto err_power_off; } return ret; + +err_power_off: + stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND); + return ret; } static int stk8ba50_remove(struct i2c_client *client) -- cgit v1.2.3 From 39b441bd30a9eff4b3d2cc039027037403ca5242 Mon Sep 17 00:00:00 2001 From: Hartmut Knaack Date: Thu, 18 Jun 2015 00:32:00 +0200 Subject: iio:light:Kconfig: fix typo in description Fix the typo in the module description for the CM3323. Signed-off-by: Hartmut Knaack Reviewed-by: Daniel Baluta Signed-off-by: Jonathan Cameron --- drivers/iio/light/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/light/Kconfig b/drivers/iio/light/Kconfig index e6198b7c9cbf..554f8ee6d64a 100644 --- a/drivers/iio/light/Kconfig +++ b/drivers/iio/light/Kconfig @@ -86,7 +86,7 @@ config CM3323 depends on I2C tristate "Capella CM3323 color light sensor" help - Say Y here if you want to build a driver for Capela CM3323 + Say Y here if you want to build a driver for Capella CM3323 color sensor. To compile this driver as a module, choose M here: the module will -- cgit v1.2.3 From e5c97027449f235415990310e47071ec371fd46c Mon Sep 17 00:00:00 2001 From: Hartmut Knaack Date: Thu, 18 Jun 2015 00:32:01 +0200 Subject: iio:light:cm3323: pass up error value cm3323_get_it_bits() returns a valid error code, so pass it up in cm3323_read_raw(). Signed-off-by: Hartmut Knaack Reviewed-by: Daniel Baluta Signed-off-by: Jonathan Cameron --- drivers/iio/light/cm3323.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/light/cm3323.c b/drivers/iio/light/cm3323.c index 869033e48a1f..9c9136309ffe 100644 --- a/drivers/iio/light/cm3323.c +++ b/drivers/iio/light/cm3323.c @@ -175,7 +175,7 @@ static int cm3323_read_raw(struct iio_dev *indio_dev, i = cm3323_get_it_bits(data); if (i < 0) { mutex_unlock(&data->mutex); - return -EINVAL; + return i; } *val = cm3323_int_time[i].val; -- cgit v1.2.3 From 0ff8c78df8d7c32394b887de4d935962a7f373ce Mon Sep 17 00:00:00 2001 From: Hartmut Knaack Date: Thu, 18 Jun 2015 00:32:03 +0200 Subject: iio:light:cm3323: replace unneeded variable In cm3323_read_raw() i is used as return variable for the integration time index. The also existing return variable ret however is unused in this case, although appropriate. Replace i with ret and drop it. Signed-off-by: Hartmut Knaack Reviewed-by: Daniel Baluta Signed-off-by: Jonathan Cameron --- drivers/iio/light/cm3323.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/iio/light/cm3323.c b/drivers/iio/light/cm3323.c index 9c9136309ffe..af1b1b025258 100644 --- a/drivers/iio/light/cm3323.c +++ b/drivers/iio/light/cm3323.c @@ -155,7 +155,7 @@ static int cm3323_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { - int i, ret; + int ret; struct cm3323_data *data = iio_priv(indio_dev); switch (mask) { @@ -172,14 +172,14 @@ static int cm3323_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; case IIO_CHAN_INFO_INT_TIME: mutex_lock(&data->mutex); - i = cm3323_get_it_bits(data); - if (i < 0) { + ret = cm3323_get_it_bits(data); + if (ret < 0) { mutex_unlock(&data->mutex); - return i; + return ret; } - *val = cm3323_int_time[i].val; - *val2 = cm3323_int_time[i].val2; + *val = cm3323_int_time[ret].val; + *val2 = cm3323_int_time[ret].val2; mutex_unlock(&data->mutex); return IIO_VAL_INT_PLUS_MICRO; -- cgit v1.2.3 From 054101c186b9e41d2b57543070c4a520d38402da Mon Sep 17 00:00:00 2001 From: Hartmut Knaack Date: Thu, 18 Jun 2015 00:32:04 +0200 Subject: iio:light:cm3323: make use of GENMASK Use GENMASK to define the integration time bitmask. Signed-off-by: Hartmut Knaack Signed-off-by: Jonathan Cameron --- drivers/iio/light/cm3323.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/light/cm3323.c b/drivers/iio/light/cm3323.c index af1b1b025258..57ff0a10890e 100644 --- a/drivers/iio/light/cm3323.c +++ b/drivers/iio/light/cm3323.c @@ -29,7 +29,7 @@ #define CM3323_CONF_SD_BIT BIT(0) /* sensor disable */ #define CM3323_CONF_AF_BIT BIT(1) /* auto/manual force mode */ -#define CM3323_CONF_IT_MASK (BIT(4) | BIT(5) | BIT(6)) +#define CM3323_CONF_IT_MASK GENMASK(6, 4) #define CM3323_CONF_IT_SHIFT 4 #define CM3323_INT_TIME_AVAILABLE "0.04 0.08 0.16 0.32 0.64 1.28" -- cgit v1.2.3 From 8bf62ec83c89eda4114aae90c593f49649af76bd Mon Sep 17 00:00:00 2001 From: Hartmut Knaack Date: Thu, 18 Jun 2015 00:32:05 +0200 Subject: iio:light:cm3323: add empty lines for code structure Add some empty lines to visually separate logical structure blocks, as after if-blocks or before regular returns. Signed-off-by: Hartmut Knaack Reviewed-by: Daniel Baluta Signed-off-by: Jonathan Cameron --- drivers/iio/light/cm3323.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/iio/light/cm3323.c b/drivers/iio/light/cm3323.c index 57ff0a10890e..54c9e2df43f2 100644 --- a/drivers/iio/light/cm3323.c +++ b/drivers/iio/light/cm3323.c @@ -133,9 +133,11 @@ static int cm3323_set_it_bits(struct cm3323_data *data, int val, int val2) return ret; data->reg_conf = reg_conf; + return 0; } } + return -EINVAL; } @@ -148,6 +150,7 @@ static int cm3323_get_it_bits(struct cm3323_data *data) if (bits >= ARRAY_SIZE(cm3323_int_time)) return -EINVAL; + return bits; } @@ -243,11 +246,13 @@ static int cm3323_probe(struct i2c_client *client, dev_err(&client->dev, "cm3323 chip init failed\n"); return ret; } + ret = iio_device_register(indio_dev); if (ret < 0) { dev_err(&client->dev, "failed to register iio dev\n"); goto err_init; } + return 0; err_init: cm3323_disable(indio_dev); -- cgit v1.2.3 From 825c50dba0139b0322436ddda7d11f043955875e Mon Sep 17 00:00:00 2001 From: Peter Meerwald Date: Tue, 16 Jun 2015 21:27:03 +0200 Subject: iio: pressure: Fix Measurement Specialties vendor name Signed-off-by: Peter Meerwald Signed-off-by: Jonathan Cameron --- drivers/iio/pressure/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/pressure/Kconfig b/drivers/iio/pressure/Kconfig index fa6295041947..b13ea6fd939d 100644 --- a/drivers/iio/pressure/Kconfig +++ b/drivers/iio/pressure/Kconfig @@ -53,9 +53,9 @@ config MPL3115 will be called mpl3115. config MS5611 - tristate "Measurement Specialities MS5611 pressure sensor driver" + tristate "Measurement Specialties MS5611 pressure sensor driver" help - Say Y here to build support for the Measurement Specialities + Say Y here to build support for the Measurement Specialties MS5611 pressure and temperature sensor. To compile this driver as a module, choose M here: the module will -- cgit v1.2.3 From fdd15f6594f6bc466a01da28ddd2f11bb0e47a9f Mon Sep 17 00:00:00 2001 From: Hartmut Knaack Date: Mon, 15 Jun 2015 23:48:25 +0200 Subject: iio:accel:bmc150-accel: make use of mask definition BMC150_ACCEL_SLOPE_THRES_MASK was defined some time ago, but its 'magic' value got used instead in bmc150_accel_write_event(). Make use of it for improved readability. Signed-off-by: Hartmut Knaack Reviewed-by: Octavian Purdila Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bmc150-accel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/accel/bmc150-accel.c b/drivers/iio/accel/bmc150-accel.c index 4e70f51c2370..b812728b438e 100644 --- a/drivers/iio/accel/bmc150-accel.c +++ b/drivers/iio/accel/bmc150-accel.c @@ -776,7 +776,7 @@ static int bmc150_accel_write_event(struct iio_dev *indio_dev, switch (info) { case IIO_EV_INFO_VALUE: - data->slope_thres = val & 0xFF; + data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK; break; case IIO_EV_INFO_PERIOD: data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK; -- cgit v1.2.3 From e20008ed931b9bdd90d1a3fd8c9ef9307547f4ed Mon Sep 17 00:00:00 2001 From: Hartmut Knaack Date: Mon, 15 Jun 2015 23:48:26 +0200 Subject: iio:accel:bmc150-accel: code style cleanup Apply the following coding style changes as indicated by checkpatch.pl in strict mode: - Please don't use multiple blank lines - braces {} should be used on all arms of this statement (if/else) - Alignment should match open parenthesis - Please don't use multiple blank lines - Blank lines aren't necessary after an open brace '{' - Missing a blank line after declarations - No space is necessary after a cast Also wrap/consolidate error messages to fit 80 characters per line and rework a comment. Signed-off-by: Hartmut Knaack Reviewed-by: Octavian Purdila Signed-off-by: Jonathan Cameron --- drivers/iio/accel/bmc150-accel.c | 91 +++++++++++++++++++++------------------- 1 file changed, 49 insertions(+), 42 deletions(-) diff --git a/drivers/iio/accel/bmc150-accel.c b/drivers/iio/accel/bmc150-accel.c index b812728b438e..47c6013ab376 100644 --- a/drivers/iio/accel/bmc150-accel.c +++ b/drivers/iio/accel/bmc150-accel.c @@ -241,7 +241,6 @@ static const struct { {500000, BMC150_ACCEL_SLEEP_500_MS}, {1000000, BMC150_ACCEL_SLEEP_1_SEC} }; - static int bmc150_accel_set_mode(struct bmc150_accel_data *data, enum bmc150_power_modes mode, int dur_us) @@ -259,8 +258,9 @@ static int bmc150_accel_set_mode(struct bmc150_accel_data *data, dur_val = bmc150_accel_sleep_value_table[i].reg_value; } - } else + } else { dur_val = 0; + } if (dur_val < 0) return -EINVAL; @@ -288,7 +288,7 @@ static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val, for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { if (bmc150_accel_samp_freq_table[i].val == val && - bmc150_accel_samp_freq_table[i].val2 == val2) { + bmc150_accel_samp_freq_table[i].val2 == val2) { ret = i2c_smbus_write_byte_data( data->client, BMC150_ACCEL_REG_PMU_BW, @@ -351,8 +351,7 @@ static int bmc150_accel_chip_init(struct bmc150_accel_data *data) ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_CHIP_ID); if (ret < 0) { - dev_err(&data->client->dev, - "Error: Reading chip id\n"); + dev_err(&data->client->dev, "Error: Reading chip id\n"); return ret; } @@ -376,8 +375,7 @@ static int bmc150_accel_chip_init(struct bmc150_accel_data *data) BMC150_ACCEL_REG_PMU_RANGE, BMC150_ACCEL_DEF_RANGE_4G); if (ret < 0) { - dev_err(&data->client->dev, - "Error writing reg_pmu_range\n"); + dev_err(&data->client->dev, "Error writing reg_pmu_range\n"); return ret; } @@ -437,12 +435,13 @@ static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) { int ret; - if (on) + if (on) { ret = pm_runtime_get_sync(&data->client->dev); - else { + } else { pm_runtime_mark_last_busy(&data->client->dev); ret = pm_runtime_put_autosuspend(&data->client->dev); } + if (ret < 0) { dev_err(&data->client->dev, "Failed: bmc150_accel_set_power_state for %d\n", on); @@ -514,13 +513,13 @@ static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i, } /* - * We will expect the enable and disable to do operation in - * in reverse order. This will happen here anyway as our - * resume operation uses sync mode runtime pm calls, the - * suspend operation will be delayed by autosuspend delay - * So the disable operation will still happen in reverse of - * enable operation. When runtime pm is disabled the mode - * is always on so sequence doesn't matter + * We will expect the enable and disable to do operation in reverse + * order. This will happen here anyway, as our resume operation uses + * sync mode runtime pm calls. The suspend operation will be delayed + * by autosuspend delay. + * So the disable operation will still happen in reverse order of + * enable operation. When runtime pm is disabled the mode is always on, + * so sequence doesn't matter. */ ret = bmc150_accel_set_power_state(data, state); if (ret < 0) @@ -574,7 +573,6 @@ out_fix_power_state: return ret; } - static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val) { int ret, i; @@ -674,8 +672,9 @@ static int bmc150_accel_read_raw(struct iio_dev *indio_dev, if (chan->type == IIO_TEMP) { *val = BMC150_ACCEL_TEMP_CENTER_VAL; return IIO_VAL_INT; - } else + } else { return -EINVAL; + } case IIO_CHAN_INFO_SCALE: *val = 0; switch (chan->type) { @@ -793,7 +792,6 @@ static int bmc150_accel_read_event_config(struct iio_dev *indio_dev, enum iio_event_type type, enum iio_event_direction dir) { - struct bmc150_accel_data *data = iio_priv(indio_dev); return data->ev_enable_state; @@ -827,7 +825,7 @@ static int bmc150_accel_write_event_config(struct iio_dev *indio_dev, } static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev, - struct iio_trigger *trig) + struct iio_trigger *trig) { struct bmc150_accel_data *data = iio_priv(indio_dev); int i; @@ -963,6 +961,7 @@ static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev, u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3]; int64_t tstamp; uint64_t sample_period; + ret = i2c_smbus_read_byte_data(data->client, BMC150_ACCEL_REG_FIFO_STATUS); if (ret < 0) { @@ -1255,7 +1254,7 @@ static int bmc150_accel_trig_try_reen(struct iio_trigger *trig) } static int bmc150_accel_trigger_set_state(struct iio_trigger *trig, - bool state) + bool state) { struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); struct bmc150_accel_data *data = t->data; @@ -1314,26 +1313,32 @@ static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev) dir = IIO_EV_DIR_RISING; if (ret & BMC150_ACCEL_ANY_MOTION_BIT_X) - iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, - 0, - IIO_MOD_X, - IIO_EV_TYPE_ROC, - dir), - data->timestamp); + iio_push_event(indio_dev, + IIO_MOD_EVENT_CODE(IIO_ACCEL, + 0, + IIO_MOD_X, + IIO_EV_TYPE_ROC, + dir), + data->timestamp); + if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Y) - iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, - 0, - IIO_MOD_Y, - IIO_EV_TYPE_ROC, - dir), - data->timestamp); + iio_push_event(indio_dev, + IIO_MOD_EVENT_CODE(IIO_ACCEL, + 0, + IIO_MOD_Y, + IIO_EV_TYPE_ROC, + dir), + data->timestamp); + if (ret & BMC150_ACCEL_ANY_MOTION_BIT_Z) - iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, - 0, - IIO_MOD_Z, - IIO_EV_TYPE_ROC, - dir), - data->timestamp); + iio_push_event(indio_dev, + IIO_MOD_EVENT_CODE(IIO_ACCEL, + 0, + IIO_MOD_Z, + IIO_EV_TYPE_ROC, + dir), + data->timestamp); + return ret; } @@ -1365,7 +1370,9 @@ static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private) BMC150_ACCEL_INT_MODE_LATCH_INT | BMC150_ACCEL_INT_MODE_LATCH_RESET); if (ret) - dev_err(&data->client->dev, "Error writing reg_int_rst_latch\n"); + dev_err(&data->client->dev, + "Error writing reg_int_rst_latch\n"); + ret = IRQ_HANDLED; } else { ret = IRQ_NONE; @@ -1412,13 +1419,13 @@ static const char *bmc150_accel_match_acpi_device(struct device *dev, int *data) if (!id) return NULL; - *data = (int) id->driver_data; + *data = (int)id->driver_data; return dev_name(dev); } static int bmc150_accel_gpio_probe(struct i2c_client *client, - struct bmc150_accel_data *data) + struct bmc150_accel_data *data) { struct device *dev; struct gpio_desc *gpio; -- cgit v1.2.3 From c6f67a1f55a7f8a8373068ca07553bd2b2731949 Mon Sep 17 00:00:00 2001 From: Octavian Purdila Date: Fri, 5 Jun 2015 15:56:47 +0300 Subject: iio: allow userspace to flush the hwfifo with non-blocking reads This patch changes the semantics of non-blocking reads so that a hardware fifo flush is triggered if the available data in the device buffer is less then the requested size. This allows userspace to accurately generate hardware fifo flushes, by doing a non-blocking read with a size greater then the sum of the device buffer and hardware fifo size. Signed-off-by: Octavian Purdila Reviewed-by: Lars-Peter Clausen Signed-off-by: Jonathan Cameron --- drivers/iio/industrialio-buffer.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/iio/industrialio-buffer.c b/drivers/iio/industrialio-buffer.c index 6eee1b044c60..f72be48e650c 100644 --- a/drivers/iio/industrialio-buffer.c +++ b/drivers/iio/industrialio-buffer.c @@ -71,8 +71,9 @@ static bool iio_buffer_ready(struct iio_dev *indio_dev, struct iio_buffer *buf, if (avail >= to_wait) { /* force a flush for non-blocking reads */ - if (!to_wait && !avail && to_flush) - iio_buffer_flush_hwfifo(indio_dev, buf, to_flush); + if (!to_wait && avail < to_flush) + iio_buffer_flush_hwfifo(indio_dev, buf, + to_flush - avail); return true; } @@ -100,8 +101,7 @@ ssize_t iio_buffer_read_first_n_outer(struct file *filp, char __user *buf, struct iio_dev *indio_dev = filp->private_data; struct iio_buffer *rb = indio_dev->buffer; size_t datum_size; - size_t to_wait = 0; - size_t to_read; + size_t to_wait; int ret; if (!indio_dev->info) @@ -119,14 +119,14 @@ ssize_t iio_buffer_read_first_n_outer(struct file *filp, char __user *buf, if (!datum_size) return 0; - to_read = min_t(size_t, n / datum_size, rb->watermark); - - if (!(filp->f_flags & O_NONBLOCK)) - to_wait = to_read; + if (filp->f_flags & O_NONBLOCK) + to_wait = 0; + else + to_wait = min_t(size_t, n / datum_size, rb->watermark); do { ret = wait_event_interruptible(rb->pollq, - iio_buffer_ready(indio_dev, rb, to_wait, to_read)); + iio_buffer_ready(indio_dev, rb, to_wait, n / datum_size)); if (ret) return ret; -- cgit v1.2.3 From 9d174b49ce05b63763e76f9f4373bc1b213ff584 Mon Sep 17 00:00:00 2001 From: Vlad Dogaru Date: Fri, 12 Jun 2015 11:31:38 +0300 Subject: iio: magn: bmc150: decouple buffer and trigger Signed-off-by: Vlad Dogaru Signed-off-by: Jonathan Cameron --- drivers/iio/magnetometer/bmc150_magn.c | 69 +++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 31 deletions(-) diff --git a/drivers/iio/magnetometer/bmc150_magn.c b/drivers/iio/magnetometer/bmc150_magn.c index d4c178869991..a0e64f19f4c4 100644 --- a/drivers/iio/magnetometer/bmc150_magn.c +++ b/drivers/iio/magnetometer/bmc150_magn.c @@ -588,17 +588,6 @@ static int bmc150_magn_write_raw(struct iio_dev *indio_dev, } } -static int bmc150_magn_validate_trigger(struct iio_dev *indio_dev, - struct iio_trigger *trig) -{ - struct bmc150_magn_data *data = iio_priv(indio_dev); - - if (data->dready_trig != trig) - return -EINVAL; - - return 0; -} - static ssize_t bmc150_magn_show_samp_freq_avail(struct device *dev, struct device_attribute *attr, char *buf) @@ -659,7 +648,6 @@ static const struct iio_info bmc150_magn_info = { .attrs = &bmc150_magn_attrs_group, .read_raw = bmc150_magn_read_raw, .write_raw = bmc150_magn_write_raw, - .validate_trigger = bmc150_magn_validate_trigger, .driver_module = THIS_MODULE, }; @@ -682,7 +670,7 @@ static irqreturn_t bmc150_magn_trigger_handler(int irq, void *p) pf->timestamp); err: - iio_trigger_notify_done(data->dready_trig); + iio_trigger_notify_done(indio_dev->trig); return IRQ_HANDLED; } @@ -827,6 +815,27 @@ static const struct iio_trigger_ops bmc150_magn_trigger_ops = { .owner = THIS_MODULE, }; +static int bmc150_magn_buffer_preenable(struct iio_dev *indio_dev) +{ + struct bmc150_magn_data *data = iio_priv(indio_dev); + + return bmc150_magn_set_power_state(data, true); +} + +static int bmc150_magn_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct bmc150_magn_data *data = iio_priv(indio_dev); + + return bmc150_magn_set_power_state(data, false); +} + +static const struct iio_buffer_setup_ops bmc150_magn_buffer_setup_ops = { + .preenable = bmc150_magn_buffer_preenable, + .postenable = iio_triggered_buffer_postenable, + .predisable = iio_triggered_buffer_predisable, + .postdisable = bmc150_magn_buffer_postdisable, +}; + static int bmc150_magn_gpio_probe(struct i2c_client *client) { struct device *dev; @@ -932,16 +941,6 @@ static int bmc150_magn_probe(struct i2c_client *client, goto err_poweroff; } - ret = iio_triggered_buffer_setup(indio_dev, - &iio_pollfunc_store_time, - bmc150_magn_trigger_handler, - NULL); - if (ret < 0) { - dev_err(&client->dev, - "iio triggered buffer setup failed\n"); - goto err_trigger_unregister; - } - ret = request_threaded_irq(client->irq, iio_trigger_generic_data_rdy_poll, NULL, @@ -951,14 +950,24 @@ static int bmc150_magn_probe(struct i2c_client *client, if (ret < 0) { dev_err(&client->dev, "request irq %d failed\n", client->irq); - goto err_buffer_cleanup; + goto err_trigger_unregister; } } + ret = iio_triggered_buffer_setup(indio_dev, + iio_pollfunc_store_time, + bmc150_magn_trigger_handler, + &bmc150_magn_buffer_setup_ops); + if (ret < 0) { + dev_err(&client->dev, + "iio triggered buffer setup failed\n"); + goto err_free_irq; + } + ret = iio_device_register(indio_dev); if (ret < 0) { dev_err(&client->dev, "unable to register iio device\n"); - goto err_free_irq; + goto err_buffer_cleanup; } ret = pm_runtime_set_active(&client->dev); @@ -976,12 +985,11 @@ static int bmc150_magn_probe(struct i2c_client *client, err_iio_unregister: iio_device_unregister(indio_dev); +err_buffer_cleanup: + iio_triggered_buffer_cleanup(indio_dev); err_free_irq: if (client->irq > 0) free_irq(client->irq, data->dready_trig); -err_buffer_cleanup: - if (data->dready_trig) - iio_triggered_buffer_cleanup(indio_dev); err_trigger_unregister: if (data->dready_trig) iio_trigger_unregister(data->dready_trig); @@ -1000,14 +1008,13 @@ static int bmc150_magn_remove(struct i2c_client *client) pm_runtime_put_noidle(&client->dev); iio_device_unregister(indio_dev); + iio_triggered_buffer_cleanup(indio_dev); if (client->irq > 0) free_irq(data->client->irq, data->dready_trig); - if (data->dready_trig) { - iio_triggered_buffer_cleanup(indio_dev); + if (data->dready_trig) iio_trigger_unregister(data->dready_trig); - } mutex_lock(&data->mutex); bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND, true); -- cgit v1.2.3 From da8ef4e77d9dfe91d69033cfa05d9f3036fb8dfd Mon Sep 17 00:00:00 2001 From: Vlad Dogaru Date: Fri, 12 Jun 2015 11:31:39 +0300 Subject: iio: magn: bmc150: add support for bmc156 The BMC156 is a slightly less capable version of BMC150 which lacks support for magnetometer thresholds. Since this driver does not support those anyway, adding support is trivial. Datasheet is available at https://ae-bst.resource.bosch.com/media/products/dokumente/bmc156_1/BST-BMC156-DS000-01.pdf Signed-off-by: Vlad Dogaru Signed-off-by: Jonathan Cameron --- drivers/iio/magnetometer/bmc150_magn.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iio/magnetometer/bmc150_magn.c b/drivers/iio/magnetometer/bmc150_magn.c index a0e64f19f4c4..cd002710dd02 100644 --- a/drivers/iio/magnetometer/bmc150_magn.c +++ b/drivers/iio/magnetometer/bmc150_magn.c @@ -1089,12 +1089,14 @@ static const struct dev_pm_ops bmc150_magn_pm_ops = { static const struct acpi_device_id bmc150_magn_acpi_match[] = { {"BMC150B", 0}, + {"BMC156B", 0}, {}, }; MODULE_DEVICE_TABLE(acpi, bmc150_magn_acpi_match); static const struct i2c_device_id bmc150_magn_id[] = { {"bmc150_magn", 0}, + {"bmc156_magn", 0}, {}, }; MODULE_DEVICE_TABLE(i2c, bmc150_magn_id); -- cgit v1.2.3 From efa86e9fa82eaeee76903f131bc326af48a7cbcf Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Wed, 17 Jun 2015 12:42:51 +0300 Subject: iio: light: Add support for ROHM RPR0521 sensor This patch adds support for ROHM RPR0521 ambient light and proximity sensor. It offers raw readings for intensity and proximity. Signed-off-by: Daniel Baluta Signed-off-by: Jonathan Cameron --- drivers/iio/light/Kconfig | 11 + drivers/iio/light/Makefile | 1 + drivers/iio/light/rpr0521.c | 615 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 627 insertions(+) create mode 100644 drivers/iio/light/rpr0521.c diff --git a/drivers/iio/light/Kconfig b/drivers/iio/light/Kconfig index 554f8ee6d64a..730fa80c83ea 100644 --- a/drivers/iio/light/Kconfig +++ b/drivers/iio/light/Kconfig @@ -168,6 +168,17 @@ config JSA1212 To compile this driver as a module, choose M here: the module will be called jsa1212. +config RPR0521 + tristate "ROHM RPR0521 ALS and proximity sensor driver" + depends on I2C + select REGMAP_I2C + help + Say Y here if you want to build support for ROHM's RPR0521 + ambient light and proximity sensor device. + + To compile this driver as a module, choose M here: + the module will be called rpr0521. + config SENSORS_LM3533 tristate "LM3533 ambient light sensor" depends on MFD_LM3533 diff --git a/drivers/iio/light/Makefile b/drivers/iio/light/Makefile index e2d50fd59c66..adf97237db72 100644 --- a/drivers/iio/light/Makefile +++ b/drivers/iio/light/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_ISL29125) += isl29125.o obj-$(CONFIG_JSA1212) += jsa1212.o obj-$(CONFIG_SENSORS_LM3533) += lm3533-als.o obj-$(CONFIG_LTR501) += ltr501.o +obj-$(CONFIG_RPR0521) += rpr0521.o obj-$(CONFIG_SENSORS_TSL2563) += tsl2563.o obj-$(CONFIG_STK3310) += stk3310.o obj-$(CONFIG_TCS3414) += tcs3414.o diff --git a/drivers/iio/light/rpr0521.c b/drivers/iio/light/rpr0521.c new file mode 100644 index 000000000000..4b75bb0998b3 --- /dev/null +++ b/drivers/iio/light/rpr0521.c @@ -0,0 +1,615 @@ +/* + * RPR-0521 ROHM Ambient Light and Proximity Sensor + * + * Copyright (c) 2015, Intel Corporation. + * + * This file is subject to the terms and conditions of version 2 of + * the GNU General Public License. See the file COPYING in the main + * directory of this archive for more details. + * + * IIO driver for RPR-0521RS (7-bit I2C slave address 0x38). + * + * TODO: illuminance channel, PM support, buffer + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define RPR0521_REG_SYSTEM_CTRL 0x40 +#define RPR0521_REG_MODE_CTRL 0x41 +#define RPR0521_REG_ALS_CTRL 0x42 +#define RPR0521_REG_PXS_CTRL 0x43 +#define RPR0521_REG_PXS_DATA 0x44 /* 16-bit, little endian */ +#define RPR0521_REG_ALS_DATA0 0x46 /* 16-bit, little endian */ +#define RPR0521_REG_ALS_DATA1 0x48 /* 16-bit, little endian */ +#define RPR0521_REG_ID 0x92 + +#define RPR0521_MODE_ALS_MASK BIT(7) +#define RPR0521_MODE_PXS_MASK BIT(6) +#define RPR0521_MODE_MEAS_TIME_MASK GENMASK(3, 0) +#define RPR0521_ALS_DATA0_GAIN_MASK GENMASK(5, 4) +#define RPR0521_ALS_DATA0_GAIN_SHIFT 4 +#define RPR0521_ALS_DATA1_GAIN_MASK GENMASK(3, 2) +#define RPR0521_ALS_DATA1_GAIN_SHIFT 2 +#define RPR0521_PXS_GAIN_MASK GENMASK(5, 4) +#define RPR0521_PXS_GAIN_SHIFT 4 + +#define RPR0521_MODE_ALS_ENABLE BIT(7) +#define RPR0521_MODE_ALS_DISABLE 0x00 +#define RPR0521_MODE_PXS_ENABLE BIT(6) +#define RPR0521_MODE_PXS_DISABLE 0x00 + +#define RPR0521_MANUFACT_ID 0xE0 +#define RPR0521_DEFAULT_MEAS_TIME 0x06 /* ALS - 100ms, PXS - 100ms */ + +#define RPR0521_DRV_NAME "RPR0521" +#define RPR0521_REGMAP_NAME "rpr0521_regmap" + +#define RPR0521_SLEEP_DELAY_MS 2000 + +#define RPR0521_ALS_SCALE_AVAIL "0.007812 0.015625 0.5 1" +#define RPR0521_PXS_SCALE_AVAIL "0.125 0.5 1" + +struct rpr0521_gain { + int scale; + int uscale; +}; + +static const struct rpr0521_gain rpr0521_als_gain[4] = { + {1, 0}, /* x1 */ + {0, 500000}, /* x2 */ + {0, 15625}, /* x64 */ + {0, 7812}, /* x128 */ +}; + +static const struct rpr0521_gain rpr0521_pxs_gain[3] = { + {1, 0}, /* x1 */ + {0, 500000}, /* x2 */ + {0, 125000}, /* x4 */ +}; + +enum rpr0521_channel { + RPR0521_CHAN_ALS_DATA0, + RPR0521_CHAN_ALS_DATA1, + RPR0521_CHAN_PXS, +}; + +struct rpr0521_reg_desc { + u8 address; + u8 device_mask; +}; + +static const struct rpr0521_reg_desc rpr0521_data_reg[] = { + [RPR0521_CHAN_ALS_DATA0] = { + .address = RPR0521_REG_ALS_DATA0, + .device_mask = RPR0521_MODE_ALS_MASK, + }, + [RPR0521_CHAN_ALS_DATA1] = { + .address = RPR0521_REG_ALS_DATA1, + .device_mask = RPR0521_MODE_ALS_MASK, + }, + [RPR0521_CHAN_PXS] = { + .address = RPR0521_REG_PXS_DATA, + .device_mask = RPR0521_MODE_PXS_MASK, + }, +}; + +static const struct rpr0521_gain_info { + u8 reg; + u8 mask; + u8 shift; + const struct rpr0521_gain *gain; + int size; +} rpr0521_gain[] = { + [RPR0521_CHAN_ALS_DATA0] = { + .reg = RPR0521_REG_ALS_CTRL, + .mask = RPR0521_ALS_DATA0_GAIN_MASK, + .shift = RPR0521_ALS_DATA0_GAIN_SHIFT, + .gain = rpr0521_als_gain, + .size = ARRAY_SIZE(rpr0521_als_gain), + }, + [RPR0521_CHAN_ALS_DATA1] = { + .reg = RPR0521_REG_ALS_CTRL, + .mask = RPR0521_ALS_DATA1_GAIN_MASK, + .shift = RPR0521_ALS_DATA1_GAIN_SHIFT, + .gain = rpr0521_als_gain, + .size = ARRAY_SIZE(rpr0521_als_gain), + }, + [RPR0521_CHAN_PXS] = { + .reg = RPR0521_REG_PXS_CTRL, + .mask = RPR0521_PXS_GAIN_MASK, + .shift = RPR0521_PXS_GAIN_SHIFT, + .gain = rpr0521_pxs_gain, + .size = ARRAY_SIZE(rpr0521_pxs_gain), + }, +}; + +struct rpr0521_data { + struct i2c_client *client; + + /* protect device params updates (e.g state, gain) */ + struct mutex lock; + + /* device active status */ + bool als_dev_en; + bool pxs_dev_en; + + /* optimize runtime pm ops - enable device only if needed */ + bool als_ps_need_en; + bool pxs_ps_need_en; + + struct regmap *regmap; +}; + +static IIO_CONST_ATTR(in_intensity_scale_available, RPR0521_ALS_SCALE_AVAIL); +static IIO_CONST_ATTR(in_proximity_scale_available, RPR0521_PXS_SCALE_AVAIL); + +static struct attribute *rpr0521_attributes[] = { + &iio_const_attr_in_intensity_scale_available.dev_attr.attr, + &iio_const_attr_in_proximity_scale_available.dev_attr.attr, + NULL, +}; + +static const struct attribute_group rpr0521_attribute_group = { + .attrs = rpr0521_attributes, +}; + +static const struct iio_chan_spec rpr0521_channels[] = { + { + .type = IIO_INTENSITY, + .modified = 1, + .address = RPR0521_CHAN_ALS_DATA0, + .channel2 = IIO_MOD_LIGHT_BOTH, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + }, + { + .type = IIO_INTENSITY, + .modified = 1, + .address = RPR0521_CHAN_ALS_DATA1, + .channel2 = IIO_MOD_LIGHT_IR, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + }, + { + .type = IIO_PROXIMITY, + .address = RPR0521_CHAN_PXS, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + } +}; + +static int rpr0521_als_enable(struct rpr0521_data *data, u8 status) +{ + int ret; + + ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL, + RPR0521_MODE_ALS_MASK, + status); + if (ret < 0) + return ret; + + data->als_dev_en = true; + + return 0; +} + +static int rpr0521_pxs_enable(struct rpr0521_data *data, u8 status) +{ + int ret; + + ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL, + RPR0521_MODE_PXS_MASK, + status); + if (ret < 0) + return ret; + + data->pxs_dev_en = true; + + return 0; +} + +/** + * rpr0521_set_power_state - handles runtime PM state and sensors enabled status + * + * @data: rpr0521 device private data + * @on: state to be set for devices in @device_mask + * @device_mask: bitmask specifying for which device we need to update @on state + * + * We rely on rpr0521_runtime_resume to enable our @device_mask devices, but + * if (for example) PXS was enabled (pxs_dev_en = true) by a previous call to + * rpr0521_runtime_resume and we want to enable ALS we MUST set ALS enable + * bit of RPR0521_REG_MODE_CTRL here because rpr0521_runtime_resume will not + * be called twice. + */ +static int rpr0521_set_power_state(struct rpr0521_data *data, bool on, + u8 device_mask) +{ +#ifdef CONFIG_PM + int ret; + u8 update_mask = 0; + + if (device_mask & RPR0521_MODE_ALS_MASK) { + if (on && !data->als_ps_need_en && data->pxs_dev_en) + update_mask |= RPR0521_MODE_ALS_MASK; + else + data->als_ps_need_en = on; + } + + if (device_mask & RPR0521_MODE_PXS_MASK) { + if (on && !data->pxs_ps_need_en && data->als_dev_en) + update_mask |= RPR0521_MODE_PXS_MASK; + else + data->pxs_ps_need_en = on; + } + + if (update_mask) { + ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL, + update_mask, update_mask); + if (ret < 0) + return ret; + } + + if (on) { + ret = pm_runtime_get_sync(&data->client->dev); + } else { + pm_runtime_mark_last_busy(&data->client->dev); + ret = pm_runtime_put_autosuspend(&data->client->dev); + } + if (ret < 0) { + dev_err(&data->client->dev, + "Failed: rpr0521_set_power_state for %d, ret %d\n", + on, ret); + if (on) + pm_runtime_put_noidle(&data->client->dev); + + return ret; + } +#endif + return 0; +} + +static int rpr0521_get_gain(struct rpr0521_data *data, int chan, + int *val, int *val2) +{ + int ret, reg, idx; + + ret = regmap_read(data->regmap, rpr0521_gain[chan].reg, ®); + if (ret < 0) + return ret; + + idx = (rpr0521_gain[chan].mask & reg) >> rpr0521_gain[chan].shift; + *val = rpr0521_gain[chan].gain[idx].scale; + *val2 = rpr0521_gain[chan].gain[idx].uscale; + + return 0; +} + +static int rpr0521_set_gain(struct rpr0521_data *data, int chan, + int val, int val2) +{ + int i, idx = -EINVAL; + + /* get gain index */ + for (i = 0; i < rpr0521_gain[chan].size; i++) + if (val == rpr0521_gain[chan].gain[i].scale && + val2 == rpr0521_gain[chan].gain[i].uscale) { + idx = i; + break; + } + + if (idx < 0) + return idx; + + return regmap_update_bits(data->regmap, rpr0521_gain[chan].reg, + rpr0521_gain[chan].mask, + idx << rpr0521_gain[chan].shift); +} + +static int rpr0521_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct rpr0521_data *data = iio_priv(indio_dev); + int ret; + u8 device_mask; + __le16 raw_data; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + if (chan->type != IIO_INTENSITY && chan->type != IIO_PROXIMITY) + return -EINVAL; + + device_mask = rpr0521_data_reg[chan->address].device_mask; + + mutex_lock(&data->lock); + ret = rpr0521_set_power_state(data, true, device_mask); + if (ret < 0) { + mutex_unlock(&data->lock); + return ret; + } + + ret = regmap_bulk_read(data->regmap, + rpr0521_data_reg[chan->address].address, + &raw_data, 2); + if (ret < 0) { + rpr0521_set_power_state(data, false, device_mask); + mutex_unlock(&data->lock); + return ret; + } + + ret = rpr0521_set_power_state(data, false, device_mask); + mutex_unlock(&data->lock); + if (ret < 0) + return ret; + + *val = le16_to_cpu(raw_data); + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + mutex_lock(&data->lock); + ret = rpr0521_get_gain(data, chan->address, val, val2); + mutex_unlock(&data->lock); + if (ret < 0) + return ret; + + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } +} + +static int rpr0521_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, + int val2, long mask) +{ + struct rpr0521_data *data = iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + mutex_lock(&data->lock); + ret = rpr0521_set_gain(data, chan->address, val, val2); + mutex_unlock(&data->lock); + + return ret; + default: + return -EINVAL; + } +} + +static const struct iio_info rpr0521_info = { + .driver_module = THIS_MODULE, + .read_raw = rpr0521_read_raw, + .write_raw = rpr0521_write_raw, + .attrs = &rpr0521_attribute_group, +}; + +static int rpr0521_init(struct rpr0521_data *data) +{ + int ret; + int id; + + ret = regmap_read(data->regmap, RPR0521_REG_ID, &id); + if (ret < 0) { + dev_err(&data->client->dev, "Failed to read REG_ID register\n"); + return ret; + } + + if (id != RPR0521_MANUFACT_ID) { + dev_err(&data->client->dev, "Wrong id, got %x, expected %x\n", + id, RPR0521_MANUFACT_ID); + return -ENODEV; + } + + /* set default measurement time - 100 ms for both ALS and PS */ + ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL, + RPR0521_MODE_MEAS_TIME_MASK, + RPR0521_DEFAULT_MEAS_TIME); + if (ret) { + pr_err("regmap_update_bits returned %d\n", ret); + return ret; + } + + ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE); + if (ret < 0) + return ret; + ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE); + if (ret < 0) + return ret; + + return 0; +} + +static int rpr0521_poweroff(struct rpr0521_data *data) +{ + int ret; + + ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL, + RPR0521_MODE_ALS_MASK | + RPR0521_MODE_PXS_MASK, + RPR0521_MODE_ALS_DISABLE | + RPR0521_MODE_PXS_DISABLE); + if (ret < 0) + return ret; + + data->als_dev_en = false; + data->pxs_dev_en = false; + + return 0; +} + +static bool rpr0521_is_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RPR0521_REG_MODE_CTRL: + case RPR0521_REG_ALS_CTRL: + case RPR0521_REG_PXS_CTRL: + return false; + default: + return true; + } +} + +static const struct regmap_config rpr0521_regmap_config = { + .name = RPR0521_REGMAP_NAME, + + .reg_bits = 8, + .val_bits = 8, + + .max_register = RPR0521_REG_ID, + .cache_type = REGCACHE_RBTREE, + .volatile_reg = rpr0521_is_volatile_reg, +}; + +static int rpr0521_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct rpr0521_data *data; + struct iio_dev *indio_dev; + struct regmap *regmap; + int ret; + + indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); + if (!indio_dev) + return -ENOMEM; + + regmap = devm_regmap_init_i2c(client, &rpr0521_regmap_config); + if (IS_ERR(regmap)) { + dev_err(&client->dev, "regmap_init failed!\n"); + return PTR_ERR(regmap); + } + + data = iio_priv(indio_dev); + i2c_set_clientdata(client, indio_dev); + data->client = client; + data->regmap = regmap; + + mutex_init(&data->lock); + + indio_dev->dev.parent = &client->dev; + indio_dev->info = &rpr0521_info; + indio_dev->name = RPR0521_DRV_NAME; + indio_dev->channels = rpr0521_channels; + indio_dev->num_channels = ARRAY_SIZE(rpr0521_channels); + indio_dev->modes = INDIO_DIRECT_MODE; + + ret = rpr0521_init(data); + if (ret < 0) { + dev_err(&client->dev, "rpr0521 chip init failed\n"); + return ret; + } + ret = iio_device_register(indio_dev); + if (ret < 0) + return ret; + + ret = pm_runtime_set_active(&client->dev); + if (ret < 0) + goto err_iio_unregister; + + pm_runtime_enable(&client->dev); + pm_runtime_set_autosuspend_delay(&client->dev, RPR0521_SLEEP_DELAY_MS); + pm_runtime_use_autosuspend(&client->dev); + + return 0; + +err_iio_unregister: + iio_device_unregister(indio_dev); + return ret; +} + +static int rpr0521_remove(struct i2c_client *client) +{ + struct iio_dev *indio_dev = i2c_get_clientdata(client); + + pm_runtime_disable(&client->dev); + pm_runtime_set_suspended(&client->dev); + pm_runtime_put_noidle(&client->dev); + + iio_device_unregister(indio_dev); + rpr0521_poweroff(iio_priv(indio_dev)); + + return 0; +} + +#ifdef CONFIG_PM +static int rpr0521_runtime_suspend(struct device *dev) +{ + struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); + struct rpr0521_data *data = iio_priv(indio_dev); + int ret; + + /* disable channels and sets {als,pxs}_dev_en to false */ + mutex_lock(&data->lock); + ret = rpr0521_poweroff(data); + mutex_unlock(&data->lock); + + return ret; +} + +static int rpr0521_runtime_resume(struct device *dev) +{ + struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); + struct rpr0521_data *data = iio_priv(indio_dev); + int ret; + + if (data->als_ps_need_en) { + ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE); + if (ret < 0) + return ret; + data->als_ps_need_en = false; + } + + if (data->pxs_ps_need_en) { + ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE); + if (ret < 0) + return ret; + data->pxs_ps_need_en = false; + } + + return 0; +} +#endif + +static const struct dev_pm_ops rpr0521_pm_ops = { + SET_RUNTIME_PM_OPS(rpr0521_runtime_suspend, + rpr0521_runtime_resume, NULL) +}; + +static const struct acpi_device_id rpr0521_acpi_match[] = { + {"RPR0521", 0}, + { } +}; +MODULE_DEVICE_TABLE(acpi, rpr0521_acpi_match); + +static const struct i2c_device_id rpr0521_id[] = { + {"rpr0521", 0}, + { } +}; + +MODULE_DEVICE_TABLE(i2c, rpr0521_id); + +static struct i2c_driver rpr0521_driver = { + .driver = { + .name = RPR0521_DRV_NAME, + .pm = &rpr0521_pm_ops, + .acpi_match_table = ACPI_PTR(rpr0521_acpi_match), + }, + .probe = rpr0521_probe, + .remove = rpr0521_remove, + .id_table = rpr0521_id, +}; + +module_i2c_driver(rpr0521_driver); + +MODULE_AUTHOR("Daniel Baluta "); +MODULE_DESCRIPTION("RPR0521 ROHM Ambient Light and Proximity Sensor driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 09a33f052190ef4d997c54e012c9466844bdae0e Mon Sep 17 00:00:00 2001 From: Hartmut Knaack Date: Wed, 10 Jun 2015 21:51:19 +0200 Subject: tools:iio:iio_event_monitor: check if event is fully read Check that the read event is of the expected size. Signed-off-by: Hartmut Knaack Signed-off-by: Jonathan Cameron --- tools/iio/iio_event_monitor.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/iio/iio_event_monitor.c b/tools/iio/iio_event_monitor.c index 1dba09062a64..703f4cb0e8e9 100644 --- a/tools/iio/iio_event_monitor.c +++ b/tools/iio/iio_event_monitor.c @@ -310,6 +310,12 @@ int main(int argc, char **argv) } } + if (ret != sizeof(event)) { + printf("Reading event failed!\n"); + ret = -EIO; + break; + } + print_event(&event); } -- cgit v1.2.3 From 12ebb05246338aa9cdee51da50f57237352b3f64 Mon Sep 17 00:00:00 2001 From: Hartmut Knaack Date: Sun, 21 Jun 2015 12:18:09 +0200 Subject: iio:adc:Kconfig: rework help descriptions Rework the help text of several ADCs to make sure that: - the module name is mentioned, if the driver can be built as a module - "If unsure, say N" messages are dropped - right indentation is maintained Signed-off-by: Hartmut Knaack Acked-by: Lars-Peter Clausen Signed-off-by: Jonathan Cameron --- drivers/iio/adc/Kconfig | 48 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 7c5565891cb8..dace593b158b 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -20,6 +20,9 @@ config AD7266 Say yes here to build support for Analog Devices AD7265 and AD7266 ADCs. + To compile this driver as a module, choose M here: the module will be + called ad7266. + config AD7291 tristate "Analog Devices AD7291 ADC driver" depends on I2C @@ -52,8 +55,6 @@ config AD7476 AD7277, AD7278, AD7475, AD7476, AD7477, AD7478, AD7466, AD7467, AD7468, AD7495, AD7910, AD7920, AD7920 SPI analog to digital converters (ADC). - If unsure, say N (but it's safe to say "Y"). - To compile this driver as a module, choose M here: the module will be called ad7476. @@ -63,8 +64,7 @@ config AD7791 select AD_SIGMA_DELTA help Say yes here to build support for Analog Devices AD7787, AD7788, AD7789, - AD7790 and AD7791 SPI analog to digital converters (ADC). If unsure, say - N (but it is safe to say "Y"). + AD7790 and AD7791 SPI analog to digital converters (ADC). To compile this driver as a module, choose M here: the module will be called ad7791. @@ -76,7 +76,6 @@ config AD7793 help Say yes here to build support for Analog Devices AD7785, AD7792, AD7793, AD7794 and AD7795 SPI analog to digital converters (ADC). - If unsure, say N (but it's safe to say "Y"). To compile this driver as a module, choose M here: the module will be called AD7793. @@ -89,7 +88,6 @@ config AD7887 help Say yes here to build support for Analog Devices AD7887 SPI analog to digital converter (ADC). - If unsure, say N (but it's safe to say "Y"). To compile this driver as a module, choose M here: the module will be called ad7887. @@ -117,6 +115,9 @@ config AD799X i2c analog to digital converters (ADC). Provides direct access via sysfs. + To compile this driver as a module, choose M here: the module will be + called ad799x. + config AT91_ADC tristate "Atmel AT91 ADC" depends on ARCH_AT91 @@ -127,6 +128,9 @@ config AT91_ADC help Say yes here to build support for Atmel AT91 ADC. + To compile this driver as a module, choose M here: the module will be + called at91_adc. + config AXP288_ADC tristate "X-Powers AXP288 ADC driver" depends on MFD_AXP20X @@ -135,6 +139,9 @@ config AXP288_ADC device. Depending on platform configuration, this general purpose ADC can be used for sampling sensors such as thermal resistors. + To compile this driver as a module, choose M here: the module will be + called axp288_adc. + config BERLIN2_ADC tristate "Marvell Berlin2 ADC driver" depends on ARCH_BERLIN @@ -151,6 +158,9 @@ config DA9150_GPADC This driver can also be built as a module. If chosen, the module name will be da9150-gpadc. + To compile this driver as a module, choose M here: the module will be + called berlin2-adc. + config CC10001_ADC tristate "Cosmic Circuits 10001 ADC driver" depends on HAVE_CLK || REGULATOR @@ -171,12 +181,18 @@ config EXYNOS_ADC of SoCs for drivers such as the touchscreen and hwmon to use to share this resource. + To compile this driver as a module, choose M here: the module will be + called exynos_adc. + config LP8788_ADC tristate "LP8788 ADC driver" depends on MFD_LP8788 help Say yes here to build support for TI LP8788 ADC. + To compile this driver as a module, choose M here: the module will be + called lp8788_adc. + config MAX1027 tristate "Maxim max1027 ADC driver" depends on SPI @@ -186,6 +202,9 @@ config MAX1027 Say yes here to build support for Maxim SPI ADC models max1027, max1029 and max1031. + To compile this driver as a module, choose M here: the module will be + called max1027. + config MAX1363 tristate "Maxim max1363 ADC driver" depends on I2C @@ -202,6 +221,9 @@ config MAX1363 max11646, max11647) Provides direct access via sysfs and buffered data via the iio dev interface. + To compile this driver as a module, choose M here: the module will be + called max1363. + config MCP320X tristate "Microchip Technology MCP3x01/02/04/08" depends on SPI @@ -310,15 +332,18 @@ config TI_AM335X_ADC Say yes here to build support for Texas Instruments ADC driver which is also a MFD client. + To compile this driver as a module, choose M here: the module will be + called ti_am335x_adc. + config TWL4030_MADC tristate "TWL4030 MADC (Monitoring A/D Converter)" depends on TWL4030_CORE help - This driver provides support for Triton TWL4030-MADC. The - driver supports both RT and SW conversion methods. + This driver provides support for Triton TWL4030-MADC. The + driver supports both RT and SW conversion methods. - This driver can also be built as a module. If so, the module will be - called twl4030-madc. + This driver can also be built as a module. If so, the module will be + called twl4030-madc. config TWL6030_GPADC tristate "TWL6030 GPADC (General Purpose A/D Converter) Support" @@ -351,6 +376,9 @@ config VIPERBOARD_ADC Say yes here to access the ADC part of the Nano River Technologies Viperboard. + To compile this driver as a module, choose M here: the module will be + called viperboard_adc. + config XILINX_XADC tristate "Xilinx XADC driver" depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST -- cgit v1.2.3 From cdeb1755d7b965ad0d58cff4db1cf6de4ba3b2ba Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Fri, 26 Jun 2015 16:28:13 -0300 Subject: [media] media/dvb: fix ts2020.c Kconfig and build Fix kconfig warning that is caused by DVB_TS2020: warning: (DVB_TS2020 && SND_SOC_ADAU1761_I2C && SND_SOC_ADAU1781_I2C && SND_SOC_ADAU1977_I2C && SND_SOC_RT5677 && EXTCON_MAX14577 && EXTCON_MAX77693 && EXTCON_MAX77843) selects REGMAP_I2C which has unmet direct dependencies (I2C) This fixes many subsequent build errors. Signed-off-by: Randy Dunlap Cc: Konstantin Dimitrov Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb-frontends/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig index 0d35f5850ff1..5ab90f36a6a6 100644 --- a/drivers/media/dvb-frontends/Kconfig +++ b/drivers/media/dvb-frontends/Kconfig @@ -240,7 +240,7 @@ config DVB_SI21XX config DVB_TS2020 tristate "Montage Tehnology TS2020 based tuners" - depends on DVB_CORE + depends on DVB_CORE && I2C select REGMAP_I2C default m if !MEDIA_SUBDRV_AUTOSELECT help -- cgit v1.2.3 From 5bab86243d949cf021b0f104faafc18f5d20283c Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Fri, 26 Jun 2015 17:43:24 -0300 Subject: [media] media/pci/cobalt: fix Kconfig and build when SND is not enabled Fix build errors in cobalt driver when CONFIG_SND is not enabled. Fixes these build errors: ERROR: "snd_pcm_period_elapsed" [drivers/media/pci/cobalt/cobalt.ko] undefined! ERROR: "_snd_pcm_stream_lock_irqsave" [drivers/media/pci/cobalt/cobalt.ko] undefined! ERROR: "snd_pcm_hw_constraint_integer" [drivers/media/pci/cobalt/cobalt.ko] undefined! ERROR: "snd_pcm_set_ops" [drivers/media/pci/cobalt/cobalt.ko] undefined! ERROR: "snd_pcm_stream_unlock_irqrestore" [drivers/media/pci/cobalt/cobalt.ko] undefined! ERROR: "snd_pcm_lib_ioctl" [drivers/media/pci/cobalt/cobalt.ko] undefined! ERROR: "snd_card_new" [drivers/media/pci/cobalt/cobalt.ko] undefined! ERROR: "snd_card_free" [drivers/media/pci/cobalt/cobalt.ko] undefined! ERROR: "snd_card_register" [drivers/media/pci/cobalt/cobalt.ko] undefined! ERROR: "snd_pcm_new" [drivers/media/pci/cobalt/cobalt.ko] undefined! Signed-off-by: Randy Dunlap Cc: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/pci/cobalt/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/pci/cobalt/Kconfig b/drivers/media/pci/cobalt/Kconfig index 3be1b2c3c386..6a1c0089bb62 100644 --- a/drivers/media/pci/cobalt/Kconfig +++ b/drivers/media/pci/cobalt/Kconfig @@ -2,6 +2,7 @@ config VIDEO_COBALT tristate "Cisco Cobalt support" depends on VIDEO_V4L2 && I2C && MEDIA_CONTROLLER depends on PCI_MSI && MTD_COMPLEX_MAPPINGS && GPIOLIB + depends on SND select I2C_ALGOBIT select VIDEO_ADV7604 select VIDEO_ADV7511 -- cgit v1.2.3 From 5d4db691ed978080435f4e5aad2ce707294a75b4 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 23 Jun 2015 15:04:28 +0200 Subject: spi: rspi: Drop variable "error" in qspi_trigger_transfer_out_in() Just use "ret" instead, for consistency with other similar functions. Signed-off-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- drivers/spi/spi-rspi.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index f9189a0c8cec..9a71fa2e53a9 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -725,24 +725,23 @@ static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx, u8 *rx, unsigned int len) { int i, n, ret; - int error; while (len > 0) { n = qspi_set_send_trigger(rspi, len); qspi_set_receive_trigger(rspi, len); if (n == QSPI_BUFFER_SIZE) { - error = rspi_wait_for_tx_empty(rspi); - if (error < 0) { + ret = rspi_wait_for_tx_empty(rspi); + if (ret < 0) { dev_err(&rspi->master->dev, "transmit timeout\n"); - return error; + return ret; } for (i = 0; i < n; i++) rspi_write_data(rspi, *tx++); - error = rspi_wait_for_rx_full(rspi); - if (error < 0) { + ret = rspi_wait_for_rx_full(rspi); + if (ret < 0) { dev_err(&rspi->master->dev, "receive timeout\n"); - return error; + return ret; } for (i = 0; i < n; i++) *rx++ = rspi_read_data(rspi); -- cgit v1.2.3 From cb76b1ca9174aa29d4c7c0f4aef113be203b600c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 23 Jun 2015 15:04:29 +0200 Subject: spi: rspi: Make qspi_set_send_trigger() return "unsigned int" qspi_set_send_trigger() returns an unsigned value, so make it return "unsigned int". Update the loop variables qspi_trigger_transfer_out_int() to match the above. Signed-off-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- drivers/spi/spi-rspi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index 9a71fa2e53a9..818843336932 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -383,7 +383,8 @@ static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg) rspi_write8(rspi, data, reg); } -static int qspi_set_send_trigger(struct rspi_data *rspi, unsigned int len) +static unsigned int qspi_set_send_trigger(struct rspi_data *rspi, + unsigned int len) { unsigned int n; @@ -724,7 +725,8 @@ static int rspi_rz_transfer_one(struct spi_master *master, static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx, u8 *rx, unsigned int len) { - int i, n, ret; + unsigned int i, n; + int ret; while (len > 0) { n = qspi_set_send_trigger(rspi, len); -- cgit v1.2.3 From e8d0927a19f11cebc4381f5f0cac8fa37154b08a Mon Sep 17 00:00:00 2001 From: Tiberiu Breana Date: Fri, 3 Jul 2015 12:57:36 +0300 Subject: tools: iio: Add single-byte case for generic_buffer Some sensors export data in an 8-bit format. Add a single-byte case for the generic_buffer tool so that these sensors' buffer data can be visualized. Signed-off-by: Tiberiu Breana Reviewed-by: Hartmut Knaack Signed-off-by: Jonathan Cameron --- tools/iio/generic_buffer.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/tools/iio/generic_buffer.c b/tools/iio/generic_buffer.c index fc362d2ff983..0e737238ca74 100644 --- a/tools/iio/generic_buffer.c +++ b/tools/iio/generic_buffer.c @@ -61,6 +61,23 @@ int size_from_channelarray(struct iio_channel_info *channels, int num_channels) return bytes; } +void print1byte(uint8_t input, struct iio_channel_info *info) +{ + /* + * Shift before conversion to avoid sign extension + * of left aligned data + */ + input >>= info->shift; + input &= info->mask; + if (info->is_signed) { + int8_t val = (int8_t)(input << (8 - info->bits_used)) >> + (8 - info->bits_used); + printf("%05f ", ((float)val + info->offset) * info->scale); + } else { + printf("%05f ", ((float)input + info->offset) * info->scale); + } +} + void print2byte(uint16_t input, struct iio_channel_info *info) { /* First swap if incorrect endian */ @@ -152,6 +169,10 @@ void process_scan(char *data, for (k = 0; k < num_channels; k++) switch (channels[k].bytes) { /* only a few cases implemented so far */ + case 1: + print1byte(*(uint8_t *)(data + channels[k].location), + &channels[k]); + break; case 2: print2byte(*(uint16_t *)(data + channels[k].location), &channels[k]); -- cgit v1.2.3 From 4acaf96f747d0cfd6030bde362c1189d248dacff Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Tue, 23 Jun 2015 22:52:28 +0800 Subject: iio: ssp_sensors: Remove redundant spi driver bus initialization In ancient times it was necessary to manually initialize the bus field of an spi_driver to spi_bus_type. These days this is done in spi_register_driver(), so we can drop the manual assignment. Signed-off-by: Antonio Borneo To: Jonathan Cameron To: Lars-Peter Clausen To: Karol Wrona To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Acked-by: Karol Wrona Signed-off-by: Jonathan Cameron --- drivers/iio/common/ssp_sensors/ssp_dev.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/iio/common/ssp_sensors/ssp_dev.c b/drivers/iio/common/ssp_sensors/ssp_dev.c index 9a40097e7cf8..d338bb595db3 100644 --- a/drivers/iio/common/ssp_sensors/ssp_dev.c +++ b/drivers/iio/common/ssp_sensors/ssp_dev.c @@ -700,7 +700,6 @@ static struct spi_driver ssp_driver = { .remove = ssp_remove, .driver = { .pm = &ssp_pm_ops, - .bus = &spi_bus_type, .owner = THIS_MODULE, .of_match_table = of_match_ptr(ssp_of_match), .name = "sensorhub" -- cgit v1.2.3 From 57f7d509c8f60e66d69ac216a03ef39c5ea1ddb8 Mon Sep 17 00:00:00 2001 From: Peter Meerwald Date: Sun, 21 Jun 2015 23:50:22 +0200 Subject: iio: tmp006: Use GENMASK Signed-off-by: Peter Meerwald Signed-off-by: Jonathan Cameron --- drivers/iio/temperature/tmp006.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/temperature/tmp006.c b/drivers/iio/temperature/tmp006.c index fcc49f89b946..ecdb6191951e 100644 --- a/drivers/iio/temperature/tmp006.c +++ b/drivers/iio/temperature/tmp006.c @@ -36,9 +36,9 @@ #define TMP006_CONFIG_DRDY_EN BIT(8) #define TMP006_CONFIG_DRDY BIT(7) -#define TMP006_CONFIG_MOD_MASK 0x7000 +#define TMP006_CONFIG_MOD_MASK GENMASK(14, 12) -#define TMP006_CONFIG_CR_MASK 0x0e00 +#define TMP006_CONFIG_CR_MASK GENMASK(11, 9) #define TMP006_CONFIG_CR_SHIFT 9 #define TMP006_MANUFACTURER_MAGIC 0x5449 -- cgit v1.2.3 From 7cb46c2a0666547493132327ccfc0698d90e52f7 Mon Sep 17 00:00:00 2001 From: Tomasz Duszynski Date: Tue, 23 Jun 2015 20:45:47 +0200 Subject: iio: pressure: ms5611: remove IIO_CHAN_INFO_SCALE from mask IIO_CHAN_INFO_SCALE is useful whenever conversion to standard units is done in userspace. In this case conversion is handled by driver so this bit is unnecessary. Signed-off-by: Tomasz Duszynski Signed-off-by: Jonathan Cameron --- drivers/iio/pressure/ms5611_core.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/iio/pressure/ms5611_core.c b/drivers/iio/pressure/ms5611_core.c index e42c8531d9b3..1109513cdda9 100644 --- a/drivers/iio/pressure/ms5611_core.c +++ b/drivers/iio/pressure/ms5611_core.c @@ -163,13 +163,11 @@ static int ms5611_read_raw(struct iio_dev *indio_dev, static const struct iio_chan_spec ms5611_channels[] = { { .type = IIO_PRESSURE, - .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | - BIT(IIO_CHAN_INFO_SCALE) + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), }, { .type = IIO_TEMP, - .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | - BIT(IIO_CHAN_INFO_SCALE) + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), } }; -- cgit v1.2.3 From 9690d81a02dc4eea78de1686c3bf23a8dd4c0f28 Mon Sep 17 00:00:00 2001 From: Tomasz Duszynski Date: Tue, 23 Jun 2015 20:45:48 +0200 Subject: iio: pressure: ms5611: add support for MS5607 temperature and pressure sensor MS5607 is temperature and pressure sensor which hardware is similar to MS5611. Both sensors share command protocol and support both I2C and SPI serial protocols. They only differ in compensation algorithms. Signed-off-by: Tomasz Duszynski Signed-off-by: Jonathan Cameron --- drivers/iio/pressure/Kconfig | 2 +- drivers/iio/pressure/ms5611.h | 16 +++++++- drivers/iio/pressure/ms5611_core.c | 76 +++++++++++++++++++++++++++++++++----- drivers/iio/pressure/ms5611_i2c.c | 5 ++- drivers/iio/pressure/ms5611_spi.c | 6 ++- 5 files changed, 88 insertions(+), 17 deletions(-) diff --git a/drivers/iio/pressure/Kconfig b/drivers/iio/pressure/Kconfig index b13ea6fd939d..4745179ff64b 100644 --- a/drivers/iio/pressure/Kconfig +++ b/drivers/iio/pressure/Kconfig @@ -56,7 +56,7 @@ config MS5611 tristate "Measurement Specialties MS5611 pressure sensor driver" help Say Y here to build support for the Measurement Specialties - MS5611 pressure and temperature sensor. + MS5611, MS5607 pressure and temperature sensors. To compile this driver as a module, choose M here: the module will be called ms5611_core. diff --git a/drivers/iio/pressure/ms5611.h b/drivers/iio/pressure/ms5611.h index 099c6cdea43f..23b93c797dba 100644 --- a/drivers/iio/pressure/ms5611.h +++ b/drivers/iio/pressure/ms5611.h @@ -27,6 +27,18 @@ #define MS5611_PROM_WORDS_NB 8 +enum { + MS5611, + MS5607, +}; + +struct ms5611_chip_info { + u16 prom[MS5611_PROM_WORDS_NB]; + + int (*temp_and_pressure_compensate)(struct ms5611_chip_info *chip_info, + s32 *temp, s32 *pressure); +}; + struct ms5611_state { void *client; struct mutex lock; @@ -36,9 +48,9 @@ struct ms5611_state { int (*read_adc_temp_and_pressure)(struct device *dev, s32 *temp, s32 *pressure); - u16 prom[MS5611_PROM_WORDS_NB]; + struct ms5611_chip_info *chip_info; }; -int ms5611_probe(struct iio_dev *indio_dev, struct device *dev); +int ms5611_probe(struct iio_dev *indio_dev, struct device *dev, int type); #endif /* _MS5611_H */ diff --git a/drivers/iio/pressure/ms5611_core.c b/drivers/iio/pressure/ms5611_core.c index 1109513cdda9..2f3d9b4aca4e 100644 --- a/drivers/iio/pressure/ms5611_core.c +++ b/drivers/iio/pressure/ms5611_core.c @@ -9,6 +9,7 @@ * * Data sheet: * http://www.meas-spec.com/downloads/MS5611-01BA03.pdf + * http://www.meas-spec.com/downloads/MS5607-02BA03.pdf * */ @@ -50,7 +51,8 @@ static int ms5611_read_prom(struct iio_dev *indio_dev) struct ms5611_state *st = iio_priv(indio_dev); for (i = 0; i < MS5611_PROM_WORDS_NB; i++) { - ret = st->read_prom_word(&indio_dev->dev, i, &st->prom[i]); + ret = st->read_prom_word(&indio_dev->dev, + i, &st->chip_info->prom[i]); if (ret < 0) { dev_err(&indio_dev->dev, "failed to read prom at %d\n", i); @@ -58,7 +60,7 @@ static int ms5611_read_prom(struct iio_dev *indio_dev) } } - if (!ms5611_prom_is_valid(st->prom, MS5611_PROM_WORDS_NB)) { + if (!ms5611_prom_is_valid(st->chip_info->prom, MS5611_PROM_WORDS_NB)) { dev_err(&indio_dev->dev, "PROM integrity check failed\n"); return -ENODEV; } @@ -70,22 +72,30 @@ static int ms5611_read_temp_and_pressure(struct iio_dev *indio_dev, s32 *temp, s32 *pressure) { int ret; - s32 t, p; - s64 off, sens, dt; struct ms5611_state *st = iio_priv(indio_dev); - ret = st->read_adc_temp_and_pressure(&indio_dev->dev, &t, &p); + ret = st->read_adc_temp_and_pressure(&indio_dev->dev, temp, pressure); if (ret < 0) { dev_err(&indio_dev->dev, "failed to read temperature and pressure\n"); return ret; } - dt = t - (st->prom[5] << 8); - off = ((s64)st->prom[2] << 16) + ((st->prom[4] * dt) >> 7); - sens = ((s64)st->prom[1] << 15) + ((st->prom[3] * dt) >> 8); + return st->chip_info->temp_and_pressure_compensate(st->chip_info, + temp, pressure); +} + +static int ms5611_temp_and_pressure_compensate(struct ms5611_chip_info *chip_info, + s32 *temp, s32 *pressure) +{ + s32 t = *temp, p = *pressure; + s64 off, sens, dt; - t = 2000 + ((st->prom[6] * dt) >> 23); + dt = t - (chip_info->prom[5] << 8); + off = ((s64)chip_info->prom[2] << 16) + ((chip_info->prom[4] * dt) >> 7); + sens = ((s64)chip_info->prom[1] << 15) + ((chip_info->prom[3] * dt) >> 8); + + t = 2000 + ((chip_info->prom[6] * dt) >> 23); if (t < 2000) { s64 off2, sens2, t2; @@ -111,6 +121,42 @@ static int ms5611_read_temp_and_pressure(struct iio_dev *indio_dev, return 0; } +static int ms5607_temp_and_pressure_compensate(struct ms5611_chip_info *chip_info, + s32 *temp, s32 *pressure) +{ + s32 t = *temp, p = *pressure; + s64 off, sens, dt; + + dt = t - (chip_info->prom[5] << 8); + off = ((s64)chip_info->prom[2] << 17) + ((chip_info->prom[4] * dt) >> 6); + sens = ((s64)chip_info->prom[1] << 16) + ((chip_info->prom[3] * dt) >> 7); + + t = 2000 + ((chip_info->prom[6] * dt) >> 23); + if (t < 2000) { + s64 off2, sens2, t2; + + t2 = (dt * dt) >> 31; + off2 = (61 * (t - 2000) * (t - 2000)) >> 4; + sens2 = off2 << 1; + + if (t < -1500) { + s64 tmp = (t + 1500) * (t + 1500); + + off2 += 15 * tmp; + sens2 += (8 * tmp); + } + + t -= t2; + off -= off2; + sens -= sens2; + } + + *temp = t; + *pressure = (((p * sens) >> 21) - off) >> 15; + + return 0; +} + static int ms5611_reset(struct iio_dev *indio_dev) { int ret; @@ -160,6 +206,15 @@ static int ms5611_read_raw(struct iio_dev *indio_dev, return -EINVAL; } +static struct ms5611_chip_info chip_info_tbl[] = { + [MS5611] = { + .temp_and_pressure_compensate = ms5611_temp_and_pressure_compensate, + }, + [MS5607] = { + .temp_and_pressure_compensate = ms5607_temp_and_pressure_compensate, + } +}; + static const struct iio_chan_spec ms5611_channels[] = { { .type = IIO_PRESSURE, @@ -187,12 +242,13 @@ static int ms5611_init(struct iio_dev *indio_dev) return ms5611_read_prom(indio_dev); } -int ms5611_probe(struct iio_dev *indio_dev, struct device *dev) +int ms5611_probe(struct iio_dev *indio_dev, struct device *dev, int type) { int ret; struct ms5611_state *st = iio_priv(indio_dev); mutex_init(&st->lock); + st->chip_info = &chip_info_tbl[type]; indio_dev->dev.parent = dev; indio_dev->name = dev->driver->name; indio_dev->info = &ms5611_info; diff --git a/drivers/iio/pressure/ms5611_i2c.c b/drivers/iio/pressure/ms5611_i2c.c index 748fd9acaad8..9d504f17669b 100644 --- a/drivers/iio/pressure/ms5611_i2c.c +++ b/drivers/iio/pressure/ms5611_i2c.c @@ -104,11 +104,12 @@ static int ms5611_i2c_probe(struct i2c_client *client, st->read_adc_temp_and_pressure = ms5611_i2c_read_adc_temp_and_pressure; st->client = client; - return ms5611_probe(indio_dev, &client->dev); + return ms5611_probe(indio_dev, &client->dev, id->driver_data); } static const struct i2c_device_id ms5611_id[] = { - { "ms5611", 0 }, + { "ms5611", MS5611 }, + { "ms5607", MS5607 }, { } }; MODULE_DEVICE_TABLE(i2c, ms5611_id); diff --git a/drivers/iio/pressure/ms5611_spi.c b/drivers/iio/pressure/ms5611_spi.c index 976726fd4e6c..08ee6e88c79f 100644 --- a/drivers/iio/pressure/ms5611_spi.c +++ b/drivers/iio/pressure/ms5611_spi.c @@ -103,11 +103,13 @@ static int ms5611_spi_probe(struct spi_device *spi) st->read_adc_temp_and_pressure = ms5611_spi_read_adc_temp_and_pressure; st->client = spi; - return ms5611_probe(indio_dev, &spi->dev); + return ms5611_probe(indio_dev, &spi->dev, + spi_get_device_id(spi)->driver_data); } static const struct spi_device_id ms5611_id[] = { - { "ms5611", 0 }, + { "ms5611", MS5611 }, + { "ms5607", MS5607 }, { } }; MODULE_DEVICE_TABLE(spi, ms5611_id); -- cgit v1.2.3 From db6a19b8251f089afcd40ed116ffdc2326f704a8 Mon Sep 17 00:00:00 2001 From: Tiberiu Breana Date: Wed, 24 Jun 2015 16:54:46 +0300 Subject: iio: accel: Add trigger support for STK8BA50 Add data-ready interrupts and trigger support for STK8BA50. Additional changes: - read_accel now returns raw acceleration data instead of the sign_extend32 value - read_raw will now enable/disable the sensor with each reading Change-Id: I9c2d7be4256b2dcc5546e4432308ea54f8004333 Signed-off-by: Tiberiu Breana Signed-off-by: Jonathan Cameron --- drivers/iio/accel/stk8ba50.c | 296 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 271 insertions(+), 25 deletions(-) diff --git a/drivers/iio/accel/stk8ba50.c b/drivers/iio/accel/stk8ba50.c index 9836880cc2d1..16cee637109b 100644 --- a/drivers/iio/accel/stk8ba50.c +++ b/drivers/iio/accel/stk8ba50.c @@ -11,11 +11,17 @@ */ #include +#include #include +#include #include #include +#include #include #include +#include +#include +#include #define STK8BA50_REG_XOUT 0x02 #define STK8BA50_REG_YOUT 0x04 @@ -24,6 +30,8 @@ #define STK8BA50_REG_BWSEL 0x10 #define STK8BA50_REG_POWMODE 0x11 #define STK8BA50_REG_SWRST 0x14 +#define STK8BA50_REG_INTEN2 0x17 +#define STK8BA50_REG_INTMAP2 0x1A #define STK8BA50_MODE_NORMAL 0 #define STK8BA50_MODE_SUSPEND 1 @@ -31,8 +39,14 @@ #define STK8BA50_DATA_SHIFT 6 #define STK8BA50_RESET_CMD 0xB6 #define STK8BA50_SR_1792HZ_IDX 7 +#define STK8BA50_DREADY_INT_MASK 0x10 +#define STK8BA50_DREADY_INT_MAP 0x81 +#define STK8BA50_ALL_CHANNEL_MASK 7 +#define STK8BA50_ALL_CHANNEL_SIZE 6 #define STK8BA50_DRIVER_NAME "stk8ba50" +#define STK8BA50_GPIO "stk8ba50_gpio" +#define STK8BA50_IRQ_NAME "stk8ba50_event" #define STK8BA50_SCALE_AVAIL "0.0384 0.0767 0.1534 0.3069" @@ -68,14 +82,29 @@ static const struct { {0x0C, 224}, {0x0D, 448}, {0x0E, 896}, {0x0F, 1792} }; +/* Used to map scan mask bits to their corresponding channel register. */ +static const int stk8ba50_channel_table[] = { + STK8BA50_REG_XOUT, + STK8BA50_REG_YOUT, + STK8BA50_REG_ZOUT +}; + struct stk8ba50_data { struct i2c_client *client; struct mutex lock; int range; u8 sample_rate_idx; + struct iio_trigger *dready_trig; + bool dready_trigger_on; + /* + * 3 x 16-bit channels (10-bit data, 6-bit padding) + + * 1 x 16 padding + + * 4 x 16 64-bit timestamp + */ + s16 buffer[8]; }; -#define STK8BA50_ACCEL_CHANNEL(reg, axis) { \ +#define STK8BA50_ACCEL_CHANNEL(index, reg, axis) { \ .type = IIO_ACCEL, \ .address = reg, \ .modified = 1, \ @@ -83,12 +112,21 @@ struct stk8ba50_data { .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index = index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 10, \ + .storagebits = 16, \ + .shift = STK8BA50_DATA_SHIFT, \ + .endianness = IIO_CPU, \ + }, \ } static const struct iio_chan_spec stk8ba50_channels[] = { - STK8BA50_ACCEL_CHANNEL(STK8BA50_REG_XOUT, X), - STK8BA50_ACCEL_CHANNEL(STK8BA50_REG_YOUT, Y), - STK8BA50_ACCEL_CHANNEL(STK8BA50_REG_ZOUT, Z), + STK8BA50_ACCEL_CHANNEL(0, STK8BA50_REG_XOUT, X), + STK8BA50_ACCEL_CHANNEL(1, STK8BA50_REG_YOUT, Y), + STK8BA50_ACCEL_CHANNEL(2, STK8BA50_REG_ZOUT, Z), + IIO_CHAN_SOFT_TIMESTAMP(3), }; static IIO_CONST_ATTR(in_accel_scale_available, STK8BA50_SCALE_AVAIL); @@ -116,7 +154,61 @@ static int stk8ba50_read_accel(struct stk8ba50_data *data, u8 reg) return ret; } - return sign_extend32(ret >> STK8BA50_DATA_SHIFT, 9); + return ret; +} + +static int stk8ba50_data_rdy_trigger_set_state(struct iio_trigger *trig, + bool state) +{ + struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); + struct stk8ba50_data *data = iio_priv(indio_dev); + int ret; + + if (state) + ret = i2c_smbus_write_byte_data(data->client, + STK8BA50_REG_INTEN2, STK8BA50_DREADY_INT_MASK); + else + ret = i2c_smbus_write_byte_data(data->client, + STK8BA50_REG_INTEN2, 0x00); + + if (ret < 0) + dev_err(&data->client->dev, "failed to set trigger state\n"); + else + data->dready_trigger_on = state; + + return ret; +} + +static const struct iio_trigger_ops stk8ba50_trigger_ops = { + .set_trigger_state = stk8ba50_data_rdy_trigger_set_state, + .owner = THIS_MODULE, +}; + +static int stk8ba50_set_power(struct stk8ba50_data *data, bool mode) +{ + int ret; + u8 masked_reg; + struct i2c_client *client = data->client; + + ret = i2c_smbus_read_byte_data(client, STK8BA50_REG_POWMODE); + if (ret < 0) + goto exit_err; + + if (mode) + masked_reg = ret | STK8BA50_MODE_POWERBIT; + else + masked_reg = ret & (~STK8BA50_MODE_POWERBIT); + + ret = i2c_smbus_write_byte_data(client, STK8BA50_REG_POWMODE, + masked_reg); + if (ret < 0) + goto exit_err; + + return ret; + +exit_err: + dev_err(&client->dev, "failed to change sensor mode\n"); + return ret; } static int stk8ba50_read_raw(struct iio_dev *indio_dev, @@ -124,11 +216,26 @@ static int stk8ba50_read_raw(struct iio_dev *indio_dev, int *val, int *val2, long mask) { struct stk8ba50_data *data = iio_priv(indio_dev); + int ret; switch (mask) { case IIO_CHAN_INFO_RAW: + if (iio_buffer_enabled(indio_dev)) + return -EBUSY; mutex_lock(&data->lock); - *val = stk8ba50_read_accel(data, chan->address); + ret = stk8ba50_set_power(data, STK8BA50_MODE_NORMAL); + if (ret < 0) { + mutex_unlock(&data->lock); + return -EINVAL; + } + ret = stk8ba50_read_accel(data, chan->address); + if (ret < 0) { + stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND); + mutex_unlock(&data->lock); + return -EINVAL; + } + *val = sign_extend32(ret >> STK8BA50_DATA_SHIFT, 9); + stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND); mutex_unlock(&data->lock); return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: @@ -208,30 +315,100 @@ static const struct iio_info stk8ba50_info = { .attrs = &stk8ba50_attribute_group, }; -static int stk8ba50_set_power(struct stk8ba50_data *data, bool mode) +static irqreturn_t stk8ba50_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct stk8ba50_data *data = iio_priv(indio_dev); + int bit, ret, i = 0; + + mutex_lock(&data->lock); + /* + * Do a bulk read if all channels are requested, + * from 0x02 (XOUT1) to 0x07 (ZOUT2) + */ + if (*(indio_dev->active_scan_mask) == STK8BA50_ALL_CHANNEL_MASK) { + ret = i2c_smbus_read_i2c_block_data(data->client, + STK8BA50_REG_XOUT, + STK8BA50_ALL_CHANNEL_SIZE, + (u8 *)data->buffer); + if (ret < STK8BA50_ALL_CHANNEL_SIZE) { + dev_err(&data->client->dev, "register read failed\n"); + goto err; + } + } else { + for_each_set_bit(bit, indio_dev->active_scan_mask, + indio_dev->masklength) { + ret = stk8ba50_read_accel(data, + stk8ba50_channel_table[bit]); + if (ret < 0) + goto err; + + data->buffer[i++] = ret; + } + } + iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, + pf->timestamp); +err: + mutex_unlock(&data->lock); + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static irqreturn_t stk8ba50_data_rdy_trig_poll(int irq, void *private) { + struct iio_dev *indio_dev = private; + struct stk8ba50_data *data = iio_priv(indio_dev); + + if (data->dready_trigger_on) + iio_trigger_poll(data->dready_trig); + + return IRQ_HANDLED; +} + +static int stk8ba50_buffer_preenable(struct iio_dev *indio_dev) +{ + struct stk8ba50_data *data = iio_priv(indio_dev); + + return stk8ba50_set_power(data, STK8BA50_MODE_NORMAL); +} + +static int stk8ba50_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct stk8ba50_data *data = iio_priv(indio_dev); + + return stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND); +} + +static const struct iio_buffer_setup_ops stk8ba50_buffer_setup_ops = { + .preenable = stk8ba50_buffer_preenable, + .postenable = iio_triggered_buffer_postenable, + .predisable = iio_triggered_buffer_predisable, + .postdisable = stk8ba50_buffer_postdisable, +}; + +static int stk8ba50_gpio_probe(struct i2c_client *client) +{ + struct device *dev; + struct gpio_desc *gpio; int ret; - u8 masked_reg; - struct i2c_client *client = data->client; - ret = i2c_smbus_read_byte_data(client, STK8BA50_REG_POWMODE); - if (ret < 0) - goto exit_err; + if (!client) + return -EINVAL; - if (mode) - masked_reg = ret | STK8BA50_MODE_POWERBIT; - else - masked_reg = ret & (~STK8BA50_MODE_POWERBIT); + dev = &client->dev; - ret = i2c_smbus_write_byte_data(client, STK8BA50_REG_POWMODE, - masked_reg); - if (ret < 0) - goto exit_err; + /* data ready gpio interrupt pin */ + gpio = devm_gpiod_get_index(dev, STK8BA50_GPIO, 0, GPIOD_IN); + if (IS_ERR(gpio)) { + dev_err(dev, "acpi gpio get index failed\n"); + return PTR_ERR(gpio); + } - return ret; + ret = gpiod_to_irq(gpio); + dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret); -exit_err: - dev_err(&client->dev, "failed to change sensor mode\n"); return ret; } @@ -274,14 +451,78 @@ static int stk8ba50_probe(struct i2c_client *client, /* The default sampling rate is 1792 Hz (maximum) */ data->sample_rate_idx = STK8BA50_SR_1792HZ_IDX; + /* Set up interrupts */ + ret = i2c_smbus_write_byte_data(client, + STK8BA50_REG_INTEN2, STK8BA50_DREADY_INT_MASK); + if (ret < 0) { + dev_err(&client->dev, "failed to set up interrupts\n"); + goto err_power_off; + } + ret = i2c_smbus_write_byte_data(client, + STK8BA50_REG_INTMAP2, STK8BA50_DREADY_INT_MAP); + if (ret < 0) { + dev_err(&client->dev, "failed to set up interrupts\n"); + goto err_power_off; + } + + if (client->irq < 0) + client->irq = stk8ba50_gpio_probe(client); + + if (client->irq >= 0) { + ret = devm_request_threaded_irq(&client->dev, client->irq, + stk8ba50_data_rdy_trig_poll, + NULL, + IRQF_TRIGGER_RISING | + IRQF_ONESHOT, + STK8BA50_IRQ_NAME, + indio_dev); + if (ret < 0) { + dev_err(&client->dev, "request irq %d failed\n", + client->irq); + goto err_power_off; + } + + data->dready_trig = devm_iio_trigger_alloc(&client->dev, + "%s-dev%d", + indio_dev->name, + indio_dev->id); + if (!data->dready_trig) { + ret = -ENOMEM; + goto err_power_off; + } + + data->dready_trig->dev.parent = &client->dev; + data->dready_trig->ops = &stk8ba50_trigger_ops; + iio_trigger_set_drvdata(data->dready_trig, indio_dev); + ret = iio_trigger_register(data->dready_trig); + if (ret) { + dev_err(&client->dev, "iio trigger register failed\n"); + goto err_power_off; + } + } + + ret = iio_triggered_buffer_setup(indio_dev, + iio_pollfunc_store_time, + stk8ba50_trigger_handler, + &stk8ba50_buffer_setup_ops); + if (ret < 0) { + dev_err(&client->dev, "iio triggered buffer setup failed\n"); + goto err_trigger_unregister; + } + ret = iio_device_register(indio_dev); if (ret < 0) { dev_err(&client->dev, "device_register failed\n"); - goto err_power_off; + goto err_buffer_cleanup; } return ret; +err_buffer_cleanup: + iio_triggered_buffer_cleanup(indio_dev); +err_trigger_unregister: + if (data->dready_trig) + iio_trigger_unregister(data->dready_trig); err_power_off: stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND); return ret; @@ -290,10 +531,15 @@ err_power_off: static int stk8ba50_remove(struct i2c_client *client) { struct iio_dev *indio_dev = i2c_get_clientdata(client); + struct stk8ba50_data *data = iio_priv(indio_dev); iio_device_unregister(indio_dev); + iio_triggered_buffer_cleanup(indio_dev); + + if (data->dready_trig) + iio_trigger_unregister(data->dready_trig); - return stk8ba50_set_power(iio_priv(indio_dev), STK8BA50_MODE_SUSPEND); + return stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND); } #ifdef CONFIG_PM_SLEEP -- cgit v1.2.3 From 95c12bba51c37359073b34f1a56fe396bd33d3cf Mon Sep 17 00:00:00 2001 From: Tiberiu Breana Date: Wed, 24 Jun 2015 17:01:48 +0300 Subject: iio: accel: Add buffer mode for Sensortek STK8312 Added triggered buffer mode support for the STK8312 accelerometer. Additional changes: - set_mode now sets operation mode directly, no longer masking the register's previous value - read_accel now returns raw acceleration data instead of the sign_extend32 value - read_raw will now enable/disable the sensor with each reading Signed-off-by: Tiberiu Breana Signed-off-by: Jonathan Cameron --- drivers/iio/accel/stk8312.c | 300 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 265 insertions(+), 35 deletions(-) diff --git a/drivers/iio/accel/stk8312.c b/drivers/iio/accel/stk8312.c index d211d9f3975b..be58d66d5d33 100644 --- a/drivers/iio/accel/stk8312.c +++ b/drivers/iio/accel/stk8312.c @@ -11,16 +11,23 @@ */ #include +#include #include +#include #include #include #include +#include #include #include +#include +#include +#include #define STK8312_REG_XOUT 0x00 #define STK8312_REG_YOUT 0x01 #define STK8312_REG_ZOUT 0x02 +#define STK8312_REG_INTSU 0x06 #define STK8312_REG_MODE 0x07 #define STK8312_REG_STH 0x13 #define STK8312_REG_RESET 0x20 @@ -29,14 +36,19 @@ #define STK8312_REG_OTPDATA 0x3E #define STK8312_REG_OTPCTRL 0x3F -#define STK8312_MODE_ACTIVE 1 -#define STK8312_MODE_STANDBY 0 -#define STK8312_MODE_MASK 0x01 +#define STK8312_MODE_ACTIVE 0x01 +#define STK8312_MODE_STANDBY 0x00 +#define STK8312_DREADY_BIT 0x10 +#define STK8312_INT_MODE 0xC0 #define STK8312_RNG_MASK 0xC0 #define STK8312_RNG_SHIFT 6 #define STK8312_READ_RETRIES 16 +#define STK8312_ALL_CHANNEL_MASK 7 +#define STK8312_ALL_CHANNEL_SIZE 3 #define STK8312_DRIVER_NAME "stk8312" +#define STK8312_GPIO "stk8312_gpio" +#define STK8312_IRQ_NAME "stk8312_event" /* * The accelerometer has two measurement ranges: @@ -53,19 +65,27 @@ static const int stk8312_scale_table[][2] = { {0, 461600}, {1, 231100} }; -#define STK8312_ACCEL_CHANNEL(reg, axis) { \ +#define STK8312_ACCEL_CHANNEL(index, reg, axis) { \ .type = IIO_ACCEL, \ .address = reg, \ .modified = 1, \ .channel2 = IIO_MOD_##axis, \ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .scan_index = index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 8, \ + .storagebits = 8, \ + .endianness = IIO_CPU, \ + }, \ } static const struct iio_chan_spec stk8312_channels[] = { - STK8312_ACCEL_CHANNEL(STK8312_REG_XOUT, X), - STK8312_ACCEL_CHANNEL(STK8312_REG_YOUT, Y), - STK8312_ACCEL_CHANNEL(STK8312_REG_ZOUT, Z), + STK8312_ACCEL_CHANNEL(0, STK8312_REG_XOUT, X), + STK8312_ACCEL_CHANNEL(1, STK8312_REG_YOUT, Y), + STK8312_ACCEL_CHANNEL(2, STK8312_REG_ZOUT, Z), + IIO_CHAN_SOFT_TIMESTAMP(3), }; struct stk8312_data { @@ -73,6 +93,9 @@ struct stk8312_data { struct mutex lock; int range; u8 mode; + struct iio_trigger *dready_trig; + bool dready_trigger_on; + s8 buffer[16]; /* 3x8-bit channels + 5x8 padding + 64-bit timestamp */ }; static IIO_CONST_ATTR(in_accel_scale_available, STK8312_SCALE_AVAIL); @@ -130,31 +153,19 @@ exit_err: static int stk8312_set_mode(struct stk8312_data *data, u8 mode) { int ret; - u8 masked_reg; struct i2c_client *client = data->client; - if (mode > 1) - return -EINVAL; - else if (mode == data->mode) + if (mode == data->mode) return 0; - ret = i2c_smbus_read_byte_data(client, STK8312_REG_MODE); - if (ret < 0) { - dev_err(&client->dev, "failed to change sensor mode\n"); - return ret; - } - masked_reg = ret & (~STK8312_MODE_MASK); - masked_reg |= mode; - - ret = i2c_smbus_write_byte_data(client, - STK8312_REG_MODE, masked_reg); + ret = i2c_smbus_write_byte_data(client, STK8312_REG_MODE, mode); if (ret < 0) { dev_err(&client->dev, "failed to change sensor mode\n"); return ret; } data->mode = mode; - if (mode == STK8312_MODE_ACTIVE) { + if (mode & STK8312_MODE_ACTIVE) { /* Need to run OTP sequence before entering active mode */ usleep_range(1000, 5000); ret = stk8312_otp_init(data); @@ -163,6 +174,52 @@ static int stk8312_set_mode(struct stk8312_data *data, u8 mode) return ret; } +static int stk8312_set_interrupts(struct stk8312_data *data, u8 int_mask) +{ + int ret; + u8 mode; + struct i2c_client *client = data->client; + + mode = data->mode; + /* We need to go in standby mode to modify registers */ + ret = stk8312_set_mode(data, STK8312_MODE_STANDBY); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, STK8312_REG_INTSU, int_mask); + if (ret < 0) + dev_err(&client->dev, "failed to set interrupts\n"); + + return stk8312_set_mode(data, mode); +} + +static int stk8312_data_rdy_trigger_set_state(struct iio_trigger *trig, + bool state) +{ + struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); + struct stk8312_data *data = iio_priv(indio_dev); + int ret; + + if (state) + ret = stk8312_set_interrupts(data, STK8312_DREADY_BIT); + else + ret = stk8312_set_interrupts(data, 0x00); + + if (ret < 0) { + dev_err(&data->client->dev, "failed to set trigger state\n"); + return ret; + } + + data->dready_trigger_on = state; + + return ret; +} + +static const struct iio_trigger_ops stk8312_trigger_ops = { + .set_trigger_state = stk8312_data_rdy_trigger_set_state, + .owner = THIS_MODULE, +}; + static int stk8312_set_range(struct stk8312_data *data, u8 range) { int ret; @@ -208,12 +265,10 @@ static int stk8312_read_accel(struct stk8312_data *data, u8 address) return -EINVAL; ret = i2c_smbus_read_byte_data(client, address); - if (ret < 0) { + if (ret < 0) dev_err(&client->dev, "register read failed\n"); - return ret; - } - return sign_extend32(ret, 7); + return ret; } static int stk8312_read_raw(struct iio_dev *indio_dev, @@ -221,14 +276,27 @@ static int stk8312_read_raw(struct iio_dev *indio_dev, int *val, int *val2, long mask) { struct stk8312_data *data = iio_priv(indio_dev); - - if (chan->type != IIO_ACCEL) - return -EINVAL; + int ret; switch (mask) { case IIO_CHAN_INFO_RAW: + if (iio_buffer_enabled(indio_dev)) + return -EBUSY; mutex_lock(&data->lock); - *val = stk8312_read_accel(data, chan->address); + ret = stk8312_set_mode(data, data->mode | STK8312_MODE_ACTIVE); + if (ret < 0) { + mutex_unlock(&data->lock); + return -EINVAL; + } + ret = stk8312_read_accel(data, chan->address); + if (ret < 0) { + stk8312_set_mode(data, + data->mode & (~STK8312_MODE_ACTIVE)); + mutex_unlock(&data->lock); + return -EINVAL; + } + *val = sign_extend32(ret, 7); + stk8312_set_mode(data, data->mode & (~STK8312_MODE_ACTIVE)); mutex_unlock(&data->lock); return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: @@ -277,6 +345,109 @@ static const struct iio_info stk8312_info = { .attrs = &stk8312_attribute_group, }; +static irqreturn_t stk8312_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct stk8312_data *data = iio_priv(indio_dev); + int bit, ret, i = 0; + u8 buffer[STK8312_ALL_CHANNEL_SIZE]; + + mutex_lock(&data->lock); + /* + * Do a bulk read if all channels are requested, + * from 0x00 (XOUT) to 0x02 (ZOUT) + */ + if (*(indio_dev->active_scan_mask) == STK8312_ALL_CHANNEL_MASK) { + ret = i2c_smbus_read_i2c_block_data(data->client, + STK8312_REG_XOUT, + STK8312_ALL_CHANNEL_SIZE, + buffer); + if (ret < STK8312_ALL_CHANNEL_SIZE) { + dev_err(&data->client->dev, "register read failed\n"); + mutex_unlock(&data->lock); + goto err; + } + data->buffer[0] = buffer[0]; + data->buffer[1] = buffer[1]; + data->buffer[2] = buffer[2]; + } else { + for_each_set_bit(bit, indio_dev->active_scan_mask, + indio_dev->masklength) { + ret = stk8312_read_accel(data, bit); + if (ret < 0) { + mutex_unlock(&data->lock); + goto err; + } + data->buffer[i++] = ret; + } + } + mutex_unlock(&data->lock); + + iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, + pf->timestamp); +err: + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static irqreturn_t stk8312_data_rdy_trig_poll(int irq, void *private) +{ + struct iio_dev *indio_dev = private; + struct stk8312_data *data = iio_priv(indio_dev); + + if (data->dready_trigger_on) + iio_trigger_poll(data->dready_trig); + + return IRQ_HANDLED; +} + +static int stk8312_buffer_preenable(struct iio_dev *indio_dev) +{ + struct stk8312_data *data = iio_priv(indio_dev); + + return stk8312_set_mode(data, data->mode | STK8312_MODE_ACTIVE); +} + +static int stk8312_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct stk8312_data *data = iio_priv(indio_dev); + + return stk8312_set_mode(data, data->mode & (~STK8312_MODE_ACTIVE)); +} + +static const struct iio_buffer_setup_ops stk8312_buffer_setup_ops = { + .preenable = stk8312_buffer_preenable, + .postenable = iio_triggered_buffer_postenable, + .predisable = iio_triggered_buffer_predisable, + .postdisable = stk8312_buffer_postdisable, +}; + +static int stk8312_gpio_probe(struct i2c_client *client) +{ + struct device *dev; + struct gpio_desc *gpio; + int ret; + + if (!client) + return -EINVAL; + + dev = &client->dev; + + /* data ready gpio interrupt pin */ + gpio = devm_gpiod_get_index(dev, STK8312_GPIO, 0, GPIOD_IN); + if (IS_ERR(gpio)) { + dev_err(dev, "acpi gpio get index failed\n"); + return PTR_ERR(gpio); + } + + ret = gpiod_to_irq(gpio); + dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret); + + return ret; +} + static int stk8312_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -312,26 +483,85 @@ static int stk8312_probe(struct i2c_client *client, if (ret < 0) return ret; - ret = stk8312_set_mode(data, STK8312_MODE_ACTIVE); + ret = stk8312_set_mode(data, STK8312_INT_MODE | STK8312_MODE_ACTIVE); if (ret < 0) return ret; + if (client->irq < 0) + client->irq = stk8312_gpio_probe(client); + + if (client->irq >= 0) { + ret = devm_request_threaded_irq(&client->dev, client->irq, + stk8312_data_rdy_trig_poll, + NULL, + IRQF_TRIGGER_RISING | + IRQF_ONESHOT, + STK8312_IRQ_NAME, + indio_dev); + if (ret < 0) { + dev_err(&client->dev, "request irq %d failed\n", + client->irq); + goto err_power_off; + } + + data->dready_trig = devm_iio_trigger_alloc(&client->dev, + "%s-dev%d", + indio_dev->name, + indio_dev->id); + if (!data->dready_trig) { + ret = -ENOMEM; + goto err_power_off; + } + + data->dready_trig->dev.parent = &client->dev; + data->dready_trig->ops = &stk8312_trigger_ops; + iio_trigger_set_drvdata(data->dready_trig, indio_dev); + ret = iio_trigger_register(data->dready_trig); + if (ret) { + dev_err(&client->dev, "iio trigger register failed\n"); + goto err_power_off; + } + } + + ret = iio_triggered_buffer_setup(indio_dev, + iio_pollfunc_store_time, + stk8312_trigger_handler, + &stk8312_buffer_setup_ops); + if (ret < 0) { + dev_err(&client->dev, "iio triggered buffer setup failed\n"); + goto err_trigger_unregister; + } + ret = iio_device_register(indio_dev); if (ret < 0) { dev_err(&client->dev, "device_register failed\n"); - stk8312_set_mode(data, STK8312_MODE_STANDBY); + goto err_buffer_cleanup; } return ret; + +err_buffer_cleanup: + iio_triggered_buffer_cleanup(indio_dev); +err_trigger_unregister: + if (data->dready_trig) + iio_trigger_unregister(data->dready_trig); +err_power_off: + stk8312_set_mode(data, STK8312_MODE_STANDBY); + return ret; } static int stk8312_remove(struct i2c_client *client) { struct iio_dev *indio_dev = i2c_get_clientdata(client); + struct stk8312_data *data = iio_priv(indio_dev); iio_device_unregister(indio_dev); + iio_triggered_buffer_cleanup(indio_dev); - return stk8312_set_mode(iio_priv(indio_dev), STK8312_MODE_STANDBY); + if (data->dready_trig) + iio_trigger_unregister(data->dready_trig); + + return stk8312_set_mode(data, STK8312_MODE_STANDBY); } #ifdef CONFIG_PM_SLEEP @@ -341,7 +571,7 @@ static int stk8312_suspend(struct device *dev) data = iio_priv(i2c_get_clientdata(to_i2c_client(dev))); - return stk8312_set_mode(data, STK8312_MODE_STANDBY); + return stk8312_set_mode(data, data->mode & (~STK8312_MODE_ACTIVE)); } static int stk8312_resume(struct device *dev) @@ -350,7 +580,7 @@ static int stk8312_resume(struct device *dev) data = iio_priv(i2c_get_clientdata(to_i2c_client(dev))); - return stk8312_set_mode(data, STK8312_MODE_ACTIVE); + return stk8312_set_mode(data, data->mode | STK8312_MODE_ACTIVE); } static SIMPLE_DEV_PM_OPS(stk8312_pm_ops, stk8312_suspend, stk8312_resume); -- cgit v1.2.3 From 5e913d27f91aa15e1311399385579bef5238e2cd Mon Sep 17 00:00:00 2001 From: Tiberiu Breana Date: Wed, 24 Jun 2015 17:01:49 +0300 Subject: iio: accel: Add sampling rate support for STK8312 Added support for setting the STK8312 accelerometer's sampling rate. Signed-off-by: Tiberiu Breana Signed-off-by: Jonathan Cameron --- drivers/iio/accel/stk8312.c | 96 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 82 insertions(+), 14 deletions(-) diff --git a/drivers/iio/accel/stk8312.c b/drivers/iio/accel/stk8312.c index be58d66d5d33..c2bd1444d6da 100644 --- a/drivers/iio/accel/stk8312.c +++ b/drivers/iio/accel/stk8312.c @@ -29,6 +29,7 @@ #define STK8312_REG_ZOUT 0x02 #define STK8312_REG_INTSU 0x06 #define STK8312_REG_MODE 0x07 +#define STK8312_REG_SR 0x08 #define STK8312_REG_STH 0x13 #define STK8312_REG_RESET 0x20 #define STK8312_REG_AFECTRL 0x24 @@ -41,6 +42,8 @@ #define STK8312_DREADY_BIT 0x10 #define STK8312_INT_MODE 0xC0 #define STK8312_RNG_MASK 0xC0 +#define STK8312_SR_MASK 0x07 +#define STK8312_SR_400HZ_IDX 0 #define STK8312_RNG_SHIFT 6 #define STK8312_READ_RETRIES 16 #define STK8312_ALL_CHANNEL_MASK 7 @@ -65,20 +68,29 @@ static const int stk8312_scale_table[][2] = { {0, 461600}, {1, 231100} }; -#define STK8312_ACCEL_CHANNEL(index, reg, axis) { \ - .type = IIO_ACCEL, \ - .address = reg, \ - .modified = 1, \ - .channel2 = IIO_MOD_##axis, \ - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ - .scan_index = index, \ - .scan_type = { \ - .sign = 's', \ - .realbits = 8, \ - .storagebits = 8, \ - .endianness = IIO_CPU, \ - }, \ +static const struct { + u16 val; + u32 val2; +} stk8312_samp_freq_table[] = { + {400, 0}, {200, 0}, {100, 0}, {50, 0}, {25, 0}, + {12, 500000}, {6, 250000}, {3, 125000} +}; + +#define STK8312_ACCEL_CHANNEL(index, reg, axis) { \ + .type = IIO_ACCEL, \ + .address = reg, \ + .modified = 1, \ + .channel2 = IIO_MOD_##axis, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index = index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 8, \ + .storagebits = 8, \ + .endianness = IIO_CPU, \ + }, \ } static const struct iio_chan_spec stk8312_channels[] = { @@ -92,6 +104,7 @@ struct stk8312_data { struct i2c_client *client; struct mutex lock; int range; + u8 sample_rate_idx; u8 mode; struct iio_trigger *dready_trig; bool dready_trigger_on; @@ -100,8 +113,11 @@ struct stk8312_data { static IIO_CONST_ATTR(in_accel_scale_available, STK8312_SCALE_AVAIL); +static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("3.125 6.25 12.5 25 50 100 200 400"); + static struct attribute *stk8312_attributes[] = { &iio_const_attr_in_accel_scale_available.dev_attr.attr, + &iio_const_attr_sampling_frequency_available.dev_attr.attr, NULL, }; @@ -220,6 +236,39 @@ static const struct iio_trigger_ops stk8312_trigger_ops = { .owner = THIS_MODULE, }; +static int stk8312_set_sample_rate(struct stk8312_data *data, int rate) +{ + int ret; + u8 masked_reg; + u8 mode; + struct i2c_client *client = data->client; + + if (rate == data->sample_rate_idx) + return 0; + + mode = data->mode; + /* We need to go in standby mode to modify registers */ + ret = stk8312_set_mode(data, STK8312_MODE_STANDBY); + if (ret < 0) + return ret; + + ret = i2c_smbus_read_byte_data(client, STK8312_REG_SR); + if (ret < 0) { + dev_err(&client->dev, "failed to set sampling rate\n"); + return ret; + } + + masked_reg = (ret & (~STK8312_SR_MASK)) | rate; + + ret = i2c_smbus_write_byte_data(client, STK8312_REG_SR, masked_reg); + if (ret < 0) + dev_err(&client->dev, "failed to set sampling rate\n"); + else + data->sample_rate_idx = rate; + + return stk8312_set_mode(data, mode); +} + static int stk8312_set_range(struct stk8312_data *data, u8 range) { int ret; @@ -303,6 +352,10 @@ static int stk8312_read_raw(struct iio_dev *indio_dev, *val = stk8312_scale_table[data->range - 1][0]; *val2 = stk8312_scale_table[data->range - 1][1]; return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_SAMP_FREQ: + *val = stk8312_samp_freq_table[data->sample_rate_idx].val; + *val2 = stk8312_samp_freq_table[data->sample_rate_idx].val2; + return IIO_VAL_INT_PLUS_MICRO; } return -EINVAL; @@ -332,6 +385,20 @@ static int stk8312_write_raw(struct iio_dev *indio_dev, ret = stk8312_set_range(data, index); mutex_unlock(&data->lock); + return ret; + case IIO_CHAN_INFO_SAMP_FREQ: + for (i = 0; i < ARRAY_SIZE(stk8312_samp_freq_table); i++) + if (val == stk8312_samp_freq_table[i].val && + val2 == stk8312_samp_freq_table[i].val2) { + index = i; + break; + } + if (index < 0) + return -EINVAL; + mutex_lock(&data->lock); + ret = stk8312_set_sample_rate(data, index); + mutex_unlock(&data->lock); + return ret; } @@ -479,6 +546,7 @@ static int stk8312_probe(struct i2c_client *client, dev_err(&client->dev, "failed to reset sensor\n"); return ret; } + data->sample_rate_idx = STK8312_SR_400HZ_IDX; ret = stk8312_set_range(data, 1); if (ret < 0) return ret; -- cgit v1.2.3 From fcc577dd55db193926537e0e4de98492d665446b Mon Sep 17 00:00:00 2001 From: Cristina Opriceana Date: Tue, 23 Jun 2015 16:34:19 +0300 Subject: iio: Fix parameters in iio_triggered_buffer_setup This patch renames the top half handler and the bottom half handler of iio_triggered_buffer_setup() in accordance with their usage. The bottom half has been renamed to reflect the fact that it is a thread based call, compliant with iio_alloc_pollfunc(). The names of the parameters were swapped, thus creating confusion. Signed-off-by: Cristina Opriceana Signed-off-by: Jonathan Cameron --- drivers/iio/industrialio-triggered-buffer.c | 12 ++++++------ include/linux/iio/triggered_buffer.h | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/iio/industrialio-triggered-buffer.c b/drivers/iio/industrialio-triggered-buffer.c index 15a5341b5e7b..4b2858ba1fd6 100644 --- a/drivers/iio/industrialio-triggered-buffer.c +++ b/drivers/iio/industrialio-triggered-buffer.c @@ -24,8 +24,8 @@ static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = { /** * iio_triggered_buffer_setup() - Setup triggered buffer and pollfunc * @indio_dev: IIO device structure - * @pollfunc_bh: Function which will be used as pollfunc bottom half - * @pollfunc_th: Function which will be used as pollfunc top half + * @h: Function which will be used as pollfunc top half + * @thread: Function which will be used as pollfunc bottom half * @setup_ops: Buffer setup functions to use for this device. * If NULL the default setup functions for triggered * buffers will be used. @@ -42,8 +42,8 @@ static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = { * iio_triggered_buffer_cleanup(). */ int iio_triggered_buffer_setup(struct iio_dev *indio_dev, - irqreturn_t (*pollfunc_bh)(int irq, void *p), - irqreturn_t (*pollfunc_th)(int irq, void *p), + irqreturn_t (*h)(int irq, void *p), + irqreturn_t (*thread)(int irq, void *p), const struct iio_buffer_setup_ops *setup_ops) { struct iio_buffer *buffer; @@ -57,8 +57,8 @@ int iio_triggered_buffer_setup(struct iio_dev *indio_dev, iio_device_attach_buffer(indio_dev, buffer); - indio_dev->pollfunc = iio_alloc_pollfunc(pollfunc_bh, - pollfunc_th, + indio_dev->pollfunc = iio_alloc_pollfunc(h, + thread, IRQF_ONESHOT, indio_dev, "%s_consumer%d", diff --git a/include/linux/iio/triggered_buffer.h b/include/linux/iio/triggered_buffer.h index c378ebec605e..f72f70d5a97b 100644 --- a/include/linux/iio/triggered_buffer.h +++ b/include/linux/iio/triggered_buffer.h @@ -7,8 +7,8 @@ struct iio_dev; struct iio_buffer_setup_ops; int iio_triggered_buffer_setup(struct iio_dev *indio_dev, - irqreturn_t (*pollfunc_bh)(int irq, void *p), - irqreturn_t (*pollfunc_th)(int irq, void *p), + irqreturn_t (*h)(int irq, void *p), + irqreturn_t (*thread)(int irq, void *p), const struct iio_buffer_setup_ops *setup_ops); void iio_triggered_buffer_cleanup(struct iio_dev *indio_dev); -- cgit v1.2.3 From e6b54649adacafb22c0c2d0496baf5396f8ed0be Mon Sep 17 00:00:00 2001 From: Romain Perier Date: Sat, 20 Jun 2015 12:27:16 +0000 Subject: ARM: dts: rockchip: Add STMMAC reset signal in GMAC interface for rk3288 Which fixes warning "no reset control found" by the same time Signed-off-by: Romain Perier Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 22316d00493e..47476d5d5227 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -447,6 +447,8 @@ "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac"; + resets = <&cru SRST_MAC>; + reset-names = "stmmaceth"; status = "disabled"; }; -- cgit v1.2.3 From 270c7b18d7c0f17cfda2bbdafba25ef2f885f9a5 Mon Sep 17 00:00:00 2001 From: Romain Perier Date: Mon, 15 Jun 2015 17:41:41 +0000 Subject: ARM: dts: rockchip: Add ramp delay for vdd_cpu in firefly board dts Adds ramp delay for the vdd_cpu output. It removes warning "ramp_delay not set" emitted by the function regulator_set_voltage_time_sel() by the same time, which floods kernel logs. Signed-off-by: Romain Perier Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-firefly.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 0b42372e4379..0c66e92a8885 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -213,6 +213,8 @@ regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-ramp-delay = <8000>; vin-supply = <&vcc_sys>; }; -- cgit v1.2.3 From 1a1b698b115467242303daf5fe1d3c9886c2fa17 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 19 Jun 2015 16:31:14 +0200 Subject: ARM: dts: rockchip: fix rk3288 watchdog irq The watchdog irq is actually SPI 79, which translates to the original 111 in the manual where the SPI irqs start at 32. The current dw_wdt driver does not use the irq at all, so this issue never surfaced. Nevertheless fix this for a time we want to use the irq. Fixes: 2ab557b72d46 ("ARM: dts: rockchip: add core rk3288 dtsi") Signed-off-by: Heiko Stuebner Reviewed-by: Douglas Anderson --- arch/arm/boot/dts/rk3288.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 47476d5d5227..22e9221877c6 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -628,7 +628,7 @@ compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; reg = <0xff800000 0x100>; clocks = <&cru PCLK_WDT>; - interrupts = ; + interrupts = ; status = "disabled"; }; -- cgit v1.2.3 From 33939403112791866da6b64875385fa1b7d9865a Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Wed, 20 May 2015 13:34:08 -0700 Subject: ARM: rockchip: restore dapswjdp after suspend In the commit (0ea001d ARM: rockchip: disable dapswjdp during suspend) we made the assumption that we didn't need to restore dapswjdp after suspend because "the MASKROM will enable it back". It turns out that's not a safe assumption. In some cases (pending interrupts) it's possible that the WFI might act as a no-op and the MaskROM will never run. Since we're changing the bit, we should restore it ourselves. Signed-off-by: Doug Anderson Reviewed-by: Chris Zhong Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/pm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index b0dcbe28f78c..a7be4657af70 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c @@ -48,6 +48,7 @@ static struct regmap *sgrf_regmap; static u32 rk3288_pmu_pwr_mode_con; static u32 rk3288_sgrf_soc_con0; +static u32 rk3288_sgrf_cpu_con0; static inline u32 rk3288_l2_config(void) { @@ -70,6 +71,7 @@ static void rk3288_slp_mode_set(int level) { u32 mode_set, mode_set1; + regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0); regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, @@ -129,6 +131,9 @@ static void rk3288_slp_mode_set(int level) static void rk3288_slp_mode_set_resume(void) { + regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, + rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE); + regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, rk3288_pmu_pwr_mode_con); -- cgit v1.2.3 From fe4407c0dc58215a7abfb7532740d79ddabe7a7a Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 9 Jun 2015 17:49:57 +0800 Subject: ARM: rockchip: fix the CPU soft reset We need different orderings when turning a core on and turning a core off. In one case we need to assert reset before turning power off. In ther other case we need to turn power on and the deassert reset. In general, the correct flow is: CPU off: reset_control_assert regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd)) wait_for_power_domain_to_turn_off CPU on: regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0) wait_for_power_domain_to_turn_on reset_control_deassert This is needed for stressing CPU up/down, as per: cd /sys/devices/system/cpu/ for i in $(seq 10000); do echo "================= $i ============" for j in $(seq 100); do while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "000"" ]] echo 0 > cpu1/online echo 0 > cpu2/online echo 0 > cpu3/online done while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "111" ]]; do echo 1 > cpu1/online echo 1 > cpu2/online echo 1 > cpu3/online done done done The following is reproducable log: [34466.186812] PM: noirq suspend of devices complete after 0.669 msecs [34466.186824] Disabling non-boot CPUs ... [34466.187509] CPU1: shutdown [34466.188672] CPU2: shutdown [34473.736627] Kernel panic - not syncing:Watchdog detected hard LOCKUP on cpu 0 ....... or others similar log: ....... [ 4072.454453] CPU1: shutdown [ 4072.504436] CPU2: shutdown [ 4072.554426] CPU3: shutdown [ 4072.577827] CPU1: Booted secondary processor [ 4072.582611] CPU2: Booted secondary processor Tested by cpu up/down scripts, the results told us need delay more time before write the sram. The wait time is affected by many aspects (e.g: cpu frequency, bootrom frequency, sram frequency, bus speed, ...). Although the cpus other than cpu0 will write the sram, the speedy is no the same as cpu0, if the cpu0 early wake up, perhaps the other cpus can't startup. As we know, the cpu0 can wake up when the cpu1/2/3 write the 'sram+4/8' and send the sev. Anyway..... At the moment, 1ms delay will be happy work for cpu up/down scripts test. Signed-off-by: Caesar Wang Reviewed-by: Doug Anderson Reviewed-by: Kever Yang Fixes: 3ee851e212d0 ("ARM: rockchip: add basic smp support for rk3288") Cc: stable@vger.kernel.org Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/platsmp.c | 40 ++++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 8fcec1cc101e..d1a5fec68887 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -72,29 +72,22 @@ static struct reset_control *rockchip_get_core_reset(int cpu) static int pmu_set_power_domain(int pd, bool on) { u32 val = (on) ? 0 : BIT(pd); + struct reset_control *rstc = rockchip_get_core_reset(pd); int ret; + if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { + pr_err("%s: could not get reset control for core %d\n", + __func__, pd); + return PTR_ERR(rstc); + } + /* * We need to soft reset the cpu when we turn off the cpu power domain, * or else the active processors might be stalled when the individual * processor is powered down. */ - if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { - struct reset_control *rstc = rockchip_get_core_reset(pd); - - if (IS_ERR(rstc)) { - pr_err("%s: could not get reset control for core %d\n", - __func__, pd); - return PTR_ERR(rstc); - } - - if (on) - reset_control_deassert(rstc); - else - reset_control_assert(rstc); - - reset_control_put(rstc); - } + if (!IS_ERR(rstc) && !on) + reset_control_assert(rstc); ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); if (ret < 0) { @@ -112,6 +105,12 @@ static int pmu_set_power_domain(int pd, bool on) } } + if (!IS_ERR(rstc)) { + if (on) + reset_control_deassert(rstc); + reset_control_put(rstc); + } + return 0; } @@ -146,9 +145,14 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) * the mailbox: * sram_base_addr + 4: 0xdeadbeaf * sram_base_addr + 8: start address for pc + * The cpu0 need to wait the other cpus other than cpu0 entering + * the wfe state.The wait time is affected by many aspects. + * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) * */ - udelay(10); - writel(virt_to_phys(secondary_startup), sram_base_addr + 8); + mdelay(1); /* ensure the cpus other than cpu0 to startup */ + + writel(virt_to_phys(rockchip_secondary_startup), + sram_base_addr + 8); writel(0xDEADBEAF, sram_base_addr + 4); dsb_sev(); } -- cgit v1.2.3 From e306bc16c53199e7440e1fee69dd91dc0a56edee Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 9 Jun 2015 17:49:58 +0800 Subject: ARM: rockchip: ensure CPU to enter WFI/WFE state The patch can ensure that v7_exit_coherency_flush() in rockchip_cpu_die() executed in time. The mdelay(1) has enough time to fix the problem of CPU offlining. That's a workaround way in rockchip hotplug code, At least, we haven't a better way to solve it. Who know, that maybe fixed by chip (hardware) in the future. Signed-off-by: Caesar Wang Reviewed-by: Douglas Anderson Reviewed-by: Kever Yang Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/platsmp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index d1a5fec68887..4187ac2b01b3 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -321,6 +321,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) #ifdef CONFIG_HOTPLUG_CPU static int rockchip_cpu_kill(unsigned int cpu) { + /* + * We need a delay here to ensure that the dying CPU can finish + * executing v7_coherency_exit() and reach the WFI/WFE state + * prior to having the power domain disabled. + */ + mdelay(1); + pmu_set_power_domain(0 + cpu, false); return 1; } -- cgit v1.2.3 From 7f0b61ad34f04b076a3d1e2b5cfc6e1fae853ec4 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 9 Jun 2015 17:49:59 +0800 Subject: ARM: rockchip: fix the SMP code style Use the below scripts to check: scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c Signed-off-by: Caesar Wang Reviewed-by: Douglas Anderson Reviewed-by: Kever Yang Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/platsmp.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 4187ac2b01b3..7ebd1c1a98c6 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -100,7 +100,7 @@ static int pmu_set_power_domain(int pd, bool on) ret = pmu_power_domain_is_on(pd); if (ret < 0) { pr_err("%s: could not read power domain state\n", - __func__); + __func__); return ret; } } @@ -129,7 +129,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) if (cpu >= ncores) { pr_err("%s: cpu %d outside maximum number of cpus %d\n", - __func__, cpu, ncores); + __func__, cpu, ncores); return -ENXIO; } @@ -139,7 +139,8 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) return ret; if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { - /* We communicate with the bootrom to active the cpus other + /* + * We communicate with the bootrom to active the cpus other * than cpu0, after a blob of initialize code, they will * stay at wfe state, once they are actived, they will check * the mailbox: @@ -148,11 +149,11 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) * The cpu0 need to wait the other cpus other than cpu0 entering * the wfe state.The wait time is affected by many aspects. * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) - * */ + */ mdelay(1); /* ensure the cpus other than cpu0 to startup */ writel(virt_to_phys(rockchip_secondary_startup), - sram_base_addr + 8); + sram_base_addr + 8); writel(0xDEADBEAF, sram_base_addr + 4); dsb_sev(); } @@ -335,7 +336,7 @@ static int rockchip_cpu_kill(unsigned int cpu) static void rockchip_cpu_die(unsigned int cpu) { v7_exit_coherency_flush(louis); - while(1) + while (1) cpu_do_idle(); } #endif @@ -348,4 +349,5 @@ static struct smp_operations rockchip_smp_ops __initdata = { .cpu_die = rockchip_cpu_die, #endif }; + CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); -- cgit v1.2.3 From 134f1f609bdf2f67ae23b7b1b686a3b9d5c67b03 Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Tue, 23 Jun 2015 20:53:39 +0800 Subject: ARM: rockchip: add support holding 24Mhz osc during suspend If we want to wake up system via usb, the 24Mhz osc could not be disabled during suspend, read the usb phy SIDDQ bit to decide whether to switch to 32khz clock-in. Signed-off-by: Chris Zhong Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/pm.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index a7be4657af70..892bace139be 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c @@ -45,6 +45,7 @@ static phys_addr_t rk3288_bootram_phy; static struct regmap *pmu_regmap; static struct regmap *sgrf_regmap; +static struct regmap *grf_regmap; static u32 rk3288_pmu_pwr_mode_con; static u32 rk3288_sgrf_soc_con0; @@ -67,9 +68,35 @@ static void rk3288_config_bootdata(void) rkpm_bootdata_l2ctlr = rk3288_l2_config(); } +#define GRF_UOC0_CON0 0x320 +#define GRF_UOC1_CON0 0x334 +#define GRF_UOC2_CON0 0x348 +#define GRF_SIDDQ BIT(13) + +static bool rk3288_slp_disable_osc(void) +{ + static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0, + GRF_UOC2_CON0 }; + u32 reg, i; + + /* + * if any usb phy is still on(GRF_SIDDQ==0), that means we need the + * function of usb wakeup, so do not switch to 32khz, since the usb phy + * clk does not connect to 32khz osc + */ + for (i = 0; i < ARRAY_SIZE(reg_offset); i++) { + regmap_read(grf_regmap, reg_offset[i], ®); + if (!(reg & GRF_SIDDQ)) + return false; + } + + return true; +} + static void rk3288_slp_mode_set(int level) { u32 mode_set, mode_set1; + bool osc_switch_to_32k = rk3288_slp_disable_osc(); regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0); regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); @@ -109,11 +136,13 @@ static void rk3288_slp_mode_set(int level) if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) { /* arm off, logic deep sleep */ - mode_set |= BIT(PMU_BUS_PD_EN) | + mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) | BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) | - BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) | BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN); + if (osc_switch_to_32k) + mode_set |= BIT(PMU_OSC_24M_DIS); + mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) | BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA); } else { @@ -198,6 +227,13 @@ static int rk3288_suspend_init(struct device_node *np) return PTR_ERR(pmu_regmap); } + grf_regmap = syscon_regmap_lookup_by_compatible( + "rockchip,rk3288-grf"); + if (IS_ERR(grf_regmap)) { + pr_err("%s: could not find grf regmap\n", __func__); + return PTR_ERR(pmu_regmap); + } + sram_np = of_find_compatible_node(NULL, NULL, "rockchip,rk3288-pmu-sram"); if (!sram_np) { -- cgit v1.2.3 From e6ef15e4f6ca9cc760030f8f0616e25eed9449e4 Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Tue, 23 Jun 2015 20:53:40 +0800 Subject: ARM: rockchip: remove some useless macro in pm.h These are actually not used in the pm code, as we moved suspend handling to the clock driver, remove them here. Signed-off-by: Chris Zhong Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/pm.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h index 3e8d39c0c3d5..b6494c2bd761 100644 --- a/arch/arm/mach-rockchip/pm.h +++ b/arch/arm/mach-rockchip/pm.h @@ -59,13 +59,6 @@ static inline void rockchip_suspend_init(void) #define SGRF_DAPDEVICEEN BIT(0) #define SGRF_DAPDEVICEEN_WRITE BIT(16) -#define RK3288_CRU_MODE_CON 0x50 -#define RK3288_CRU_SEL0_CON 0x60 -#define RK3288_CRU_SEL1_CON 0x64 -#define RK3288_CRU_SEL10_CON 0x88 -#define RK3288_CRU_SEL33_CON 0xe4 -#define RK3288_CRU_SEL37_CON 0xf4 - /* PMU_WAKEUP_CFG1 bits */ #define PMU_ARMINT_WAKEUP_EN BIT(0) -- cgit v1.2.3 From 23758258220c2fcdabb30a3c6fe0a3ce6c705550 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 4 Jun 2015 20:22:25 +0200 Subject: ARM: shmobile: R-Mobile: Move to_rmobile_pd from header to source file to_rmobile_pd() is only used inside pm-rmobile.c Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/pm-rmobile.c | 6 ++++++ arch/arm/mach-shmobile/pm-rmobile.h | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c index 95018209ff0b..94161c9b1878 100644 --- a/arch/arm/mach-shmobile/pm-rmobile.c +++ b/arch/arm/mach-shmobile/pm-rmobile.c @@ -34,6 +34,12 @@ #define PSTR_RETRIES 100 #define PSTR_DELAY_US 10 +static inline +struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d) +{ + return container_of(d, struct rmobile_pm_domain, genpd); +} + static int rmobile_pd_power_down(struct generic_pm_domain *genpd) { struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd); diff --git a/arch/arm/mach-shmobile/pm-rmobile.h b/arch/arm/mach-shmobile/pm-rmobile.h index 53219786f539..3992b619c127 100644 --- a/arch/arm/mach-shmobile/pm-rmobile.h +++ b/arch/arm/mach-shmobile/pm-rmobile.h @@ -26,12 +26,6 @@ struct rmobile_pm_domain { bool no_debug; }; -static inline -struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d) -{ - return container_of(d, struct rmobile_pm_domain, genpd); -} - struct pm_domain_device { const char *domain_name; struct platform_device *pdev; -- cgit v1.2.3 From 23e95fc2964de5a38c1c76109188756420268858 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 4 Jun 2015 20:22:26 +0200 Subject: ARM: shmobile: R-Mobile: Use BIT() macro instead of open coding Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/pm-rmobile.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c index 94161c9b1878..b9b494f5ca99 100644 --- a/arch/arm/mach-shmobile/pm-rmobile.c +++ b/arch/arm/mach-shmobile/pm-rmobile.c @@ -48,7 +48,7 @@ static int rmobile_pd_power_down(struct generic_pm_domain *genpd) if (rmobile_pd->bit_shift == ~0) return -EBUSY; - mask = 1 << rmobile_pd->bit_shift; + mask = BIT(rmobile_pd->bit_shift); if (rmobile_pd->suspend) { int ret = rmobile_pd->suspend(); @@ -85,7 +85,7 @@ static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd, if (rmobile_pd->bit_shift == ~0) return 0; - mask = 1 << rmobile_pd->bit_shift; + mask = BIT(rmobile_pd->bit_shift); if (__raw_readl(rmobile_pd->base + PSTR) & mask) goto out; -- cgit v1.2.3 From 564ec128320b3a69e7be6bed938be5b78e5aac95 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 4 Jun 2015 20:22:33 +0200 Subject: ARM: shmobile: r8a7779: Remove GENPD_FLAG_PM_CLK flag The R-Car SYSC PM Domain only manages power domains for the main CPUs and for coprocessors. It does not fill in the genpd .{at,de}tach_dev() callbacks, and no power management clocks are registered for devices. Hence pm_clk_{suspend,resume}() are no-ops, and setting of the GENPD_FLAG_PM_CLK flag can be removed. Originally the clock handling was copied from the R-Mobile PM Domain code, which does manage a clock domain, in addition to device power domains. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/pm-r8a7779.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c index 44a74c4c5a01..d5f258e4d890 100644 --- a/arch/arm/mach-shmobile/pm-r8a7779.c +++ b/arch/arm/mach-shmobile/pm-r8a7779.c @@ -83,7 +83,6 @@ static void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd) { struct generic_pm_domain *genpd = &r8a7779_pd->genpd; - genpd->flags = GENPD_FLAG_PM_CLK; pm_genpd_init(genpd, NULL, false); genpd->dev_ops.active_wakeup = pd_active_wakeup; genpd->power_off = pd_power_down; -- cgit v1.2.3 From 30f8925a57d8ad4990fca14bcf454abd91228afd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 17 Jun 2015 11:31:17 +0200 Subject: ARM: shmobile: Remove legacy board code for KZM-A9-GT The KZM-A9-GT board is sufficiently supported by DT-based and board-less SH-Mobile AG5 (sh73a0) multiplatform kernels. Hence remove the legacy board code to reduce maintenance effort. Lacking areas are: - USB (it does't work in legacy, neither), - LCDC (the LCDC is wired to the legacy INTC, which is not planned to be supported with DT). - DMAC/IPMMU (no DT bindings are planned). Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 8 - arch/arm/mach-shmobile/Makefile | 1 - arch/arm/mach-shmobile/Makefile.boot | 1 - arch/arm/mach-shmobile/board-kzm9g.c | 916 --------------------- arch/arm/mach-shmobile/include/mach/head-kzm9g.txt | 410 --------- arch/arm/mach-shmobile/include/mach/zboot.h | 5 - arch/arm/mach-shmobile/intc-sh73a0.c | 337 -------- 7 files changed, 1678 deletions(-) delete mode 100644 arch/arm/mach-shmobile/board-kzm9g.c delete mode 100644 arch/arm/mach-shmobile/include/mach/head-kzm9g.txt delete mode 100644 arch/arm/mach-shmobile/intc-sh73a0.c diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 45006479d461..3cebc4cbb8ca 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -171,14 +171,6 @@ config MACH_MARZEN select REGULATOR_FIXED_VOLTAGE if REGULATOR select USE_OF -config MACH_KZM9G - bool "KZM-A9-GT board" - depends on ARCH_SH73A0 - select ARCH_REQUIRE_GPIOLIB - select REGULATOR_FIXED_VOLTAGE if REGULATOR - select SND_SOC_AK4642 if SND_SIMPLE_CARD - select USE_OF - comment "Renesas ARM SoCs System Configuration" config CPU_HAS_INTEVT diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 89e463de4479..a4d7f5734e91 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -58,7 +58,6 @@ obj-$(CONFIG_MACH_BOCKW) += board-bockw.o obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o obj-$(CONFIG_MACH_MARZEN) += board-marzen.o obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o -obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o intc-sh73a0.o endif # Framework support diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot index e1ef19cef89c..2269b1c3c30b 100644 --- a/arch/arm/mach-shmobile/Makefile.boot +++ b/arch/arm/mach-shmobile/Makefile.boot @@ -3,7 +3,6 @@ loadaddr-y := loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 -loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 __ZRELADDR := $(sort $(loadaddr-y)) diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c deleted file mode 100644 index 260d8319fd82..000000000000 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ /dev/null @@ -1,916 +0,0 @@ -/* - * KZM-A9-GT board support - * - * Copyright (C) 2012 Kuninori Morimoto - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include