From b609338b26f5653aa211fc7af83477e2df6e3f0b Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 1 Apr 2017 15:02:25 +0200 Subject: clk: meson: mpll: use 64bit math in rate_from_params On Meson8b the MPLL parent clock (fixed_pll) has a rate of 2550MHz. Multiplying this with SDM_DEN results in a value greater than 32bits. This is not a problem on the 64bit Meson GX SoCs, but it may result in undefined behavior on the older 32bit Meson8b SoC. While rate_from_params was only introduced recently to make the math reusable from _round_rate and _recalc_rate the original bug exists much longer. Fixes: 1c50da4f27 ("clk: meson: add mpll support") Reviewed-by: Neil Armstrong Signed-off-by: Martin Blumenstingl [as discussed on the ml, use DIV_ROUND_UP_ULL] Signed-off-by: Jerome Brunet --- drivers/clk/meson/clk-mpll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index d9462b505dcc..39eab69fe51a 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -79,7 +79,7 @@ static long rate_from_params(unsigned long parent_rate, if (n2 < N2_MIN) return -EINVAL; - return (parent_rate * SDM_DEN) / divisor; + return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor); } static void params_from_rate(unsigned long requested_rate, -- cgit v1.2.3