From cfc2928cb213d5c20b6313abb2d603c0c60d7637 Mon Sep 17 00:00:00 2001 From: Amit Kumar Mahapatra Date: Fri, 30 Jun 2023 19:52:32 +0530 Subject: dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register If the WP# signal of the flash device is either not connected or is wrongly tied to GND (that includes internal pull-downs), and the software sets the status register write disable (SRWD) bit in the status register then the status register permanently becomes read-only. To avoid this added a new boolean DT property "no-wp". If this property is set in the DT then the software avoids setting the SRWD during status register write operation. Signed-off-by: Amit Kumar Mahapatra Reviewed-by: Conor Dooley Reviewed-by: Rob Herring Reviewed-by: Michael Walle Link: https://lore.kernel.org/r/20230630142233.63585-2-amit.kumar-mahapatra@amd.com Signed-off-by: Tudor Ambarus --- Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation/devicetree/bindings/mtd') diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 89959e5c47ba..97344969b02d 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -70,6 +70,21 @@ properties: be used on such systems, to denote the absence of a reliable reset mechanism. + no-wp: + type: boolean + description: + The status register write disable (SRWD) bit in status register, combined + with the WP# signal, provides hardware data protection for the device. When + the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard + strapped to LOW, the status register nonvolatile bits become read-only and + the WRITE STATUS REGISTER operation will not execute. The only way to exit + this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the + flash device is not connected or is wrongly tied to GND (that includes internal + pull-downs) then status register permanently becomes read-only as the SRWD bit + cannot be reset. This boolean flag can be used on such systems to avoid setting + the SRWD bit while writing the status register. WP# signal hard strapped to GND + can be a valid use case. + reset-gpios: description: A GPIO line connected to the RESET (active low) signal of the device. -- cgit v1.2.3 From 4b0cb4e7ab2f777c0dd07b6d381047db85801a89 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 16 Jun 2023 16:00:54 +0200 Subject: dt-bindings: mtd: spi-nor: clarify the need for spi-nor compatibles Most SPI NOR devices do not require a specific compatible, their ID can in general be discovered with the JEDEC READ ID opcode. In this case, only the "jedec,spi-nor" generic compatible is expected. Clarify this information in the compatible description to (i) help device-tree writers and (ii) prevent further attempts to extend this list with useless information. Signed-off-by: Miquel Raynal Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230616140054.2788684-1-miquel.raynal@bootlin.com [ta: s/JEDEC/JEDEC SFDP for clarity and s/JEDEC READ ID/READ ID as the opcode is not part of the JEDEC SFDP standard.] Signed-off-by: Tudor Ambarus --- Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings/mtd') diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 97344969b02d..58f0cea160ef 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -43,8 +43,10 @@ properties: - const: jedec,spi-nor - const: jedec,spi-nor description: - Must also include "jedec,spi-nor" for any SPI NOR flash that can be - identified by the JEDEC READ ID opcode (0x9F). + SPI NOR flashes compatible with the JEDEC SFDP standard or which may be + identified with the READ ID opcode (0x9F) do not deserve a specific + compatible. They should instead only be matched against the generic + "jedec,spi-nor" compatible. reg: minItems: 1 -- cgit v1.2.3