From 2467f1102dd117d4276498d30bb255796db7171c Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 27 Aug 2013 15:26:05 +0200 Subject: ARM: at91/at91-pinctrl documentation: add missing sam9x5 compatible string Add missing "atmel,at91sam9x5-pinctrl" compatible string to the documentation. Signed-off-by: Boris BREZILLON Acked-by: Nicolas Ferre Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/pinctrl') diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index 7ccae490ff6d..02ab5ab198a4 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt @@ -18,7 +18,7 @@ mode) this pin can work on and the 'config' configures various pad settings such as pull-up, multi drive, etc. Required properties for iomux controller: -- compatible: "atmel,at91rm9200-pinctrl" +- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be configured in this periph mode. All the periph and bank need to be describe. -- cgit v1.2.3 From a047914e7f123074bc8ee6f40e4502111a1b4cc4 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 2 Oct 2013 17:07:12 +0530 Subject: pinctrl: palmas: remove pin config BIAS_PULL_PIN_DEFAULT support Palmas devices do not support the default bias configuration and hence removing this option from valid pin config parameters. Acked-by: Stephen Warren Signed-off-by: Laxman Dewangan Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt | 2 +- drivers/pinctrl/pinctrl-palmas.c | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'Documentation/devicetree/bindings/pinctrl') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt index 734d9b04d533..caf297bee1fb 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt @@ -41,7 +41,7 @@ pinctrl-bindings.txt: Required: pins Options: function, bias-disable, bias-pull-up, bias-pull-down, - bias-pin-default, drive-open-drain. + drive-open-drain. Note that many of these properties are only valid for certain specific pins. See the Palmas device datasheet for complete details regarding which pins diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c index 61643815e73e..f13d0e78a41c 100644 --- a/drivers/pinctrl/pinctrl-palmas.c +++ b/drivers/pinctrl/pinctrl-palmas.c @@ -891,9 +891,6 @@ static int palmas_pinconf_set(struct pinctrl_dev *pctldev, param = pinconf_to_config_param(configs[i]); param_val = pinconf_to_config_argument(configs[i]); - if (param == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) - continue; - switch (param) { case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_UP: -- cgit v1.2.3 From d1c30115d06e255a7ba69c7b63129a92c2f34de6 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 9 Oct 2013 14:52:11 +0800 Subject: pinctrl: imx: update fsl,pins description in bindings doc While commit e164153 (pinctrl: imx: move hard-coding data into device tree) moves to use DTC macro for imx pinctrl device tree setting, it changes the semantics of fsl,pins without updating the bindings doc properly. Let's update the fsl,pins description to stop confusing people. While at it, the example in the document is updated, and the stale TODO gets removed. Signed-off-by: Shawn Guo Signed-off-by: Linus Walleij --- .../bindings/pinctrl/fsl,imx-pinctrl.txt | 37 +++++++++++----------- 1 file changed, 18 insertions(+), 19 deletions(-) (limited to 'Documentation/devicetree/bindings/pinctrl') diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt index 3a7caf7a744a..9fde25f1401a 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt @@ -22,11 +22,12 @@ Required properties for iomux controller: Please refer to each fsl,-pinctrl.txt binding doc for supported SoCs. Required properties for pin configuration node: -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, which consists of a tuple of - . CONFIG is the pad setting - value like pull-up on this pin. +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in + imx*-pinfunc.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. And that's why fsl,pins entry + looks like in the example below. Bits used for CONFIG: NO_PAD_CTL(1 << 31): indicate this pin does not need config. @@ -72,17 +73,18 @@ iomuxc@020e0000 { /* shared pinctrl settings */ usdhc4 { pinctrl_usdhc4_1: usdhc4grp-1 { - fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ - 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ - 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ - 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ - 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ - 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ - 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ - 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ - 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ - 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ - }; + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; }; .... }; @@ -90,6 +92,3 @@ Refer to the IOMUXC controller chapter in imx6q datasheet, 0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed, 80Ohm driver strength and Fast Slew Rate. User should refer to each SoC spec to set the correct value. - -TODO: when dtc macro support is available, we can change above raw data -to dt macro which can get better readability in dts file. -- cgit v1.2.3 From 5aad0db1c1ebb0f5be79f0adbecc16a2f0259b21 Mon Sep 17 00:00:00 2001 From: Christian Ruppert Date: Tue, 15 Oct 2013 15:39:38 +0200 Subject: pinctrl: add TB10x pin control driver The pinmux driver of the Abilis Systems TB10x platform based on ARC700 CPUs. Used to control the pinmux and is a prerequisite for the GPIO driver. Signed-off-by: Christian Ruppert Signed-off-by: Pierrick Hascoet Signed-off-by: Linus Walleij --- .../bindings/pinctrl/abilis,tb10x-iomux.txt | 80 ++ drivers/pinctrl/Kconfig | 4 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-tb10x.c | 886 +++++++++++++++++++++ 4 files changed, 971 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt create mode 100644 drivers/pinctrl/pinctrl-tb10x.c (limited to 'Documentation/devicetree/bindings/pinctrl') diff --git a/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt b/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt new file mode 100644 index 000000000000..2c11866221c2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt @@ -0,0 +1,80 @@ +Abilis Systems TB10x pin controller +=================================== + +Required properties +------------------- + +- compatible: should be "abilis,tb10x-iomux"; +- reg: should contain the physical address and size of the pin controller's + register range. + + +Function definitions +-------------------- + +Functions are defined (and referenced) by sub-nodes of the pin controller. +Every sub-node defines exactly one function (implying a set of pins). +Every function is associated to one named pin group inside the pin controller +driver and these names are used to associate pin group predefinitions to pin +controller sub-nodes. + +Required function definition subnode properties: + - abilis,function: should be set to the name of the function's pin group. + +The following pin groups are available: + - GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog, + gpioh, gpioi, gpioj, gpiok, gpiol, gpiom, gpion + - Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7 + - Parallel TS input ports: mip1, mip3, mip5, mip7 + - Serial TS output ports: mos0, mos1, mos2, mos3 + - Parallel TS output port: mop + - CI+ port: ciplus + - CableCard (Mcard) port: mcard + - Smart card ports: stc0, stc1 + - UART ports: uart0, uart1 + - SPI ports: spi1, spi3 + - JTAG: jtag + +All other ports of the chip are not multiplexed and thus not managed by this +driver. + + +GPIO ranges definition +---------------------- + +The named pin groups of GPIO ports can be used to define GPIO ranges as +explained in Documentation/devicetree/bindings/gpio/gpio.txt. + + +Example +------- + +iomux: iomux@FF10601c { + compatible = "abilis,tb10x-iomux"; + reg = <0xFF10601c 0x4>; + pctl_gpio_a: pctl-gpio-a { + abilis,function = "gpioa"; + }; + pctl_uart0: pctl-uart0 { + abilis,function = "uart0"; + }; +}; +uart@FF100000 { + compatible = "snps,dw-apb-uart"; + reg = <0xFF100000 0x100>; + clock-frequency = <166666666>; + interrupts = <25 1>; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pctl_uart0>; +}; +gpioa: gpio@FF140000 { + compatible = "abilis,tb10x-gpio"; + reg = <0xFF140000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpio = <3>; + gpio-ranges = <&iomux 0 0>; + gpio-ranges-group-names = "gpioa"; +}; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 85f5462460aa..e283c4970d1d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -321,6 +321,10 @@ config PINCTRL_XWAY depends on SOC_TYPE_XWAY depends on PINCTRL_LANTIQ +config PINCTRL_TB10X + bool + depends on ARC_PLAT_TB10X + endmenu endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 3d14cb855b2c..8476cd902069 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o +obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c new file mode 100644 index 000000000000..2e1ea568c9a2 --- /dev/null +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -0,0 +1,886 @@ +/* + * Abilis Systems TB10x pin control driver + * + * Copyright (C) Abilis Systems 2012 + * + * Author: Christian Ruppert + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-utils.h" + +#define TB10X_PORT1 (0) +#define TB10X_PORT2 (16) +#define TB10X_PORT3 (32) +#define TB10X_PORT4 (48) +#define TB10X_PORT5 (128) +#define TB10X_PORT6 (64) +#define TB10X_PORT7 (80) +#define TB10X_PORT8 (96) +#define TB10X_PORT9 (112) +#define TB10X_GPIOS (256) + +#define PCFG_PORT_BITWIDTH (2) +#define PCFG_PORT_MASK(PORT) \ + (((1 << PCFG_PORT_BITWIDTH) - 1) << (PCFG_PORT_BITWIDTH * (PORT))) + +static const struct pinctrl_pin_desc tb10x_pins[] = { + /* Port 1 */ + PINCTRL_PIN(TB10X_PORT1 + 0, "MICLK_S0"), + PINCTRL_PIN(TB10X_PORT1 + 1, "MISTRT_S0"), + PINCTRL_PIN(TB10X_PORT1 + 2, "MIVAL_S0"), + PINCTRL_PIN(TB10X_PORT1 + 3, "MDI_S0"), + PINCTRL_PIN(TB10X_PORT1 + 4, "GPIOA0"), + PINCTRL_PIN(TB10X_PORT1 + 5, "GPIOA1"), + PINCTRL_PIN(TB10X_PORT1 + 6, "GPIOA2"), + PINCTRL_PIN(TB10X_PORT1 + 7, "MDI_S1"), + PINCTRL_PIN(TB10X_PORT1 + 8, "MIVAL_S1"), + PINCTRL_PIN(TB10X_PORT1 + 9, "MISTRT_S1"), + PINCTRL_PIN(TB10X_PORT1 + 10, "MICLK_S1"), + /* Port 2 */ + PINCTRL_PIN(TB10X_PORT2 + 0, "MICLK_S2"), + PINCTRL_PIN(TB10X_PORT2 + 1, "MISTRT_S2"), + PINCTRL_PIN(TB10X_PORT2 + 2, "MIVAL_S2"), + PINCTRL_PIN(TB10X_PORT2 + 3, "MDI_S2"), + PINCTRL_PIN(TB10X_PORT2 + 4, "GPIOC0"), + PINCTRL_PIN(TB10X_PORT2 + 5, "GPIOC1"), + PINCTRL_PIN(TB10X_PORT2 + 6, "GPIOC2"), + PINCTRL_PIN(TB10X_PORT2 + 7, "MDI_S3"), + PINCTRL_PIN(TB10X_PORT2 + 8, "MIVAL_S3"), + PINCTRL_PIN(TB10X_PORT2 + 9, "MISTRT_S3"), + PINCTRL_PIN(TB10X_PORT2 + 10, "MICLK_S3"), + /* Port 3 */ + PINCTRL_PIN(TB10X_PORT3 + 0, "MICLK_S4"), + PINCTRL_PIN(TB10X_PORT3 + 1, "MISTRT_S4"), + PINCTRL_PIN(TB10X_PORT3 + 2, "MIVAL_S4"), + PINCTRL_PIN(TB10X_PORT3 + 3, "MDI_S4"), + PINCTRL_PIN(TB10X_PORT3 + 4, "GPIOE0"), + PINCTRL_PIN(TB10X_PORT3 + 5, "GPIOE1"), + PINCTRL_PIN(TB10X_PORT3 + 6, "GPIOE2"), + PINCTRL_PIN(TB10X_PORT3 + 7, "MDI_S5"), + PINCTRL_PIN(TB10X_PORT3 + 8, "MIVAL_S5"), + PINCTRL_PIN(TB10X_PORT3 + 9, "MISTRT_S5"), + PINCTRL_PIN(TB10X_PORT3 + 10, "MICLK_S5"), + /* Port 4 */ + PINCTRL_PIN(TB10X_PORT4 + 0, "MICLK_S6"), + PINCTRL_PIN(TB10X_PORT4 + 1, "MISTRT_S6"), + PINCTRL_PIN(TB10X_PORT4 + 2, "MIVAL_S6"), + PINCTRL_PIN(TB10X_PORT4 + 3, "MDI_S6"), + PINCTRL_PIN(TB10X_PORT4 + 4, "GPIOG0"), + PINCTRL_PIN(TB10X_PORT4 + 5, "GPIOG1"), + PINCTRL_PIN(TB10X_PORT4 + 6, "GPIOG2"), + PINCTRL_PIN(TB10X_PORT4 + 7, "MDI_S7"), + PINCTRL_PIN(TB10X_PORT4 + 8, "MIVAL_S7"), + PINCTRL_PIN(TB10X_PORT4 + 9, "MISTRT_S7"), + PINCTRL_PIN(TB10X_PORT4 + 10, "MICLK_S7"), + /* Port 5 */ + PINCTRL_PIN(TB10X_PORT5 + 0, "PC_CE1N"), + PINCTRL_PIN(TB10X_PORT5 + 1, "PC_CE2N"), + PINCTRL_PIN(TB10X_PORT5 + 2, "PC_REGN"), + PINCTRL_PIN(TB10X_PORT5 + 3, "PC_INPACKN"), + PINCTRL_PIN(TB10X_PORT5 + 4, "PC_OEN"), + PINCTRL_PIN(TB10X_PORT5 + 5, "PC_WEN"), + PINCTRL_PIN(TB10X_PORT5 + 6, "PC_IORDN"), + PINCTRL_PIN(TB10X_PORT5 + 7, "PC_IOWRN"), + PINCTRL_PIN(TB10X_PORT5 + 8, "PC_RDYIRQN"), + PINCTRL_PIN(TB10X_PORT5 + 9, "PC_WAITN"), + PINCTRL_PIN(TB10X_PORT5 + 10, "PC_A0"), + PINCTRL_PIN(TB10X_PORT5 + 11, "PC_A1"), + PINCTRL_PIN(TB10X_PORT5 + 12, "PC_A2"), + PINCTRL_PIN(TB10X_PORT5 + 13, "PC_A3"), + PINCTRL_PIN(TB10X_PORT5 + 14, "PC_A4"), + PINCTRL_PIN(TB10X_PORT5 + 15, "PC_A5"), + PINCTRL_PIN(TB10X_PORT5 + 16, "PC_A6"), + PINCTRL_PIN(TB10X_PORT5 + 17, "PC_A7"), + PINCTRL_PIN(TB10X_PORT5 + 18, "PC_A8"), + PINCTRL_PIN(TB10X_PORT5 + 19, "PC_A9"), + PINCTRL_PIN(TB10X_PORT5 + 20, "PC_A10"), + PINCTRL_PIN(TB10X_PORT5 + 21, "PC_A11"), + PINCTRL_PIN(TB10X_PORT5 + 22, "PC_A12"), + PINCTRL_PIN(TB10X_PORT5 + 23, "PC_A13"), + PINCTRL_PIN(TB10X_PORT5 + 24, "PC_A14"), + PINCTRL_PIN(TB10X_PORT5 + 25, "PC_D0"), + PINCTRL_PIN(TB10X_PORT5 + 26, "PC_D1"), + PINCTRL_PIN(TB10X_PORT5 + 27, "PC_D2"), + PINCTRL_PIN(TB10X_PORT5 + 28, "PC_D3"), + PINCTRL_PIN(TB10X_PORT5 + 29, "PC_D4"), + PINCTRL_PIN(TB10X_PORT5 + 30, "PC_D5"), + PINCTRL_PIN(TB10X_PORT5 + 31, "PC_D6"), + PINCTRL_PIN(TB10X_PORT5 + 32, "PC_D7"), + PINCTRL_PIN(TB10X_PORT5 + 33, "PC_MOSTRT"), + PINCTRL_PIN(TB10X_PORT5 + 34, "PC_MOVAL"), + PINCTRL_PIN(TB10X_PORT5 + 35, "PC_MDO0"), + PINCTRL_PIN(TB10X_PORT5 + 36, "PC_MDO1"), + PINCTRL_PIN(TB10X_PORT5 + 37, "PC_MDO2"), + PINCTRL_PIN(TB10X_PORT5 + 38, "PC_MDO3"), + PINCTRL_PIN(TB10X_PORT5 + 39, "PC_MDO4"), + PINCTRL_PIN(TB10X_PORT5 + 40, "PC_MDO5"), + PINCTRL_PIN(TB10X_PORT5 + 41, "PC_MDO6"), + PINCTRL_PIN(TB10X_PORT5 + 42, "PC_MDO7"), + PINCTRL_PIN(TB10X_PORT5 + 43, "PC_MISTRT"), + PINCTRL_PIN(TB10X_PORT5 + 44, "PC_MIVAL"), + PINCTRL_PIN(TB10X_PORT5 + 45, "PC_MDI0"), + PINCTRL_PIN(TB10X_PORT5 + 46, "PC_MDI1"), + PINCTRL_PIN(TB10X_PORT5 + 47, "PC_MDI2"), + PINCTRL_PIN(TB10X_PORT5 + 48, "PC_MDI3"), + PINCTRL_PIN(TB10X_PORT5 + 49, "PC_MDI4"), + PINCTRL_PIN(TB10X_PORT5 + 50, "PC_MDI5"), + PINCTRL_PIN(TB10X_PORT5 + 51, "PC_MDI6"), + PINCTRL_PIN(TB10X_PORT5 + 52, "PC_MDI7"), + PINCTRL_PIN(TB10X_PORT5 + 53, "PC_MICLK"), + /* Port 6 */ + PINCTRL_PIN(TB10X_PORT6 + 0, "T_MOSTRT_S0"), + PINCTRL_PIN(TB10X_PORT6 + 1, "T_MOVAL_S0"), + PINCTRL_PIN(TB10X_PORT6 + 2, "T_MDO_S0"), + PINCTRL_PIN(TB10X_PORT6 + 3, "T_MOSTRT_S1"), + PINCTRL_PIN(TB10X_PORT6 + 4, "T_MOVAL_S1"), + PINCTRL_PIN(TB10X_PORT6 + 5, "T_MDO_S1"), + PINCTRL_PIN(TB10X_PORT6 + 6, "T_MOSTRT_S2"), + PINCTRL_PIN(TB10X_PORT6 + 7, "T_MOVAL_S2"), + PINCTRL_PIN(TB10X_PORT6 + 8, "T_MDO_S2"), + PINCTRL_PIN(TB10X_PORT6 + 9, "T_MOSTRT_S3"), + /* Port 7 */ + PINCTRL_PIN(TB10X_PORT7 + 0, "UART0_TXD"), + PINCTRL_PIN(TB10X_PORT7 + 1, "UART0_RXD"), + PINCTRL_PIN(TB10X_PORT7 + 2, "UART0_CTS"), + PINCTRL_PIN(TB10X_PORT7 + 3, "UART0_RTS"), + PINCTRL_PIN(TB10X_PORT7 + 4, "UART1_TXD"), + PINCTRL_PIN(TB10X_PORT7 + 5, "UART1_RXD"), + PINCTRL_PIN(TB10X_PORT7 + 6, "UART1_CTS"), + PINCTRL_PIN(TB10X_PORT7 + 7, "UART1_RTS"), + /* Port 8 */ + PINCTRL_PIN(TB10X_PORT8 + 0, "SPI3_CLK"), + PINCTRL_PIN(TB10X_PORT8 + 1, "SPI3_MISO"), + PINCTRL_PIN(TB10X_PORT8 + 2, "SPI3_MOSI"), + PINCTRL_PIN(TB10X_PORT8 + 3, "SPI3_SSN"), + /* Port 9 */ + PINCTRL_PIN(TB10X_PORT9 + 0, "SPI1_CLK"), + PINCTRL_PIN(TB10X_PORT9 + 1, "SPI1_MISO"), + PINCTRL_PIN(TB10X_PORT9 + 2, "SPI1_MOSI"), + PINCTRL_PIN(TB10X_PORT9 + 3, "SPI1_SSN0"), + PINCTRL_PIN(TB10X_PORT9 + 4, "SPI1_SSN1"), + /* Unmuxed GPIOs */ + PINCTRL_PIN(TB10X_GPIOS + 0, "GPIOB0"), + PINCTRL_PIN(TB10X_GPIOS + 1, "GPIOB1"), + + PINCTRL_PIN(TB10X_GPIOS + 2, "GPIOD0"), + PINCTRL_PIN(TB10X_GPIOS + 3, "GPIOD1"), + + PINCTRL_PIN(TB10X_GPIOS + 4, "GPIOF0"), + PINCTRL_PIN(TB10X_GPIOS + 5, "GPIOF1"), + + PINCTRL_PIN(TB10X_GPIOS + 6, "GPIOH0"), + PINCTRL_PIN(TB10X_GPIOS + 7, "GPIOH1"), + + PINCTRL_PIN(TB10X_GPIOS + 8, "GPIOI0"), + PINCTRL_PIN(TB10X_GPIOS + 9, "GPIOI1"), + PINCTRL_PIN(TB10X_GPIOS + 10, "GPIOI2"), + PINCTRL_PIN(TB10X_GPIOS + 11, "GPIOI3"), + PINCTRL_PIN(TB10X_GPIOS + 12, "GPIOI4"), + PINCTRL_PIN(TB10X_GPIOS + 13, "GPIOI5"), + PINCTRL_PIN(TB10X_GPIOS + 14, "GPIOI6"), + PINCTRL_PIN(TB10X_GPIOS + 15, "GPIOI7"), + PINCTRL_PIN(TB10X_GPIOS + 16, "GPIOI8"), + PINCTRL_PIN(TB10X_GPIOS + 17, "GPIOI9"), + PINCTRL_PIN(TB10X_GPIOS + 18, "GPIOI10"), + PINCTRL_PIN(TB10X_GPIOS + 19, "GPIOI11"), + + PINCTRL_PIN(TB10X_GPIOS + 20, "GPION0"), + PINCTRL_PIN(TB10X_GPIOS + 21, "GPION1"), + PINCTRL_PIN(TB10X_GPIOS + 22, "GPION2"), + PINCTRL_PIN(TB10X_GPIOS + 23, "GPION3"), +#define MAX_PIN (TB10X_GPIOS + 24) + PINCTRL_PIN(MAX_PIN, "GPION4"), +}; + + +/* Port 1 */ +static const unsigned mis0_pins[] = { TB10X_PORT1 + 0, TB10X_PORT1 + 1, + TB10X_PORT1 + 2, TB10X_PORT1 + 3}; +static const unsigned gpioa_pins[] = { TB10X_PORT1 + 4, TB10X_PORT1 + 5, + TB10X_PORT1 + 6}; +static const unsigned mis1_pins[] = { TB10X_PORT1 + 7, TB10X_PORT1 + 8, + TB10X_PORT1 + 9, TB10X_PORT1 + 10}; +static const unsigned mip1_pins[] = { TB10X_PORT1 + 0, TB10X_PORT1 + 1, + TB10X_PORT1 + 2, TB10X_PORT1 + 3, + TB10X_PORT1 + 4, TB10X_PORT1 + 5, + TB10X_PORT1 + 6, TB10X_PORT1 + 7, + TB10X_PORT1 + 8, TB10X_PORT1 + 9, + TB10X_PORT1 + 10}; + +/* Port 2 */ +static const unsigned mis2_pins[] = { TB10X_PORT2 + 0, TB10X_PORT2 + 1, + TB10X_PORT2 + 2, TB10X_PORT2 + 3}; +static const unsigned gpioc_pins[] = { TB10X_PORT2 + 4, TB10X_PORT2 + 5, + TB10X_PORT2 + 6}; +static const unsigned mis3_pins[] = { TB10X_PORT2 + 7, TB10X_PORT2 + 8, + TB10X_PORT2 + 9, TB10X_PORT2 + 10}; +static const unsigned mip3_pins[] = { TB10X_PORT2 + 0, TB10X_PORT2 + 1, + TB10X_PORT2 + 2, TB10X_PORT2 + 3, + TB10X_PORT2 + 4, TB10X_PORT2 + 5, + TB10X_PORT2 + 6, TB10X_PORT2 + 7, + TB10X_PORT2 + 8, TB10X_PORT2 + 9, + TB10X_PORT2 + 10}; + +/* Port 3 */ +static const unsigned mis4_pins[] = { TB10X_PORT3 + 0, TB10X_PORT3 + 1, + TB10X_PORT3 + 2, TB10X_PORT3 + 3}; +static const unsigned gpioe_pins[] = { TB10X_PORT3 + 4, TB10X_PORT3 + 5, + TB10X_PORT3 + 6}; +static const unsigned mis5_pins[] = { TB10X_PORT3 + 7, TB10X_PORT3 + 8, + TB10X_PORT3 + 9, TB10X_PORT3 + 10}; +static const unsigned mip5_pins[] = { TB10X_PORT3 + 0, TB10X_PORT3 + 1, + TB10X_PORT3 + 2, TB10X_PORT3 + 3, + TB10X_PORT3 + 4, TB10X_PORT3 + 5, + TB10X_PORT3 + 6, TB10X_PORT3 + 7, + TB10X_PORT3 + 8, TB10X_PORT3 + 9, + TB10X_PORT3 + 10}; + +/* Port 4 */ +static const unsigned mis6_pins[] = { TB10X_PORT4 + 0, TB10X_PORT4 + 1, + TB10X_PORT4 + 2, TB10X_PORT4 + 3}; +static const unsigned gpiog_pins[] = { TB10X_PORT4 + 4, TB10X_PORT4 + 5, + TB10X_PORT4 + 6}; +static const unsigned mis7_pins[] = { TB10X_PORT4 + 7, TB10X_PORT4 + 8, + TB10X_PORT4 + 9, TB10X_PORT4 + 10}; +static const unsigned mip7_pins[] = { TB10X_PORT4 + 0, TB10X_PORT4 + 1, + TB10X_PORT4 + 2, TB10X_PORT4 + 3, + TB10X_PORT4 + 4, TB10X_PORT4 + 5, + TB10X_PORT4 + 6, TB10X_PORT4 + 7, + TB10X_PORT4 + 8, TB10X_PORT4 + 9, + TB10X_PORT4 + 10}; + +/* Port 6 */ +static const unsigned mop_pins[] = { TB10X_PORT6 + 0, TB10X_PORT6 + 1, + TB10X_PORT6 + 2, TB10X_PORT6 + 3, + TB10X_PORT6 + 4, TB10X_PORT6 + 5, + TB10X_PORT6 + 6, TB10X_PORT6 + 7, + TB10X_PORT6 + 8, TB10X_PORT6 + 9}; +static const unsigned mos0_pins[] = { TB10X_PORT6 + 0, TB10X_PORT6 + 1, + TB10X_PORT6 + 2}; +static const unsigned mos1_pins[] = { TB10X_PORT6 + 3, TB10X_PORT6 + 4, + TB10X_PORT6 + 5}; +static const unsigned mos2_pins[] = { TB10X_PORT6 + 6, TB10X_PORT6 + 7, + TB10X_PORT6 + 8}; +static const unsigned mos3_pins[] = { TB10X_PORT6 + 9}; + +/* Port 7 */ +static const unsigned uart0_pins[] = { TB10X_PORT7 + 0, TB10X_PORT7 + 1, + TB10X_PORT7 + 2, TB10X_PORT7 + 3}; +static const unsigned uart1_pins[] = { TB10X_PORT7 + 4, TB10X_PORT7 + 5, + TB10X_PORT7 + 6, TB10X_PORT7 + 7}; +static const unsigned gpiol_pins[] = { TB10X_PORT7 + 0, TB10X_PORT7 + 1, + TB10X_PORT7 + 2, TB10X_PORT7 + 3}; +static const unsigned gpiom_pins[] = { TB10X_PORT7 + 4, TB10X_PORT7 + 5, + TB10X_PORT7 + 6, TB10X_PORT7 + 7}; + +/* Port 8 */ +static const unsigned spi3_pins[] = { TB10X_PORT8 + 0, TB10X_PORT8 + 1, + TB10X_PORT8 + 2, TB10X_PORT8 + 3}; +static const unsigned jtag_pins[] = { TB10X_PORT8 + 0, TB10X_PORT8 + 1, + TB10X_PORT8 + 2, TB10X_PORT8 + 3}; + +/* Port 9 */ +static const unsigned spi1_pins[] = { TB10X_PORT9 + 0, TB10X_PORT9 + 1, + TB10X_PORT9 + 2, TB10X_PORT9 + 3, + TB10X_PORT9 + 4}; +static const unsigned gpion_pins[] = { TB10X_PORT9 + 0, TB10X_PORT9 + 1, + TB10X_PORT9 + 2, TB10X_PORT9 + 3, + TB10X_PORT9 + 4}; + +/* Port 5 */ +static const unsigned gpioj_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1, + TB10X_PORT5 + 2, TB10X_PORT5 + 3, + TB10X_PORT5 + 4, TB10X_PORT5 + 5, + TB10X_PORT5 + 6, TB10X_PORT5 + 7, + TB10X_PORT5 + 8, TB10X_PORT5 + 9, + TB10X_PORT5 + 10, TB10X_PORT5 + 11, + TB10X_PORT5 + 12, TB10X_PORT5 + 13, + TB10X_PORT5 + 14, TB10X_PORT5 + 15, + TB10X_PORT5 + 16, TB10X_PORT5 + 17, + TB10X_PORT5 + 18, TB10X_PORT5 + 19, + TB10X_PORT5 + 20, TB10X_PORT5 + 21, + TB10X_PORT5 + 22, TB10X_PORT5 + 23, + TB10X_PORT5 + 24, TB10X_PORT5 + 25, + TB10X_PORT5 + 26, TB10X_PORT5 + 27, + TB10X_PORT5 + 28, TB10X_PORT5 + 29, + TB10X_PORT5 + 30, TB10X_PORT5 + 31}; +static const unsigned gpiok_pins[] = { TB10X_PORT5 + 32, TB10X_PORT5 + 33, + TB10X_PORT5 + 34, TB10X_PORT5 + 35, + TB10X_PORT5 + 36, TB10X_PORT5 + 37, + TB10X_PORT5 + 38, TB10X_PORT5 + 39, + TB10X_PORT5 + 40, TB10X_PORT5 + 41, + TB10X_PORT5 + 42, TB10X_PORT5 + 43, + TB10X_PORT5 + 44, TB10X_PORT5 + 45, + TB10X_PORT5 + 46, TB10X_PORT5 + 47, + TB10X_PORT5 + 48, TB10X_PORT5 + 49, + TB10X_PORT5 + 50, TB10X_PORT5 + 51, + TB10X_PORT5 + 52, TB10X_PORT5 + 53}; +static const unsigned ciplus_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1, + TB10X_PORT5 + 2, TB10X_PORT5 + 3, + TB10X_PORT5 + 4, TB10X_PORT5 + 5, + TB10X_PORT5 + 6, TB10X_PORT5 + 7, + TB10X_PORT5 + 8, TB10X_PORT5 + 9, + TB10X_PORT5 + 10, TB10X_PORT5 + 11, + TB10X_PORT5 + 12, TB10X_PORT5 + 13, + TB10X_PORT5 + 14, TB10X_PORT5 + 15, + TB10X_PORT5 + 16, TB10X_PORT5 + 17, + TB10X_PORT5 + 18, TB10X_PORT5 + 19, + TB10X_PORT5 + 20, TB10X_PORT5 + 21, + TB10X_PORT5 + 22, TB10X_PORT5 + 23, + TB10X_PORT5 + 24, TB10X_PORT5 + 25, + TB10X_PORT5 + 26, TB10X_PORT5 + 27, + TB10X_PORT5 + 28, TB10X_PORT5 + 29, + TB10X_PORT5 + 30, TB10X_PORT5 + 31, + TB10X_PORT5 + 32, TB10X_PORT5 + 33, + TB10X_PORT5 + 34, TB10X_PORT5 + 35, + TB10X_PORT5 + 36, TB10X_PORT5 + 37, + TB10X_PORT5 + 38, TB10X_PORT5 + 39, + TB10X_PORT5 + 40, TB10X_PORT5 + 41, + TB10X_PORT5 + 42, TB10X_PORT5 + 43, + TB10X_PORT5 + 44, TB10X_PORT5 + 45, + TB10X_PORT5 + 46, TB10X_PORT5 + 47, + TB10X_PORT5 + 48, TB10X_PORT5 + 49, + TB10X_PORT5 + 50, TB10X_PORT5 + 51, + TB10X_PORT5 + 52, TB10X_PORT5 + 53}; +static const unsigned mcard_pins[] = { TB10X_PORT5 + 3, TB10X_PORT5 + 10, + TB10X_PORT5 + 11, TB10X_PORT5 + 12, + TB10X_PORT5 + 22, TB10X_PORT5 + 23, + TB10X_PORT5 + 33, TB10X_PORT5 + 35, + TB10X_PORT5 + 36, TB10X_PORT5 + 37, + TB10X_PORT5 + 38, TB10X_PORT5 + 39, + TB10X_PORT5 + 40, TB10X_PORT5 + 41, + TB10X_PORT5 + 42, TB10X_PORT5 + 43, + TB10X_PORT5 + 45, TB10X_PORT5 + 46, + TB10X_PORT5 + 47, TB10X_PORT5 + 48, + TB10X_PORT5 + 49, TB10X_PORT5 + 50, + TB10X_PORT5 + 51, TB10X_PORT5 + 52, + TB10X_PORT5 + 53}; +static const unsigned stc0_pins[] = { TB10X_PORT5 + 34, TB10X_PORT5 + 35, + TB10X_PORT5 + 36, TB10X_PORT5 + 37, + TB10X_PORT5 + 38, TB10X_PORT5 + 39, + TB10X_PORT5 + 40}; +static const unsigned stc1_pins[] = { TB10X_PORT5 + 25, TB10X_PORT5 + 26, + TB10X_PORT5 + 27, TB10X_PORT5 + 28, + TB10X_PORT5 + 29, TB10X_PORT5 + 30, + TB10X_PORT5 + 44}; + +/* Unmuxed GPIOs */ +static const unsigned gpiob_pins[] = { TB10X_GPIOS + 0, TB10X_GPIOS + 1}; +static const unsigned gpiod_pins[] = { TB10X_GPIOS + 2, TB10X_GPIOS + 3}; +static const unsigned gpiof_pins[] = { TB10X_GPIOS + 4, TB10X_GPIOS + 5}; +static const unsigned gpioh_pins[] = { TB10X_GPIOS + 6, TB10X_GPIOS + 7}; +static const unsigned gpioi_pins[] = { TB10X_GPIOS + 8, TB10X_GPIOS + 9, + TB10X_GPIOS + 10, TB10X_GPIOS + 11, + TB10X_GPIOS + 12, TB10X_GPIOS + 13, + TB10X_GPIOS + 14, TB10X_GPIOS + 15, + TB10X_GPIOS + 16, TB10X_GPIOS + 17, + TB10X_GPIOS + 18, TB10X_GPIOS + 19}; + +struct tb10x_pinfuncgrp { + const char *name; + const unsigned int *pins; + const unsigned int pincnt; + const int port; + const unsigned int mode; + const int isgpio; +}; +#define DEFPINFUNCGRP(NAME, PORT, MODE, ISGPIO) { \ + .name = __stringify(NAME), \ + .pins = NAME##_pins, .pincnt = ARRAY_SIZE(NAME##_pins), \ + .port = (PORT), .mode = (MODE), \ + .isgpio = (ISGPIO), \ + } +static const struct tb10x_pinfuncgrp tb10x_pingroups[] = { + DEFPINFUNCGRP(mis0, 0, 0, 0), + DEFPINFUNCGRP(gpioa, 0, 0, 1), + DEFPINFUNCGRP(mis1, 0, 0, 0), + DEFPINFUNCGRP(mip1, 0, 1, 0), + DEFPINFUNCGRP(mis2, 1, 0, 0), + DEFPINFUNCGRP(gpioc, 1, 0, 1), + DEFPINFUNCGRP(mis3, 1, 0, 0), + DEFPINFUNCGRP(mip3, 1, 1, 0), + DEFPINFUNCGRP(mis4, 2, 0, 0), + DEFPINFUNCGRP(gpioe, 2, 0, 1), + DEFPINFUNCGRP(mis5, 2, 0, 0), + DEFPINFUNCGRP(mip5, 2, 1, 0), + DEFPINFUNCGRP(mis6, 3, 0, 0), + DEFPINFUNCGRP(gpiog, 3, 0, 1), + DEFPINFUNCGRP(mis7, 3, 0, 0), + DEFPINFUNCGRP(mip7, 3, 1, 0), + DEFPINFUNCGRP(gpioj, 4, 0, 1), + DEFPINFUNCGRP(gpiok, 4, 0, 1), + DEFPINFUNCGRP(ciplus, 4, 1, 0), + DEFPINFUNCGRP(mcard, 4, 2, 0), + DEFPINFUNCGRP(stc0, 4, 3, 0), + DEFPINFUNCGRP(stc1, 4, 3, 0), + DEFPINFUNCGRP(mop, 5, 0, 0), + DEFPINFUNCGRP(mos0, 5, 1, 0), + DEFPINFUNCGRP(mos1, 5, 1, 0), + DEFPINFUNCGRP(mos2, 5, 1, 0), + DEFPINFUNCGRP(mos3, 5, 1, 0), + DEFPINFUNCGRP(uart0, 6, 0, 0), + DEFPINFUNCGRP(uart1, 6, 0, 0), + DEFPINFUNCGRP(gpiol, 6, 1, 1), + DEFPINFUNCGRP(gpiom, 6, 1, 1), + DEFPINFUNCGRP(spi3, 7, 0, 0), + DEFPINFUNCGRP(jtag, 7, 1, 0), + DEFPINFUNCGRP(spi1, 8, 0, 0), + DEFPINFUNCGRP(gpion, 8, 1, 1), + DEFPINFUNCGRP(gpiob, -1, 0, 1), + DEFPINFUNCGRP(gpiod, -1, 0, 1), + DEFPINFUNCGRP(gpiof, -1, 0, 1), + DEFPINFUNCGRP(gpioh, -1, 0, 1), + DEFPINFUNCGRP(gpioi, -1, 0, 1), +}; +#undef DEFPINFUNCGRP + +struct tb10x_of_pinfunc { + const char *name; + const char *group; +}; + +#define TB10X_PORTS (9) + +/** + * struct tb10x_port - state of an I/O port + * @mode: Node this port is currently in. + * @count: Number of enabled functions which require this port to be + * configured in @mode. + */ +struct tb10x_port { + unsigned int mode; + unsigned int count; +}; + +/** + * struct tb10x_pinctrl - TB10x pin controller internal state + * @pctl: pointer to the pinctrl_dev structure of this pin controller. + * @base: register set base address. + * @pingroups: pointer to an array of the pin groups this driver manages. + * @pinfuncgrpcnt: number of pingroups in @pingroups. + * @pinfuncs: pointer to an array of pin functions this driver manages. + * @pinfuncnt: number of pin functions in @pinfuncs. + * @mutex: mutex for exclusive access to a pin controller's state. + * @ports: current state of each port. + * @gpios: Indicates if a given pin is currently used as GPIO (1) or not (0). + */ +struct tb10x_pinctrl { + struct pinctrl_dev *pctl; + void *base; + const struct tb10x_pinfuncgrp *pingroups; + unsigned int pinfuncgrpcnt; + struct tb10x_of_pinfunc *pinfuncs; + unsigned int pinfuncnt; + struct mutex mutex; + struct tb10x_port ports[TB10X_PORTS]; + DECLARE_BITMAP(gpios, MAX_PIN + 1); +}; + +static inline void tb10x_pinctrl_set_config(struct tb10x_pinctrl *state, + unsigned int port, unsigned int mode) +{ + u32 pcfg; + + if (state->ports[port].count) + return; + + state->ports[port].mode = mode; + + pcfg = ioread32(state->base) & ~(PCFG_PORT_MASK(port)); + pcfg |= (mode << (PCFG_PORT_BITWIDTH * port)) & PCFG_PORT_MASK(port); + iowrite32(pcfg, state->base); +} + +static inline unsigned int tb10x_pinctrl_get_config( + struct tb10x_pinctrl *state, + unsigned int port) +{ + return (ioread32(state->base) & PCFG_PORT_MASK(port)) + >> (PCFG_PORT_BITWIDTH * port); +} + +static int tb10x_get_groups_count(struct pinctrl_dev *pctl) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + return state->pinfuncgrpcnt; +} + +static const char *tb10x_get_group_name(struct pinctrl_dev *pctl, unsigned n) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + return state->pingroups[n].name; +} + +static int tb10x_get_group_pins(struct pinctrl_dev *pctl, unsigned n, + unsigned const **pins, + unsigned * const num_pins) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + + *pins = state->pingroups[n].pins; + *num_pins = state->pingroups[n].pincnt; + + return 0; +} + +static int tb10x_dt_node_to_map(struct pinctrl_dev *pctl, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + const char *string; + unsigned reserved_maps = 0; + int ret = 0; + + if (of_property_read_string(np_config, "abilis,function", &string)) { + pr_err("%s: No abilis,function property in device tree.\n", + np_config->full_name); + return -EINVAL; + } + + *map = NULL; + *num_maps = 0; + + ret = pinctrl_utils_reserve_map(pctl, map, &reserved_maps, + num_maps, 1); + if (ret) + goto out; + + ret = pinctrl_utils_add_map_mux(pctl, map, &reserved_maps, + num_maps, string, np_config->name); + +out: + return ret; +} + +static struct pinctrl_ops tb10x_pinctrl_ops = { + .get_groups_count = tb10x_get_groups_count, + .get_group_name = tb10x_get_group_name, + .get_group_pins = tb10x_get_group_pins, + .dt_node_to_map = tb10x_dt_node_to_map, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int tb10x_get_functions_count(struct pinctrl_dev *pctl) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + return state->pinfuncnt; +} + +static const char *tb10x_get_function_name(struct pinctrl_dev *pctl, + unsigned n) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + return state->pinfuncs[n].name; +} + +static int tb10x_get_function_groups(struct pinctrl_dev *pctl, + unsigned n, const char * const **groups, + unsigned * const num_groups) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + + *groups = &state->pinfuncs[n].group; + *num_groups = 1; + + return 0; +} + +static int tb10x_gpio_request_enable(struct pinctrl_dev *pctl, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + int muxport = -1; + int muxmode = -1; + int i; + + mutex_lock(&state->mutex); + + /* + * Figure out to which port the requested GPIO belongs and how to + * configure that port. + * This loop also checks for pin conflicts between GPIOs and other + * functions. + */ + for (i = 0; i < state->pinfuncgrpcnt; i++) { + const struct tb10x_pinfuncgrp *pfg = &state->pingroups[i]; + unsigned int port = pfg->port; + unsigned int mode = pfg->mode; + int j; + + /* + * Skip pin groups which are always mapped and don't need + * to be configured. + */ + if (port < 0) + continue; + + for (j = 0; j < pfg->pincnt; j++) { + if (pin == pfg->pins[j]) { + if (pfg->isgpio) { + /* + * Remember the GPIO-only setting of + * the port this pin belongs to. + */ + muxport = port; + muxmode = mode; + } else if (state->ports[port].count + && (state->ports[port].mode == mode)) { + /* + * Error: The requested pin is already + * used for something else. + */ + mutex_unlock(&state->mutex); + return -EBUSY; + } + break; + } + } + } + + /* + * If we haven't returned an error at this point, the GPIO pin is not + * used by another function and the GPIO request can be granted: + * Register pin as being used as GPIO so we don't allocate it to + * another function later. + */ + set_bit(pin, state->gpios); + + /* + * Potential conflicts between GPIOs and pin functions were caught + * earlier in this function and tb10x_pinctrl_set_config will do the + * Right Thing, either configure the port in GPIO only mode or leave + * another mode compatible with this GPIO request untouched. + */ + if (muxport >= 0) + tb10x_pinctrl_set_config(state, muxport, muxmode); + + mutex_unlock(&state->mutex); + + return 0; +} + +static void tb10x_gpio_disable_free(struct pinctrl_dev *pctl, + struct pinctrl_gpio_range *range, + unsigned pin) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + + mutex_lock(&state->mutex); + + clear_bit(pin, state->gpios); + + mutex_unlock(&state->mutex); +} + +static int tb10x_pctl_enable(struct pinctrl_dev *pctl, + unsigned func_selector, unsigned group_selector) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector]; + int i; + + if (grp->port < 0) + return 0; + + mutex_lock(&state->mutex); + + /* + * Check if the requested function is compatible with previously + * requested functions. + */ + if (state->ports[grp->port].count + && (state->ports[grp->port].mode != grp->mode)) { + mutex_unlock(&state->mutex); + return -EBUSY; + } + + /* + * Check if the requested function is compatible with previously + * requested GPIOs. + */ + for (i = 0; i < grp->pincnt; i++) + if (test_bit(grp->pins[i], state->gpios)) { + mutex_unlock(&state->mutex); + return -EBUSY; + } + + tb10x_pinctrl_set_config(state, grp->port, grp->mode); + + state->ports[grp->port].count++; + + mutex_unlock(&state->mutex); + + return 0; +} + +static void tb10x_pctl_disable(struct pinctrl_dev *pctl, + unsigned func_selector, unsigned group_selector) +{ + struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); + const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector]; + + if (grp->port < 0) + return; + + mutex_lock(&state->mutex); + + state->ports[grp->port].count--; + + mutex_unlock(&state->mutex); +} + +static struct pinmux_ops tb10x_pinmux_ops = { + .get_functions_count = tb10x_get_functions_count, + .get_function_name = tb10x_get_function_name, + .get_function_groups = tb10x_get_function_groups, + .gpio_request_enable = tb10x_gpio_request_enable, + .gpio_disable_free = tb10x_gpio_disable_free, + .enable = tb10x_pctl_enable, + .disable = tb10x_pctl_disable, +}; + +static struct pinctrl_desc tb10x_pindesc = { + .name = "TB10x", + .pins = tb10x_pins, + .npins = ARRAY_SIZE(tb10x_pins), + .owner = THIS_MODULE, + .pctlops = &tb10x_pinctrl_ops, + .pmxops = &tb10x_pinmux_ops, +}; + +static int tb10x_pinctrl_probe(struct platform_device *pdev) +{ + int ret = -EINVAL; + struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct device *dev = &pdev->dev; + struct device_node *of_node = dev->of_node; + struct device_node *child; + struct tb10x_pinctrl *state; + int i; + + if (!of_node) { + dev_err(dev, "No device tree node found.\n"); + return -EINVAL; + } + + if (!mem) { + dev_err(dev, "No memory resource defined.\n"); + return -EINVAL; + } + + state = devm_kzalloc(dev, sizeof(struct tb10x_pinctrl) + + of_get_child_count(of_node) + * sizeof(struct tb10x_of_pinfunc), + GFP_KERNEL); + if (!state) + return -ENOMEM; + + platform_set_drvdata(pdev, state); + state->pinfuncs = (struct tb10x_of_pinfunc *)(state + 1); + mutex_init(&state->mutex); + + state->base = devm_ioremap_resource(dev, mem); + if (!state->base) { + dev_err(dev, "Request register region failed.\n"); + ret = -EBUSY; + goto fail; + } + + state->pingroups = tb10x_pingroups; + state->pinfuncgrpcnt = ARRAY_SIZE(tb10x_pingroups); + + for (i = 0; i < TB10X_PORTS; i++) + state->ports[i].mode = tb10x_pinctrl_get_config(state, i); + + for_each_child_of_node(of_node, child) { + const char *name; + + if (!of_property_read_string(child, "abilis,function", + &name)) { + state->pinfuncs[state->pinfuncnt].name = child->name; + state->pinfuncs[state->pinfuncnt].group = name; + state->pinfuncnt++; + } + } + + state->pctl = pinctrl_register(&tb10x_pindesc, dev, state); + if (IS_ERR(state->pctl)) { + dev_err(dev, "could not register TB10x pin driver\n"); + ret = PTR_ERR(state->pctl); + goto fail; + } + + return 0; + +fail: + mutex_destroy(&state->mutex); + return ret; +} + +static int tb10x_pinctrl_remove(struct platform_device *pdev) +{ + struct tb10x_pinctrl *state = platform_get_drvdata(pdev); + + pinctrl_unregister(state->pctl); + mutex_destroy(&state->mutex); + + return 0; +} + + +static const struct of_device_id tb10x_pinctrl_dt_ids[] = { + { .compatible = "abilis,tb10x-iomux" }, + { } +}; +MODULE_DEVICE_TABLE(of, tb10x_pinctrl_dt_ids); + +static struct platform_driver tb10x_pinctrl_pdrv = { + .probe = tb10x_pinctrl_probe, + .remove = tb10x_pinctrl_remove, + .driver = { + .name = "tb10x_pinctrl", + .of_match_table = of_match_ptr(tb10x_pinctrl_dt_ids), + .owner = THIS_MODULE + } +}; + +static int __init tb10x_iopinctrl_init(void) +{ + return platform_driver_register(&tb10x_pinctrl_pdrv); +} + +static void __exit tb10x_iopinctrl_exit(void) +{ + platform_driver_unregister(&tb10x_pinctrl_pdrv); +} + +MODULE_AUTHOR("Christian Ruppert "); +MODULE_LICENSE("GPL"); +module_init(tb10x_iopinctrl_init); +module_exit(tb10x_iopinctrl_exit); -- cgit v1.2.3 From 6ca5274d1d1258b0e84bc1a0d67ca160d8658e5a Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Wed, 16 Oct 2013 01:08:42 +0200 Subject: pinctrl: rockchip: add rk3188 specifics Besides the pull registers sitting in a separate place, the rk3188 also has the peculiarity that the pull registers of the first bank are split and the first half is sitting in the register space of the pmu. Therefore this adds a special bank-type for the first bank, to handle the two register sources. Signed-off-by: Heiko Stuebner Signed-off-by: Linus Walleij --- .../bindings/pinctrl/rockchip,pinctrl.txt | 46 +++++++- drivers/pinctrl/pinctrl-rockchip.c | 119 +++++++++++++++++++-- 2 files changed, 157 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree/bindings/pinctrl') diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index b0fb1018d7ad..f378d342aae4 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -21,10 +21,13 @@ defined as gpio sub-nodes of the pinmux controller. Required properties for iomux controller: - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" + - reg: first element is the general register space of the iomux controller + second element is the separate pull register space of the rk3188 Required properties for gpio sub nodes: - - compatible: "rockchip,gpio-bank" + - compatible: "rockchip,gpio-bank", "rockchip,rk3188-gpio-bank0" - reg: register of the gpio bank (different than the iomux registerset) + second element: separate pull register for rk3188 bank0 - interrupts: base interrupt of the gpio bank in the interrupt controller - clocks: clock that drives this bank - gpio-controller: identifies the node as a gpio controller and pin bank. @@ -95,3 +98,44 @@ uart2: serial@20064000 { pinctrl-names = "default"; pinctrl-0 = <&uart2_xfer>; }; + +Example for rk3188: + + pinctrl@20008000 { + compatible = "rockchip,rk3188-pinctrl"; + reg = <0x20008000 0xa0>, + <0x20008164 0x1a0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@0x2000a000 { + compatible = "rockchip,rk3188-gpio-bank0"; + reg = <0x2000a000 0x100>, + <0x20004064 0x8>; + interrupts = ; + clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@0x2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = ; + clocks = <&clk_gates8 10>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + ... + + }; diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 91027dd19f89..f5e53a723152 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -64,10 +64,12 @@ enum rockchip_pinctrl_type { enum rockchip_pin_bank_type { COMMON_BANK, + RK3188_BANK0, }; /** * @reg_base: register base of the gpio bank + * @reg_pull: optional separate register for additional pull settings * @clk: clock of the gpio bank * @irq: interrupt of the gpio bank * @pin_base: first pin number @@ -84,6 +86,7 @@ enum rockchip_pin_bank_type { */ struct rockchip_pin_bank { void __iomem *reg_base; + void __iomem *reg_pull; struct clk *clk; int irq; u32 pin_base; @@ -157,6 +160,7 @@ struct rockchip_pmx_func { struct rockchip_pinctrl { void __iomem *reg_base; + void __iomem *reg_pull; struct device *dev; struct rockchip_pin_ctrl *ctrl; struct pinctrl_desc pctl; @@ -379,25 +383,71 @@ static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *bit = pin_num % RK2928_PULL_PINS_PER_REG; }; +#define RK3188_PULL_BITS_PER_PIN 2 +#define RK3188_PULL_PINS_PER_REG 8 +#define RK3188_PULL_BANK_STRIDE 16 + +static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, void __iomem **reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* The first 12 pins of the first bank are located elsewhere */ + if (bank->bank_type == RK3188_BANK0 && pin_num < 12) { + *reg = bank->reg_pull + + ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3188_PULL_PINS_PER_REG; + *bit *= RK3188_PULL_BITS_PER_PIN; + } else { + *reg = info->reg_pull - 4; + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + + /* + * The bits in these registers have an inverse ordering + * with the lowest pin being in bits 15:14 and the highest + * pin in bits 1:0 + */ + *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); + *bit *= RK3188_PULL_BITS_PER_PIN; + } +} + static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; void __iomem *reg; u8 bit; + u32 data; /* rk3066b does support any pulls */ if (ctrl->type == RK3066B) return PIN_CONFIG_BIAS_DISABLE; + ctrl->pull_calc_reg(bank, pin_num, ®, &bit); + switch (ctrl->type) { case RK2928: - ctrl->pull_calc_reg(bank, pin_num, ®, &bit); return !(readl_relaxed(reg) & BIT(bit)) ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT : PIN_CONFIG_BIAS_DISABLE; case RK3188: - dev_err(info->dev, "pull support for rk31xx not implemented\n"); + data = readl_relaxed(reg) >> bit; + data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; + + switch (data) { + case 0: + return PIN_CONFIG_BIAS_DISABLE; + case 1: + return PIN_CONFIG_BIAS_PULL_UP; + case 2: + return PIN_CONFIG_BIAS_PULL_DOWN; + case 3: + return PIN_CONFIG_BIAS_BUS_HOLD; + } + + dev_err(info->dev, "unknown pull setting\n"); return -EIO; default: dev_err(info->dev, "unsupported pinctrl type\n"); @@ -422,10 +472,10 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, if (ctrl->type == RK3066B) return pull ? -EINVAL : 0; + ctrl->pull_calc_reg(bank, pin_num, ®, &bit); + switch (ctrl->type) { case RK2928: - ctrl->pull_calc_reg(bank, pin_num, ®, &bit); - spin_lock_irqsave(&bank->slock, flags); data = BIT(bit + 16); @@ -436,8 +486,33 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, spin_unlock_irqrestore(&bank->slock, flags); break; case RK3188: - dev_err(info->dev, "pull support for rk31xx not implemented\n"); - return -EIO; + spin_lock_irqsave(&bank->slock, flags); + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); + + switch (pull) { + case PIN_CONFIG_BIAS_DISABLE: + break; + case PIN_CONFIG_BIAS_PULL_UP: + data |= (1 << bit); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + data |= (2 << bit); + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + data |= (3 << bit); + break; + default: + dev_err(info->dev, "unsupported pull setting %d\n", + pull); + return -EINVAL; + } + + writel(data, reg); + + spin_unlock_irqrestore(&bank->slock, flags); + break; default: dev_err(info->dev, "unsupported pinctrl type\n"); return -EINVAL; @@ -608,6 +683,7 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + case PIN_CONFIG_BIAS_BUS_HOLD: if (!rockchip_pinconf_pull_valid(info->ctrl, param)) return -ENOTSUPP; @@ -646,6 +722,7 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + case PIN_CONFIG_BIAS_BUS_HOLD: if (!rockchip_pinconf_pull_valid(info->ctrl, param)) return -ENOTSUPP; @@ -669,6 +746,7 @@ static const struct pinconf_ops rockchip_pinconf_ops = { static const struct of_device_id rockchip_bank_match[] = { { .compatible = "rockchip,gpio-bank" }, + { .compatible = "rockchip,rk3188-gpio-bank0" }, {}, }; @@ -1220,7 +1298,25 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, if (IS_ERR(bank->reg_base)) return PTR_ERR(bank->reg_base); - bank->bank_type = COMMON_BANK; + /* + * special case, where parts of the pull setting-registers are + * part of the PMU register space + */ + if (of_device_is_compatible(bank->of_node, + "rockchip,rk3188-gpio-bank0")) { + bank->bank_type = RK3188_BANK0; + + if (of_address_to_resource(bank->of_node, 1, &res)) { + dev_err(dev, "cannot find IO resource for bank\n"); + return -ENOENT; + } + + bank->reg_pull = devm_ioremap_resource(dev, &res); + if (IS_ERR(bank->reg_pull)) + return PTR_ERR(bank->reg_pull); + } else { + bank->bank_type = COMMON_BANK; + } bank->irq = irq_of_parse_and_map(bank->of_node, 0); @@ -1306,6 +1402,14 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(info->reg_base)) return PTR_ERR(info->reg_base); + /* The RK3188 has its pull registers in a separate place */ + if (ctrl->type == RK3188) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + info->reg_pull = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(info->reg_base)) + return PTR_ERR(info->reg_base); + } + ret = rockchip_gpiolib_register(pdev, info); if (ret) return ret; @@ -1383,6 +1487,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .label = "RK3188-GPIO", .type = RK3188, .mux_offset = 0x68, + .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; static const struct of_device_id rockchip_pinctrl_dt_match[] = { -- cgit v1.2.3 From e16dbf6011137343f51685c1e0c5be36a68fc501 Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Tue, 29 Oct 2013 15:32:19 +0100 Subject: pinctrl: imx27: imx27 pincontrol driver imx27 pincontrol driver using the imx1 core driver. The DT bindings are similar to other imx pincontrol drivers. Signed-off-by: Markus Pargmann Acked-by: Sascha Hauer Acked-by: Shawn Guo Signed-off-by: Linus Walleij --- .../bindings/pinctrl/fsl,imx27-pinctrl.txt | 99 +++++ drivers/pinctrl/Kconfig | 8 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-imx27.c | 477 +++++++++++++++++++++ 4 files changed, 585 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt create mode 100644 drivers/pinctrl/pinctrl-imx27.c (limited to 'Documentation/devicetree/bindings/pinctrl') diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt new file mode 100644 index 000000000000..353eca0efbf8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt @@ -0,0 +1,99 @@ +* Freescale IMX27 IOMUX Controller + +Required properties: +- compatible: "fsl,imx27-iomuxc" + +The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes. + +Required properties for pin configuration node: +- fsl,pins: three integers array, represents a group of pins mux and config + setting. The format is fsl,pins = . + + PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable + configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin + number on the specific port (between 0 and 31). + + MUX_ID is + function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) + + function value is used to select the pin function. + Possible values: + 0 - Primary function + 1 - Alternate function + 2 - GPIO + Registers: GIUS (GPIO In Use), GPR (General Purpose Register) + + direction defines the data direction of the pin. + Possible values: + 0 - Input + 1 - Output + Register: DDIR + + gpio_oconf configures the gpio submodule output signal. This does not + have any effect unless GPIO function is selected. A/B/C_IN are output + signals of function blocks A,B and C. Specific function blocks are + described in the reference manual. + Possible values: + 0 - A_IN + 1 - B_IN + 2 - C_IN + 3 - Data Register + Registers: OCR1, OCR2 + + gpio_iconfa/b configures the gpio submodule input to functionblocks A and + B. GPIO function should be selected if this is configured. + Possible values: + 0 - GPIO_IN + 1 - Interrupt Status Register + 2 - Pulldown + 3 - Pullup + Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2 + + CONFIG can be 0 or 1, meaning Pullup disable/enable. + + + +Example: + +iomuxc: iomuxc@10015000 { + compatible = "fsl,imx27-iomuxc"; + reg = <0x10015000 0x600>; + + uart { + pinctrl_uart1: uart-1 { + fsl,pins = < + 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */ + 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */ + 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */ + 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */ + >; + }; + + ... + }; +}; + + +For convenience there are macros defined in imx27-pinfunc.h which provide PIN +and MUX_ID. They are structured as MX27_PAD___. The names +are defined in the i.MX27 reference manual. + +The above example using macros: + +iomuxc: iomuxc@10015000 { + compatible = "fsl,imx27-iomuxc"; + reg = <0x10015000 0x600>; + + uart { + pinctrl_uart1: uart-1 { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + ... + }; +}; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index fcc748f68f4a..db1ddcaebf05 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -114,6 +114,14 @@ config PINCTRL_IMX1_CORE select PINMUX select PINCONF +config PINCTRL_IMX27 + bool "IMX27 pinctrl driver" + depends on OF + depends on SOC_IMX27 + select PINCTRL_IMX1_CORE + help + Say Y here to enable the imx27 pinctrl driver + config PINCTRL_IMX35 bool "IMX35 pinctrl driver" depends on OF diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 8b334e305537..915d19c1cdc6 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o +obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/pinctrl-imx27.c new file mode 100644 index 000000000000..417c99205bc2 --- /dev/null +++ b/drivers/pinctrl/pinctrl-imx27.c @@ -0,0 +1,477 @@ +/* + * imx27 pinctrl driver based on imx pinmux core + * + * Copyright (C) 2013 Pengutronix + * + * Author: Markus Pargmann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx1.h" + +#define PAD_ID(port, pin) (port*32 + pin) +#define PA 0 +#define PB 1 +#define PC 2 +#define PD 3 +#define PE 4 +#define PF 5 + +enum imx27_pads { + MX27_PAD_USBH2_CLK = PAD_ID(PA, 0), + MX27_PAD_USBH2_DIR = PAD_ID(PA, 1), + MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2), + MX27_PAD_USBH2_NXT = PAD_ID(PA, 3), + MX27_PAD_USBH2_STP = PAD_ID(PA, 4), + MX27_PAD_LSCLK = PAD_ID(PA, 5), + MX27_PAD_LD0 = PAD_ID(PA, 6), + MX27_PAD_LD1 = PAD_ID(PA, 7), + MX27_PAD_LD2 = PAD_ID(PA, 8), + MX27_PAD_LD3 = PAD_ID(PA, 9), + MX27_PAD_LD4 = PAD_ID(PA, 10), + MX27_PAD_LD5 = PAD_ID(PA, 11), + MX27_PAD_LD6 = PAD_ID(PA, 12), + MX27_PAD_LD7 = PAD_ID(PA, 13), + MX27_PAD_LD8 = PAD_ID(PA, 14), + MX27_PAD_LD9 = PAD_ID(PA, 15), + MX27_PAD_LD10 = PAD_ID(PA, 16), + MX27_PAD_LD11 = PAD_ID(PA, 17), + MX27_PAD_LD12 = PAD_ID(PA, 18), + MX27_PAD_LD13 = PAD_ID(PA, 19), + MX27_PAD_LD14 = PAD_ID(PA, 20), + MX27_PAD_LD15 = PAD_ID(PA, 21), + MX27_PAD_LD16 = PAD_ID(PA, 22), + MX27_PAD_LD17 = PAD_ID(PA, 23), + MX27_PAD_REV = PAD_ID(PA, 24), + MX27_PAD_CLS = PAD_ID(PA, 25), + MX27_PAD_PS = PAD_ID(PA, 26), + MX27_PAD_SPL_SPR = PAD_ID(PA, 27), + MX27_PAD_HSYNC = PAD_ID(PA, 28), + MX27_PAD_VSYNC = PAD_ID(PA, 29), + MX27_PAD_CONTRAST = PAD_ID(PA, 30), + MX27_PAD_OE_ACD = PAD_ID(PA, 31), + + MX27_PAD_UNUSED0 = PAD_ID(PB, 0), + MX27_PAD_UNUSED1 = PAD_ID(PB, 1), + MX27_PAD_UNUSED2 = PAD_ID(PB, 2), + MX27_PAD_UNUSED3 = PAD_ID(PB, 3), + MX27_PAD_SD2_D0 = PAD_ID(PB, 4), + MX27_PAD_SD2_D1 = PAD_ID(PB, 5), + MX27_PAD_SD2_D2 = PAD_ID(PB, 6), + MX27_PAD_SD2_D3 = PAD_ID(PB, 7), + MX27_PAD_SD2_CMD = PAD_ID(PB, 8), + MX27_PAD_SD2_CLK = PAD_ID(PB, 9), + MX27_PAD_CSI_D0 = PAD_ID(PB, 10), + MX27_PAD_CSI_D1 = PAD_ID(PB, 11), + MX27_PAD_CSI_D2 = PAD_ID(PB, 12), + MX27_PAD_CSI_D3 = PAD_ID(PB, 13), + MX27_PAD_CSI_D4 = PAD_ID(PB, 14), + MX27_PAD_CSI_MCLK = PAD_ID(PB, 15), + MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16), + MX27_PAD_CSI_D5 = PAD_ID(PB, 17), + MX27_PAD_CSI_D6 = PAD_ID(PB, 18), + MX27_PAD_CSI_D7 = PAD_ID(PB, 19), + MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20), + MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21), + MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22), + MX27_PAD_USB_PWR = PAD_ID(PB, 23), + MX27_PAD_USB_OC_B = PAD_ID(PB, 24), + MX27_PAD_USBH1_RCV = PAD_ID(PB, 25), + MX27_PAD_USBH1_FS = PAD_ID(PB, 26), + MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27), + MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28), + MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29), + MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30), + MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31), + + MX27_PAD_UNUSED4 = PAD_ID(PC, 0), + MX27_PAD_UNUSED5 = PAD_ID(PC, 1), + MX27_PAD_UNUSED6 = PAD_ID(PC, 2), + MX27_PAD_UNUSED7 = PAD_ID(PC, 3), + MX27_PAD_UNUSED8 = PAD_ID(PC, 4), + MX27_PAD_I2C2_SDA = PAD_ID(PC, 5), + MX27_PAD_I2C2_SCL = PAD_ID(PC, 6), + MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7), + MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8), + MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9), + MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10), + MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11), + MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12), + MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13), + MX27_PAD_TOUT = PAD_ID(PC, 14), + MX27_PAD_TIN = PAD_ID(PC, 15), + MX27_PAD_SSI4_FS = PAD_ID(PC, 16), + MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17), + MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18), + MX27_PAD_SSI4_CLK = PAD_ID(PC, 19), + MX27_PAD_SSI1_FS = PAD_ID(PC, 20), + MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21), + MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22), + MX27_PAD_SSI1_CLK = PAD_ID(PC, 23), + MX27_PAD_SSI2_FS = PAD_ID(PC, 24), + MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25), + MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26), + MX27_PAD_SSI2_CLK = PAD_ID(PC, 27), + MX27_PAD_SSI3_FS = PAD_ID(PC, 28), + MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29), + MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30), + MX27_PAD_SSI3_CLK = PAD_ID(PC, 31), + + MX27_PAD_SD3_CMD = PAD_ID(PD, 0), + MX27_PAD_SD3_CLK = PAD_ID(PD, 1), + MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2), + MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3), + MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4), + MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5), + MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6), + MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7), + MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8), + MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9), + MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10), + MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11), + MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12), + MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13), + MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14), + MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15), + MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16), + MX27_PAD_I2C_DATA = PAD_ID(PD, 17), + MX27_PAD_I2C_CLK = PAD_ID(PD, 18), + MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19), + MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20), + MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21), + MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22), + MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23), + MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24), + MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25), + MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26), + MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27), + MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28), + MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29), + MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30), + MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31), + + MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0), + MX27_PAD_USBOTG_STP = PAD_ID(PE, 1), + MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2), + MX27_PAD_UART2_CTS = PAD_ID(PE, 3), + MX27_PAD_UART2_RTS = PAD_ID(PE, 4), + MX27_PAD_PWMO = PAD_ID(PE, 5), + MX27_PAD_UART2_TXD = PAD_ID(PE, 6), + MX27_PAD_UART2_RXD = PAD_ID(PE, 7), + MX27_PAD_UART3_TXD = PAD_ID(PE, 8), + MX27_PAD_UART3_RXD = PAD_ID(PE, 9), + MX27_PAD_UART3_CTS = PAD_ID(PE, 10), + MX27_PAD_UART3_RTS = PAD_ID(PE, 11), + MX27_PAD_UART1_TXD = PAD_ID(PE, 12), + MX27_PAD_UART1_RXD = PAD_ID(PE, 13), + MX27_PAD_UART1_CTS = PAD_ID(PE, 14), + MX27_PAD_UART1_RTS = PAD_ID(PE, 15), + MX27_PAD_RTCK = PAD_ID(PE, 16), + MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17), + MX27_PAD_SD1_D0 = PAD_ID(PE, 18), + MX27_PAD_SD1_D1 = PAD_ID(PE, 19), + MX27_PAD_SD1_D2 = PAD_ID(PE, 20), + MX27_PAD_SD1_D3 = PAD_ID(PE, 21), + MX27_PAD_SD1_CMD = PAD_ID(PE, 22), + MX27_PAD_SD1_CLK = PAD_ID(PE, 23), + MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24), + MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25), + MX27_PAD_UNUSED9 = PAD_ID(PE, 26), + MX27_PAD_UNUSED10 = PAD_ID(PE, 27), + MX27_PAD_UNUSED11 = PAD_ID(PE, 28), + MX27_PAD_UNUSED12 = PAD_ID(PE, 29), + MX27_PAD_UNUSED13 = PAD_ID(PE, 30), + MX27_PAD_UNUSED14 = PAD_ID(PE, 31), + + MX27_PAD_NFRB = PAD_ID(PF, 0), + MX27_PAD_NFCLE = PAD_ID(PF, 1), + MX27_PAD_NFWP_B = PAD_ID(PF, 2), + MX27_PAD_NFCE_B = PAD_ID(PF, 3), + MX27_PAD_NFALE = PAD_ID(PF, 4), + MX27_PAD_NFRE_B = PAD_ID(PF, 5), + MX27_PAD_NFWE_B = PAD_ID(PF, 6), + MX27_PAD_PC_POE = PAD_ID(PF, 7), + MX27_PAD_PC_RW_B = PAD_ID(PF, 8), + MX27_PAD_IOIS16 = PAD_ID(PF, 9), + MX27_PAD_PC_RST = PAD_ID(PF, 10), + MX27_PAD_PC_BVD2 = PAD_ID(PF, 11), + MX27_PAD_PC_BVD1 = PAD_ID(PF, 12), + MX27_PAD_PC_VS2 = PAD_ID(PF, 13), + MX27_PAD_PC_VS1 = PAD_ID(PF, 14), + MX27_PAD_CLKO = PAD_ID(PF, 15), + MX27_PAD_PC_PWRON = PAD_ID(PF, 16), + MX27_PAD_PC_READY = PAD_ID(PF, 17), + MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18), + MX27_PAD_PC_CD2_B = PAD_ID(PF, 19), + MX27_PAD_PC_CD1_B = PAD_ID(PF, 20), + MX27_PAD_CS4_B = PAD_ID(PF, 21), + MX27_PAD_CS5_B = PAD_ID(PF, 22), + MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23), + MX27_PAD_UNUSED15 = PAD_ID(PF, 24), + MX27_PAD_UNUSED16 = PAD_ID(PF, 25), + MX27_PAD_UNUSED17 = PAD_ID(PF, 26), + MX27_PAD_UNUSED18 = PAD_ID(PF, 27), + MX27_PAD_UNUSED19 = PAD_ID(PF, 28), + MX27_PAD_UNUSED20 = PAD_ID(PF, 29), + MX27_PAD_UNUSED21 = PAD_ID(PF, 30), + MX27_PAD_UNUSED22 = PAD_ID(PF, 31), +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK), + IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR), + IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7), + IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT), + IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP), + IMX_PINCTRL_PIN(MX27_PAD_LSCLK), + IMX_PINCTRL_PIN(MX27_PAD_LD0), + IMX_PINCTRL_PIN(MX27_PAD_LD1), + IMX_PINCTRL_PIN(MX27_PAD_LD2), + IMX_PINCTRL_PIN(MX27_PAD_LD3), + IMX_PINCTRL_PIN(MX27_PAD_LD4), + IMX_PINCTRL_PIN(MX27_PAD_LD5), + IMX_PINCTRL_PIN(MX27_PAD_LD6), + IMX_PINCTRL_PIN(MX27_PAD_LD7), + IMX_PINCTRL_PIN(MX27_PAD_LD8), + IMX_PINCTRL_PIN(MX27_PAD_LD9), + IMX_PINCTRL_PIN(MX27_PAD_LD10), + IMX_PINCTRL_PIN(MX27_PAD_LD11), + IMX_PINCTRL_PIN(MX27_PAD_LD12), + IMX_PINCTRL_PIN(MX27_PAD_LD13), + IMX_PINCTRL_PIN(MX27_PAD_LD14), + IMX_PINCTRL_PIN(MX27_PAD_LD15), + IMX_PINCTRL_PIN(MX27_PAD_LD16), + IMX_PINCTRL_PIN(MX27_PAD_LD17), + IMX_PINCTRL_PIN(MX27_PAD_REV), + IMX_PINCTRL_PIN(MX27_PAD_CLS), + IMX_PINCTRL_PIN(MX27_PAD_PS), + IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR), + IMX_PINCTRL_PIN(MX27_PAD_HSYNC), + IMX_PINCTRL_PIN(MX27_PAD_VSYNC), + IMX_PINCTRL_PIN(MX27_PAD_CONTRAST), + IMX_PINCTRL_PIN(MX27_PAD_OE_ACD), + + IMX_PINCTRL_PIN(MX27_PAD_UNUSED0), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED1), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED2), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED3), + IMX_PINCTRL_PIN(MX27_PAD_SD2_D0), + IMX_PINCTRL_PIN(MX27_PAD_SD2_D1), + IMX_PINCTRL_PIN(MX27_PAD_SD2_D2), + IMX_PINCTRL_PIN(MX27_PAD_SD2_D3), + IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD), + IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D0), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D1), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D2), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D3), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D4), + IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D5), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D6), + IMX_PINCTRL_PIN(MX27_PAD_CSI_D7), + IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP), + IMX_PINCTRL_PIN(MX27_PAD_USB_PWR), + IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM), + IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP), + + IMX_PINCTRL_PIN(MX27_PAD_UNUSED4), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED5), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED6), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED7), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED8), + IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA), + IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3), + IMX_PINCTRL_PIN(MX27_PAD_TOUT), + IMX_PINCTRL_PIN(MX27_PAD_TIN), + IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS), + IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK), + IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS), + IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK), + IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS), + IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK), + IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS), + IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT), + IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK), + + IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD), + IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14), + IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA), + IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO), + IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO), + IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI), + + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR), + IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS), + IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS), + IMX_PINCTRL_PIN(MX27_PAD_PWMO), + IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD), + IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD), + IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD), + IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD), + IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS), + IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS), + IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD), + IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD), + IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS), + IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS), + IMX_PINCTRL_PIN(MX27_PAD_RTCK), + IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B), + IMX_PINCTRL_PIN(MX27_PAD_SD1_D0), + IMX_PINCTRL_PIN(MX27_PAD_SD1_D1), + IMX_PINCTRL_PIN(MX27_PAD_SD1_D2), + IMX_PINCTRL_PIN(MX27_PAD_SD1_D3), + IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK), + IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED9), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED10), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED11), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED12), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED13), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED14), + + IMX_PINCTRL_PIN(MX27_PAD_NFRB), + IMX_PINCTRL_PIN(MX27_PAD_NFCLE), + IMX_PINCTRL_PIN(MX27_PAD_NFWP_B), + IMX_PINCTRL_PIN(MX27_PAD_NFCE_B), + IMX_PINCTRL_PIN(MX27_PAD_NFALE), + IMX_PINCTRL_PIN(MX27_PAD_NFRE_B), + IMX_PINCTRL_PIN(MX27_PAD_NFWE_B), + IMX_PINCTRL_PIN(MX27_PAD_PC_POE), + IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B), + IMX_PINCTRL_PIN(MX27_PAD_IOIS16), + IMX_PINCTRL_PIN(MX27_PAD_PC_RST), + IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2), + IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1), + IMX_PINCTRL_PIN(MX27_PAD_PC_VS2), + IMX_PINCTRL_PIN(MX27_PAD_PC_VS1), + IMX_PINCTRL_PIN(MX27_PAD_CLKO), + IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON), + IMX_PINCTRL_PIN(MX27_PAD_PC_READY), + IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B), + IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B), + IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B), + IMX_PINCTRL_PIN(MX27_PAD_CS4_B), + IMX_PINCTRL_PIN(MX27_PAD_CS5_B), + IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED15), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED16), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED17), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED18), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED19), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED20), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED21), + IMX_PINCTRL_PIN(MX27_PAD_UNUSED22), +}; + +static struct imx1_pinctrl_soc_info imx27_pinctrl_info = { + .pins = imx27_pinctrl_pads, + .npins = ARRAY_SIZE(imx27_pinctrl_pads), +}; + +static struct of_device_id imx27_pinctrl_of_match[] = { + { .compatible = "fsl,imx27-iomuxc", }, + { /* sentinel */ } +}; + +struct imx27_pinctrl_private { + int num_gpio_childs; + struct platform_device **gpio_dev; + struct mxc_gpio_platform_data *gpio_pdata; +}; + +static int imx27_pinctrl_probe(struct platform_device *pdev) +{ + return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info); +} + +static struct platform_driver imx27_pinctrl_driver = { + .driver = { + .name = "imx27-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx27_pinctrl_of_match), + }, + .probe = imx27_pinctrl_probe, + .remove = imx1_pinctrl_core_remove, +}; + +static int __init imx27_pinctrl_init(void) +{ + return platform_driver_register(&imx27_pinctrl_driver); +} +arch_initcall(imx27_pinctrl_init); + +static void __exit imx27_pinctrl_exit(void) +{ + platform_driver_unregister(&imx27_pinctrl_driver); +} +module_exit(imx27_pinctrl_exit); +MODULE_AUTHOR("Markus Pargmann "); +MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3