From b43502e925487d6f9d9305f172569335aace9cc8 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Tue, 11 Jun 2019 14:06:40 +0100 Subject: dt-bindings: timer: renesas: tmu: Document r8a774a1 bindings Document RZ/G2M (R8A774A1) SoC in the Renesas TMU bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Rob Herring Acked-by: Daniel Lezcano Link: https://lore.kernel.org/r/1560258401-9517-6-git-send-email-fabrizio.castro@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/timer/renesas,tmu.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.txt b/Documentation/devicetree/bindings/timer/renesas,tmu.txt index 13ad07416bdd..9dff7e5cae6a 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.txt +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.txt @@ -10,6 +10,7 @@ Required Properties: - compatible: must contain one or more of the following: - "renesas,tmu-r8a7740" for the r8a7740 TMU + - "renesas,tmu-r8a774a1" for the r8a774A1 TMU - "renesas,tmu-r8a774c0" for the r8a774C0 TMU - "renesas,tmu-r8a7778" for the r8a7778 TMU - "renesas,tmu-r8a7779" for the r8a7779 TMU -- cgit v1.2.3 From 28a5f64ad9c41bfc8a12982fb95637e842b3cd7c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 5 Sep 2019 10:30:41 +0100 Subject: dt-bindings: arm: renesas: Document RZ/G2N SoC DT bindings Add device tree bindings documentation for the Renesas RZ/G2N (r8a774b1) SoC. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/1567675844-19247-2-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 28eb458f761a..9ad31f10f70b 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -116,6 +116,10 @@ properties: - const: hoperun,hihope-rzg2m - const: renesas,r8a774a1 + - description: RZ/G2N (R8A774B1) + items: + - const: renesas,r8a774b1 + - description: RZ/G2E (R8A774C0) items: - enum: -- cgit v1.2.3 From d30286ebbace486af71d3fc35a6ea941c19eb66d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 17 Sep 2019 13:48:12 +0100 Subject: dt-bindings: arm: renesas: Add HopeRun RZ/G2N boards This patch adds board HiHope RZ/G2N (the main board, powered by the R8A774B1) and board HiHope RZ/G2 EX (the expansion board that sits on top of the HiHope RZ/G2N). Both boards are made by Jiangsu HopeRun Software Co., Ltd. (a.k.a. HopeRun). Signed-off-by: Biju Das Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/1568724492-32087-1-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 9ad31f10f70b..bc0b4ec54756 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -118,6 +118,14 @@ properties: - description: RZ/G2N (R8A774B1) items: + - enum: + - hoperun,hihope-rzg2n # HopeRun HiHope RZ/G2N platform + - const: renesas,r8a774b1 + + - items: + - enum: + - hoperun,hihope-rzg2-ex # HopeRun expansion board for HiHope RZ/G2 platforms + - const: hoperun,hihope-rzg2n - const: renesas,r8a774b1 - description: RZ/G2E (R8A774C0) -- cgit v1.2.3 From 56abd14af3c18e8f22dfc74f34c617101b748a4a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 19 Sep 2019 09:17:09 +0100 Subject: dt-bindings: power: rcar-sysc: Document r8a774b1 sysc Document bindings for the RZ/G2N (a.k.a. R8A774B1) system controller. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/1568881036-4404-2-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt index eae2a880155a..712caa5726f7 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -12,6 +12,7 @@ Required properties: - "renesas,r8a7745-sysc" (RZ/G1E) - "renesas,r8a77470-sysc" (RZ/G1C) - "renesas,r8a774a1-sysc" (RZ/G2M) + - "renesas,r8a774b1-sysc" (RZ/G2N) - "renesas,r8a774c0-sysc" (RZ/G2E) - "renesas,r8a7779-sysc" (R-Car H1) - "renesas,r8a7790-sysc" (R-Car H2) -- cgit v1.2.3 From 4d3cae42544775c71521e8ed5adb64c1839036b9 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 19 Sep 2019 09:17:11 +0100 Subject: dt-bindings: reset: rcar-rst: Document r8a774b1 reset module Document bindings for the RZ/G2N (R8A774B1) reset module. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/1568881036-4404-4-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt index b03c48a1150e..d6d6769a0c42 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.txt +++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt @@ -20,6 +20,7 @@ Required properties: - "renesas,r8a7745-rst" (RZ/G1E) - "renesas,r8a77470-rst" (RZ/G1C) - "renesas,r8a774a1-rst" (RZ/G2M) + - "renesas,r8a774b1-rst" (RZ/G2N) - "renesas,r8a774c0-rst" (RZ/G2E) - "renesas,r8a7778-reset-wdt" (R-Car M1A) - "renesas,r8a7779-reset-wdt" (R-Car H1) -- cgit v1.2.3 From e9920bc28a4f9d677f1cf49223142a405c4d615f Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:42:56 +0200 Subject: dt-bindings: ddr: Rename lpddr2 directory Change directory name to be ready for new types of memories. Signed-off-by: Lukasz Luba Reviewed-by: Rob Herring Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/ddr/lpddr2-timings.txt | 52 +++++++++++ Documentation/devicetree/bindings/ddr/lpddr2.txt | 102 +++++++++++++++++++++ .../devicetree/bindings/lpddr2/lpddr2-timings.txt | 52 ----------- .../devicetree/bindings/lpddr2/lpddr2.txt | 102 --------------------- 4 files changed, 154 insertions(+), 154 deletions(-) create mode 100644 Documentation/devicetree/bindings/ddr/lpddr2-timings.txt create mode 100644 Documentation/devicetree/bindings/ddr/lpddr2.txt delete mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt delete mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt new file mode 100644 index 000000000000..9ceb19e0c7fd --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt @@ -0,0 +1,52 @@ +* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin + +Required properties: +- compatible : Should be "jedec,lpddr2-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- max-freq : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). Parameters with +a different unit have a suffix indicating the unit such as 'tRAS-max-ns' +- tRCD +- tWR +- tRAS-min +- tRRD +- tWTR +- tXP +- tRTP +- tDQSCK-max +- tFAW +- tZQCS +- tZQinit +- tRPab +- tZQCL +- tCKESR +- tRAS-max-ns +- tDQSCK-max-derated + +Example: + +timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; +}; diff --git a/Documentation/devicetree/bindings/ddr/lpddr2.txt b/Documentation/devicetree/bindings/ddr/lpddr2.txt new file mode 100644 index 000000000000..ddd40121e6f6 --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr2.txt @@ -0,0 +1,102 @@ +* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2 + +Required properties: +- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2", + "jedec,lpddr2-s4" + + "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type + + "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type + + "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type + +- density : representing density in Mb (Mega bits) + +- io-width : representing bus width. Possible values are 8, 16, and 32 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRRD-min-tck +- tWTR-min-tck +- tXP-min-tck +- tRTP-min-tck +- tCKE-min-tck +- tRPab-min-tck +- tRCD-min-tck +- tWR-min-tck +- tRASmin-min-tck +- tCKESR-min-tck +- tFAW-min-tck + +Child nodes: +- The lpddr2 node may have one or more child nodes of type "lpddr2-timings". + "lpddr2-timings" provides AC timing parameters of the device for + a given speed-bin. The user may provide the timings for as many + speed-bins as is required. Please see Documentation/devicetree/ + bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings" + +Example: + +elpida_ECB240ABACN : lpddr2 { + compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; + density = <2048>; + io-width = <32>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + + timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <200000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <10000>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + +} diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt deleted file mode 100644 index 9ceb19e0c7fd..000000000000 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt +++ /dev/null @@ -1,52 +0,0 @@ -* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin - -Required properties: -- compatible : Should be "jedec,lpddr2-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- max-freq : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). Parameters with -a different unit have a suffix indicating the unit such as 'tRAS-max-ns' -- tRCD -- tWR -- tRAS-min -- tRRD -- tWTR -- tXP -- tRTP -- tDQSCK-max -- tFAW -- tZQCS -- tZQinit -- tRPab -- tZQCL -- tCKESR -- tRAS-max-ns -- tDQSCK-max-derated - -Example: - -timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; -}; diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt deleted file mode 100644 index 58354a075e13..000000000000 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt +++ /dev/null @@ -1,102 +0,0 @@ -* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2 - -Required properties: -- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2", - "jedec,lpddr2-s4" - - "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type - - "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type - - "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type - -- density : representing density in Mb (Mega bits) - -- io-width : representing bus width. Possible values are 8, 16, and 32 - -Optional properties: - -The following optional properties represent the minimum value of some AC -timing parameters of the DDR device in terms of number of clock cycles. -These values shall be obtained from the device data-sheet. -- tRRD-min-tck -- tWTR-min-tck -- tXP-min-tck -- tRTP-min-tck -- tCKE-min-tck -- tRPab-min-tck -- tRCD-min-tck -- tWR-min-tck -- tRASmin-min-tck -- tCKESR-min-tck -- tFAW-min-tck - -Child nodes: -- The lpddr2 node may have one or more child nodes of type "lpddr2-timings". - "lpddr2-timings" provides AC timing parameters of the device for - a given speed-bin. The user may provide the timings for as many - speed-bins as is required. Please see Documentation/devicetree/ - bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" - -Example: - -elpida_ECB240ABACN : lpddr2 { - compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; - density = <2048>; - io-width = <32>; - - tRPab-min-tck = <3>; - tRCD-min-tck = <3>; - tWR-min-tck = <3>; - tRASmin-min-tck = <3>; - tRRD-min-tck = <2>; - tWTR-min-tck = <2>; - tXP-min-tck = <2>; - tRTP-min-tck = <2>; - tCKE-min-tck = <3>; - tCKESR-min-tck = <3>; - tFAW-min-tck = <8>; - - timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - }; - - timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <200000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <10000>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - }; - -} -- cgit v1.2.3 From 1d816d3454427481b08a6bbc16287b1aba395672 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:42:57 +0200 Subject: dt-bindings: ddr: Add bindings for LPDDR3 memories Specifies the AC timing parameters of the LPDDR3 memory device. Signed-off-by: Lukasz Luba Reviewed-by: Rob Herring Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/ddr/lpddr3-timings.txt | 58 +++++++++++++ Documentation/devicetree/bindings/ddr/lpddr3.txt | 97 ++++++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3-timings.txt create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt new file mode 100644 index 000000000000..84705e50a3fd --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt @@ -0,0 +1,58 @@ +* AC timing parameters of LPDDR3 memories for a given speed-bin. + +The structures are based on LPDDR2 and extended where needed. + +Required properties: +- compatible : Should be "jedec,lpddr3-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- reg : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). +- tRFC +- tRRD +- tRPab +- tRPpb +- tRCD +- tRC +- tRAS +- tWTR +- tWR +- tRTP +- tW2W-C2C +- tR2R-C2C +- tFAW +- tXSR +- tXP +- tCKE +- tCKESR +- tMRD + +Example: + +timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; +}; diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt new file mode 100644 index 000000000000..3b2485b84b3f --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt @@ -0,0 +1,97 @@ +* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C + +Required properties: +- compatible : Should be - "jedec,lpddr3" +- density : representing density in Mb (Mega bits) +- io-width : representing bus width. Possible values are 8, 16, 32, 64 +- #address-cells: Must be set to 1 +- #size-cells: Must be set to 0 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRFC-min-tck +- tRRD-min-tck +- tRPab-min-tck +- tRPpb-min-tck +- tRCD-min-tck +- tRC-min-tck +- tRAS-min-tck +- tWTR-min-tck +- tWR-min-tck +- tRTP-min-tck +- tW2W-C2C-min-tck +- tR2R-C2C-min-tck +- tWL-min-tck +- tDQSCK-min-tck +- tRL-min-tck +- tFAW-min-tck +- tXSR-min-tck +- tXP-min-tck +- tCKE-min-tck +- tCKESR-min-tck +- tMRD-min-tck + +Child nodes: +- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". + "lpddr3-timings" provides AC timing parameters of the device for + a given speed-bin. Please see Documentation/devicetree/ + bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings" + +Example: + +samsung_K3QF2F20DB: lpddr3 { + compatible = "Samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; +} -- cgit v1.2.3 From c6d46248cd15f519e83398aef433884238f93c36 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 21 Aug 2019 12:42:59 +0200 Subject: dt-bindings: memory-controllers: Add Exynos5422 DMC device description Add device tree bindings for a new Exynos5422 Dynamic Memory Controller device. Signed-off-by: Lukasz Luba Reviewed-by: Rob Herring Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/exynos5422-dmc.txt | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt new file mode 100644 index 000000000000..02aeb3b5a820 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -0,0 +1,73 @@ +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device + +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM +memory chips are connected. The driver is to monitor the controller in runtime +and switch frequency and voltage. To monitor the usage of the controller in +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which +is able to measure the current load of the memory. +When 'userspace' governor is used for the driver, an application is able to +switch the DMC and memory frequency. + +Required properties for DMC device for Exynos5422: +- compatible: Should be "samsung,exynos5422-dmc". +- clocks : list of clock specifiers, must contain an entry for each + required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL, + CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL, + CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX, +- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2", + "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", + "mout_mclk_cdrex" entries +- devfreq-events : phandles for PPMU devices connected to this DMC. +- vdd-supply : phandle for voltage regulator which is connected. +- reg : registers of two CDREX controllers. +- operating-points-v2 : phandle for OPPs described in v2 definition. +- device-handle : phandle of the connected DRAM memory device. For more + information please refer to documentation file: + Documentation/devicetree/bindings/ddr/lpddr3.txt +- devfreq-events : phandles of the PPMU events used by the controller. +- samsung,syscon-clk : phandle of the clock register set used by the controller, + these registers are used for enabling a 'pause' feature and are not + exposed by clock framework but they must be used in a safe way. + The register offsets are in the driver code and specyfic for this SoC + type. + +Example: + + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x100>, <0x10c30000 0x100>, + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MCLK_CDREX>, + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mclk_cdrex", + operating-points-v2 = <&dmc_opp_table>; + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + device-handle = <&samsung_K3QF2F20DB>; + vdd-supply = <&buck1_reg>; + samsung,syscon-clk = <&clock>; + }; -- cgit v1.2.3 From 296523d933060cad754626c751dc20f64dba7d01 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Thu, 19 Sep 2019 11:26:41 +0200 Subject: dt-bindings: ddr: Add bindings for Samsung LPDDR3 memories Add compatible for Samsung k3qf2f20db LPDDR3 memory bindings, based on at25.txt compatible section. Introduce minor fixes in the old documentation. Suggested-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/ddr/lpddr3.txt | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt index 3b2485b84b3f..a0eda35a86ee 100644 --- a/Documentation/devicetree/bindings/ddr/lpddr3.txt +++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt @@ -1,7 +1,10 @@ * LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C Required properties: -- compatible : Should be - "jedec,lpddr3" +- compatible : Should be ",", and generic value "jedec,lpddr3". + Example "," values: + "samsung,K3QF2F20DB" + - density : representing density in Mb (Mega bits) - io-width : representing bus width. Possible values are 8, 16, 32, 64 - #address-cells: Must be set to 1 @@ -43,7 +46,7 @@ Child nodes: Example: samsung_K3QF2F20DB: lpddr3 { - compatible = "Samsung,K3QF2F20DB", "jedec,lpddr3"; + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; density = <16384>; io-width = <32>; #address-cells = <1>; @@ -73,7 +76,8 @@ samsung_K3QF2F20DB: lpddr3 { timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { compatible = "jedec,lpddr3-timings"; - reg = <800000000>; /* workaround: it shows max-freq */ + /* workaround: 'reg' shows max-freq */ + reg = <800000000>; min-freq = <100000000>; tRFC = <65000>; tRRD = <6000>; -- cgit v1.2.3 From 3d735471d066d7e3ea95c73000edb71c85b6d51f Mon Sep 17 00:00:00 2001 From: Sébastien Szymanski Date: Wed, 24 Jul 2019 14:06:23 +0200 Subject: dt-bindings: arm: Document Armadeus SoM and Dev boards devicetree binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the following Armadeus SoM and Dev boards devicetree binding already supported: - armadeus,imx27-apf27 and armadeus,imx27-apf27dev - armadeus,imx28-apf28 and armadeus,imx28-apf28dev - armadeus,imx51-apf51 and armadeus,imx51-apf51dev - armadeus,imx6{q,dl}-apf6 and armadeus,imx{q,dl}-apf6dev - armadeus,imx6{ul,ull}-opos6ul and armadeus,imx{ul,ull}-opos6uldev Signed-off-by: Sébastien Szymanski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 1b4b4e6573b5..41db01d77c23 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -38,12 +38,16 @@ properties: - description: i.MX27 Product Development Kit items: - enum: + - armadeus,imx27-apf27 # APF27 SoM + - armadeus,imx27-apf27dev # APF27 SoM on APF27Dev board - fsl,imx27-pdk - const: fsl,imx27 - description: i.MX28 based Boards items: - enum: + - armadeus,imx28-apf28 # APF28 SoM + - armadeus,imx28-apf28dev # APF28 SoM on APF28Dev board - fsl,imx28-evk - i2se,duckbill - i2se,duckbill-2 @@ -87,7 +91,8 @@ properties: - description: i.MX51 Babbage Board items: - enum: - - armadeus,imx51-apf51 + - armadeus,imx51-apf51 # APF51 SoM + - armadeus,imx51-apf51dev # APF51 SoM on APF51Dev board - fsl,imx51-babbage - technologic,imx51-ts4800 - const: fsl,imx51 @@ -106,6 +111,8 @@ properties: - description: i.MX6Q based Boards items: - enum: + - armadeus,imx6q-apf6 # APF6 (Quad/Dual) SoM + - armadeus,imx6q-apf6dev # APF6 (Quad/Dual) SoM on APF6Dev board - emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM - emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base - fsl,imx6q-arm2 @@ -126,6 +133,8 @@ properties: - description: i.MX6DL based Boards items: - enum: + - armadeus,imx6dl-apf6 # APF6 (Solo) SoM + - armadeus,imx6dl-apf6dldev # APF6 (Solo) SoM on APF6Dev board - eckelmann,imx6dl-ci4x10 - emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM - emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base @@ -160,6 +169,8 @@ properties: - description: i.MX6UL based Boards items: - enum: + - armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM + - armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board - kontron,imx6ul-n6310-som # Kontron N6310 SOM - const: fsl,imx6ul @@ -180,6 +191,8 @@ properties: - description: i.MX6ULL based Boards items: - enum: + - armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM + - armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board - const: fsl,imx6ull -- cgit v1.2.3 From 40192209b96b65ff3588e063c5b984e946baaaae Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 2 Oct 2019 08:04:52 +0200 Subject: dt-bindings: memory-controllers: exynos5422-dmc: Add interrupt mode Add description for optional interrupt lines. It provides a new operation mode, which uses internal performance counters interrupt when overflow. This is more reliable than using default polling mode implemented in devfreq. Signed-off-by: Lukasz Luba Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/exynos5422-dmc.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt index 02aeb3b5a820..e2434cac4858 100644 --- a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -31,6 +31,14 @@ Required properties for DMC device for Exynos5422: The register offsets are in the driver code and specyfic for this SoC type. +Optional properties for DMC device for Exynos5422: +- interrupt-parent : The parent interrupt controller. +- interrupts : Contains the IRQ line numbers for the DMC internal performance + event counters in DREX0 and DREX1 channels. Align with specification of the + interrupt line(s) in the interrupt-parent controller. +- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the + same as in the 'interrupts' list above. + Example: ppmu_dmc0_0: ppmu@10d00000 { @@ -70,4 +78,7 @@ Example: device-handle = <&samsung_K3QF2F20DB>; vdd-supply = <&buck1_reg>; samsung,syscon-clk = <&clock>; + interrupt-parent = <&combiner>; + interrupts = <16 0>, <16 1>; + interrupt-names = "drex_0", "drex_1"; }; -- cgit v1.2.3 From 45cb61b4f3bf991ac2011dbc4a155bd5f3b29ebe Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:55 +0200 Subject: arm64: dts: rockchip: document explicit px30 cru dependencies The px30 contains 2 separate clock controllers the regular cru creating most clocks as well as the pmucru managing the GPLL and some other clocks. The gpll of course also is needed by the cru, so while we normally do rely on clock names to associate clocks getting probed later on (for example xin32k coming from an i2c device in most cases) it is safer to declare the explicit dependency between the two crus. This makes sure that for example the clock-framework probes them in the correct order from the start. The assigned-clocks properties were simply working by chance in the past so split them accordingly to the 2 crus to honor the loading direction. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20190917082659.25549-9-heiko@sntech.de --- .../bindings/clock/rockchip,px30-cru.txt | 5 +++++ arch/arm64/boot/dts/rockchip/px30.dtsi | 25 +++++++++++++--------- 2 files changed, 20 insertions(+), 10 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt index 39f0c1ac84ee..55e78cddec8c 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt +++ b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt @@ -10,6 +10,11 @@ Required Properties: - compatible: CRU should be "rockchip,px30-cru" - reg: physical base address of the controller and length of memory mapped region. +- clocks: A list of phandle + clock-specifier pairs for the clocks listed + in clock-names +- clock-names: Should contain the following: + - "xin24m" for both PMUCRU and CRU + - "gpll" for CRU (sourced from PMUCRU) - #clock-cells: should be 1. - #reset-cells: should be 1. diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 63499d27994c..9ad1c2f04ea9 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -667,33 +667,38 @@ cru: clock-controller@ff2b0000 { compatible = "rockchip,px30-cru"; reg = <0x0 0xff2b0000 0x0 0x1000>; + clocks = <&xin24m>, <&pmucru PLL_GPLL>; + clock-names = "xin24m", "gpll"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_NPLL>; - assigned-clock-rates = <1188000000>; + assigned-clocks = <&cru PLL_NPLL>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; + + assigned-clock-rates = <1188000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <200000000>; }; pmucru: clock-controller@ff2bc000 { compatible = "rockchip,px30-pmucru"; reg = <0x0 0xff2bc000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, - <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; + <&pmucru SCLK_WIFI_PMU>; assigned-clock-rates = <1200000000>, <100000000>, - <26000000>, <600000000>, - <200000000>, <200000000>, - <150000000>, <150000000>, - <100000000>, <200000000>; + <26000000>; }; usb20_otg: usb@ff300000 { -- cgit v1.2.3 From c595826faa9705e04ef6ec4de2b1c6775815482b Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 17 Sep 2019 10:26:57 +0200 Subject: dt-bindings: document PX30 usb2phy General Register Files One of the separate General Register Files contains the registers for controlling the usb2phy, so add the necessary binding compatible for it. Signed-off-by: Heiko Stuebner Acked-by: Rob Herring Link: https://lore.kernel.org/r/20190917082659.25549-11-heiko@sntech.de --- Documentation/devicetree/bindings/soc/rockchip/grf.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt index 46e27cd69f18..d7debec26ba4 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt @@ -30,6 +30,7 @@ Required Properties: - compatible: SGRF should be one of the following - "rockchip,rk3288-sgrf", "syscon": for rk3288 - compatible: USB2PHYGRF should be one of the followings + - "rockchip,px30-usb2phy-grf", "syscon": for px30 - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328 - compatible: USBGRF should be one of the following - "rockchip,rv1108-usbgrf", "syscon": for rv1108 -- cgit v1.2.3 From 41f277be1d028e64fb8d5e91a7ce74df600bde54 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 2 Oct 2019 19:44:01 +0200 Subject: dt-bindings: memory-controllers: exynos5422-dmc: Correct example syntax and memory region After adding the interrupt properties to Exynos5422 DMC bindings example, the mapped memory region must be big enough to access performance counters registers. Fix also syntax errors (semicolons) and adjust indentation. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Lukasz Luba --- .../devicetree/bindings/memory-controllers/exynos5422-dmc.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt index e2434cac4858..02e4a1f862f1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt @@ -55,7 +55,7 @@ Example: dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; - reg = <0x10c20000 0x100>, <0x10c30000 0x100>, + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>, @@ -63,7 +63,7 @@ Example: <&clock CLK_MOUT_BPLL>, <&clock CLK_SCLK_BPLL>, <&clock CLK_MOUT_MX_MSPLL_CCORE>, - <&clock CLK_MOUT_MCLK_CDREX>, + <&clock CLK_MOUT_MCLK_CDREX>; clock-names = "fout_spll", "mout_sclk_spll", "ff_dout_spll2", @@ -71,10 +71,10 @@ Example: "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", - "mout_mclk_cdrex", + "mout_mclk_cdrex"; operating-points-v2 = <&dmc_opp_table>; devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, - <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; device-handle = <&samsung_K3QF2F20DB>; vdd-supply = <&buck1_reg>; samsung,syscon-clk = <&clock>; -- cgit v1.2.3 From b7dda5cae714db40c9c161e0cab10d00b2d1f8a1 Mon Sep 17 00:00:00 2001 From: Jianxin Pan Date: Thu, 12 Sep 2019 04:19:28 -0400 Subject: dt-bindings: arm: amlogic: add A1 bindings Add bindings for the new Amlogic A1 SoC family. A1 is an application processor designed for smart audio and IoT applications, with dual core Cortex-A35. Signed-off-by: Jianxin Pan Reviewed-by: Rob Herring Reviewed-by: Martin Blumenstingl Reviewed-by: Kevin Hilman Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 99015cef8bb1..0ef45ac2ecb6 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -156,4 +156,8 @@ properties: - seirobotics,sei610 - khadas,vim3l - const: amlogic,sm1 + + - description: Boards with the Amlogic Meson A1 A113L SoC + items: + - const: amlogic,a1 ... -- cgit v1.2.3 From 46e723133fdc5ef903e5d11121a44fdbd2ca306c Mon Sep 17 00:00:00 2001 From: Jianxin Pan Date: Thu, 12 Sep 2019 04:19:29 -0400 Subject: dt-bindings: arm: amlogic: add Amlogic AD401 bindings Add the compatible for the Amlogic A1 Based AD401 board. Signed-off-by: Jianxin Pan Reviewed-by: Rob Herring Reviewed-by: Martin Blumenstingl Reviewed-by: Kevin Hilman Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 0ef45ac2ecb6..ee5703c4eded 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -159,5 +159,7 @@ properties: - description: Boards with the Amlogic Meson A1 A113L SoC items: + - enum: + - amlogic,ad401 - const: amlogic,a1 ... -- cgit v1.2.3 From 46f4fa76fc7d0d8ec9dbd83044bb7e10f4d7b9a0 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 23 Sep 2019 18:13:54 +0400 Subject: dt-bindings: Add vendor prefix for Ugoos Ugoos Industrial Co., Ltd. are a manufacturer of ARM based TV Boxes/Dongles, Digital Signage and Advertisement Solutions [0]. [0] (https://ugoos.com) Acked-by: Rob Herring Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 967e78c5ec0a..e711cbc8e55b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -988,6 +988,8 @@ patternProperties: description: Ubiquiti Networks "^udoo,.*": description: Udoo + "^ugoos,.*": + description: Ugoos Industrial Co., Ltd. "^uniwest,.*": description: United Western Technologies Corp (UniWest) "^upisemi,.*": -- cgit v1.2.3 From 150778111f8bac18034a54511aaec05ee6424c72 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 23 Sep 2019 18:13:55 +0400 Subject: dt-bindings: arm: amlogic: Add support for the Ugoos AM6 The Ugoos AM6 is based on the Amlogic W400 (G12B) reference design using the S922X chipset. Acked-by: Rob Herring Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index ee5703c4eded..84b07ef9864e 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -147,6 +147,7 @@ properties: - enum: - hardkernel,odroid-n2 - khadas,vim3 + - ugoos,am6 - const: amlogic,s922x - const: amlogic,g12b -- cgit v1.2.3 From 39f137f55cc26992da897dac0450fb53076d8d5b Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 9 Sep 2019 19:01:26 +0400 Subject: dt-bindings: arm: amlogic: update libretech-cc compatible Update the compatible for the Libre Computer aml-s905x-cc to be more descriptive using the format introduced with the aml-s805x-ac board. Signed-off-by: Christian Hewitt Reviewed-by: Kevin Hilman Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 84b07ef9864e..c6a443352ef8 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -94,7 +94,7 @@ properties: - amlogic,p212 - hwacom,amazetv - khadas,vim - - libretech,cc + - libretech,aml-s905x-cc - nexbox,a95x - const: amlogic,s905x - const: amlogic,meson-gxl -- cgit v1.2.3 From 2537831bbc19bbc797366d72a5a71c4383d64c8b Mon Sep 17 00:00:00 2001 From: Ben Peled Date: Fri, 4 Oct 2019 16:27:20 +0200 Subject: dt-bindings: ap80x: replace AP806 with AP80x Rename the text file and update "AP806" into "AP806/AP807" where relevant. Signed-off-by: Ben Peled Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Signed-off-by: Gregory CLEMENT --- .../arm/marvell/ap806-system-controller.txt | 177 --------------------- .../arm/marvell/ap80x-system-controller.txt | 177 +++++++++++++++++++++ 2 files changed, 177 insertions(+), 177 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt create mode 100644 Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt deleted file mode 100644 index 26410fbb85be..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt +++ /dev/null @@ -1,177 +0,0 @@ -Marvell Armada AP806 System Controller -====================================== - -The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K -SoCs. It contains system controllers, which provide several registers -giving access to numerous features: clocks, pin-muxing and many other -SoC configuration items. This DT binding allows to describe these -system controllers. - -For the top level node: - - compatible: must be: "syscon", "simple-mfd"; - - reg: register area of the AP806 system controller - -SYSTEM CONTROLLER 0 -=================== - -Clocks: -------- - - -The Device Tree node representing the AP806/AP807 system controller -provides a number of clocks: - - - 0: reference clock of CPU cluster 0 - - 1: reference clock of CPU cluster 1 - - 2: fixed PLL at 1200 Mhz - - 3: MSS clock, derived from the fixed PLL - -Required properties: - - - compatible: must be one of: - * "marvell,ap806-clock" - * "marvell,ap807-clock" - - #clock-cells: must be set to 1 - -Pinctrl: --------- - -For common binding part and usage, refer to -Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt. - -Required properties: -- compatible must be "marvell,ap806-pinctrl", - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -name pins functions -================================================================================ -mpp0 0 gpio, sdio(clk), spi0(clk) -mpp1 1 gpio, sdio(cmd), spi0(miso) -mpp2 2 gpio, sdio(d0), spi0(mosi) -mpp3 3 gpio, sdio(d1), spi0(cs0n) -mpp4 4 gpio, sdio(d2), i2c0(sda) -mpp5 5 gpio, sdio(d3), i2c0(sdk) -mpp6 6 gpio, sdio(ds) -mpp7 7 gpio, sdio(d4), uart1(rxd) -mpp8 8 gpio, sdio(d5), uart1(txd) -mpp9 9 gpio, sdio(d6), spi0(cs1n) -mpp10 10 gpio, sdio(d7) -mpp11 11 gpio, uart0(txd) -mpp12 12 gpio, sdio(pw_off), sdio(hw_rst) -mpp13 13 gpio -mpp14 14 gpio -mpp15 15 gpio -mpp16 16 gpio -mpp17 17 gpio -mpp18 18 gpio -mpp19 19 gpio, uart0(rxd), sdio(pw_off) - -GPIO: ------ -For common binding part and usage, refer to -Documentation/devicetree/bindings/gpio/gpio-mvebu.txt. - -Required properties: - -- compatible: "marvell,armada-8k-gpio" - -- offset: offset address inside the syscon block - -Example: -ap_syscon: system-controller@6f4000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f4000 0x1000>; - - ap_clk: clock { - compatible = "marvell,ap806-clock"; - #clock-cells = <1>; - }; - - ap_pinctrl: pinctrl { - compatible = "marvell,ap806-pinctrl"; - }; - - ap_gpio: gpio { - compatible = "marvell,armada-8k-gpio"; - offset = <0x1040>; - ngpios = <19>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&ap_pinctrl 0 0 19>; - }; -}; - -SYSTEM CONTROLLER 1 -=================== - -Thermal: --------- - -For common binding part and usage, refer to -Documentation/devicetree/bindings/thermal/thermal.txt - -The thermal IP can probe the temperature all around the processor. It -may feature several channels, each of them wired to one sensor. - -It is possible to setup an overheat interrupt by giving at least one -critical point to any subnode of the thermal-zone node. - -Required properties: -- compatible: must be one of: - * marvell,armada-ap806-thermal -- reg: register range associated with the thermal functions. - -Optional properties: -- interrupts: overheat interrupt handle. Should point to line 18 of the - SEI irqchip. See interrupt-controller/interrupts.txt -- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer - to this IP and represents the channel ID. There is one sensor per - channel. O refers to the thermal IP internal channel, while positive - IDs refer to each CPU. - -Example: -ap_syscon1: system-controller@6f8000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f8000 0x1000>; - - ap_thermal: thermal-sensor@80 { - compatible = "marvell,armada-ap806-thermal"; - reg = <0x80 0x10>; - interrupt-parent = <&sei>; - interrupts = <18>; - #thermal-sensor-cells = <1>; - }; -}; - -Cluster clocks: ---------------- - -Device Tree Clock bindings for cluster clock of Marvell -AP806/AP807. Each cluster contain up to 2 CPUs running at the same -frequency. - -Required properties: - - compatible: must be one of: - * "marvell,ap806-cpu-clock" - * "marvell,ap807-cpu-clock" -- #clock-cells : should be set to 1. - -- clocks : shall be the input parent clock(s) phandle for the clock - (one per cluster) - -- reg: register range associated with the cluster clocks - -ap_syscon1: system-controller@6f8000 { - compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd"; - reg = <0x6f8000 0x1000>; - - cpu_clk: clock-cpu@278 { - compatible = "marvell,ap806-cpu-clock"; - clocks = <&ap_clk 0>, <&ap_clk 1>; - #clock-cells = <1>; - reg = <0x278 0xa30>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt new file mode 100644 index 000000000000..098d932fc963 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt @@ -0,0 +1,177 @@ +Marvell Armada AP80x System Controller +====================================== + +The AP806/AP807 is one of the two core HW blocks of the Marvell Armada +7K/8K/931x SoCs. It contains system controllers, which provide several +registers giving access to numerous features: clocks, pin-muxing and +many other SoC configuration items. This DT binding allows to describe +these system controllers. + +For the top level node: + - compatible: must be: "syscon", "simple-mfd"; + - reg: register area of the AP80x system controller + +SYSTEM CONTROLLER 0 +=================== + +Clocks: +------- + + +The Device Tree node representing the AP806/AP807 system controller +provides a number of clocks: + + - 0: reference clock of CPU cluster 0 + - 1: reference clock of CPU cluster 1 + - 2: fixed PLL at 1200 Mhz + - 3: MSS clock, derived from the fixed PLL + +Required properties: + + - compatible: must be one of: + * "marvell,ap806-clock" + * "marvell,ap807-clock" + - #clock-cells: must be set to 1 + +Pinctrl: +-------- + +For common binding part and usage, refer to +Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt. + +Required properties: +- compatible must be "marvell,ap806-pinctrl", + +Available mpp pins/groups and functions: +Note: brackets (x) are not part of the mpp name for marvell,function and given +only for more detailed description in this document. + +name pins functions +================================================================================ +mpp0 0 gpio, sdio(clk), spi0(clk) +mpp1 1 gpio, sdio(cmd), spi0(miso) +mpp2 2 gpio, sdio(d0), spi0(mosi) +mpp3 3 gpio, sdio(d1), spi0(cs0n) +mpp4 4 gpio, sdio(d2), i2c0(sda) +mpp5 5 gpio, sdio(d3), i2c0(sdk) +mpp6 6 gpio, sdio(ds) +mpp7 7 gpio, sdio(d4), uart1(rxd) +mpp8 8 gpio, sdio(d5), uart1(txd) +mpp9 9 gpio, sdio(d6), spi0(cs1n) +mpp10 10 gpio, sdio(d7) +mpp11 11 gpio, uart0(txd) +mpp12 12 gpio, sdio(pw_off), sdio(hw_rst) +mpp13 13 gpio +mpp14 14 gpio +mpp15 15 gpio +mpp16 16 gpio +mpp17 17 gpio +mpp18 18 gpio +mpp19 19 gpio, uart0(rxd), sdio(pw_off) + +GPIO: +----- +For common binding part and usage, refer to +Documentation/devicetree/bindings/gpio/gpio-mvebu.txt. + +Required properties: + +- compatible: "marvell,armada-8k-gpio" + +- offset: offset address inside the syscon block + +Example: +ap_syscon: system-controller@6f4000 { + compatible = "syscon", "simple-mfd"; + reg = <0x6f4000 0x1000>; + + ap_clk: clock { + compatible = "marvell,ap806-clock"; + #clock-cells = <1>; + }; + + ap_pinctrl: pinctrl { + compatible = "marvell,ap806-pinctrl"; + }; + + ap_gpio: gpio { + compatible = "marvell,armada-8k-gpio"; + offset = <0x1040>; + ngpios = <19>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&ap_pinctrl 0 0 19>; + }; +}; + +SYSTEM CONTROLLER 1 +=================== + +Thermal: +-------- + +For common binding part and usage, refer to +Documentation/devicetree/bindings/thermal/thermal.txt + +The thermal IP can probe the temperature all around the processor. It +may feature several channels, each of them wired to one sensor. + +It is possible to setup an overheat interrupt by giving at least one +critical point to any subnode of the thermal-zone node. + +Required properties: +- compatible: must be one of: + * marvell,armada-ap806-thermal +- reg: register range associated with the thermal functions. + +Optional properties: +- interrupts: overheat interrupt handle. Should point to line 18 of the + SEI irqchip. See interrupt-controller/interrupts.txt +- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer + to this IP and represents the channel ID. There is one sensor per + channel. O refers to the thermal IP internal channel, while positive + IDs refer to each CPU. + +Example: +ap_syscon1: system-controller@6f8000 { + compatible = "syscon", "simple-mfd"; + reg = <0x6f8000 0x1000>; + + ap_thermal: thermal-sensor@80 { + compatible = "marvell,armada-ap806-thermal"; + reg = <0x80 0x10>; + interrupt-parent = <&sei>; + interrupts = <18>; + #thermal-sensor-cells = <1>; + }; +}; + +Cluster clocks: +--------------- + +Device Tree Clock bindings for cluster clock of Marvell +AP806/AP807. Each cluster contain up to 2 CPUs running at the same +frequency. + +Required properties: + - compatible: must be one of: + * "marvell,ap806-cpu-clock" + * "marvell,ap807-cpu-clock" +- #clock-cells : should be set to 1. + +- clocks : shall be the input parent clock(s) phandle for the clock + (one per cluster) + +- reg: register range associated with the cluster clocks + +ap_syscon1: system-controller@6f8000 { + compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd"; + reg = <0x6f8000 0x1000>; + + cpu_clk: clock-cpu@278 { + compatible = "marvell,ap806-cpu-clock"; + clocks = <&ap_clk 0>, <&ap_clk 1>; + #clock-cells = <1>; + reg = <0x278 0xa30>; + }; +}; -- cgit v1.2.3 From e1e42ae4ca2a3f16b0f9da4149e3e2f5fe169e6d Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 4 Oct 2019 16:27:33 +0200 Subject: dt-bindings: marvell: Convert the SoC compatibles description to YAML Convert the file detailing Marvell EBU compatibles to json-schema. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Signed-off-by: Gregory CLEMENT --- .../bindings/arm/marvell/armada-7k-8k.txt | 24 ------------- .../bindings/arm/marvell/armada-7k-8k.yaml | 40 ++++++++++++++++++++++ 2 files changed, 40 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt create mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt deleted file mode 100644 index df98a9c82a8c..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt +++ /dev/null @@ -1,24 +0,0 @@ -Marvell Armada 7K/8K Platforms Device Tree Bindings ---------------------------------------------------- - -Boards using a SoC of the Marvell Armada 7K or 8K families must carry -the following root node property: - - - compatible, with one of the following values: - - - "marvell,armada7020", "marvell,armada-ap806-dual", "marvell,armada-ap806" - when the SoC being used is the Armada 7020 - - - "marvell,armada7040", "marvell,armada-ap806-quad", "marvell,armada-ap806" - when the SoC being used is the Armada 7040 - - - "marvell,armada8020", "marvell,armada-ap806-dual", "marvell,armada-ap806" - when the SoC being used is the Armada 8020 - - - "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806" - when the SoC being used is the Armada 8040 - -Example: - -compatible = "marvell,armada7040-db", "marvell,armada7040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml new file mode 100644 index 000000000000..294595e00028 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR X11) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/armada-7k-8k.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 7K/8K Platforms Device Tree Bindings + +maintainers: + - Gregory CLEMENT + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Armada 7020 SoC + items: + - const: marvell,armada7020 + - const: marvell,armada-ap806-dual + - const: marvell,armada-ap806 + + - description: Armada 7040 SoC + items: + - const: marvell,armada7040 + - const: marvell,armada-ap806-quad + - const: marvell,armada-ap806 + + - description: Armada 8020 SoC + items: + - const: marvell,armada8020 + - const: marvell,armada-ap806-dual + - const: marvell,armada-ap806 + + - description: Armada 8040 SoC + items: + - const: marvell,armada8040 + - const: marvell,armada-ap806-quad + - const: marvell,armada-ap806 -- cgit v1.2.3 From 6a380172f171d81259e90ddc99d25fec20e56e1e Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Fri, 4 Oct 2019 16:27:34 +0200 Subject: dt-bindings: marvell: Declare the CN913x SoC compatibles Describe the compatible properties for the new Marvell SoCs: * CN9130: 1x AP807-quad + 1x CP115 (1x embedded) * CN9131: 1x AP807-quad + 2x CP115 (1x embedded + 1x modular) * CN9132: 1x AP807-quad + 3x CP115 (1x embedded + 2x modular) CP115 are similar to CP110 in terms of features. There are three development boards based on these SoCs: * CN9130-DB: comes as a single mother board (with the CP115 bundled) * CN9131-DB: same as CN9130-DB with one additional modular CP115 * CN9132-DB: same as CN9130-DB with two additional modular CP115 Signed-off-by: Grzegorz Jaszczyk Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Signed-off-by: Gregory CLEMENT --- .../bindings/arm/marvell/armada-7k-8k.yaml | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml index 294595e00028..a9828c50c0fb 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml @@ -38,3 +38,24 @@ properties: - const: marvell,armada8040 - const: marvell,armada-ap806-quad - const: marvell,armada-ap806 + + - description: Armada CN9130 SoC with no external CP + items: + - const: marvell,cn9130 + - const: marvell,armada-ap807-quad + - const: marvell,armada-ap807 + + - description: Armada CN9131 SoC with one external CP + items: + - const: marvell,cn9131 + - const: marvell,cn9130 + - const: marvell,armada-ap807-quad + - const: marvell,armada-ap807 + + - description: Armada CN9132 SoC with two external CPs + items: + - const: marvell,cn9132 + - const: marvell,cn9131 + - const: marvell,cn9130 + - const: marvell,armada-ap807-quad + - const: marvell,armada-ap807 -- cgit v1.2.3 From ab06837dd269b600396b298e9f4678d02b11b71d Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 16 Aug 2019 21:01:08 +0200 Subject: dt-bindings: arm: Convert BCM2835 board/soc bindings to json-schema Convert the BCM2835/6/7 SoC bindings to DT schema format using json-schema. All the other Broadcom boards are maintained by Florian Fainelli. Signed-off-by: Stefan Wahren Acked-by: Eric Anholt Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/bcm/bcm2835.yaml | 48 ++++++++++++++++ .../devicetree/bindings/arm/bcm/brcm,bcm2835.txt | 67 ---------------------- 2 files changed, 48 insertions(+), 67 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml delete mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml new file mode 100644 index 000000000000..67bf9e236c42 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/bcm2835.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2711/BCM2835 Platforms Device Tree Bindings + +maintainers: + - Eric Anholt + - Stefan Wahren + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BCM2835 based Boards + items: + - enum: + - raspberrypi,model-a + - raspberrypi,model-a-plus + - raspberrypi,model-b + - raspberrypi,model-b-i2c0 # Raspberry Pi Model B (no P5) + - raspberrypi,model-b-rev2 + - raspberrypi,model-b-plus + - raspberrypi,compute-module + - raspberrypi,model-zero + - raspberrypi,model-zero-w + - const: brcm,bcm2835 + + - description: BCM2836 based Boards + items: + - enum: + - raspberrypi,2-model-b + - const: brcm,bcm2836 + + - description: BCM2837 based Boards + items: + - enum: + - raspberrypi,3-model-a-plus + - raspberrypi,3-model-b + - raspberrypi,3-model-b-plus + - raspberrypi,3-compute-module + - raspberrypi,3-compute-module-lite + - const: brcm,bcm2837 + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt deleted file mode 100644 index 245328f36580..000000000000 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +++ /dev/null @@ -1,67 +0,0 @@ -Broadcom BCM2835 device tree bindings -------------------------------------------- - -Raspberry Pi Model A -Required root node properties: -compatible = "raspberrypi,model-a", "brcm,bcm2835"; - -Raspberry Pi Model A+ -Required root node properties: -compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; - -Raspberry Pi Model B -Required root node properties: -compatible = "raspberrypi,model-b", "brcm,bcm2835"; - -Raspberry Pi Model B (no P5) -early model B with I2C0 rather than I2C1 routed to the expansion header -Required root node properties: -compatible = "raspberrypi,model-b-i2c0", "brcm,bcm2835"; - -Raspberry Pi Model B rev2 -Required root node properties: -compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; - -Raspberry Pi Model B+ -Required root node properties: -compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; - -Raspberry Pi 2 Model B -Required root node properties: -compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; - -Raspberry Pi 3 Model A+ -Required root node properties: -compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837"; - -Raspberry Pi 3 Model B -Required root node properties: -compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; - -Raspberry Pi 3 Model B+ -Required root node properties: -compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837"; - -Raspberry Pi Compute Module -Required root node properties: -compatible = "raspberrypi,compute-module", "brcm,bcm2835"; - -Raspberry Pi Compute Module 3 -Required root node properties: -compatible = "raspberrypi,3-compute-module", "brcm,bcm2837"; - -Raspberry Pi Compute Module 3 Lite -Required root node properties: -compatible = "raspberrypi,3-compute-module-lite", "brcm,bcm2837"; - -Raspberry Pi Zero -Required root node properties: -compatible = "raspberrypi,model-zero", "brcm,bcm2835"; - -Raspberry Pi Zero W -Required root node properties: -compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; - -Generic BCM2835 board -Required root node properties: -compatible = "brcm,bcm2835"; -- cgit v1.2.3 From 091d3aecc5154bfd9056094b813ef5384294ef4b Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 16 Aug 2019 22:09:20 +0200 Subject: dt-bindings: arm: bcm2835: Add Raspberry Pi 4 to DT schema Add new Raspberry Pi 4 to DT schema. Signed-off-by: Stefan Wahren Acked-by: Eric Anholt Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml index 67bf9e236c42..dd52e29b0642 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -15,6 +15,12 @@ properties: const: '/' compatible: oneOf: + - description: BCM2711 based Boards + items: + - enum: + - raspberrypi,4-model-b + - const: brcm,bcm2711 + - description: BCM2835 based Boards items: - enum: -- cgit v1.2.3 From d9bd62baf0db5f67c428f19f210183be4b21ced7 Mon Sep 17 00:00:00 2001 From: Kamel Bouhara Date: Fri, 11 Oct 2019 14:50:20 +0200 Subject: dt-bindings: Add vendor prefix for Overkiz SAS Overkiz is a smarthome solutions provider, more information on: https://www.overkiz.com Signed-off-by: Kamel Bouhara Link: https://lore.kernel.org/r/20191011125022.16329-2-kamel.bouhara@bootlin.com Acked-by: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 967e78c5ec0a..9b1582b3bdc3 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -705,6 +705,8 @@ patternProperties: description: Ortus Technology Co., Ltd. "^osddisplays,.*": description: OSD Displays + "^overkiz,.*": + description: Overkiz SAS "^ovti,.*": description: OmniVision Technologies "^oxsemi,.*": -- cgit v1.2.3 From caa1e65783c919f316e4f93410c6f59e5661c359 Mon Sep 17 00:00:00 2001 From: Kamel Bouhara Date: Fri, 11 Oct 2019 14:50:21 +0200 Subject: dt-bindings: arm: at91: Document Kizbox3 HS board binding Document devicetree binding of SAMA5D27 Kizbox3 HS board from Overkiz SAS. Signed-off-by: Kamel Bouhara Link: https://lore.kernel.org/r/20191011125022.16329-3-kamel.bouhara@bootlin.com Reviewed-by: Rob Herring Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 6e168abcd4d1..c0869cb860f3 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -45,6 +45,13 @@ properties: - const: atmel,at91sam9x5 - const: atmel,at91sam9 + - description: Overkiz kizbox3 board + items: + - const: overkiz,kizbox3-hs + - const: atmel,sama5d27 + - const: atmel,sama5d2 + - const: atmel,sama5 + - items: - const: atmel,sama5d27 - const: atmel,sama5d2 -- cgit v1.2.3 From 6780153607e21c497ec2a2db590492b71f211844 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Fri, 12 Jul 2019 11:52:30 +0200 Subject: dt-bindings: arm: cpu: Add Marvell MMP3 SMP enable method Add the enable method for the second PJ4B core of the Marvell MMP3 SoC. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index cb30895e3b67..c23c24ff7575 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -189,6 +189,7 @@ properties: - marvell,armada-390-smp - marvell,armada-xp-smp - marvell,98dx3236-smp + - marvell,mmp3-smp - mediatek,mt6589-smp - mediatek,mt81xx-tz-smp - qcom,gcc-msm8660 -- cgit v1.2.3 From c3294ea3417056c85d0eaaab1b76ed8a98e29171 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Thu, 22 Aug 2019 10:34:23 +0200 Subject: dt-bindings: arm: Convert Marvell MMP board/soc bindings to json-schema Convert Marvell MMP SoC bindings to DT schema format using json-schema. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/mrvl/mrvl.txt | 14 ---------- .../devicetree/bindings/arm/mrvl/mrvl.yaml | 32 ++++++++++++++++++++++ 2 files changed, 32 insertions(+), 14 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mrvl/mrvl.txt create mode 100644 Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt deleted file mode 100644 index 951687528efb..000000000000 --- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt +++ /dev/null @@ -1,14 +0,0 @@ -Marvell Platforms Device Tree Bindings ----------------------------------------------------- - -PXA168 Aspenite Board -Required root node properties: - - compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168"; - -PXA910 DKB Board -Required root node properties: - - compatible = "mrvl,pxa910-dkb"; - -MMP2 Brownstone Board -Required root node properties: - - compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2"; diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml new file mode 100644 index 000000000000..ef59d6e35bb6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mrvl/mrvl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Platforms Device Tree Bindings + +maintainers: + - Lubomir Rintel + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: PXA168 Aspenite Board + items: + - enum: + - mrvl,pxa168-aspenite + - const: mrvl,pxa168 + - description: PXA910 DKB Board + items: + - enum: + - mrvl,pxa910-dkb + - const: mrvl,pxa910 + - description: MMP2 based boards + items: + - enum: + - mrvl,mmp2-brownstone + - const: mrvl,mmp2 +... -- cgit v1.2.3 From 95aecb71b84e01704a36cae8016e12e486374784 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Fri, 21 Jun 2019 14:20:59 +0200 Subject: dt-bindings: arm: mrvl: Document MMP3 compatible string Marvel MMP3 is a successor to MMP2, containing similar peripherals with two PJ4B cores. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml index ef59d6e35bb6..818dfe6de512 100644 --- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml +++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml @@ -29,4 +29,7 @@ properties: - enum: - mrvl,mmp2-brownstone - const: mrvl,mmp2 + - description: MMP3 based boards + items: + - const: mrvl,mmp3 ... -- cgit v1.2.3 From f79a13fe5cb0395b5b7dd2caed463d9563fac0d0 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Fri, 12 Jul 2019 11:45:40 +0200 Subject: dt-bindings: mrvl,intc: Add a MMP3 interrupt controller Similar to MMP2 one, but has an extra range for the other core. The muxes stay the same. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring --- .../devicetree/bindings/interrupt-controller/mrvl,intc.txt | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt index 608fee15a4cf..a0ed02725a9d 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt @@ -1,13 +1,17 @@ * Marvell MMP Interrupt controller Required properties: -- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or - "mrvl,mmp2-mux-intc" +- compatible : Should be + "mrvl,mmp-intc" on Marvel MMP, + "mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or + "marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3 - reg : Address and length of the register set of the interrupt controller. If the interrupt controller is intc, address and length means the range - of the whole interrupt controller. If the interrupt controller is mux-intc, - address and length means one register. Since address of mux-intc is in the - range of intc. mux-intc is secondary interrupt controller. + of the whole interrupt controller. The "marvell,mmp3-intc" controller + also has a secondary range for the second CPU core. If the interrupt + controller is mux-intc, address and length means one register. Since + address of mux-intc is in the range of intc. mux-intc is secondary + interrupt controller. - reg-names : Name of the register set of the interrupt controller. It's only required in mux-intc interrupt controller. - interrupts : Should be the port interrupt shared by mux interrupts. It's -- cgit v1.2.3 From e50a0c6247be96de1ad5c1454bc929eb6eea69ff Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Fri, 21 Jun 2019 14:31:06 +0200 Subject: dt-bindings: phy-mmp3-usb: Add bindings This is the PHY chip for USB OTG on MMP3 platform. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt b/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt new file mode 100644 index 000000000000..7183b9102f91 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt @@ -0,0 +1,13 @@ +Marvell MMP3 USB PHY +-------------------- + +Required properties: +- compatible: must be "marvell,mmp3-usb-phy" +- #phy-cells: must be 0 + +Example: + usb-phy: usb-phy@d4207000 { + compatible = "marvell,mmp3-usb-phy"; + reg = <0xd4207000 0x40>; + #phy-cells = <0>; + }; -- cgit v1.2.3 From 577dd5de09906e37a407a4326d17e58f6051fa2d Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 30 Sep 2019 16:24:58 +0100 Subject: arm64: dts: juno: add GPU subsystem Since we now have bindings for Mali Midgard GPUs, let's use them to describe Juno's GPU subsystem, if only because we can. Juno sports a Mali-T624 integrated behind an MMU-400 (as a gesture towards virtualisation), in their own dedicated power domain with DVFS controlled by the SCP. CC: Liviu Dudau CC: Sudeep Holla CC: Lorenzo Pieralisi Signed-off-by: Robin Murphy Acked-by: Liviu Dudau Reviewed-by: Rob Herring Signed-off-by: Sudeep Holla --- .../devicetree/bindings/gpu/arm,mali-midgard.yaml | 5 +++- arch/arm64/boot/dts/arm/juno-base.dtsi | 27 ++++++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index 47bc1ac36426..018f3ae4b43c 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -22,6 +22,10 @@ properties: - enum: - amlogic,meson-gxm-mali - const: arm,mali-t820 + - items: + - enum: + - arm,juno-mali + - const: arm,mali-t624 - items: - enum: - rockchip,rk3288-mali @@ -39,7 +43,6 @@ properties: - samsung,exynos5433-mali - const: arm,mali-t760 - # "arm,mali-t624" # "arm,mali-t628" # "arm,mali-t830" # "arm,mali-t880" diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 26a039a028b8..9e3e8ce6adfe 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -35,6 +35,18 @@ clock-names = "apb_pclk"; }; + smmu_gpu: iommu@2b400000 { + compatible = "arm,mmu-400", "arm,smmu-v1"; + reg = <0x0 0x2b400000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + power-domains = <&scpi_devpd 1>; + dma-coherent; + status = "disabled"; + }; + smmu_pcie: iommu@2b500000 { compatible = "arm,mmu-401", "arm,smmu-v1"; reg = <0x0 0x2b500000 0x0 0x10000>; @@ -487,6 +499,21 @@ }; }; + gpu: gpu@2d000000 { + compatible = "arm,juno-mali", "arm,mali-t624"; + reg = <0 0x2d000000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "gpu", "job", "mmu"; + clocks = <&scpi_dvfs 2>; + power-domains = <&scpi_devpd 1>; + dma-coherent; + /* The SMMU is only really of interest to bare-metal hypervisors */ + /* iommus = <&smmu_gpu 0>; */ + status = "disabled"; + }; + sram: sram@2e000000 { compatible = "arm,juno-sram-ns", "mmio-sram"; reg = <0x0 0x2e000000 0x0 0x8000>; -- cgit v1.2.3 From 09f156d97e530c2ac631620f7b29508ff5cc4e6f Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Sun, 8 Sep 2019 13:05:28 +0100 Subject: dt-bindings: arm: renesas: Convert 'renesas,prr' to json-schema Convert Renesas Product Register bindings documentation to json-schema. Signed-off-by: Simon Horman Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20190908120528.9392-1-horms+renesas@verge.net.au Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/arm/renesas,prr.txt | 20 ------------- .../devicetree/bindings/arm/renesas,prr.yaml | 35 ++++++++++++++++++++++ 2 files changed, 35 insertions(+), 20 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.txt create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.txt b/Documentation/devicetree/bindings/arm/renesas,prr.txt deleted file mode 100644 index 08e482e953ca..000000000000 --- a/Documentation/devicetree/bindings/arm/renesas,prr.txt +++ /dev/null @@ -1,20 +0,0 @@ -Renesas Product Register - -Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that -allows to retrieve SoC product and revision information. If present, a device -node for this register should be added. - -Required properties: - - compatible: Must be one of: - "renesas,prr" - "renesas,bsid" - - reg: Base address and length of the register block. - - -Examples --------- - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.yaml b/Documentation/devicetree/bindings/arm/renesas,prr.yaml new file mode 100644 index 000000000000..7f8d17f33983 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/renesas,prr.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/renesas,prr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Product Register + +maintainers: + - Geert Uytterhoeven + - Magnus Damm + +description: | + Most Renesas ARM SoCs have a Product Register or Boundary Scan ID + Register that allows to retrieve SoC product and revision information. + If present, a device node for this register should be added. + +properties: + compatible: + enum: + - renesas,prr + - renesas,bsid + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; -- cgit v1.2.3 From 24169f0a453754a7c463cb7d480d6358aaf72c30 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 16 Oct 2019 17:11:09 +0200 Subject: dt-bindings: arm: renesas: Add R-Car M3-N ULCB with Kingfisher Document the use of the Kingfisher expansion board with the R-Car Starter Kit Pro equipped with an R-Car M3-N SoC. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20191016151109.30747-1-geert+renesas@glider.be --- Documentation/devicetree/bindings/arm/renesas.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index bc0b4ec54756..397eb7f8b0a4 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -211,9 +211,11 @@ properties: - enum: - renesas,h3ulcb - renesas,m3ulcb + - renesas,m3nulcb - enum: - renesas,r8a7795 - renesas,r8a7796 + - renesas,r8a77965 - description: R-Car M3-N (R8A77965) items: -- cgit v1.2.3 From 997c5329a5ab2942be3c9a84fbb0b05fa8f24194 Mon Sep 17 00:00:00 2001 From: Eddy Petrișor Date: Wed, 16 Oct 2019 15:48:23 +0300 Subject: dt-bindings: arm: fsl: Add the S32V234-EVB board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add entry for the NXP S32V234 Customer Evaluation Board to the board/SoC bindings. Signed-off-by: Eddy Petrișor Signed-off-by: Stefan-Gabriel Mirea Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 41db01d77c23..8c3fb5b1ba8b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -348,4 +348,10 @@ properties: - fsl,ls2088a-rdb - const: fsl,ls2088a + - description: S32V234 based Boards + items: + - enum: + - fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board + - const: fsl,s32v234 + ... -- cgit v1.2.3 From 0d3ccc1cdeb75269e2a7e849c3c4ce2f73cc1e18 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sat, 19 Oct 2019 20:39:39 +0200 Subject: dt-bindings: arm: realtek: Tidy up conversion to json-schema MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Restore the device names for compatible strings as comments. Prepare for adding more SoCs by inserting oneOf. Fixes: 693af5f3eeaa ("dt-bindings: arm: Convert Realtek board/soc bindings to json-schema") Reviewed-by: Rob Herring Signed-off-by: Andreas Färber --- Documentation/devicetree/bindings/arm/realtek.yaml | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documentation/devicetree/bindings/arm/realtek.yaml index 3528b61963b4..66458a3f422d 100644 --- a/Documentation/devicetree/bindings/arm/realtek.yaml +++ b/Documentation/devicetree/bindings/arm/realtek.yaml @@ -13,11 +13,12 @@ properties: $nodename: const: '/' compatible: - # RTD1295 SoC based boards - items: - - enum: - - mele,v9 - - probox2,ava - - zidoo,x9s - - const: realtek,rtd1295 + oneOf: + # RTD1295 SoC based boards + - items: + - enum: + - mele,v9 # MeLE V9 + - probox2,ava # ProBox2 AVA + - zidoo,x9s # Zidoo X9S + - const: realtek,rtd1295 ... -- cgit v1.2.3 From 085d610c501638cc8310086ad33920f7fbf78c51 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Mon, 21 Oct 2019 16:45:55 +0800 Subject: dt-bindings: Add doc about rk3308 General Register Files RK3308 GRF is divided into four sections: GRF, SGRF, DETECTGRF, COREGRF. This patch add documentation for it. Signed-off-by: Andy Yan Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20191021084555.28356-1-andy.yan@rock-chips.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/soc/rockchip/grf.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt index d7debec26ba4..61d89749918a 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt @@ -10,6 +10,12 @@ From RK3368 SoCs, the GRF is divided into two sections, On RK3328 SoCs, the GRF adds a section for USB2PHYGRF, +ON RK3308 SoC, the GRF is divided into four sections: +- GRF, used for general non-secure system, +- SGRF, used for general secure system, +- DETECTGRF, used for audio codec system, +- COREGRF, used for pvtm, + Required Properties: - compatible: GRF should be one of the following: @@ -19,10 +25,15 @@ Required Properties: - "rockchip,rk3188-grf", "syscon": for rk3188 - "rockchip,rk3228-grf", "syscon": for rk3228 - "rockchip,rk3288-grf", "syscon": for rk3288 + - "rockchip,rk3308-grf", "syscon": for rk3308 - "rockchip,rk3328-grf", "syscon": for rk3328 - "rockchip,rk3368-grf", "syscon": for rk3368 - "rockchip,rk3399-grf", "syscon": for rk3399 - "rockchip,rv1108-grf", "syscon": for rv1108 +- compatible: DETECTGRF should be one of the following: + - "rockchip,rk3308-detect-grf", "syscon": for rk3308 +- compatilbe: COREGRF should be one of the following: + - "rockchip,rk3308-core-grf", "syscon": for rk3308 - compatible: PMUGRF should be one of the following: - "rockchip,px30-pmugrf", "syscon": for px30 - "rockchip,rk3368-pmugrf", "syscon": for rk3368 -- cgit v1.2.3 From 1ebed0392519dc69078e7593517c0b970d3c4448 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Mon, 21 Oct 2019 16:46:42 +0800 Subject: dt-bindings: Add doc for rk3308-evb Add compatible for RK3308 Evaluation board Signed-off-by: Andy Yan Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20191021084642.28562-1-andy.yan@rock-chips.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index c82c5e57d44c..dd38d060cdd7 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -464,6 +464,11 @@ properties: - rockchip,rk3288-evb-rk808 - const: rockchip,rk3288 + - description: Rockchip RK3308 Evaluation board + items: + - const: rockchip,rk3308-evb + - const: rockchip,rk3308 + - description: Rockchip RK3328 Evaluation board items: - const: rockchip,rk3328-evb -- cgit v1.2.3 From 2e91e788570d56c3eba944a1560318fd8666d651 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 17 Oct 2019 11:13:03 +0800 Subject: dt-bindings: arm: imx: Add the i.MX8MN LPDDR4 EVK board Add board binding for i.MX8MN LPDDR4 EVK board. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 8c3fb5b1ba8b..38017a97fcea 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -246,6 +246,7 @@ properties: items: - enum: - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board + - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board - const: fsl,imx8mn - description: i.MX8MQ based Boards -- cgit v1.2.3 From d4c9be5142cd672a0e80a831e607c1e55e222f78 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Thu, 24 Oct 2019 09:22:37 +0000 Subject: dt-bindings: arm: fsl: Document Variscite i.MX6q devicetree Document the Variscite i.MX6qdl board devicetree binding already supported: - variscite,dt6customboard Signed-off-by: Oliver Graute Cc: Shawn Guo Cc: Neil Armstrong Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 38017a97fcea..b08ae59cc57f 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -121,6 +121,7 @@ properties: - fsl,imx6q-sabresd - technologic,imx6q-ts4900 - technologic,imx6q-ts7970 + - variscite,dt6customboard - const: fsl,imx6q - description: i.MX6QP based Boards -- cgit v1.2.3 From 6013b8b0005e33cb130a0f2e5c4126e74a34021f Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 16 Oct 2017 05:24:06 +0200 Subject: dt-bindings: arm: realtek: Document RTD1293 and Synology DS418j MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define compatible strings for Realtek RTD1293 SoC and Synology DiskStation DS418j NAS. Cc: info@synology.com Acked-by: Rob Herring [AF: Converted to json-schema] Signed-off-by: Andreas Färber --- Documentation/devicetree/bindings/arm/realtek.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documentation/devicetree/bindings/arm/realtek.yaml index 66458a3f422d..6ea3a79825cc 100644 --- a/Documentation/devicetree/bindings/arm/realtek.yaml +++ b/Documentation/devicetree/bindings/arm/realtek.yaml @@ -14,6 +14,12 @@ properties: const: '/' compatible: oneOf: + # RTD1293 SoC based boards + - items: + - enum: + - synology,ds418j # Synology DiskStation DS418j + - const: realtek,rtd1293 + # RTD1295 SoC based boards - items: - enum: -- cgit v1.2.3 From 1f3295994dc572b9928df748361df3bbbf2e68f3 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 16 Oct 2017 05:42:42 +0200 Subject: dt-bindings: arm: realtek: Document RTD1296 and Synology DS418 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define compatible strings for Realtek RTD1296 SoC and Synology DiskStation DS418 NAS. Cc: info@synology.com Acked-by: Rob Herring [AF: Converted to json-schema] Signed-off-by: Andreas Färber --- Documentation/devicetree/bindings/arm/realtek.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documentation/devicetree/bindings/arm/realtek.yaml index 6ea3a79825cc..ab59de17152d 100644 --- a/Documentation/devicetree/bindings/arm/realtek.yaml +++ b/Documentation/devicetree/bindings/arm/realtek.yaml @@ -27,4 +27,10 @@ properties: - probox2,ava # ProBox2 AVA - zidoo,x9s # Zidoo X9S - const: realtek,rtd1295 + + # RTD1296 SoC based boards + - items: + - enum: + - synology,ds418 # Synology DiskStation DS418 + - const: realtek,rtd1296 ... -- cgit v1.2.3 From db45f0f05c3ae9f9e9c2784e779fcf5e812db425 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Thu, 25 Jul 2019 18:18:30 +0300 Subject: dt-bindings: regulator: Document regulators coupling of NVIDIA Tegra20/30 SoCs There is voltage coupling between three regulators on Tegra20 boards and between two on Tegra30. The voltage coupling is a SoC-level feature and thus it is mandatory and common for all of the Tegra boards. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../regulator/nvidia,tegra-regulators-coupling.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/nvidia,tegra-regulators-coupling.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/regulator/nvidia,tegra-regulators-coupling.txt b/Documentation/devicetree/bindings/regulator/nvidia,tegra-regulators-coupling.txt new file mode 100644 index 000000000000..4bf2dbf7c6cc --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/nvidia,tegra-regulators-coupling.txt @@ -0,0 +1,65 @@ +NVIDIA Tegra Regulators Coupling +================================ + +NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators. +Thus on Tegra20 there are 3 coupled regulators and on NVIDIA Tegra30 +there are 2. + +Tegra20 voltage coupling +------------------------ + +On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU. +The CORE and RTC voltages shall be in a range of 170mV from each other +and they both shall be higher than the CPU voltage by at least 120mV. + +Tegra30 voltage coupling +------------------------ + +On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE +and CPU voltages shall be in a range of 300mV from each other and CORE +voltage shall be higher than the CPU by N mV, where N depends on the CPU +voltage. + +Required properties: +- nvidia,tegra-core-regulator: Boolean property that designates regulator + as the "Core domain" voltage regulator. +- nvidia,tegra-rtc-regulator: Boolean property that designates regulator + as the "RTC domain" voltage regulator. +- nvidia,tegra-cpu-regulator: Boolean property that designates regulator + as the "CPU domain" voltage regulator. + +Example: + + pmic { + regulators { + core_vdd_reg: core { + regulator-name = "vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>; + regulator-coupled-max-spread = <170000 550000>; + + nvidia,tegra-core-regulator; + }; + + rtc_vdd_reg: rtc { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>; + regulator-coupled-max-spread = <170000 550000>; + + nvidia,tegra-rtc-regulator; + }; + + cpu_vdd_reg: cpu { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; + regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>; + regulator-coupled-max-spread = <550000 550000>; + + nvidia,tegra-cpu-regulator; + }; + }; + }; -- cgit v1.2.3 From 8da65c377b21d1b3607f42f7f7646ca9bd87cb2a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 12 Aug 2019 00:00:37 +0300 Subject: dt-bindings: memory: tegra30: Convert to Tegra124 YAML The Tegra30 binding will actually differ from the Tegra124 a tad, in particular the EMEM configuration description. Hence rename the binding to Tegra124 during of the conversion to YAML. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../memory-controllers/nvidia,tegra124-mc.yaml | 152 +++++++++++++++++++++ .../memory-controllers/nvidia,tegra30-mc.txt | 123 ----------------- 2 files changed, 152 insertions(+), 123 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml new file mode 100644 index 000000000000..30d9fb193d7f --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra124 SoC Memory Controller + +maintainers: + - Jon Hunter + - Thierry Reding + +description: | + Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller. + These are interleaved to provide high performance with the load shared across + two memory channels. The Tegra124 Memory Controller handles memory requests + from internal clients and arbitrates among them to allocate memory bandwidth + for DDR3L and LPDDR3 SDRAMs. + +properties: + compatible: + const: nvidia,tegra124-mc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: mc + + interrupts: + maxItems: 1 + + "#reset-cells": + const: 1 + + "#iommu-cells": + const: 1 + +patternProperties: + "^emc-timings-[0-9]+$": + type: object + properties: + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Value of RAM_CODE this timing set is used for. + + patternProperties: + "^timing-[0-9]+$": + type: object + properties: + clock-frequency: + description: + Memory clock rate in Hz. + minimum: 1000000 + maximum: 1066000000 + + nvidia,emem-configuration: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Values to be written to the EMEM register block. See section + "15.6.1 MC Registers" in the TRM. + items: + - description: MC_EMEM_ARB_CFG + - description: MC_EMEM_ARB_OUTSTANDING_REQ + - description: MC_EMEM_ARB_TIMING_RCD + - description: MC_EMEM_ARB_TIMING_RP + - description: MC_EMEM_ARB_TIMING_RC + - description: MC_EMEM_ARB_TIMING_RAS + - description: MC_EMEM_ARB_TIMING_FAW + - description: MC_EMEM_ARB_TIMING_RRD + - description: MC_EMEM_ARB_TIMING_RAP2PRE + - description: MC_EMEM_ARB_TIMING_WAP2PRE + - description: MC_EMEM_ARB_TIMING_R2R + - description: MC_EMEM_ARB_TIMING_W2W + - description: MC_EMEM_ARB_TIMING_R2W + - description: MC_EMEM_ARB_TIMING_W2R + - description: MC_EMEM_ARB_DA_TURNS + - description: MC_EMEM_ARB_DA_COVERS + - description: MC_EMEM_ARB_MISC0 + - description: MC_EMEM_ARB_MISC1 + - description: MC_EMEM_ARB_RING1_THROTTLE + + required: + - clock-frequency + - nvidia,emem-configuration + + additionalProperties: false + + required: + - nvidia,ram-code + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#reset-cells" + - "#iommu-cells" + +additionalProperties: false + +examples: + - | + memory-controller@70019000 { + compatible = "nvidia,tegra124-mc"; + reg = <0x0 0x70019000 0x0 0x1000>; + clocks = <&tegra_car 32>; + clock-names = "mc"; + + interrupts = <0 77 4>; + + #iommu-cells = <1>; + #reset-cells = <1>; + + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt deleted file mode 100644 index a878b5908a4d..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt +++ /dev/null @@ -1,123 +0,0 @@ -NVIDIA Tegra Memory Controller device tree bindings -=================================================== - -memory-controller node ----------------------- - -Required properties: -- compatible: Should be "nvidia,tegra-mc" -- reg: Physical base address and length of the controller's registers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - mc: the module's clock input -- interrupts: The interrupt outputs from the controller. -- #reset-cells : Should be 1. This cell represents memory client module ID. - The assignments may be found in header file - or in the TRM documentation. - -Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210: -- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines - the SWGROUP of the master. - -This device implements an IOMMU that complies with the generic IOMMU binding. -See ../iommu/iommu.txt for details. - -emc-timings subnode -------------------- - -The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in -register PMC_STRAPPING_OPT_A). - -Required properties for "emc-timings" nodes : -- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for. - -timing subnode --------------- - -Each "emc-timings" node should contain a subnode for every supported EMC clock rate. - -Required properties for timing nodes : -- clock-frequency : Should contain the memory clock rate in Hz. -- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC -(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be -specified, according to the board documentation: - - MC_EMEM_ARB_CFG - MC_EMEM_ARB_OUTSTANDING_REQ - MC_EMEM_ARB_TIMING_RCD - MC_EMEM_ARB_TIMING_RP - MC_EMEM_ARB_TIMING_RC - MC_EMEM_ARB_TIMING_RAS - MC_EMEM_ARB_TIMING_FAW - MC_EMEM_ARB_TIMING_RRD - MC_EMEM_ARB_TIMING_RAP2PRE - MC_EMEM_ARB_TIMING_WAP2PRE - MC_EMEM_ARB_TIMING_R2R - MC_EMEM_ARB_TIMING_W2W - MC_EMEM_ARB_TIMING_R2W - MC_EMEM_ARB_TIMING_W2R - MC_EMEM_ARB_DA_TURNS - MC_EMEM_ARB_DA_COVERS - MC_EMEM_ARB_MISC0 - MC_EMEM_ARB_MISC1 - MC_EMEM_ARB_RING1_THROTTLE - -Example SoC include file: - -/ { - mc: memory-controller@70019000 { - compatible = "nvidia,tegra124-mc"; - reg = <0x0 0x70019000 0x0 0x1000>; - clocks = <&tegra_car TEGRA124_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - #reset-cells = <1>; - }; - - sdhci@700b0000 { - compatible = "nvidia,tegra124-sdhci"; - ... - iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; - resets = <&mc TEGRA124_MC_RESET_SDMMC1>; - }; -}; - -Example board file: - -/ { - memory-controller@70019000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - - nvidia,emem-configuration = < - 0x40040001 /* MC_EMEM_ARB_CFG */ - 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303 /* MC_EMEM_ARB_MISC0 */ - 0x70000f03 /* MC_EMEM_ARB_MISC1 */ - 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ - >; - }; - }; - }; -}; -- cgit v1.2.3 From 785685b7a106185c63cb927ff5e4f518e47ad08c Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 12 Aug 2019 00:00:38 +0300 Subject: dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller Add binding for the NVIDIA Tegra30 SoC Memory Controller. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../memory-controllers/nvidia,tegra30-mc.yaml | 167 +++++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml new file mode 100644 index 000000000000..84fd57bcf0dc --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra30 SoC Memory Controller + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +description: | + Tegra30 Memory Controller architecturally consists of the following parts: + + Arbitration Domains, which can handle a single request or response per + clock from a group of clients. Typically, a system has a single Arbitration + Domain, but an implementation may divide the client space into multiple + Arbitration Domains to increase the effective system bandwidth. + + Protocol Arbiter, which manage a related pool of memory devices. A system + may have a single Protocol Arbiter or multiple Protocol Arbiters. + + Memory Crossbar, which routes request and responses between Arbitration + Domains and Protocol Arbiters. In the simplest version of the system, the + Memory Crossbar is just a pass through between a single Arbitration Domain + and a single Protocol Arbiter. + + Global Resources, which include things like configuration registers which + are shared across the Memory Subsystem. + + The Tegra30 Memory Controller handles memory requests from internal clients + and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2 + SDRAMs. + +properties: + compatible: + const: nvidia,tegra30-mc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: mc + + interrupts: + maxItems: 1 + + "#reset-cells": + const: 1 + + "#iommu-cells": + const: 1 + +patternProperties: + "^emc-timings-[0-9]+$": + type: object + properties: + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Value of RAM_CODE this timing set is used for. + + patternProperties: + "^timing-[0-9]+$": + type: object + properties: + clock-frequency: + description: + Memory clock rate in Hz. + minimum: 1000000 + maximum: 900000000 + + nvidia,emem-configuration: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Values to be written to the EMEM register block. See section + "18.13.1 MC Registers" in the TRM. + items: + - description: MC_EMEM_ARB_CFG + - description: MC_EMEM_ARB_OUTSTANDING_REQ + - description: MC_EMEM_ARB_TIMING_RCD + - description: MC_EMEM_ARB_TIMING_RP + - description: MC_EMEM_ARB_TIMING_RC + - description: MC_EMEM_ARB_TIMING_RAS + - description: MC_EMEM_ARB_TIMING_FAW + - description: MC_EMEM_ARB_TIMING_RRD + - description: MC_EMEM_ARB_TIMING_RAP2PRE + - description: MC_EMEM_ARB_TIMING_WAP2PRE + - description: MC_EMEM_ARB_TIMING_R2R + - description: MC_EMEM_ARB_TIMING_W2W + - description: MC_EMEM_ARB_TIMING_R2W + - description: MC_EMEM_ARB_TIMING_W2R + - description: MC_EMEM_ARB_DA_TURNS + - description: MC_EMEM_ARB_DA_COVERS + - description: MC_EMEM_ARB_MISC0 + - description: MC_EMEM_ARB_RING1_THROTTLE + + required: + - clock-frequency + - nvidia,emem-configuration + + additionalProperties: false + + required: + - nvidia,ram-code + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#reset-cells" + - "#iommu-cells" + +additionalProperties: false + +examples: + - | + memory-controller@7000f000 { + compatible = "nvidia,tegra30-mc"; + reg = <0x7000f000 0x400>; + clocks = <&tegra_car 32>; + clock-names = "mc"; + + interrupts = <0 77 4>; + + #iommu-cells = <1>; + #reset-cells = <1>; + + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < + 0x0000000a /* MC_EMEM_ARB_CFG */ + 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000010 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */ + 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + }; -- cgit v1.2.3 From 641262f5e1ed5c96799e17595893fa1a703616ac Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 12 Aug 2019 00:00:39 +0300 Subject: dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory Controller Add device-tree binding for NVIDIA Tegra30 External Memory Controller. The binding is based on the Tegra124 EMC binding since hardware is similar, although there are couple significant differences. Note that the memory timing description is given in a platform-specific form because there is no detailed information on how to convert a typical-common DDR timing into the register values. The timing format is borrowed from downstream kernel, hence there is no hurdle in regards to upstreaming of memory timings for the boards. Acked-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../memory-controllers/nvidia,tegra30-emc.yaml | 336 +++++++++++++++++++++ 1 file changed, 336 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml new file mode 100644 index 000000000000..7fe0ca14e324 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -0,0 +1,336 @@ +# SPDX-License-Identifier: (GPL-2.0) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra30 SoC External Memory Controller + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +description: | + The EMC interfaces with the off-chip SDRAM to service the request stream + sent from Memory Controller. The EMC also has various performance-affecting + settings beyond the obvious SDRAM configuration parameters and initialization + settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2, + LPDDR3, and DDR3. + +properties: + compatible: + const: nvidia,tegra30-emc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + nvidia,memory-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of the Memory Controller node. + +patternProperties: + "^emc-timings-[0-9]+$": + type: object + properties: + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Value of RAM_CODE this timing set is used for. + + patternProperties: + "^timing-[0-9]+$": + type: object + properties: + clock-frequency: + description: + Memory clock rate in Hz. + minimum: 1000000 + maximum: 900000000 + + nvidia,emc-auto-cal-interval: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Pad calibration interval in microseconds. + minimum: 0 + maximum: 2097151 + + nvidia,emc-mode-1: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Mode Register 1. + + nvidia,emc-mode-2: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Mode Register 2. + + nvidia,emc-mode-reset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Mode Register 0. + + nvidia,emc-zcal-cnt-long: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of EMC clocks to wait before issuing any commands after + sending ZCAL_MRW_CMD. + minimum: 0 + maximum: 1023 + + nvidia,emc-cfg-dyn-self-ref: + type: boolean + description: + Dynamic self-refresh enabled. + + nvidia,emc-cfg-periodic-qrst: + type: boolean + description: + FBIO "read" FIFO periodic resetting enabled. + + nvidia,emc-configuration: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + EMC timing characterization data. These are the registers + (see section "18.13.2 EMC Registers" in the TRM) whose values + need to be specified, according to the board documentation. + items: + - description: EMC_RC + - description: EMC_RFC + - description: EMC_RAS + - description: EMC_RP + - description: EMC_R2W + - description: EMC_W2R + - description: EMC_R2P + - description: EMC_W2P + - description: EMC_RD_RCD + - description: EMC_WR_RCD + - description: EMC_RRD + - description: EMC_REXT + - description: EMC_WEXT + - description: EMC_WDV + - description: EMC_QUSE + - description: EMC_QRST + - description: EMC_QSAFE + - description: EMC_RDV + - description: EMC_REFRESH + - description: EMC_BURST_REFRESH_NUM + - description: EMC_PRE_REFRESH_REQ_CNT + - description: EMC_PDEX2WR + - description: EMC_PDEX2RD + - description: EMC_PCHG2PDEN + - description: EMC_ACT2PDEN + - description: EMC_AR2PDEN + - description: EMC_RW2PDEN + - description: EMC_TXSR + - description: EMC_TXSRDLL + - description: EMC_TCKE + - description: EMC_TFAW + - description: EMC_TRPAB + - description: EMC_TCLKSTABLE + - description: EMC_TCLKSTOP + - description: EMC_TREFBW + - description: EMC_QUSE_EXTRA + - description: EMC_FBIO_CFG6 + - description: EMC_ODT_WRITE + - description: EMC_ODT_READ + - description: EMC_FBIO_CFG5 + - description: EMC_CFG_DIG_DLL + - description: EMC_CFG_DIG_DLL_PERIOD + - description: EMC_DLL_XFORM_DQS0 + - description: EMC_DLL_XFORM_DQS1 + - description: EMC_DLL_XFORM_DQS2 + - description: EMC_DLL_XFORM_DQS3 + - description: EMC_DLL_XFORM_DQS4 + - description: EMC_DLL_XFORM_DQS5 + - description: EMC_DLL_XFORM_DQS6 + - description: EMC_DLL_XFORM_DQS7 + - description: EMC_DLL_XFORM_QUSE0 + - description: EMC_DLL_XFORM_QUSE1 + - description: EMC_DLL_XFORM_QUSE2 + - description: EMC_DLL_XFORM_QUSE3 + - description: EMC_DLL_XFORM_QUSE4 + - description: EMC_DLL_XFORM_QUSE5 + - description: EMC_DLL_XFORM_QUSE6 + - description: EMC_DLL_XFORM_QUSE7 + - description: EMC_DLI_TRIM_TXDQS0 + - description: EMC_DLI_TRIM_TXDQS1 + - description: EMC_DLI_TRIM_TXDQS2 + - description: EMC_DLI_TRIM_TXDQS3 + - description: EMC_DLI_TRIM_TXDQS4 + - description: EMC_DLI_TRIM_TXDQS5 + - description: EMC_DLI_TRIM_TXDQS6 + - description: EMC_DLI_TRIM_TXDQS7 + - description: EMC_DLL_XFORM_DQ0 + - description: EMC_DLL_XFORM_DQ1 + - description: EMC_DLL_XFORM_DQ2 + - description: EMC_DLL_XFORM_DQ3 + - description: EMC_XM2CMDPADCTRL + - description: EMC_XM2DQSPADCTRL2 + - description: EMC_XM2DQPADCTRL2 + - description: EMC_XM2CLKPADCTRL + - description: EMC_XM2COMPPADCTRL + - description: EMC_XM2VTTGENPADCTRL + - description: EMC_XM2VTTGENPADCTRL2 + - description: EMC_XM2QUSEPADCTRL + - description: EMC_XM2DQSPADCTRL3 + - description: EMC_CTT_TERM_CTRL + - description: EMC_ZCAL_INTERVAL + - description: EMC_ZCAL_WAIT_CNT + - description: EMC_MRS_WAIT_CNT + - description: EMC_AUTO_CAL_CONFIG + - description: EMC_CTT + - description: EMC_CTT_DURATION + - description: EMC_DYN_SELF_REF_CONTROL + - description: EMC_FBIO_SPARE + - description: EMC_CFG_RSV + + required: + - clock-frequency + - nvidia,emc-auto-cal-interval + - nvidia,emc-mode-1 + - nvidia,emc-mode-2 + - nvidia,emc-mode-reset + - nvidia,emc-zcal-cnt-long + - nvidia,emc-configuration + + additionalProperties: false + + required: + - nvidia,ram-code + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - nvidia,memory-controller + +additionalProperties: false + +examples: + - | + external-memory-controller@7000f400 { + compatible = "nvidia,tegra30-emc"; + reg = <0x7000f400 0x400>; + interrupts = <0 78 4>; + clocks = <&tegra_car 57>; + + nvidia,memory-controller = <&mc>; + + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000020 /* EMC_RC */ + 0x0000006a /* EMC_RFC */ + 0x00000017 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000c /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000011 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001412 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000e /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x00000016 /* EMC_RW2PDEN */ + 0x00000072 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000007 /* EMC_TCLKSTOP */ + 0x00001453 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf00b0191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008 /* EMC_DLL_XFORM_DQS0 */ + 0x00000008 /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x00000008 /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0c000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0155000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + }; -- cgit v1.2.3 From a24607032359297c4d7cc629e9c52bb5159730b1 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 23 Oct 2019 22:05:05 +0200 Subject: dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine This patch adds documentation for Device-Tree bindings for the Crypto Engine cryptographic accelerator driver. Reviewed-by: Rob Herring Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- .../bindings/crypto/allwinner,sun8i-ce.yaml | 88 ++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml new file mode 100644 index 000000000000..2c459b8c76ff --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/allwinner,sun8i-ce.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner Crypto Engine driver + +maintainers: + - Corentin Labbe + +properties: + compatible: + enum: + - allwinner,sun8i-h3-crypto + - allwinner,sun8i-r40-crypto + - allwinner,sun50i-a64-crypto + - allwinner,sun50i-h5-crypto + - allwinner,sun50i-h6-crypto + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Bus clock + - description: Module clock + - description: MBus clock + minItems: 2 + maxItems: 3 + + clock-names: + items: + - const: bus + - const: mod + - const: ram + minItems: 2 + maxItems: 3 + + resets: + maxItems: 1 + +if: + properties: + compatible: + items: + const: allwinner,sun50i-h6-crypto +then: + properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 +else: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + + crypto: crypto@1c15000 { + compatible = "allwinner,sun8i-h3-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CE>; + }; + -- cgit v1.2.3 From 193ffd3656602d857a576df7fd77a1423584da25 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 23 Oct 2019 14:29:07 +0200 Subject: dt-bindings: arm: renesas: Document R-Car M3-W+ SoC DT bindings Add device tree binding documentation for the Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Reviewed-by: Rob Herring Reviewed-by: Eugeniu Rosca Link: https://lore.kernel.org/r/20191023122911.12166-2-geert+renesas@glider.be --- Documentation/devicetree/bindings/arm/renesas.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 397eb7f8b0a4..a157285a1a1a 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -205,6 +205,10 @@ properties: - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) - const: renesas,r8a7796 + - description: R-Car M3-W+ (R8A77961) + items: + - const: renesas,r8a77961 + - description: Kingfisher (SBEV-RCAR-KF-M03) items: - const: shimafuji,kingfisher -- cgit v1.2.3 From fec526521be4283dc736273e288a1df4412abffc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 23 Oct 2019 14:29:08 +0200 Subject: dt-bindings: arm: renesas: Add Salvator-XS board with R-Car M3-W+ Add device tree binding documentation for the Renesas Salvator-XS board equipped with an R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Reviewed-by: Rob Herring Reviewed-by: Eugeniu Rosca Link: https://lore.kernel.org/r/20191023122911.12166-3-geert+renesas@glider.be --- Documentation/devicetree/bindings/arm/renesas.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index a157285a1a1a..9436124c5809 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -207,6 +207,8 @@ properties: - description: R-Car M3-W+ (R8A77961) items: + - enum: + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012SA5A) - const: renesas,r8a77961 - description: Kingfisher (SBEV-RCAR-KF-M03) -- cgit v1.2.3 From 248a887fc1aadd6681f772d5f797895fd9f0f863 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 23 Oct 2019 14:29:09 +0200 Subject: dt-bindings: reset: rcar-rst: Document r8a77961 support Add DT binding documentation for the Reset block in the Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Reviewed-by: Eugeniu Rosca Acked-by: Philipp Zabel Acked-by: Rob Herring Link: https://lore.kernel.org/r/20191023122911.12166-4-geert+renesas@glider.be --- Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt index d6d6769a0c42..de7f06ccd003 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.txt +++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt @@ -31,6 +31,7 @@ Required properties: - "renesas,r8a7794-rst" (R-Car E2) - "renesas,r8a7795-rst" (R-Car H3) - "renesas,r8a7796-rst" (R-Car M3-W) + - "renesas,r8a77961-rst" (R-Car M3-W+) - "renesas,r8a77965-rst" (R-Car M3-N) - "renesas,r8a77970-rst" (R-Car V3M) - "renesas,r8a77980-rst" (R-Car V3H) -- cgit v1.2.3 From e7f1eb321b1a8497c5ddd59303c18864a95ab8bd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 23 Oct 2019 14:29:10 +0200 Subject: dt-bindings: power: rcar-sysc: Document r8a77961 support Add DT binding documentation for the System Controller in the Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Reviewed-by: Eugeniu Rosca Acked-by: Rob Herring Link: https://lore.kernel.org/r/20191023122911.12166-5-geert+renesas@glider.be --- Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt index 712caa5726f7..acb41fade926 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -22,6 +22,7 @@ Required properties: - "renesas,r8a7794-sysc" (R-Car E2) - "renesas,r8a7795-sysc" (R-Car H3) - "renesas,r8a7796-sysc" (R-Car M3-W) + - "renesas,r8a77961-sysc" (R-Car M3-W+) - "renesas,r8a77965-sysc" (R-Car M3-N) - "renesas,r8a77970-sysc" (R-Car V3M) - "renesas,r8a77980-sysc" (R-Car V3H) -- cgit v1.2.3 From d79ccef07b36cf9e0bf57b24a7c580d1e5f4fc39 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 1 Nov 2019 20:55:36 +0000 Subject: dt-bindings: arm: sunxi: add FriendlyARM NanoPi Duo2 Adds bindings for the newly added NanoPi Duo2 board. Signed-off-by: Karl Palsson Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 972b1e9ee804..8a1e38a1d7ab 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -211,6 +211,11 @@ properties: - const: friendlyarm,nanopi-a64 - const: allwinner,sun50i-a64 + - description: FriendlyARM NanoPi Duo2 + items: + - const: friendlyarm,nanopi-duo2 + - const: allwinner,sun8i-h3 + - description: FriendlyARM NanoPi M1 items: - const: friendlyarm,nanopi-m1 -- cgit v1.2.3 From 0bfadbcdc7a4f1bee105d55f3893c8bf67010861 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 26 Oct 2019 11:04:00 +0200 Subject: dt-bindings: arm: fsl: add nxp based toradex apalis/colibri bindings Document the following NXP SoC based Toradex Apalis and Colibri module and carrier board devicetree bindings already supported: - toradex,apalis_imx6q # Apalis iMX6 Module - toradex,apalis_imx6q-eval # Apalis iMX6 Module on Apalisi Evaluation Board - toradex,apalis_imx6q-ixora # Apalis iMX6 Module on Ixora - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6 Module on Ixora V1.1 - toradex,colibri_imx6dl # Colibri iMX6 Module - toradex,colibri_imx6dl-eval-v3 # Colibri iMX6 Module on Colibri Evaluation Board V3 - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / Bluetooth Module on Colibri Evaluation Board - toradex,colibri-imx7s # Colibri iMX7 Solo Module - toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3 - toradex,colibri-imx7d # Colibri iMX7 Dual Module - toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module - toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on Colibri Evaluation Board V3 - toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on Colibri Evaluation Board V3 - toradex,vf500-colibri_vf50 # Colibri VF50 Module - toradex,vf500-colibri_vf50-on-eval # Colibri VF50 Module on Colibri Evaluation Board - toradex,vf610-colibri_vf61 # Colibri VF61 Module - toradex,vf610-colibri_vf61-on-eval # Colibri VF61 Module on Colibri Evaluation Board Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b08ae59cc57f..a2d5911c26e1 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -121,6 +121,10 @@ properties: - fsl,imx6q-sabresd - technologic,imx6q-ts4900 - technologic,imx6q-ts7970 + - toradex,apalis_imx6q # Apalis iMX6 Module + - toradex,apalis_imx6q-eval # Apalis iMX6 Module on Apalis Evaluation Board + - toradex,apalis_imx6q-ixora # Apalis iMX6 Module on Ixora + - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6 Module on Ixora V1.1 - variscite,dt6customboard - const: fsl,imx6q @@ -143,6 +147,8 @@ properties: - fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 + - toradex,colibri_imx6dl # Colibri iMX6 Module + - toradex,colibri_imx6dl-eval-v3 # Colibri iMX6 Module on Colibri Evaluation Board V3 - ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board - ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board - ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board @@ -195,6 +201,8 @@ properties: - armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM - armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board + - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board + - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / Bluetooth Module on Colibri Evaluation Board - const: fsl,imx6ull - description: i.MX6ULZ based Boards @@ -207,6 +215,8 @@ properties: - description: i.MX7S based Boards items: - enum: + - toradex,colibri-imx7s # Colibri iMX7 Solo Module + - toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3 - tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM - const: fsl,imx7s @@ -215,6 +225,10 @@ properties: - enum: - fsl,imx7d-sdb # i.MX7 SabreSD Board - novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board + - toradex,colibri-imx7d # Colibri iMX7 Dual Module + - toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module + - toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on Colibri Evaluation Board V3 + - toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on Colibri Evaluation Board V3 - tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM - zii,imx7d-rmu2 # ZII RMU2 Board - zii,imx7d-rpu2 # ZII RPU2 Board @@ -282,6 +296,10 @@ properties: - fsl,vf600 - fsl,vf610 - fsl,vf610m4 + - toradex,vf500-colibri_vf50 # Colibri VF50 Module + - toradex,vf500-colibri_vf50-on-eval # Colibri VF50 Module on Colibri Evaluation Board + - toradex,vf610-colibri_vf61 # Colibri VF61 Module + - toradex,vf610-colibri_vf61-on-eval # Colibri VF61 Module on Colibri Evaluation Board - description: ZII's VF610 based Boards items: -- cgit v1.2.3 From a5c959ef99d97a1138633ab7ff671f116fb371a5 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 26 Oct 2019 11:04:03 +0200 Subject: dt-bindings: arm: fsl: add nxp based toradex colibri-imx8x bindings Document the NXP SoC based Toradex Colibri iMX8X module and carrier board devicetree bindings previously added. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a2d5911c26e1..e32e1e0c92c9 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -279,6 +279,8 @@ properties: - enum: - einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board - fsl,imx8qxp-mek # i.MX8QXP MEK Board + - toradex,colibri-imx8x # Colibri iMX8X Module + - toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3 - const: fsl,imx8qxp - description: -- cgit v1.2.3 From aa2f77ceb8ab83ede4507cd58a5c1ee902e1d7cb Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Sat, 26 Oct 2019 21:57:46 +0200 Subject: dt-bindings: arm: fsl: add compatible string for Kobo Clara HD This adds a compatible string for the Kobo Clara HD eBook reader. Signed-off-by: Andreas Kemnade Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index e32e1e0c92c9..ea968b466955 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -164,6 +164,7 @@ properties: items: - enum: - fsl,imx6sll-evk + - kobo,clarahd - const: fsl,imx6sll - description: i.MX6SX based Boards -- cgit v1.2.3 From bb40c3f7d63afaf7665effaf2e75a9f5563e560a Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 4 Nov 2019 11:54:21 +0000 Subject: dt-bindings: arm: fsl: Add more Kontron i.MX6UL/ULL compatibles Add the compatibles for Kontron i.MX6UL N6311 SoM and boards and the compatibles for Kontron i.MX6ULL N6411 SoM and boards. Signed-off-by: Frieder Schrempf Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index ea968b466955..f79683a628f0 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -181,6 +181,7 @@ properties: - armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board - kontron,imx6ul-n6310-som # Kontron N6310 SOM + - kontron,imx6ul-n6311-som # Kontron N6311 SOM - const: fsl,imx6ul - description: Kontron N6310 S Board @@ -189,6 +190,12 @@ properties: - const: kontron,imx6ul-n6310-som - const: fsl,imx6ul + - description: Kontron N6311 S Board + items: + - const: kontron,imx6ul-n6311-s + - const: kontron,imx6ul-n6311-som + - const: fsl,imx6ul + - description: Kontron N6310 S 43 Board items: - const: kontron,imx6ul-n6310-s-43 @@ -202,10 +209,17 @@ properties: - armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM - armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board + - kontron,imx6ull-n6411-som # Kontron N6411 SOM - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / Bluetooth Module on Colibri Evaluation Board - const: fsl,imx6ull + - description: Kontron N6411 S Board + items: + - const: kontron,imx6ull-n6411-s + - const: kontron,imx6ull-n6411-som + - const: fsl,imx6ull + - description: i.MX6ULZ based Boards items: - enum: -- cgit v1.2.3 From ab883313ef625a48704eec3159b43eabe1e5fa38 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 24 Oct 2019 00:13:27 +0200 Subject: dt-bindings: bus: sunxi: Add H3 MBUS compatible Allwinner H3 SoC also contains MBUS controller. Add compatible for it. Acked-by: Maxime Ripard Acked-by: Rob Herring Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt b/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt index 1464a4713553..2005bb486705 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt +++ b/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt @@ -8,6 +8,7 @@ bus. Required properties: - compatible: Must be one of: - allwinner,sun5i-a13-mbus + - allwinner,sun8i-h3-mbus - reg: Offset and length of the register set for the controller - clocks: phandle to the clock driving the controller - dma-ranges: See section 2.3.9 of the DeviceTree Specification -- cgit v1.2.3 From 1e92dbeae806c6a49ef25d34e279af45632120b3 Mon Sep 17 00:00:00 2001 From: Torsten Duwe Date: Tue, 29 Oct 2019 13:16:57 +0100 Subject: dt-bindings: Add ANX6345 DP/eDP transmitter binding The anx6345 is an ultra-low power DisplayPort/eDP transmitter designed for portable devices. Add a binding document for it. Signed-off-by: Icenowy Zheng Signed-off-by: Vasily Khoruzhick Reviewed-by: Rob Herring Signed-off-by: Torsten Duwe Reviewed-by: Laurent Pinchart Signed-off-by: Maxime Ripard --- .../bindings/display/bridge/anx6345.yaml | 102 +++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/anx6345.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/display/bridge/anx6345.yaml b/Documentation/devicetree/bindings/display/bridge/anx6345.yaml new file mode 100644 index 000000000000..6d72b3d11fbc --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/anx6345.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/anx6345.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analogix ANX6345 eDP Transmitter Device Tree Bindings + +maintainers: + - Torsten Duwe + +description: | + The ANX6345 is an ultra-low power Full-HD eDP transmitter designed for + portable devices. + +properties: + compatible: + const: analogix,anx6345 + + reg: + maxItems: 1 + description: base I2C address of the device + + reset-gpios: + maxItems: 1 + description: GPIO connected to active low reset + + dvdd12-supply: + maxItems: 1 + description: Regulator for 1.2V digital core power. + + dvdd25-supply: + maxItems: 1 + description: Regulator for 2.5V digital core power. + + ports: + type: object + + properties: + port@0: + type: object + description: | + Video port for LVTTL input + + port@1: + type: object + description: | + Video port for eDP output (panel or connector). + May be omitted if EDID works reliably. + + required: + - port@0 + +required: + - compatible + - reg + - reset-gpios + - dvdd12-supply + - dvdd25-supply + - ports + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + anx6345: anx6345@38 { + compatible = "analogix,anx6345"; + reg = <0x38>; + reset-gpios = <&pio42 1 /* GPIO_ACTIVE_LOW */>; + dvdd25-supply = <®_dldo2>; + dvdd12-supply = <®_fldo1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + anx6345_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + anx6345_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_anx6345>; + }; + }; + + anx6345_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + anx6345_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + }; + }; -- cgit v1.2.3 From 21e3311a6a15cce30d6903d3bd4870c16f4672a2 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Mon, 28 Oct 2019 18:22:51 +0000 Subject: dt-bindings: clean up rockchip grf binding document Fixup some typos and inconsistencies in the grf binding. Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20191028182254.30739-3-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/soc/rockchip/grf.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt index 61d89749918a..f96511aa3897 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt @@ -38,12 +38,12 @@ Required Properties: - "rockchip,px30-pmugrf", "syscon": for px30 - "rockchip,rk3368-pmugrf", "syscon": for rk3368 - "rockchip,rk3399-pmugrf", "syscon": for rk3399 -- compatible: SGRF should be one of the following +- compatible: SGRF should be one of the following: - "rockchip,rk3288-sgrf", "syscon": for rk3288 -- compatible: USB2PHYGRF should be one of the followings +- compatible: USB2PHYGRF should be one of the following: - "rockchip,px30-usb2phy-grf", "syscon": for px30 - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328 -- compatible: USBGRF should be one of the following +- compatible: USBGRF should be one of the following: - "rockchip,rv1108-usbgrf", "syscon": for rv1108 - reg: physical base address of the controller and length of memory mapped region. -- cgit v1.2.3 From ab14c422a1d1877676a001d27f8c64a916ec077e Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Wed, 30 Oct 2019 15:26:48 +0800 Subject: dt-bindings: Add doc for Firefly ROC-RK3308-CC board Add compatible for Firefly ROC-RK3308-CC board. Signed-off-by: Andy Yan Link: https://lore.kernel.org/r/20191030072648.29738-1-andy.yan@rock-chips.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index dd38d060cdd7..45a87c6e0a88 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -82,6 +82,11 @@ properties: - const: firefly,firefly-rk3399 - const: rockchip,rk3399 + - description: Firefly ROC-RK3308-CC + items: + - const: firefly,roc-rk3308-cc + - const: rockchip,rk3308 + - description: Firefly roc-rk3328-cc items: - const: firefly,roc-rk3328-cc -- cgit v1.2.3 From cd584d251554f736e0d3830be0d7cf2b62152b18 Mon Sep 17 00:00:00 2001 From: Kamel Bouhara Date: Tue, 5 Nov 2019 22:22:33 +0100 Subject: dt-bindings: arm: at91: Document Kizbox2-2 board binding Document devicetree's binding for the Kizbox2-2 board of Overkiz SAS based on SAMA5D31 SoC. Signed-off-by: Kamel Bouhara Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20191105212234.22999-1-kamel.bouhara@bootlin.com Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index c0869cb860f3..6dd8be401673 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -80,6 +80,13 @@ properties: - const: atmel,sama5d3 - const: atmel,sama5 + - description: Overkiz kizbox2 board with two heads + items: + - const: overkiz,kizbox2-2 + - const: atmel,sama5d31 + - const: atmel,sama5d3 + - const: atmel,sama5 + - items: - enum: - atmel,sama5d31 -- cgit v1.2.3 From e09a17df35c4d2185befd4e6db0f8e035aa86e57 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 14 Oct 2019 23:19:04 +0100 Subject: dt-bindings: ARM: rockchip: Add Beelink A1 Add a binding for the RK3328-based Beelink A1 TV box. Signed-off-by: Robin Murphy Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/82324d17b770fa8ea189fa708490d2c8c0c9290e.1571090991.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 45a87c6e0a88..952f1212fa9c 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -40,6 +40,11 @@ properties: - const: asus,rk3288-tinker-s - const: rockchip,rk3288 + - description: Beelink A1 + items: + - const: azw,beelink-a1 + - const: rockchip,rk3328 + - description: bq Curie 2 tablet items: - const: mundoreader,bq-curie2 -- cgit v1.2.3 From f9010b0edcd5a3112ab3d4fc79c296c5a1c5ee16 Mon Sep 17 00:00:00 2001 From: Markus Reichl Date: Fri, 8 Nov 2019 22:04:33 +0100 Subject: arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board. For rk3399-roc-pc is a mezzanine board available that carries M.2 and POE interfaces. Use it with a separate dts. Signed-off-by: Markus Reichl Acked-by: Rob Herring Link: https://lore.kernel.org/r/0fb4e21a-fe78-00aa-6142-ca8682a913eb@fivetechno.de Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/arm/rockchip.yaml | 4 +- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts | 72 ++ arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts | 757 +------------------- arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 767 +++++++++++++++++++++ 5 files changed, 844 insertions(+), 757 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 952f1212fa9c..f7470ed1e17d 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -99,7 +99,9 @@ properties: - description: Firefly ROC-RK3399-PC items: - - const: firefly,roc-rk3399-pc + - enum: + - firefly,roc-rk3399-pc + - firefly,roc-rk3399-pc-mezzanine - const: rockchip,rk3399 - description: FriendlyElec NanoPi4 series boards diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 1f03f36559aa..48fb631d5451 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts new file mode 100644 index 000000000000..d6b3042cffa9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + * Copyright (c) 2019 Markus Reichl + */ + +/dts-v1/; +#include "rk3399-roc-pc.dtsi" + +/ { + model = "Firefly ROC-RK3399-PC Mezzanine Board"; + compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399"; + + vcc3v3_ngff: vcc3v3-ngff { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_ngff"; + enable-active-high; + gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_ngff_en>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_pcie: vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + enable-active-high; + gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie_en>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_perst>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + ngff { + vcc3v3_ngff_en: vcc3v3-ngff-en { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_pcie_en: vcc3v3-pcie-en { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_perst: pcie-perst { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts index 07ae4b1d53d4..cd4195425309 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts @@ -4,764 +4,9 @@ */ /dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" +#include "rk3399-roc-pc.dtsi" / { model = "Firefly ROC-RK3399-PC Board"; compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1500000>; - poll-interval = <100>; - - recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <18000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key_l>; - - power { - label = "GPIO Key Power"; - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>, <&yellow_led_gpio>; - - work-led { - label = "green:work"; - gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - diy-led { - label = "red:diy"; - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc1"; - }; - - yellow-led { - label = "yellow:yellow-led"; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - vcc_vbus_typec0: vcc-vbus-typec0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_vbus_typec0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - /* - * should be placed inside mp8859, but not until mp8859 has - * its own dt-binding. - */ - dc_12v: mp8859-dcdc1 { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <&vcc_vbus_typec0>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en &hub_rst>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_vbus_typec1: vcc-vbus-typec1 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_vbus_typec1_en>; - regulator-name = "vcc_vbus_typec1"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_sys_en>; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vcc3v3_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vcc13-supply = <&vcc3v3_sys>; - vcc14-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_codec: LDO_REG1 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca0v9_hdmi: LDO_REG7 { - regulator-name = "vcca0v9_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb1: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&fusb1_int>; - vbus-supply = <&vcc_vbus_typec1>; - status = "okay"; - }; -}; - -&i2c7 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb0: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc_vbus_typec0>; - status = "okay"; - }; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcca1v8_codec>; - bt656-supply = <&vcc_3v0>; - gpio1830-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pinctrl { - buttons { - pwr_key_l: pwr-key-l { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd-panel { - lcd_panel_reset: lcd-panel-reset { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - diy_led_gpio: diy_led-gpio { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - work_led_gpio: work_led-gpio { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - yellow_led_gpio: yellow_led-gpio { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc_sys_en: vcc-sys-en { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - hub_rst: hub-rst { - rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb-typec { - vcc_vbus_typec1_en: vcc-vbus-typec1-en { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - fusb30x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - fusb1_int: fusb1-int { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - phy-supply = <&vcc_vbus_typec0>; - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - phy-supply = <&vcc_vbus_typec1>; - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi new file mode 100644 index 000000000000..7e07dae33d0f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -0,0 +1,767 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Firefly ROC-RK3399-PC Board"; + compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1500000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <18000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key_l>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>, <&yellow_led_gpio>; + + work-led { + label = "green:work"; + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + diy-led { + label = "red:diy"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc1"; + }; + + yellow-led { + label = "yellow:yellow-led"; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc_vbus_typec0: vcc-vbus-typec0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_vbus_typec0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* + * should be placed inside mp8859, but not until mp8859 has + * its own dt-binding. + */ + dc_12v: mp8859-dcdc1 { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc_vbus_typec0>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en &hub_rst>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_vbus_typec1: vcc-vbus-typec1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_vbus_typec1_en>; + regulator-name = "vcc_vbus_typec1"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sys_en>; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vcc13-supply = <&vcc3v3_sys>; + vcc14-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_codec: LDO_REG1 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_hdmi: LDO_REG2 { + regulator-name = "vcc1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb1: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb1_int>; + vbus-supply = <&vcc_vbus_typec1>; + status = "okay"; + }; +}; + +&i2c7 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc_vbus_typec0>; + status = "okay"; + }; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + audio-supply = <&vcca1v8_codec>; + bt656-supply = <&vcc_3v0>; + gpio1830-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + buttons { + pwr_key_l: pwr-key-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + diy_led_gpio: diy_led-gpio { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led_gpio: work_led-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + yellow_led_gpio: yellow_led-gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_sys_en: vcc-sys-en { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hub_rst: hub-rst { + rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + usb-typec { + vcc_vbus_typec1_en: vcc-vbus-typec1-en { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + fusb1_int: fusb1-int { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + phy-supply = <&vcc_vbus_typec0>; + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_vbus_typec1>; + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; -- cgit v1.2.3 From d14e0fe39c6204f0c35d7d7da50b5727df8a3560 Mon Sep 17 00:00:00 2001 From: Dehui Sun Date: Mon, 28 Oct 2019 14:09:43 +0800 Subject: dt-bindings: mediatek: update bindings for MT8183 systimer This commit adds mt8183 compatible node in mtk-timer binding document. Reviewed-by: Rob Herring Signed-off-by: Dehui Sun Acked-by: Daniel Lezcano Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index 74c3eadad844..0d256486f886 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -21,6 +21,7 @@ Required properties: * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT) For those SoCs that use SYST + * "mediatek,mt8183-timer" for MT8183 compatible timers (SYST) * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST) -- cgit v1.2.3