From 71fb2c74287d186938cde830ad8980f57a38b597 Mon Sep 17 00:00:00 2001 From: Songjun Wu Date: Wed, 17 Aug 2016 03:05:29 -0300 Subject: [media] MAINTAINERS: atmel-isc: add entry for Atmel ISC Add the MAINTAINERS' entry for Microchip / Atmel Image Sensor Controller. Signed-off-by: Songjun Wu Acked-by: Nicolas Ferre Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 20bb1d00098c..21a6f6f4c2d6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7733,6 +7733,14 @@ T: git git://git.monstr.eu/linux-2.6-microblaze.git S: Supported F: arch/microblaze/ +MICROCHIP / ATMEL ISC DRIVER +M: Songjun Wu +L: linux-media@vger.kernel.org +S: Supported +F: drivers/media/platform/atmel/atmel-isc.c +F: drivers/media/platform/atmel/atmel-isc-regs.h +F: devicetree/bindings/media/atmel-isc.txt + MICROSOFT SURFACE PRO 3 BUTTON DRIVER M: Chen Yu L: platform-driver-x86@vger.kernel.org -- cgit v1.2.3 From aaf578e12e06160792ae5dd71dee3b074e0f9475 Mon Sep 17 00:00:00 2001 From: Nick Dyer Date: Mon, 18 Jul 2016 18:10:29 -0300 Subject: [media] Input: atmel_mxt_ts - update MAINTAINERS email address I'm leaving ITDev, so change to my personal email. My understanding is that someone at Atmel will take this on once their takeover by Microchip has settled down. Signed-off-by: Nick Dyer Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab Acked-by: Dmitry Torokhov --- MAINTAINERS | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 7e09a5169a5f..6c33d29f79b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2211,9 +2211,9 @@ S: Maintained F: drivers/net/wireless/atmel/atmel* ATMEL MAXTOUCH DRIVER -M: Nick Dyer -T: git git://github.com/atmel-maxtouch/linux.git -S: Supported +M: Nick Dyer +T: git git://github.com/ndyer/linux.git +S: Maintained F: Documentation/devicetree/bindings/input/atmel,maxtouch.txt F: drivers/input/touchscreen/atmel_mxt_ts.c F: include/linux/platform_data/atmel_mxt_ts.h -- cgit v1.2.3 From d0d44516f8e989392d1fa545ae58ea6694743db9 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 5 Aug 2016 10:38:32 -0300 Subject: [media] s5p-tv: remove obsolete driver The s5p-tv driver has been replaced by the exynos drm driver for quite a long time now. Remove this driver to avoid having duplicate drivers, of which this one is considered dead code by Samsung. Signed-off-by: Hans Verkuil Acked-by: Sylwester Nawrocki Acked-by: Krzysztof Kozlowski Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 8 - drivers/gpu/drm/exynos/Kconfig | 3 +- drivers/media/platform/Kconfig | 1 - drivers/media/platform/Makefile | 1 - drivers/media/platform/s5p-tv/Kconfig | 88 -- drivers/media/platform/s5p-tv/Makefile | 19 - drivers/media/platform/s5p-tv/hdmi_drv.c | 1059 --------------------- drivers/media/platform/s5p-tv/hdmiphy_drv.c | 324 ------- drivers/media/platform/s5p-tv/mixer.h | 364 -------- drivers/media/platform/s5p-tv/mixer_drv.c | 527 ----------- drivers/media/platform/s5p-tv/mixer_grp_layer.c | 270 ------ drivers/media/platform/s5p-tv/mixer_reg.c | 551 ----------- drivers/media/platform/s5p-tv/mixer_video.c | 1130 ----------------------- drivers/media/platform/s5p-tv/mixer_vp_layer.c | 242 ----- drivers/media/platform/s5p-tv/regs-hdmi.h | 146 --- drivers/media/platform/s5p-tv/regs-mixer.h | 122 --- drivers/media/platform/s5p-tv/regs-sdo.h | 63 -- drivers/media/platform/s5p-tv/regs-vp.h | 88 -- drivers/media/platform/s5p-tv/sdo_drv.c | 497 ---------- drivers/media/platform/s5p-tv/sii9234_drv.c | 407 -------- 20 files changed, 1 insertion(+), 5909 deletions(-) delete mode 100644 drivers/media/platform/s5p-tv/Kconfig delete mode 100644 drivers/media/platform/s5p-tv/Makefile delete mode 100644 drivers/media/platform/s5p-tv/hdmi_drv.c delete mode 100644 drivers/media/platform/s5p-tv/hdmiphy_drv.c delete mode 100644 drivers/media/platform/s5p-tv/mixer.h delete mode 100644 drivers/media/platform/s5p-tv/mixer_drv.c delete mode 100644 drivers/media/platform/s5p-tv/mixer_grp_layer.c delete mode 100644 drivers/media/platform/s5p-tv/mixer_reg.c delete mode 100644 drivers/media/platform/s5p-tv/mixer_video.c delete mode 100644 drivers/media/platform/s5p-tv/mixer_vp_layer.c delete mode 100644 drivers/media/platform/s5p-tv/regs-hdmi.h delete mode 100644 drivers/media/platform/s5p-tv/regs-mixer.h delete mode 100644 drivers/media/platform/s5p-tv/regs-sdo.h delete mode 100644 drivers/media/platform/s5p-tv/regs-vp.h delete mode 100644 drivers/media/platform/s5p-tv/sdo_drv.c delete mode 100644 drivers/media/platform/s5p-tv/sii9234_drv.c (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 6c33d29f79b0..998fd6b767f2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1666,14 +1666,6 @@ S: Maintained F: arch/arm/plat-samsung/s5p-dev-mfc.c F: drivers/media/platform/s5p-mfc/ -ARM/SAMSUNG S5P SERIES TV SUBSYSTEM SUPPORT -M: Kyungmin Park -M: Tomasz Stanislawski -L: linux-arm-kernel@lists.infradead.org -L: linux-media@vger.kernel.org -S: Maintained -F: drivers/media/platform/s5p-tv/ - ARM/SAMSUNG S5P SERIES HDMI CEC SUBSYSTEM SUPPORT M: Kyungmin Park L: linux-arm-kernel@lists.infradead.org diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index 83f61c513b7e..465d344f3391 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -38,7 +38,6 @@ config DRM_EXYNOS7_DECON config DRM_EXYNOS_MIXER bool "Mixer" - depends on !VIDEO_SAMSUNG_S5P_TV help Choose this option if you want to use Exynos Mixer for DRM. @@ -77,7 +76,7 @@ config DRM_EXYNOS_DP config DRM_EXYNOS_HDMI bool "HDMI" - depends on !VIDEO_SAMSUNG_S5P_TV && (DRM_EXYNOS_MIXER || DRM_EXYNOS5433_DECON) + depends on DRM_EXYNOS_MIXER || DRM_EXYNOS5433_DECON help Choose this option if you want to use Exynos HDMI for DRM. diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index b23db1779808..7843e8f3d37d 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -107,7 +107,6 @@ config VIDEO_S3C_CAMIF source "drivers/media/platform/soc_camera/Kconfig" source "drivers/media/platform/exynos4-is/Kconfig" -source "drivers/media/platform/s5p-tv/Kconfig" source "drivers/media/platform/am437x/Kconfig" source "drivers/media/platform/xilinx/Kconfig" source "drivers/media/platform/rcar-vin/Kconfig" diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index 37b6c75f0b15..536d1d8ef022 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -30,7 +30,6 @@ obj-$(CONFIG_VIDEO_S3C_CAMIF) += s3c-camif/ obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS) += exynos4-is/ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_JPEG) += s5p-jpeg/ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MFC) += s5p-mfc/ -obj-$(CONFIG_VIDEO_SAMSUNG_S5P_TV) += s5p-tv/ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_G2D) += s5p-g2d/ obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC) += exynos-gsc/ diff --git a/drivers/media/platform/s5p-tv/Kconfig b/drivers/media/platform/s5p-tv/Kconfig deleted file mode 100644 index 697aaed42486..000000000000 --- a/drivers/media/platform/s5p-tv/Kconfig +++ /dev/null @@ -1,88 +0,0 @@ -# drivers/media/platform/s5p-tv/Kconfig -# -# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. -# http://www.samsung.com/ -# Tomasz Stanislawski -# -# Licensed under GPL - -config VIDEO_SAMSUNG_S5P_TV - bool "Samsung TV driver for S5P platform" - depends on PM - depends on ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST - default n - ---help--- - Say Y here to enable selecting the TV output devices for - Samsung S5P platform. - -if VIDEO_SAMSUNG_S5P_TV - -config VIDEO_SAMSUNG_S5P_HDMI - tristate "Samsung HDMI Driver" - depends on VIDEO_V4L2 - depends on I2C - depends on VIDEO_SAMSUNG_S5P_TV - select VIDEO_SAMSUNG_S5P_HDMIPHY - help - Say Y here if you want support for the HDMI output - interface in S5P Samsung SoC. The driver can be compiled - as module. It is an auxiliary driver, that exposes a V4L2 - subdev for use by other drivers. This driver requires - hdmiphy driver to work correctly. - -config VIDEO_SAMSUNG_S5P_HDMI_DEBUG - bool "Enable debug for HDMI Driver" - depends on VIDEO_SAMSUNG_S5P_HDMI - default n - help - Enables debugging for HDMI driver. - -config VIDEO_SAMSUNG_S5P_HDMIPHY - tristate "Samsung HDMIPHY Driver" - depends on VIDEO_DEV && VIDEO_V4L2 && I2C - depends on VIDEO_SAMSUNG_S5P_TV - help - Say Y here if you want support for the physical HDMI - interface in S5P Samsung SoC. The driver can be compiled - as module. It is an I2C driver, that exposes a V4L2 - subdev for use by other drivers. - -config VIDEO_SAMSUNG_S5P_SII9234 - tristate "Samsung SII9234 Driver" - depends on VIDEO_DEV && VIDEO_V4L2 && I2C - depends on VIDEO_SAMSUNG_S5P_TV - help - Say Y here if you want support for the MHL interface - in S5P Samsung SoC. The driver can be compiled - as module. It is an I2C driver, that exposes a V4L2 - subdev for use by other drivers. - -config VIDEO_SAMSUNG_S5P_SDO - tristate "Samsung Analog TV Driver" - depends on VIDEO_DEV && VIDEO_V4L2 - depends on VIDEO_SAMSUNG_S5P_TV - help - Say Y here if you want support for the analog TV output - interface in S5P Samsung SoC. The driver can be compiled - as module. It is an auxiliary driver, that exposes a V4L2 - subdev for use by other drivers. This driver requires - hdmiphy driver to work correctly. - -config VIDEO_SAMSUNG_S5P_MIXER - tristate "Samsung Mixer and Video Processor Driver" - depends on VIDEO_DEV && VIDEO_V4L2 - depends on VIDEO_SAMSUNG_S5P_TV - depends on HAS_DMA - select VIDEOBUF2_DMA_CONTIG - help - Say Y here if you want support for the Mixer in Samsung S5P SoCs. - This device produce image data to one of output interfaces. - -config VIDEO_SAMSUNG_S5P_MIXER_DEBUG - bool "Enable debug for Mixer Driver" - depends on VIDEO_SAMSUNG_S5P_MIXER - default n - help - Enables debugging for Mixer driver. - -endif # VIDEO_SAMSUNG_S5P_TV diff --git a/drivers/media/platform/s5p-tv/Makefile b/drivers/media/platform/s5p-tv/Makefile deleted file mode 100644 index 7cd47902e269..000000000000 --- a/drivers/media/platform/s5p-tv/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -# drivers/media/platform/samsung/tvout/Makefile -# -# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. -# http://www.samsung.com/ -# Tomasz Stanislawski -# -# Licensed under GPL - -obj-$(CONFIG_VIDEO_SAMSUNG_S5P_HDMIPHY) += s5p-hdmiphy.o -s5p-hdmiphy-y += hdmiphy_drv.o -obj-$(CONFIG_VIDEO_SAMSUNG_S5P_SII9234) += s5p-sii9234.o -s5p-sii9234-y += sii9234_drv.o -obj-$(CONFIG_VIDEO_SAMSUNG_S5P_HDMI) += s5p-hdmi.o -s5p-hdmi-y += hdmi_drv.o -obj-$(CONFIG_VIDEO_SAMSUNG_S5P_SDO) += s5p-sdo.o -s5p-sdo-y += sdo_drv.o -obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MIXER) += s5p-mixer.o -s5p-mixer-y += mixer_drv.o mixer_video.o mixer_reg.o mixer_grp_layer.o mixer_vp_layer.o - diff --git a/drivers/media/platform/s5p-tv/hdmi_drv.c b/drivers/media/platform/s5p-tv/hdmi_drv.c deleted file mode 100644 index e71b13e40f59..000000000000 --- a/drivers/media/platform/s5p-tv/hdmi_drv.c +++ /dev/null @@ -1,1059 +0,0 @@ -/* - * Samsung HDMI interface driver - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * - * Tomasz Stanislawski, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundiation. either version 2 of the License, - * or (at your option) any later version - */ - -#define pr_fmt(fmt) "s5p-tv (hdmi_drv): " fmt - -#ifdef CONFIG_VIDEO_SAMSUNG_S5P_HDMI_DEBUG -#define DEBUG -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "regs-hdmi.h" - -MODULE_AUTHOR("Tomasz Stanislawski, "); -MODULE_DESCRIPTION("Samsung HDMI"); -MODULE_LICENSE("GPL"); - -struct hdmi_pulse { - u32 beg; - u32 end; -}; - -struct hdmi_timings { - struct hdmi_pulse hact; - u32 hsyn_pol; /* 0 - high, 1 - low */ - struct hdmi_pulse hsyn; - u32 interlaced; - struct hdmi_pulse vact[2]; - u32 vsyn_pol; /* 0 - high, 1 - low */ - u32 vsyn_off; - struct hdmi_pulse vsyn[2]; -}; - -struct hdmi_resources { - struct clk *hdmi; - struct clk *sclk_hdmi; - struct clk *sclk_pixel; - struct clk *sclk_hdmiphy; - struct clk *hdmiphy; - struct regulator_bulk_data *regul_bulk; - int regul_count; -}; - -struct hdmi_device { - /** base address of HDMI registers */ - void __iomem *regs; - /** HDMI interrupt */ - unsigned int irq; - /** pointer to device parent */ - struct device *dev; - /** subdev generated by HDMI device */ - struct v4l2_subdev sd; - /** V4L2 device structure */ - struct v4l2_device v4l2_dev; - /** subdev of HDMIPHY interface */ - struct v4l2_subdev *phy_sd; - /** subdev of MHL interface */ - struct v4l2_subdev *mhl_sd; - /** configuration of current graphic mode */ - const struct hdmi_timings *cur_conf; - /** flag indicating that timings are dirty */ - int cur_conf_dirty; - /** current timings */ - struct v4l2_dv_timings cur_timings; - /** other resources */ - struct hdmi_resources res; -}; - -static const struct platform_device_id hdmi_driver_types[] = { - { - .name = "s5pv210-hdmi", - }, { - .name = "exynos4-hdmi", - }, { - /* end node */ - } -}; - -static const struct v4l2_subdev_ops hdmi_sd_ops; - -static struct hdmi_device *sd_to_hdmi_dev(struct v4l2_subdev *sd) -{ - return container_of(sd, struct hdmi_device, sd); -} - -static inline -void hdmi_write(struct hdmi_device *hdev, u32 reg_id, u32 value) -{ - writel(value, hdev->regs + reg_id); -} - -static inline -void hdmi_write_mask(struct hdmi_device *hdev, u32 reg_id, u32 value, u32 mask) -{ - u32 old = readl(hdev->regs + reg_id); - value = (value & mask) | (old & ~mask); - writel(value, hdev->regs + reg_id); -} - -static inline -void hdmi_writeb(struct hdmi_device *hdev, u32 reg_id, u8 value) -{ - writeb(value, hdev->regs + reg_id); -} - -static inline -void hdmi_writebn(struct hdmi_device *hdev, u32 reg_id, int n, u32 value) -{ - switch (n) { - default: - writeb(value >> 24, hdev->regs + reg_id + 12); - case 3: - writeb(value >> 16, hdev->regs + reg_id + 8); - case 2: - writeb(value >> 8, hdev->regs + reg_id + 4); - case 1: - writeb(value >> 0, hdev->regs + reg_id + 0); - } -} - -static inline u32 hdmi_read(struct hdmi_device *hdev, u32 reg_id) -{ - return readl(hdev->regs + reg_id); -} - -static irqreturn_t hdmi_irq_handler(int irq, void *dev_data) -{ - struct hdmi_device *hdev = dev_data; - u32 intc_flag; - - (void)irq; - intc_flag = hdmi_read(hdev, HDMI_INTC_FLAG); - /* clearing flags for HPD plug/unplug */ - if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) { - pr_info("unplugged\n"); - hdmi_write_mask(hdev, HDMI_INTC_FLAG, ~0, - HDMI_INTC_FLAG_HPD_UNPLUG); - } - if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) { - pr_info("plugged\n"); - hdmi_write_mask(hdev, HDMI_INTC_FLAG, ~0, - HDMI_INTC_FLAG_HPD_PLUG); - } - - return IRQ_HANDLED; -} - -static void hdmi_reg_init(struct hdmi_device *hdev) -{ - /* enable HPD interrupts */ - hdmi_write_mask(hdev, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL | - HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG); - /* choose DVI mode */ - hdmi_write_mask(hdev, HDMI_MODE_SEL, - HDMI_MODE_DVI_EN, HDMI_MODE_MASK); - hdmi_write_mask(hdev, HDMI_CON_2, ~0, - HDMI_DVI_PERAMBLE_EN | HDMI_DVI_BAND_EN); - /* disable bluescreen */ - hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN); - /* choose bluescreen (fecal) color */ - hdmi_writeb(hdev, HDMI_BLUE_SCREEN_0, 0x12); - hdmi_writeb(hdev, HDMI_BLUE_SCREEN_1, 0x34); - hdmi_writeb(hdev, HDMI_BLUE_SCREEN_2, 0x56); -} - -static void hdmi_timing_apply(struct hdmi_device *hdev, - const struct hdmi_timings *t) -{ - /* setting core registers */ - hdmi_writebn(hdev, HDMI_H_BLANK_0, 2, t->hact.beg); - hdmi_writebn(hdev, HDMI_H_SYNC_GEN_0, 3, - (t->hsyn_pol << 20) | (t->hsyn.end << 10) | t->hsyn.beg); - hdmi_writeb(hdev, HDMI_VSYNC_POL, t->vsyn_pol); - hdmi_writebn(hdev, HDMI_V_BLANK_0, 3, - (t->vact[0].beg << 11) | t->vact[0].end); - hdmi_writebn(hdev, HDMI_V_SYNC_GEN_1_0, 3, - (t->vsyn[0].beg << 12) | t->vsyn[0].end); - if (t->interlaced) { - u32 vsyn_trans = t->hsyn.beg + t->vsyn_off; - - hdmi_writeb(hdev, HDMI_INT_PRO_MODE, 1); - hdmi_writebn(hdev, HDMI_H_V_LINE_0, 3, - (t->hact.end << 12) | t->vact[1].end); - hdmi_writebn(hdev, HDMI_V_BLANK_F_0, 3, - (t->vact[1].end << 11) | t->vact[1].beg); - hdmi_writebn(hdev, HDMI_V_SYNC_GEN_2_0, 3, - (t->vsyn[1].beg << 12) | t->vsyn[1].end); - hdmi_writebn(hdev, HDMI_V_SYNC_GEN_3_0, 3, - (vsyn_trans << 12) | vsyn_trans); - } else { - hdmi_writeb(hdev, HDMI_INT_PRO_MODE, 0); - hdmi_writebn(hdev, HDMI_H_V_LINE_0, 3, - (t->hact.end << 12) | t->vact[0].end); - } - - /* Timing generator registers */ - hdmi_writebn(hdev, HDMI_TG_H_FSZ_L, 2, t->hact.end); - hdmi_writebn(hdev, HDMI_TG_HACT_ST_L, 2, t->hact.beg); - hdmi_writebn(hdev, HDMI_TG_HACT_SZ_L, 2, t->hact.end - t->hact.beg); - hdmi_writebn(hdev, HDMI_TG_VSYNC_L, 2, t->vsyn[0].beg); - hdmi_writebn(hdev, HDMI_TG_VACT_ST_L, 2, t->vact[0].beg); - hdmi_writebn(hdev, HDMI_TG_VACT_SZ_L, 2, - t->vact[0].end - t->vact[0].beg); - hdmi_writebn(hdev, HDMI_TG_VSYNC_TOP_HDMI_L, 2, t->vsyn[0].beg); - hdmi_writebn(hdev, HDMI_TG_FIELD_TOP_HDMI_L, 2, t->vsyn[0].beg); - if (t->interlaced) { - hdmi_write_mask(hdev, HDMI_TG_CMD, ~0, HDMI_TG_FIELD_EN); - hdmi_writebn(hdev, HDMI_TG_V_FSZ_L, 2, t->vact[1].end); - hdmi_writebn(hdev, HDMI_TG_VSYNC2_L, 2, t->vsyn[1].beg); - hdmi_writebn(hdev, HDMI_TG_FIELD_CHG_L, 2, t->vact[0].end); - hdmi_writebn(hdev, HDMI_TG_VACT_ST2_L, 2, t->vact[1].beg); - hdmi_writebn(hdev, HDMI_TG_VSYNC_BOT_HDMI_L, 2, t->vsyn[1].beg); - hdmi_writebn(hdev, HDMI_TG_FIELD_BOT_HDMI_L, 2, t->vsyn[1].beg); - } else { - hdmi_write_mask(hdev, HDMI_TG_CMD, 0, HDMI_TG_FIELD_EN); - hdmi_writebn(hdev, HDMI_TG_V_FSZ_L, 2, t->vact[0].end); - } -} - -static int hdmi_conf_apply(struct hdmi_device *hdmi_dev) -{ - struct device *dev = hdmi_dev->dev; - const struct hdmi_timings *conf = hdmi_dev->cur_conf; - int ret; - - dev_dbg(dev, "%s\n", __func__); - - /* skip if conf is already synchronized with HW */ - if (!hdmi_dev->cur_conf_dirty) - return 0; - - /* reset hdmiphy */ - hdmi_write_mask(hdmi_dev, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT); - mdelay(10); - hdmi_write_mask(hdmi_dev, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT); - mdelay(10); - - /* configure timings */ - ret = v4l2_subdev_call(hdmi_dev->phy_sd, video, s_dv_timings, - &hdmi_dev->cur_timings); - if (ret) { - dev_err(dev, "failed to set timings\n"); - return ret; - } - - /* resetting HDMI core */ - hdmi_write_mask(hdmi_dev, HDMI_CORE_RSTOUT, 0, HDMI_CORE_SW_RSTOUT); - mdelay(10); - hdmi_write_mask(hdmi_dev, HDMI_CORE_RSTOUT, ~0, HDMI_CORE_SW_RSTOUT); - mdelay(10); - - hdmi_reg_init(hdmi_dev); - - /* setting core registers */ - hdmi_timing_apply(hdmi_dev, conf); - - hdmi_dev->cur_conf_dirty = 0; - - return 0; -} - -static void hdmi_dumpregs(struct hdmi_device *hdev, char *prefix) -{ -#define DUMPREG(reg_id) \ - dev_dbg(hdev->dev, "%s:" #reg_id " = %08x\n", prefix, \ - readl(hdev->regs + reg_id)) - - dev_dbg(hdev->dev, "%s: ---- CONTROL REGISTERS ----\n", prefix); - DUMPREG(HDMI_INTC_FLAG); - DUMPREG(HDMI_INTC_CON); - DUMPREG(HDMI_HPD_STATUS); - DUMPREG(HDMI_PHY_RSTOUT); - DUMPREG(HDMI_PHY_VPLL); - DUMPREG(HDMI_PHY_CMU); - DUMPREG(HDMI_CORE_RSTOUT); - - dev_dbg(hdev->dev, "%s: ---- CORE REGISTERS ----\n", prefix); - DUMPREG(HDMI_CON_0); - DUMPREG(HDMI_CON_1); - DUMPREG(HDMI_CON_2); - DUMPREG(HDMI_SYS_STATUS); - DUMPREG(HDMI_PHY_STATUS); - DUMPREG(HDMI_STATUS_EN); - DUMPREG(HDMI_HPD); - DUMPREG(HDMI_MODE_SEL); - DUMPREG(HDMI_HPD_GEN); - DUMPREG(HDMI_DC_CONTROL); - DUMPREG(HDMI_VIDEO_PATTERN_GEN); - - dev_dbg(hdev->dev, "%s: ---- CORE SYNC REGISTERS ----\n", prefix); - DUMPREG(HDMI_H_BLANK_0); - DUMPREG(HDMI_H_BLANK_1); - DUMPREG(HDMI_V_BLANK_0); - DUMPREG(HDMI_V_BLANK_1); - DUMPREG(HDMI_V_BLANK_2); - DUMPREG(HDMI_H_V_LINE_0); - DUMPREG(HDMI_H_V_LINE_1); - DUMPREG(HDMI_H_V_LINE_2); - DUMPREG(HDMI_VSYNC_POL); - DUMPREG(HDMI_INT_PRO_MODE); - DUMPREG(HDMI_V_BLANK_F_0); - DUMPREG(HDMI_V_BLANK_F_1); - DUMPREG(HDMI_V_BLANK_F_2); - DUMPREG(HDMI_H_SYNC_GEN_0); - DUMPREG(HDMI_H_SYNC_GEN_1); - DUMPREG(HDMI_H_SYNC_GEN_2); - DUMPREG(HDMI_V_SYNC_GEN_1_0); - DUMPREG(HDMI_V_SYNC_GEN_1_1); - DUMPREG(HDMI_V_SYNC_GEN_1_2); - DUMPREG(HDMI_V_SYNC_GEN_2_0); - DUMPREG(HDMI_V_SYNC_GEN_2_1); - DUMPREG(HDMI_V_SYNC_GEN_2_2); - DUMPREG(HDMI_V_SYNC_GEN_3_0); - DUMPREG(HDMI_V_SYNC_GEN_3_1); - DUMPREG(HDMI_V_SYNC_GEN_3_2); - - dev_dbg(hdev->dev, "%s: ---- TG REGISTERS ----\n", prefix); - DUMPREG(HDMI_TG_CMD); - DUMPREG(HDMI_TG_H_FSZ_L); - DUMPREG(HDMI_TG_H_FSZ_H); - DUMPREG(HDMI_TG_HACT_ST_L); - DUMPREG(HDMI_TG_HACT_ST_H); - DUMPREG(HDMI_TG_HACT_SZ_L); - DUMPREG(HDMI_TG_HACT_SZ_H); - DUMPREG(HDMI_TG_V_FSZ_L); - DUMPREG(HDMI_TG_V_FSZ_H); - DUMPREG(HDMI_TG_VSYNC_L); - DUMPREG(HDMI_TG_VSYNC_H); - DUMPREG(HDMI_TG_VSYNC2_L); - DUMPREG(HDMI_TG_VSYNC2_H); - DUMPREG(HDMI_TG_VACT_ST_L); - DUMPREG(HDMI_TG_VACT_ST_H); - DUMPREG(HDMI_TG_VACT_SZ_L); - DUMPREG(HDMI_TG_VACT_SZ_H); - DUMPREG(HDMI_TG_FIELD_CHG_L); - DUMPREG(HDMI_TG_FIELD_CHG_H); - DUMPREG(HDMI_TG_VACT_ST2_L); - DUMPREG(HDMI_TG_VACT_ST2_H); - DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L); - DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H); - DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L); - DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H); - DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L); - DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H); - DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L); - DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H); -#undef DUMPREG -} - -static const struct hdmi_timings hdmi_timings_480p = { - .hact = { .beg = 138, .end = 858 }, - .hsyn_pol = 1, - .hsyn = { .beg = 16, .end = 16 + 62 }, - .interlaced = 0, - .vact[0] = { .beg = 42 + 3, .end = 522 + 3 }, - .vsyn_pol = 1, - .vsyn[0] = { .beg = 6 + 3, .end = 12 + 3}, -}; - -static const struct hdmi_timings hdmi_timings_576p50 = { - .hact = { .beg = 144, .end = 864 }, - .hsyn_pol = 1, - .hsyn = { .beg = 12, .end = 12 + 64 }, - .interlaced = 0, - .vact[0] = { .beg = 44 + 5, .end = 620 + 5 }, - .vsyn_pol = 1, - .vsyn[0] = { .beg = 0 + 5, .end = 5 + 5}, -}; - -static const struct hdmi_timings hdmi_timings_720p60 = { - .hact = { .beg = 370, .end = 1650 }, - .hsyn_pol = 0, - .hsyn = { .beg = 110, .end = 110 + 40 }, - .interlaced = 0, - .vact[0] = { .beg = 25 + 5, .end = 745 + 5 }, - .vsyn_pol = 0, - .vsyn[0] = { .beg = 0 + 5, .end = 5 + 5}, -}; - -static const struct hdmi_timings hdmi_timings_720p50 = { - .hact = { .beg = 700, .end = 1980 }, - .hsyn_pol = 0, - .hsyn = { .beg = 440, .end = 440 + 40 }, - .interlaced = 0, - .vact[0] = { .beg = 25 + 5, .end = 745 + 5 }, - .vsyn_pol = 0, - .vsyn[0] = { .beg = 0 + 5, .end = 5 + 5}, -}; - -static const struct hdmi_timings hdmi_timings_1080p24 = { - .hact = { .beg = 830, .end = 2750 }, - .hsyn_pol = 0, - .hsyn = { .beg = 638, .end = 638 + 44 }, - .interlaced = 0, - .vact[0] = { .beg = 41 + 4, .end = 1121 + 4 }, - .vsyn_pol = 0, - .vsyn[0] = { .beg = 0 + 4, .end = 5 + 4}, -}; - -static const struct hdmi_timings hdmi_timings_1080p60 = { - .hact = { .beg = 280, .end = 2200 }, - .hsyn_pol = 0, - .hsyn = { .beg = 88, .end = 88 + 44 }, - .interlaced = 0, - .vact[0] = { .beg = 41 + 4, .end = 1121 + 4 }, - .vsyn_pol = 0, - .vsyn[0] = { .beg = 0 + 4, .end = 5 + 4}, -}; - -static const struct hdmi_timings hdmi_timings_1080i60 = { - .hact = { .beg = 280, .end = 2200 }, - .hsyn_pol = 0, - .hsyn = { .beg = 88, .end = 88 + 44 }, - .interlaced = 1, - .vact[0] = { .beg = 20 + 2, .end = 560 + 2 }, - .vact[1] = { .beg = 583 + 2, .end = 1123 + 2 }, - .vsyn_pol = 0, - .vsyn_off = 1100, - .vsyn[0] = { .beg = 0 + 2, .end = 5 + 2}, - .vsyn[1] = { .beg = 562 + 2, .end = 567 + 2}, -}; - -static const struct hdmi_timings hdmi_timings_1080i50 = { - .hact = { .beg = 720, .end = 2640 }, - .hsyn_pol = 0, - .hsyn = { .beg = 528, .end = 528 + 44 }, - .interlaced = 1, - .vact[0] = { .beg = 20 + 2, .end = 560 + 2 }, - .vact[1] = { .beg = 583 + 2, .end = 1123 + 2 }, - .vsyn_pol = 0, - .vsyn_off = 1320, - .vsyn[0] = { .beg = 0 + 2, .end = 5 + 2}, - .vsyn[1] = { .beg = 562 + 2, .end = 567 + 2}, -}; - -static const struct hdmi_timings hdmi_timings_1080p50 = { - .hact = { .beg = 720, .end = 2640 }, - .hsyn_pol = 0, - .hsyn = { .beg = 528, .end = 528 + 44 }, - .interlaced = 0, - .vact[0] = { .beg = 41 + 4, .end = 1121 + 4 }, - .vsyn_pol = 0, - .vsyn[0] = { .beg = 0 + 4, .end = 5 + 4}, -}; - -/* default hdmi_timings index of the timings configured on probe */ -#define HDMI_DEFAULT_TIMINGS_IDX (0) - -static const struct { - bool reduced_fps; - const struct v4l2_dv_timings dv_timings; - const struct hdmi_timings *hdmi_timings; -} hdmi_timings[] = { - { false, V4L2_DV_BT_CEA_720X480P59_94, &hdmi_timings_480p }, - { false, V4L2_DV_BT_CEA_720X576P50, &hdmi_timings_576p50 }, - { false, V4L2_DV_BT_CEA_1280X720P50, &hdmi_timings_720p50 }, - { true, V4L2_DV_BT_CEA_1280X720P60, &hdmi_timings_720p60 }, - { false, V4L2_DV_BT_CEA_1920X1080P24, &hdmi_timings_1080p24 }, - { false, V4L2_DV_BT_CEA_1920X1080P30, &hdmi_timings_1080p60 }, - { false, V4L2_DV_BT_CEA_1920X1080P50, &hdmi_timings_1080p50 }, - { false, V4L2_DV_BT_CEA_1920X1080I50, &hdmi_timings_1080i50 }, - { false, V4L2_DV_BT_CEA_1920X1080I60, &hdmi_timings_1080i60 }, - { false, V4L2_DV_BT_CEA_1920X1080P60, &hdmi_timings_1080p60 }, -}; - -static int hdmi_streamon(struct hdmi_device *hdev) -{ - struct device *dev = hdev->dev; - struct hdmi_resources *res = &hdev->res; - int ret, tries; - - dev_dbg(dev, "%s\n", __func__); - - ret = hdmi_conf_apply(hdev); - if (ret) - return ret; - - ret = v4l2_subdev_call(hdev->phy_sd, video, s_stream, 1); - if (ret) - return ret; - - /* waiting for HDMIPHY's PLL to get to steady state */ - for (tries = 100; tries; --tries) { - u32 val = hdmi_read(hdev, HDMI_PHY_STATUS); - if (val & HDMI_PHY_STATUS_READY) - break; - mdelay(1); - } - /* steady state not achieved */ - if (tries == 0) { - dev_err(dev, "hdmiphy's pll could not reach steady state.\n"); - v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0); - hdmi_dumpregs(hdev, "hdmiphy - s_stream"); - return -EIO; - } - - /* starting MHL */ - ret = v4l2_subdev_call(hdev->mhl_sd, video, s_stream, 1); - if (hdev->mhl_sd && ret) { - v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0); - hdmi_dumpregs(hdev, "mhl - s_stream"); - return -EIO; - } - - /* hdmiphy clock is used for HDMI in streaming mode */ - clk_disable(res->sclk_hdmi); - clk_set_parent(res->sclk_hdmi, res->sclk_hdmiphy); - clk_enable(res->sclk_hdmi); - - /* enable HDMI and timing generator */ - hdmi_write_mask(hdev, HDMI_CON_0, ~0, HDMI_EN); - hdmi_write_mask(hdev, HDMI_TG_CMD, ~0, HDMI_TG_EN); - hdmi_dumpregs(hdev, "streamon"); - return 0; -} - -static int hdmi_streamoff(struct hdmi_device *hdev) -{ - struct device *dev = hdev->dev; - struct hdmi_resources *res = &hdev->res; - - dev_dbg(dev, "%s\n", __func__); - - hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_EN); - hdmi_write_mask(hdev, HDMI_TG_CMD, 0, HDMI_TG_EN); - - /* pixel(vpll) clock is used for HDMI in config mode */ - clk_disable(res->sclk_hdmi); - clk_set_parent(res->sclk_hdmi, res->sclk_pixel); - clk_enable(res->sclk_hdmi); - - v4l2_subdev_call(hdev->mhl_sd, video, s_stream, 0); - v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0); - - hdmi_dumpregs(hdev, "streamoff"); - return 0; -} - -static int hdmi_s_stream(struct v4l2_subdev *sd, int enable) -{ - struct hdmi_device *hdev = sd_to_hdmi_dev(sd); - struct device *dev = hdev->dev; - - dev_dbg(dev, "%s(%d)\n", __func__, enable); - if (enable) - return hdmi_streamon(hdev); - return hdmi_streamoff(hdev); -} - -static int hdmi_resource_poweron(struct hdmi_resources *res) -{ - int ret; - - /* turn HDMI power on */ - ret = regulator_bulk_enable(res->regul_count, res->regul_bulk); - if (ret < 0) - return ret; - /* power-on hdmi physical interface */ - clk_enable(res->hdmiphy); - /* use VPP as parent clock; HDMIPHY is not working yet */ - clk_set_parent(res->sclk_hdmi, res->sclk_pixel); - /* turn clocks on */ - clk_enable(res->sclk_hdmi); - - return 0; -} - -static void hdmi_resource_poweroff(struct hdmi_resources *res) -{ - /* turn clocks off */ - clk_disable(res->sclk_hdmi); - /* power-off hdmiphy */ - clk_disable(res->hdmiphy); - /* turn HDMI power off */ - regulator_bulk_disable(res->regul_count, res->regul_bulk); -} - -static int hdmi_s_power(struct v4l2_subdev *sd, int on) -{ - struct hdmi_device *hdev = sd_to_hdmi_dev(sd); - int ret; - - if (on) - ret = pm_runtime_get_sync(hdev->dev); - else - ret = pm_runtime_put_sync(hdev->dev); - /* only values < 0 indicate errors */ - return ret < 0 ? ret : 0; -} - -static int hdmi_s_dv_timings(struct v4l2_subdev *sd, - struct v4l2_dv_timings *timings) -{ - struct hdmi_device *hdev = sd_to_hdmi_dev(sd); - struct device *dev = hdev->dev; - int i; - - for (i = 0; i < ARRAY_SIZE(hdmi_timings); i++) - if (v4l2_match_dv_timings(&hdmi_timings[i].dv_timings, - timings, 0, false)) - break; - if (i == ARRAY_SIZE(hdmi_timings)) { - dev_err(dev, "timings not supported\n"); - return -EINVAL; - } - hdev->cur_conf = hdmi_timings[i].hdmi_timings; - hdev->cur_conf_dirty = 1; - hdev->cur_timings = *timings; - if (!hdmi_timings[i].reduced_fps) - hdev->cur_timings.bt.flags &= ~V4L2_DV_FL_CAN_REDUCE_FPS; - return 0; -} - -static int hdmi_g_dv_timings(struct v4l2_subdev *sd, - struct v4l2_dv_timings *timings) -{ - *timings = sd_to_hdmi_dev(sd)->cur_timings; - return 0; -} - -static int hdmi_get_fmt(struct v4l2_subdev *sd, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_format *format) -{ - struct v4l2_mbus_framefmt *fmt = &format->format; - struct hdmi_device *hdev = sd_to_hdmi_dev(sd); - const struct hdmi_timings *t = hdev->cur_conf; - - dev_dbg(hdev->dev, "%s\n", __func__); - if (!hdev->cur_conf) - return -EINVAL; - if (format->pad) - return -EINVAL; - - memset(fmt, 0, sizeof(*fmt)); - fmt->width = t->hact.end - t->hact.beg; - fmt->height = t->vact[0].end - t->vact[0].beg; - fmt->code = MEDIA_BUS_FMT_FIXED; /* means RGB888 */ - fmt->colorspace = V4L2_COLORSPACE_SRGB; - if (t->interlaced) { - fmt->field = V4L2_FIELD_INTERLACED; - fmt->height *= 2; - } else { - fmt->field = V4L2_FIELD_NONE; - } - return 0; -} - -static int hdmi_enum_dv_timings(struct v4l2_subdev *sd, - struct v4l2_enum_dv_timings *timings) -{ - if (timings->pad != 0) - return -EINVAL; - if (timings->index >= ARRAY_SIZE(hdmi_timings)) - return -EINVAL; - timings->timings = hdmi_timings[timings->index].dv_timings; - if (!hdmi_timings[timings->index].reduced_fps) - timings->timings.bt.flags &= ~V4L2_DV_FL_CAN_REDUCE_FPS; - return 0; -} - -static int hdmi_dv_timings_cap(struct v4l2_subdev *sd, - struct v4l2_dv_timings_cap *cap) -{ - struct hdmi_device *hdev = sd_to_hdmi_dev(sd); - - if (cap->pad != 0) - return -EINVAL; - - /* Let the phy fill in the pixelclock range */ - v4l2_subdev_call(hdev->phy_sd, pad, dv_timings_cap, cap); - cap->type = V4L2_DV_BT_656_1120; - cap->bt.min_width = 720; - cap->bt.max_width = 1920; - cap->bt.min_height = 480; - cap->bt.max_height = 1080; - cap->bt.standards = V4L2_DV_BT_STD_CEA861; - cap->bt.capabilities = V4L2_DV_BT_CAP_INTERLACED | - V4L2_DV_BT_CAP_PROGRESSIVE; - return 0; -} - -static const struct v4l2_subdev_core_ops hdmi_sd_core_ops = { - .s_power = hdmi_s_power, -}; - -static const struct v4l2_subdev_video_ops hdmi_sd_video_ops = { - .s_dv_timings = hdmi_s_dv_timings, - .g_dv_timings = hdmi_g_dv_timings, - .s_stream = hdmi_s_stream, -}; - -static const struct v4l2_subdev_pad_ops hdmi_sd_pad_ops = { - .enum_dv_timings = hdmi_enum_dv_timings, - .dv_timings_cap = hdmi_dv_timings_cap, - .get_fmt = hdmi_get_fmt, -}; - -static const struct v4l2_subdev_ops hdmi_sd_ops = { - .core = &hdmi_sd_core_ops, - .video = &hdmi_sd_video_ops, - .pad = &hdmi_sd_pad_ops, -}; - -static int hdmi_runtime_suspend(struct device *dev) -{ - struct v4l2_subdev *sd = dev_get_drvdata(dev); - struct hdmi_device *hdev = sd_to_hdmi_dev(sd); - - dev_dbg(dev, "%s\n", __func__); - v4l2_subdev_call(hdev->mhl_sd, core, s_power, 0); - hdmi_resource_poweroff(&hdev->res); - /* flag that device context is lost */ - hdev->cur_conf_dirty = 1; - return 0; -} - -static int hdmi_runtime_resume(struct device *dev) -{ - struct v4l2_subdev *sd = dev_get_drvdata(dev); - struct hdmi_device *hdev = sd_to_hdmi_dev(sd); - int ret; - - dev_dbg(dev, "%s\n", __func__); - - ret = hdmi_resource_poweron(&hdev->res); - if (ret < 0) - return ret; - - /* starting MHL */ - ret = v4l2_subdev_call(hdev->mhl_sd, core, s_power, 1); - if (hdev->mhl_sd && ret) - goto fail; - - dev_dbg(dev, "poweron succeed\n"); - - return 0; - -fail: - hdmi_resource_poweroff(&hdev->res); - dev_err(dev, "poweron failed\n"); - - return ret; -} - -static const struct dev_pm_ops hdmi_pm_ops = { - .runtime_suspend = hdmi_runtime_suspend, - .runtime_resume = hdmi_runtime_resume, -}; - -static void hdmi_resource_clear_clocks(struct hdmi_resources *res) -{ - res->hdmi = ERR_PTR(-EINVAL); - res->sclk_hdmi = ERR_PTR(-EINVAL); - res->sclk_pixel = ERR_PTR(-EINVAL); - res->sclk_hdmiphy = ERR_PTR(-EINVAL); - res->hdmiphy = ERR_PTR(-EINVAL); -} - -static void hdmi_resources_cleanup(struct hdmi_device *hdev) -{ - struct hdmi_resources *res = &hdev->res; - - dev_dbg(hdev->dev, "HDMI resource cleanup\n"); - /* put clocks, power */ - if (res->regul_count) - regulator_bulk_free(res->regul_count, res->regul_bulk); - /* kfree is NULL-safe */ - kfree(res->regul_bulk); - if (!IS_ERR(res->hdmiphy)) - clk_put(res->hdmiphy); - if (!IS_ERR(res->sclk_hdmiphy)) - clk_put(res->sclk_hdmiphy); - if (!IS_ERR(res->sclk_pixel)) - clk_put(res->sclk_pixel); - if (!IS_ERR(res->sclk_hdmi)) - clk_put(res->sclk_hdmi); - if (!IS_ERR(res->hdmi)) - clk_put(res->hdmi); - memset(res, 0, sizeof(*res)); - hdmi_resource_clear_clocks(res); -} - -static int hdmi_resources_init(struct hdmi_device *hdev) -{ - struct device *dev = hdev->dev; - struct hdmi_resources *res = &hdev->res; - static char *supply[] = { - "hdmi-en", - "vdd", - "vdd_osc", - "vdd_pll", - }; - int i, ret; - - dev_dbg(dev, "HDMI resource init\n"); - - memset(res, 0, sizeof(*res)); - hdmi_resource_clear_clocks(res); - - /* get clocks, power */ - res->hdmi = clk_get(dev, "hdmi"); - if (IS_ERR(res->hdmi)) { - dev_err(dev, "failed to get clock 'hdmi'\n"); - goto fail; - } - res->sclk_hdmi = clk_get(dev, "sclk_hdmi"); - if (IS_ERR(res->sclk_hdmi)) { - dev_err(dev, "failed to get clock 'sclk_hdmi'\n"); - goto fail; - } - res->sclk_pixel = clk_get(dev, "sclk_pixel"); - if (IS_ERR(res->sclk_pixel)) { - dev_err(dev, "failed to get clock 'sclk_pixel'\n"); - goto fail; - } - res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy"); - if (IS_ERR(res->sclk_hdmiphy)) { - dev_err(dev, "failed to get clock 'sclk_hdmiphy'\n"); - goto fail; - } - res->hdmiphy = clk_get(dev, "hdmiphy"); - if (IS_ERR(res->hdmiphy)) { - dev_err(dev, "failed to get clock 'hdmiphy'\n"); - goto fail; - } - res->regul_bulk = kcalloc(ARRAY_SIZE(supply), - sizeof(res->regul_bulk[0]), GFP_KERNEL); - if (!res->regul_bulk) { - dev_err(dev, "failed to get memory for regulators\n"); - goto fail; - } - for (i = 0; i < ARRAY_SIZE(supply); ++i) { - res->regul_bulk[i].supply = supply[i]; - res->regul_bulk[i].consumer = NULL; - } - - ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk); - if (ret) { - dev_err(dev, "failed to get regulators\n"); - goto fail; - } - res->regul_count = ARRAY_SIZE(supply); - - return 0; -fail: - dev_err(dev, "HDMI resource init - failed\n"); - hdmi_resources_cleanup(hdev); - return -ENODEV; -} - -static int hdmi_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct resource *res; - struct i2c_adapter *adapter; - struct v4l2_subdev *sd; - struct hdmi_device *hdmi_dev = NULL; - struct s5p_hdmi_platform_data *pdata = dev->platform_data; - int ret; - - dev_dbg(dev, "probe start\n"); - - if (!pdata) { - dev_err(dev, "platform data is missing\n"); - ret = -ENODEV; - goto fail; - } - - hdmi_dev = devm_kzalloc(&pdev->dev, sizeof(*hdmi_dev), GFP_KERNEL); - if (!hdmi_dev) { - dev_err(dev, "out of memory\n"); - ret = -ENOMEM; - goto fail; - } - - hdmi_dev->dev = dev; - - ret = hdmi_resources_init(hdmi_dev); - if (ret) - goto fail; - - /* mapping HDMI registers */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res == NULL) { - dev_err(dev, "get memory resource failed.\n"); - ret = -ENXIO; - goto fail_init; - } - - hdmi_dev->regs = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); - if (hdmi_dev->regs == NULL) { - dev_err(dev, "register mapping failed.\n"); - ret = -ENXIO; - goto fail_init; - } - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (res == NULL) { - dev_err(dev, "get interrupt resource failed.\n"); - ret = -ENXIO; - goto fail_init; - } - - ret = devm_request_irq(&pdev->dev, res->start, hdmi_irq_handler, 0, - "hdmi", hdmi_dev); - if (ret) { - dev_err(dev, "request interrupt failed.\n"); - goto fail_init; - } - hdmi_dev->irq = res->start; - - /* setting v4l2 name to prevent WARN_ON in v4l2_device_register */ - strlcpy(hdmi_dev->v4l2_dev.name, dev_name(dev), - sizeof(hdmi_dev->v4l2_dev.name)); - /* passing NULL owner prevents driver from erasing drvdata */ - ret = v4l2_device_register(NULL, &hdmi_dev->v4l2_dev); - if (ret) { - dev_err(dev, "could not register v4l2 device.\n"); - goto fail_init; - } - - /* testing if hdmiphy info is present */ - if (!pdata->hdmiphy_info) { - dev_err(dev, "hdmiphy info is missing in platform data\n"); - ret = -ENXIO; - goto fail_vdev; - } - - adapter = i2c_get_adapter(pdata->hdmiphy_bus); - if (adapter == NULL) { - dev_err(dev, "hdmiphy adapter request failed\n"); - ret = -ENXIO; - goto fail_vdev; - } - - hdmi_dev->phy_sd = v4l2_i2c_new_subdev_board(&hdmi_dev->v4l2_dev, - adapter, pdata->hdmiphy_info, NULL); - /* on failure or not adapter is no longer useful */ - i2c_put_adapter(adapter); - if (hdmi_dev->phy_sd == NULL) { - dev_err(dev, "missing subdev for hdmiphy\n"); - ret = -ENODEV; - goto fail_vdev; - } - - /* initialization of MHL interface if present */ - if (pdata->mhl_info) { - adapter = i2c_get_adapter(pdata->mhl_bus); - if (adapter == NULL) { - dev_err(dev, "MHL adapter request failed\n"); - ret = -ENXIO; - goto fail_vdev; - } - - hdmi_dev->mhl_sd = v4l2_i2c_new_subdev_board( - &hdmi_dev->v4l2_dev, adapter, - pdata->mhl_info, NULL); - /* on failure or not adapter is no longer useful */ - i2c_put_adapter(adapter); - if (hdmi_dev->mhl_sd == NULL) { - dev_err(dev, "missing subdev for MHL\n"); - ret = -ENODEV; - goto fail_vdev; - } - } - - clk_enable(hdmi_dev->res.hdmi); - - pm_runtime_enable(dev); - - sd = &hdmi_dev->sd; - v4l2_subdev_init(sd, &hdmi_sd_ops); - sd->owner = THIS_MODULE; - - strlcpy(sd->name, "s5p-hdmi", sizeof(sd->name)); - hdmi_dev->cur_timings = - hdmi_timings[HDMI_DEFAULT_TIMINGS_IDX].dv_timings; - /* FIXME: missing fail timings is not supported */ - hdmi_dev->cur_conf = - hdmi_timings[HDMI_DEFAULT_TIMINGS_IDX].hdmi_timings; - hdmi_dev->cur_conf_dirty = 1; - - /* storing subdev for call that have only access to struct device */ - dev_set_drvdata(dev, sd); - - dev_info(dev, "probe successful\n"); - - return 0; - -fail_vdev: - v4l2_device_unregister(&hdmi_dev->v4l2_dev); - -fail_init: - hdmi_resources_cleanup(hdmi_dev); - -fail: - dev_err(dev, "probe failed\n"); - return ret; -} - -static int hdmi_remove(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct v4l2_subdev *sd = dev_get_drvdata(dev); - struct hdmi_device *hdmi_dev = sd_to_hdmi_dev(sd); - - pm_runtime_disable(dev); - clk_disable(hdmi_dev->res.hdmi); - v4l2_device_unregister(&hdmi_dev->v4l2_dev); - disable_irq(hdmi_dev->irq); - hdmi_resources_cleanup(hdmi_dev); - dev_info(dev, "remove successful\n"); - - return 0; -} - -static struct platform_driver hdmi_driver __refdata = { - .probe = hdmi_probe, - .remove = hdmi_remove, - .id_table = hdmi_driver_types, - .driver = { - .name = "s5p-hdmi", - .pm = &hdmi_pm_ops, - } -}; - -module_platform_driver(hdmi_driver); diff --git a/drivers/media/platform/s5p-tv/hdmiphy_drv.c b/drivers/media/platform/s5p-tv/hdmiphy_drv.c deleted file mode 100644 index aae652351aa8..000000000000 --- a/drivers/media/platform/s5p-tv/hdmiphy_drv.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Samsung HDMI Physical interface driver - * - * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd - * Author: Tomasz Stanislawski - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -MODULE_AUTHOR("Tomasz Stanislawski "); -MODULE_DESCRIPTION("Samsung HDMI Physical interface driver"); -MODULE_LICENSE("GPL"); - -struct hdmiphy_conf { - unsigned long pixclk; - const u8 *data; -}; - -struct hdmiphy_ctx { - struct v4l2_subdev sd; - const struct hdmiphy_conf *conf_tab; -}; - -static const struct hdmiphy_conf hdmiphy_conf_s5pv210[] = { - { .pixclk = 27000000, .data = (u8 [32]) { - 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40, - 0x6B, 0x10, 0x02, 0x52, 0xDF, 0xF2, 0x54, 0x87, - 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00, } - }, - { .pixclk = 27027000, .data = (u8 [32]) { - 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64, - 0x6B, 0x10, 0x02, 0x52, 0xDF, 0xF2, 0x54, 0x87, - 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x22, 0x40, 0xE2, 0x26, 0x00, 0x00, 0x00, 0x00, } - }, - { .pixclk = 74176000, .data = (u8 [32]) { - 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xEF, 0x5B, - 0x6D, 0x10, 0x01, 0x52, 0xEF, 0xF3, 0x54, 0xB9, - 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x22, 0x40, 0xA5, 0x26, 0x01, 0x00, 0x00, 0x00, } - }, - { .pixclk = 74250000, .data = (u8 [32]) { - 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xF8, 0x40, - 0x6A, 0x10, 0x01, 0x52, 0xFF, 0xF1, 0x54, 0xBA, - 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x22, 0x40, 0xA4, 0x26, 0x01, 0x00, 0x00, 0x00, } - }, - { /* end marker */ } -}; - -static const struct hdmiphy_conf hdmiphy_conf_exynos4210[] = { - { .pixclk = 27000000, .data = (u8 [32]) { - 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40, - 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, - 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00, } - }, - { .pixclk = 27027000, .data = (u8 [32]) { - 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64, - 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, - 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x22, 0x40, 0xE2, 0x26, 0x00, 0x00, 0x00, 0x00, } - }, - { .pixclk = 74176000, .data = (u8 [32]) { - 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xEF, 0x5B, - 0x6D, 0x10, 0x01, 0x51, 0xEF, 0xF3, 0x54, 0xB9, - 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x22, 0x40, 0xA5, 0x26, 0x01, 0x00, 0x00, 0x00, } - }, - { .pixclk = 74250000, .data = (u8 [32]) { - 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xF8, 0x40, - 0x6A, 0x10, 0x01, 0x51, 0xFF, 0xF1, 0x54, 0xBA, - 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x22, 0x40, 0xA4, 0x26, 0x01, 0x00, 0x00, 0x00, } - }, - { .pixclk = 148352000, .data = (u8 [32]) { - 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xEF, 0x5B, - 0x6D, 0x18, 0x00, 0x51, 0xEF, 0xF3, 0x54, 0xB9, - 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x11, 0x40, 0xA5, 0x26, 0x02, 0x00, 0x00, 0x00, } - }, - { .pixclk = 148500000, .data = (u8 [32]) { - 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xF8, 0x40, - 0x6A, 0x18, 0x00, 0x51, 0xFF, 0xF1, 0x54, 0xBA, - 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x11, 0x40, 0xA4, 0x26, 0x02, 0x00, 0x00, 0x00, } - }, - { /* end marker */ } -}; - -static const struct hdmiphy_conf hdmiphy_conf_exynos4212[] = { - { .pixclk = 27000000, .data = (u8 [32]) { - 0x01, 0x11, 0x2D, 0x75, 0x00, 0x01, 0x00, 0x08, - 0x82, 0x00, 0x0E, 0xD9, 0x45, 0xA0, 0x34, 0xC0, - 0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0x71, - 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, } - }, - { .pixclk = 27027000, .data = (u8 [32]) { - 0x01, 0x91, 0x2D, 0x72, 0x00, 0x64, 0x12, 0x08, - 0x43, 0x20, 0x0E, 0xD9, 0x45, 0xA0, 0x34, 0xC0, - 0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0x71, - 0x54, 0xE2, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, } - }, - { .pixclk = 74176000, .data = (u8 [32]) { - 0x01, 0x91, 0x3E, 0x35, 0x00, 0x5B, 0xDE, 0x08, - 0x82, 0x20, 0x73, 0xD9, 0x45, 0xA0, 0x34, 0xC0, - 0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0x52, - 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, } - }, - { .pixclk = 74250000, .data = (u8 [32]) { - 0x01, 0x91, 0x3E, 0x35, 0x00, 0x40, 0xF0, 0x08, - 0x82, 0x20, 0x73, 0xD9, 0x45, 0xA0, 0x34, 0xC0, - 0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0x52, - 0x54, 0xA4, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, } - }, - { .pixclk = 148500000, .data = (u8 [32]) { - 0x01, 0x91, 0x3E, 0x15, 0x00, 0x40, 0xF0, 0x08, - 0x82, 0x20, 0x73, 0xD9, 0x45, 0xA0, 0x34, 0xC0, - 0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0xA4, - 0x54, 0x4A, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00, } - }, - { /* end marker */ } -}; - -static const struct hdmiphy_conf hdmiphy_conf_exynos4412[] = { - { .pixclk = 27000000, .data = (u8 [32]) { - 0x01, 0x11, 0x2D, 0x75, 0x40, 0x01, 0x00, 0x08, - 0x82, 0x00, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, - 0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, } - }, - { .pixclk = 27027000, .data = (u8 [32]) { - 0x01, 0x91, 0x2D, 0x72, 0x40, 0x64, 0x12, 0x08, - 0x43, 0x20, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, - 0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, } - }, - { .pixclk = 74176000, .data = (u8 [32]) { - 0x01, 0x91, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0x08, - 0x81, 0x20, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80, - 0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, } - }, - { .pixclk = 74250000, .data = (u8 [32]) { - 0x01, 0x91, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08, - 0x81, 0x20, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, - 0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, } - }, - { .pixclk = 148500000, .data = (u8 [32]) { - 0x01, 0x91, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08, - 0x81, 0x20, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, - 0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86, - 0x54, 0x4B, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00, } - }, - { /* end marker */ } -}; - -static inline struct hdmiphy_ctx *sd_to_ctx(struct v4l2_subdev *sd) -{ - return container_of(sd, struct hdmiphy_ctx, sd); -} - -static const u8 *hdmiphy_find_conf(unsigned long pixclk, - const struct hdmiphy_conf *conf) -{ - for (; conf->pixclk; ++conf) - if (conf->pixclk == pixclk) - return conf->data; - return NULL; -} - -static int hdmiphy_s_power(struct v4l2_subdev *sd, int on) -{ - /* to be implemented */ - return 0; -} - -static int hdmiphy_s_dv_timings(struct v4l2_subdev *sd, - struct v4l2_dv_timings *timings) -{ - const u8 *data; - u8 buffer[32]; - int ret; - struct hdmiphy_ctx *ctx = sd_to_ctx(sd); - struct i2c_client *client = v4l2_get_subdevdata(sd); - struct device *dev = &client->dev; - unsigned long pixclk = timings->bt.pixelclock; - - dev_info(dev, "s_dv_timings\n"); - if ((timings->bt.flags & V4L2_DV_FL_REDUCED_FPS) && pixclk == 74250000) - pixclk = 74176000; - data = hdmiphy_find_conf(pixclk, ctx->conf_tab); - if (!data) { - dev_err(dev, "format not supported\n"); - return -EINVAL; - } - - /* storing configuration to the device */ - memcpy(buffer, data, 32); - ret = i2c_master_send(client, buffer, 32); - if (ret != 32) { - dev_err(dev, "failed to configure HDMIPHY via I2C\n"); - return -EIO; - } - - return 0; -} - -static int hdmiphy_dv_timings_cap(struct v4l2_subdev *sd, - struct v4l2_dv_timings_cap *cap) -{ - if (cap->pad != 0) - return -EINVAL; - - cap->type = V4L2_DV_BT_656_1120; - /* The phy only determines the pixelclock, leave the other values - * at 0 to signify that we have no information for them. */ - cap->bt.min_pixelclock = 27000000; - cap->bt.max_pixelclock = 148500000; - return 0; -} - -static int hdmiphy_s_stream(struct v4l2_subdev *sd, int enable) -{ - struct i2c_client *client = v4l2_get_subdevdata(sd); - struct device *dev = &client->dev; - u8 buffer[2]; - int ret; - - dev_info(dev, "s_stream(%d)\n", enable); - /* going to/from configuration from/to operation mode */ - buffer[0] = 0x1f; - buffer[1] = enable ? 0x80 : 0x00; - - ret = i2c_master_send(client, buffer, 2); - if (ret != 2) { - dev_err(dev, "stream (%d) failed\n", enable); - return -EIO; - } - return 0; -} - -static const struct v4l2_subdev_core_ops hdmiphy_core_ops = { - .s_power = hdmiphy_s_power, -}; - -static const struct v4l2_subdev_video_ops hdmiphy_video_ops = { - .s_dv_timings = hdmiphy_s_dv_timings, - .s_stream = hdmiphy_s_stream, -}; - -static const struct v4l2_subdev_pad_ops hdmiphy_pad_ops = { - .dv_timings_cap = hdmiphy_dv_timings_cap, -}; - -static const struct v4l2_subdev_ops hdmiphy_ops = { - .core = &hdmiphy_core_ops, - .video = &hdmiphy_video_ops, - .pad = &hdmiphy_pad_ops, -}; - -static int hdmiphy_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct hdmiphy_ctx *ctx; - - ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return -ENOMEM; - - ctx->conf_tab = (struct hdmiphy_conf *)id->driver_data; - v4l2_i2c_subdev_init(&ctx->sd, client, &hdmiphy_ops); - - dev_info(&client->dev, "probe successful\n"); - return 0; -} - -static int hdmiphy_remove(struct i2c_client *client) -{ - struct v4l2_subdev *sd = i2c_get_clientdata(client); - struct hdmiphy_ctx *ctx = sd_to_ctx(sd); - - kfree(ctx); - dev_info(&client->dev, "remove successful\n"); - - return 0; -} - -static const struct i2c_device_id hdmiphy_id[] = { - { "hdmiphy", (unsigned long)hdmiphy_conf_exynos4210 }, - { "hdmiphy-s5pv210", (unsigned long)hdmiphy_conf_s5pv210 }, - { "hdmiphy-exynos4210", (unsigned long)hdmiphy_conf_exynos4210 }, - { "hdmiphy-exynos4212", (unsigned long)hdmiphy_conf_exynos4212 }, - { "hdmiphy-exynos4412", (unsigned long)hdmiphy_conf_exynos4412 }, - { }, -}; -MODULE_DEVICE_TABLE(i2c, hdmiphy_id); - -static struct i2c_driver hdmiphy_driver = { - .driver = { - .name = "s5p-hdmiphy", - }, - .probe = hdmiphy_probe, - .remove = hdmiphy_remove, - .id_table = hdmiphy_id, -}; - -module_i2c_driver(hdmiphy_driver); diff --git a/drivers/media/platform/s5p-tv/mixer.h b/drivers/media/platform/s5p-tv/mixer.h deleted file mode 100644 index 869f0ce86f6e..000000000000 --- a/drivers/media/platform/s5p-tv/mixer.h +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Samsung TV Mixer driver - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * - * Tomasz Stanislawski, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundiation. either version 2 of the License, - * or (at your option) any later version - */ - -#ifndef SAMSUNG_MIXER_H -#define SAMSUNG_MIXER_H - -#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MIXER_DEBUG - #define DEBUG -#endif - -#include -#include -#include -#include -#include -#include -#include - -#include "regs-mixer.h" - -/** maximum number of output interfaces */ -#define MXR_MAX_OUTPUTS 2 -/** maximum number of input interfaces (layers) */ -#define MXR_MAX_LAYERS 3 -#define MXR_DRIVER_NAME "s5p-mixer" -/** maximal number of planes for every layer */ -#define MXR_MAX_PLANES 2 - -#define MXR_ENABLE 1 -#define MXR_DISABLE 0 - -/** description of a macroblock for packed formats */ -struct mxr_block { - /** vertical number of pixels in macroblock */ - unsigned int width; - /** horizontal number of pixels in macroblock */ - unsigned int height; - /** size of block in bytes */ - unsigned int size; -}; - -/** description of supported format */ -struct mxr_format { - /** format name/mnemonic */ - const char *name; - /** fourcc identifier */ - u32 fourcc; - /** colorspace identifier */ - enum v4l2_colorspace colorspace; - /** number of planes in image data */ - int num_planes; - /** description of block for each plane */ - struct mxr_block plane[MXR_MAX_PLANES]; - /** number of subframes in image data */ - int num_subframes; - /** specifies to which subframe belong given plane */ - int plane2subframe[MXR_MAX_PLANES]; - /** internal code, driver dependent */ - unsigned long cookie; -}; - -/** description of crop configuration for image */ -struct mxr_crop { - /** width of layer in pixels */ - unsigned int full_width; - /** height of layer in pixels */ - unsigned int full_height; - /** horizontal offset of first pixel to be displayed */ - unsigned int x_offset; - /** vertical offset of first pixel to be displayed */ - unsigned int y_offset; - /** width of displayed data in pixels */ - unsigned int width; - /** height of displayed data in pixels */ - unsigned int height; - /** indicate which fields are present in buffer */ - unsigned int field; -}; - -/** stages of geometry operations */ -enum mxr_geometry_stage { - MXR_GEOMETRY_SINK, - MXR_GEOMETRY_COMPOSE, - MXR_GEOMETRY_CROP, - MXR_GEOMETRY_SOURCE, -}; - -/* flag indicating that offset should be 0 */ -#define MXR_NO_OFFSET 0x80000000 - -/** description of transformation from source to destination image */ -struct mxr_geometry { - /** cropping for source image */ - struct mxr_crop src; - /** cropping for destination image */ - struct mxr_crop dst; - /** layer-dependant description of horizontal scaling */ - unsigned int x_ratio; - /** layer-dependant description of vertical scaling */ - unsigned int y_ratio; -}; - -/** instance of a buffer */ -struct mxr_buffer { - /** common v4l buffer stuff -- must be first */ - struct vb2_v4l2_buffer vb; - /** node for layer's lists */ - struct list_head list; -}; - - -/** internal states of layer */ -enum mxr_layer_state { - /** layers is not shown */ - MXR_LAYER_IDLE = 0, - /** layer is shown */ - MXR_LAYER_STREAMING, - /** state before STREAMOFF is finished */ - MXR_LAYER_STREAMING_FINISH, -}; - -/** forward declarations */ -struct mxr_device; -struct mxr_layer; - -/** callback for layers operation */ -struct mxr_layer_ops { - /* TODO: try to port it to subdev API */ - /** handler for resource release function */ - void (*release)(struct mxr_layer *); - /** setting buffer to HW */ - void (*buffer_set)(struct mxr_layer *, struct mxr_buffer *); - /** setting format and geometry in HW */ - void (*format_set)(struct mxr_layer *); - /** streaming stop/start */ - void (*stream_set)(struct mxr_layer *, int); - /** adjusting geometry */ - void (*fix_geometry)(struct mxr_layer *, - enum mxr_geometry_stage, unsigned long); -}; - -/** layer instance, a single window and content displayed on output */ -struct mxr_layer { - /** parent mixer device */ - struct mxr_device *mdev; - /** layer index (unique identifier) */ - int idx; - /** callbacks for layer methods */ - struct mxr_layer_ops ops; - /** format array */ - const struct mxr_format **fmt_array; - /** size of format array */ - unsigned long fmt_array_size; - - /** lock for protection of list and state fields */ - spinlock_t enq_slock; - /** list for enqueued buffers */ - struct list_head enq_list; - /** buffer currently owned by hardware in temporary registers */ - struct mxr_buffer *update_buf; - /** buffer currently owned by hardware in shadow registers */ - struct mxr_buffer *shadow_buf; - /** state of layer IDLE/STREAMING */ - enum mxr_layer_state state; - - /** mutex for protection of fields below */ - struct mutex mutex; - /** handler for video node */ - struct video_device vfd; - /** queue for output buffers */ - struct vb2_queue vb_queue; - /** current image format */ - const struct mxr_format *fmt; - /** current geometry of image */ - struct mxr_geometry geo; -}; - -/** description of mixers output interface */ -struct mxr_output { - /** name of output */ - char name[32]; - /** output subdev */ - struct v4l2_subdev *sd; - /** cookie used for configuration of registers */ - int cookie; -}; - -/** specify source of output subdevs */ -struct mxr_output_conf { - /** name of output (connector) */ - char *output_name; - /** name of module that generates output subdev */ - char *module_name; - /** cookie need for mixer HW */ - int cookie; -}; - -struct clk; -struct regulator; - -/** auxiliary resources used my mixer */ -struct mxr_resources { - /** interrupt index */ - int irq; - /** pointer to Mixer registers */ - void __iomem *mxr_regs; - /** pointer to Video Processor registers */ - void __iomem *vp_regs; - /** other resources, should used under mxr_device.mutex */ - struct clk *mixer; - struct clk *vp; - struct clk *sclk_mixer; - struct clk *sclk_hdmi; - struct clk *sclk_dac; -}; - -/* event flags used */ -enum mxr_devide_flags { - MXR_EVENT_VSYNC = 0, - MXR_EVENT_TOP = 1, -}; - -/** drivers instance */ -struct mxr_device { - /** master device */ - struct device *dev; - /** state of each layer */ - struct mxr_layer *layer[MXR_MAX_LAYERS]; - /** state of each output */ - struct mxr_output *output[MXR_MAX_OUTPUTS]; - /** number of registered outputs */ - int output_cnt; - - /* video resources */ - - /** V4L2 device */ - struct v4l2_device v4l2_dev; - /** event wait queue */ - wait_queue_head_t event_queue; - /** state flags */ - unsigned long event_flags; - - /** spinlock for protection of registers */ - spinlock_t reg_slock; - - /** mutex for protection of fields below */ - struct mutex mutex; - /** number of entities depndant on output configuration */ - int n_output; - /** number of users that do streaming */ - int n_streamer; - /** index of current output */ - int current_output; - /** auxiliary resources used my mixer */ - struct mxr_resources res; -}; - -/** transform device structure into mixer device */ -static inline struct mxr_device *to_mdev(struct device *dev) -{ - struct v4l2_device *vdev = dev_get_drvdata(dev); - return container_of(vdev, struct mxr_device, v4l2_dev); -} - -/** get current output data, should be called under mdev's mutex */ -static inline struct mxr_output *to_output(struct mxr_device *mdev) -{ - return mdev->output[mdev->current_output]; -} - -/** get current output subdev, should be called under mdev's mutex */ -static inline struct v4l2_subdev *to_outsd(struct mxr_device *mdev) -{ - struct mxr_output *out = to_output(mdev); - return out ? out->sd : NULL; -} - -/** forward declaration for mixer platform data */ -struct mxr_platform_data; - -/** acquiring common video resources */ -int mxr_acquire_video(struct mxr_device *mdev, - struct mxr_output_conf *output_cont, int output_count); - -/** releasing common video resources */ -void mxr_release_video(struct mxr_device *mdev); - -struct mxr_layer *mxr_graph_layer_create(struct mxr_device *mdev, int idx); -struct mxr_layer *mxr_vp_layer_create(struct mxr_device *mdev, int idx); -struct mxr_layer *mxr_base_layer_create(struct mxr_device *mdev, - int idx, char *name, const struct mxr_layer_ops *ops); - -void mxr_base_layer_release(struct mxr_layer *layer); -void mxr_layer_release(struct mxr_layer *layer); - -int mxr_base_layer_register(struct mxr_layer *layer); -void mxr_base_layer_unregister(struct mxr_layer *layer); - -unsigned long mxr_get_plane_size(const struct mxr_block *blk, - unsigned int width, unsigned int height); - -/** adds new consumer for mixer's power */ -int __must_check mxr_power_get(struct mxr_device *mdev); -/** removes consumer for mixer's power */ -void mxr_power_put(struct mxr_device *mdev); -/** add new client for output configuration */ -void mxr_output_get(struct mxr_device *mdev); -/** removes new client for output configuration */ -void mxr_output_put(struct mxr_device *mdev); -/** add new client for streaming */ -void mxr_streamer_get(struct mxr_device *mdev); -/** removes new client for streaming */ -void mxr_streamer_put(struct mxr_device *mdev); -/** returns format of data delivared to current output */ -void mxr_get_mbus_fmt(struct mxr_device *mdev, - struct v4l2_mbus_framefmt *mbus_fmt); - -/* Debug */ - -#define mxr_err(mdev, fmt, ...) dev_err(mdev->dev, fmt, ##__VA_ARGS__) -#define mxr_warn(mdev, fmt, ...) dev_warn(mdev->dev, fmt, ##__VA_ARGS__) -#define mxr_info(mdev, fmt, ...) dev_info(mdev->dev, fmt, ##__VA_ARGS__) - -#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MIXER_DEBUG - #define mxr_dbg(mdev, fmt, ...) dev_dbg(mdev->dev, fmt, ##__VA_ARGS__) -#else - #define mxr_dbg(mdev, fmt, ...) do { (void) mdev; } while (0) -#endif - -/* accessing Mixer's and Video Processor's registers */ - -void mxr_vsync_set_update(struct mxr_device *mdev, int en); -void mxr_reg_reset(struct mxr_device *mdev); -irqreturn_t mxr_irq_handler(int irq, void *dev_data); -void mxr_reg_s_output(struct mxr_device *mdev, int cookie); -void mxr_reg_streamon(struct mxr_device *mdev); -void mxr_reg_streamoff(struct mxr_device *mdev); -int mxr_reg_wait4vsync(struct mxr_device *mdev); -void mxr_reg_set_mbus_fmt(struct mxr_device *mdev, - struct v4l2_mbus_framefmt *fmt); -void mxr_reg_graph_layer_stream(struct mxr_device *mdev, int idx, int en); -void mxr_reg_graph_buffer(struct mxr_device *mdev, int idx, dma_addr_t addr); -void mxr_reg_graph_format(struct mxr_device *mdev, int idx, - const struct mxr_format *fmt, const struct mxr_geometry *geo); - -void mxr_reg_vp_layer_stream(struct mxr_device *mdev, int en); -void mxr_reg_vp_buffer(struct mxr_device *mdev, - dma_addr_t luma_addr[2], dma_addr_t chroma_addr[2]); -void mxr_reg_vp_format(struct mxr_device *mdev, - const struct mxr_format *fmt, const struct mxr_geometry *geo); -void mxr_reg_dump(struct mxr_device *mdev); - -#endif /* SAMSUNG_MIXER_H */ - diff --git a/drivers/media/platform/s5p-tv/mixer_drv.c b/drivers/media/platform/s5p-tv/mixer_drv.c deleted file mode 100644 index 8a5d19469ddc..000000000000 --- a/drivers/media/platform/s5p-tv/mixer_drv.c +++ /dev/null @@ -1,527 +0,0 @@ -/* - * Samsung TV Mixer driver - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * - * Tomasz Stanislawski, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundiation. either version 2 of the License, - * or (at your option) any later version - */ - -#include "mixer.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -MODULE_AUTHOR("Tomasz Stanislawski, "); -MODULE_DESCRIPTION("Samsung MIXER"); -MODULE_LICENSE("GPL"); - -/* --------- DRIVER PARAMETERS ---------- */ - -static struct mxr_output_conf mxr_output_conf[] = { - { - .output_name = "S5P HDMI connector", - .module_name = "s5p-hdmi", - .cookie = 1, - }, - { - .output_name = "S5P SDO connector", - .module_name = "s5p-sdo", - .cookie = 0, - }, -}; - -void mxr_get_mbus_fmt(struct mxr_device *mdev, - struct v4l2_mbus_framefmt *mbus_fmt) -{ - struct v4l2_subdev *sd; - struct v4l2_subdev_format fmt = { - .which = V4L2_SUBDEV_FORMAT_ACTIVE, - }; - int ret; - - mutex_lock(&mdev->mutex); - sd = to_outsd(mdev); - ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt); - *mbus_fmt = fmt.format; - WARN(ret, "failed to get mbus_fmt for output %s\n", sd->name); - mutex_unlock(&mdev->mutex); -} - -void mxr_streamer_get(struct mxr_device *mdev) -{ - mutex_lock(&mdev->mutex); - ++mdev->n_streamer; - mxr_dbg(mdev, "%s(%d)\n", __func__, mdev->n_streamer); - if (mdev->n_streamer == 1) { - struct v4l2_subdev *sd = to_outsd(mdev); - struct v4l2_subdev_format fmt = { - .which = V4L2_SUBDEV_FORMAT_ACTIVE, - }; - struct v4l2_mbus_framefmt *mbus_fmt = &fmt.format; - struct mxr_resources *res = &mdev->res; - int ret; - - if (to_output(mdev)->cookie == 0) - clk_set_parent(res->sclk_mixer, res->sclk_dac); - else - clk_set_parent(res->sclk_mixer, res->sclk_hdmi); - mxr_reg_s_output(mdev, to_output(mdev)->cookie); - - ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt); - WARN(ret, "failed to get mbus_fmt for output %s\n", sd->name); - ret = v4l2_subdev_call(sd, video, s_stream, 1); - WARN(ret, "starting stream failed for output %s\n", sd->name); - - mxr_reg_set_mbus_fmt(mdev, mbus_fmt); - mxr_reg_streamon(mdev); - ret = mxr_reg_wait4vsync(mdev); - WARN(ret, "failed to get vsync (%d) from output\n", ret); - } - mutex_unlock(&mdev->mutex); - mxr_reg_dump(mdev); - /* FIXME: what to do when streaming fails? */ -} - -void mxr_streamer_put(struct mxr_device *mdev) -{ - mutex_lock(&mdev->mutex); - --mdev->n_streamer; - mxr_dbg(mdev, "%s(%d)\n", __func__, mdev->n_streamer); - if (mdev->n_streamer == 0) { - int ret; - struct v4l2_subdev *sd = to_outsd(mdev); - - mxr_reg_streamoff(mdev); - /* vsync applies Mixer setup */ - ret = mxr_reg_wait4vsync(mdev); - WARN(ret, "failed to get vsync (%d) from output\n", ret); - ret = v4l2_subdev_call(sd, video, s_stream, 0); - WARN(ret, "stopping stream failed for output %s\n", sd->name); - } - WARN(mdev->n_streamer < 0, "negative number of streamers (%d)\n", - mdev->n_streamer); - mutex_unlock(&mdev->mutex); - mxr_reg_dump(mdev); -} - -void mxr_output_get(struct mxr_device *mdev) -{ - mutex_lock(&mdev->mutex); - ++mdev->n_output; - mxr_dbg(mdev, "%s(%d)\n", __func__, mdev->n_output); - /* turn on auxiliary driver */ - if (mdev->n_output == 1) - v4l2_subdev_call(to_outsd(mdev), core, s_power, 1); - mutex_unlock(&mdev->mutex); -} - -void mxr_output_put(struct mxr_device *mdev) -{ - mutex_lock(&mdev->mutex); - --mdev->n_output; - mxr_dbg(mdev, "%s(%d)\n", __func__, mdev->n_output); - /* turn on auxiliary driver */ - if (mdev->n_output == 0) - v4l2_subdev_call(to_outsd(mdev), core, s_power, 0); - WARN(mdev->n_output < 0, "negative number of output users (%d)\n", - mdev->n_output); - mutex_unlock(&mdev->mutex); -} - -int mxr_power_get(struct mxr_device *mdev) -{ - int ret = pm_runtime_get_sync(mdev->dev); - - /* returning 1 means that power is already enabled, - * so zero success be returned */ - if (ret < 0) - return ret; - return 0; -} - -void mxr_power_put(struct mxr_device *mdev) -{ - pm_runtime_put_sync(mdev->dev); -} - -/* --------- RESOURCE MANAGEMENT -------------*/ - -static int mxr_acquire_plat_resources(struct mxr_device *mdev, - struct platform_device *pdev) -{ - struct resource *res; - int ret; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mxr"); - if (res == NULL) { - mxr_err(mdev, "get memory resource failed.\n"); - ret = -ENXIO; - goto fail; - } - - mdev->res.mxr_regs = ioremap(res->start, resource_size(res)); - if (mdev->res.mxr_regs == NULL) { - mxr_err(mdev, "register mapping failed.\n"); - ret = -ENXIO; - goto fail; - } - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vp"); - if (res == NULL) { - mxr_err(mdev, "get memory resource failed.\n"); - ret = -ENXIO; - goto fail_mxr_regs; - } - - mdev->res.vp_regs = ioremap(res->start, resource_size(res)); - if (mdev->res.vp_regs == NULL) { - mxr_err(mdev, "register mapping failed.\n"); - ret = -ENXIO; - goto fail_mxr_regs; - } - - res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq"); - if (res == NULL) { - mxr_err(mdev, "get interrupt resource failed.\n"); - ret = -ENXIO; - goto fail_vp_regs; - } - - ret = request_irq(res->start, mxr_irq_handler, 0, "s5p-mixer", mdev); - if (ret) { - mxr_err(mdev, "request interrupt failed.\n"); - goto fail_vp_regs; - } - mdev->res.irq = res->start; - - return 0; - -fail_vp_regs: - iounmap(mdev->res.vp_regs); - -fail_mxr_regs: - iounmap(mdev->res.mxr_regs); - -fail: - return ret; -} - -static void mxr_resource_clear_clocks(struct mxr_resources *res) -{ - res->mixer = ERR_PTR(-EINVAL); - res->vp = ERR_PTR(-EINVAL); - res->sclk_mixer = ERR_PTR(-EINVAL); - res->sclk_hdmi = ERR_PTR(-EINVAL); - res->sclk_dac = ERR_PTR(-EINVAL); -} - -static void mxr_release_plat_resources(struct mxr_device *mdev) -{ - free_irq(mdev->res.irq, mdev); - iounmap(mdev->res.vp_regs); - iounmap(mdev->res.mxr_regs); -} - -static void mxr_release_clocks(struct mxr_device *mdev) -{ - struct mxr_resources *res = &mdev->res; - - if (!IS_ERR(res->sclk_dac)) - clk_put(res->sclk_dac); - if (!IS_ERR(res->sclk_hdmi)) - clk_put(res->sclk_hdmi); - if (!IS_ERR(res->sclk_mixer)) - clk_put(res->sclk_mixer); - if (!IS_ERR(res->vp)) - clk_put(res->vp); - if (!IS_ERR(res->mixer)) - clk_put(res->mixer); -} - -static int mxr_acquire_clocks(struct mxr_device *mdev) -{ - struct mxr_resources *res = &mdev->res; - struct device *dev = mdev->dev; - - mxr_resource_clear_clocks(res); - - res->mixer = clk_get(dev, "mixer"); - if (IS_ERR(res->mixer)) { - mxr_err(mdev, "failed to get clock 'mixer'\n"); - goto fail; - } - res->vp = clk_get(dev, "vp"); - if (IS_ERR(res->vp)) { - mxr_err(mdev, "failed to get clock 'vp'\n"); - goto fail; - } - res->sclk_mixer = clk_get(dev, "sclk_mixer"); - if (IS_ERR(res->sclk_mixer)) { - mxr_err(mdev, "failed to get clock 'sclk_mixer'\n"); - goto fail; - } - res->sclk_hdmi = clk_get(dev, "sclk_hdmi"); - if (IS_ERR(res->sclk_hdmi)) { - mxr_err(mdev, "failed to get clock 'sclk_hdmi'\n"); - goto fail; - } - res->sclk_dac = clk_get(dev, "sclk_dac"); - if (IS_ERR(res->sclk_dac)) { - mxr_err(mdev, "failed to get clock 'sclk_dac'\n"); - goto fail; - } - - return 0; -fail: - mxr_release_clocks(mdev); - return -ENODEV; -} - -static int mxr_acquire_resources(struct mxr_device *mdev, - struct platform_device *pdev) -{ - int ret; - ret = mxr_acquire_plat_resources(mdev, pdev); - - if (ret) - goto fail; - - ret = mxr_acquire_clocks(mdev); - if (ret) - goto fail_plat; - - mxr_info(mdev, "resources acquired\n"); - return 0; - -fail_plat: - mxr_release_plat_resources(mdev); -fail: - mxr_err(mdev, "resources acquire failed\n"); - return ret; -} - -static void mxr_release_resources(struct mxr_device *mdev) -{ - mxr_release_clocks(mdev); - mxr_release_plat_resources(mdev); - memset(&mdev->res, 0, sizeof(mdev->res)); - mxr_resource_clear_clocks(&mdev->res); -} - -static void mxr_release_layers(struct mxr_device *mdev) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mdev->layer); ++i) - if (mdev->layer[i]) - mxr_layer_release(mdev->layer[i]); -} - -static int mxr_acquire_layers(struct mxr_device *mdev, - struct mxr_platform_data *pdata) -{ - mdev->layer[0] = mxr_graph_layer_create(mdev, 0); - mdev->layer[1] = mxr_graph_layer_create(mdev, 1); - mdev->layer[2] = mxr_vp_layer_create(mdev, 0); - - if (!mdev->layer[0] || !mdev->layer[1] || !mdev->layer[2]) { - mxr_err(mdev, "failed to acquire layers\n"); - goto fail; - } - - return 0; - -fail: - mxr_release_layers(mdev); - return -ENODEV; -} - -/* ---------- POWER MANAGEMENT ----------- */ - -static int mxr_runtime_resume(struct device *dev) -{ - struct mxr_device *mdev = to_mdev(dev); - struct mxr_resources *res = &mdev->res; - int ret; - - mxr_dbg(mdev, "resume - start\n"); - mutex_lock(&mdev->mutex); - /* turn clocks on */ - ret = clk_prepare_enable(res->mixer); - if (ret < 0) { - dev_err(mdev->dev, "clk_prepare_enable(mixer) failed\n"); - goto fail; - } - ret = clk_prepare_enable(res->vp); - if (ret < 0) { - dev_err(mdev->dev, "clk_prepare_enable(vp) failed\n"); - goto fail_mixer; - } - ret = clk_prepare_enable(res->sclk_mixer); - if (ret < 0) { - dev_err(mdev->dev, "clk_prepare_enable(sclk_mixer) failed\n"); - goto fail_vp; - } - /* apply default configuration */ - mxr_reg_reset(mdev); - mxr_dbg(mdev, "resume - finished\n"); - - mutex_unlock(&mdev->mutex); - return 0; - -fail_vp: - clk_disable_unprepare(res->vp); -fail_mixer: - clk_disable_unprepare(res->mixer); -fail: - mutex_unlock(&mdev->mutex); - dev_err(mdev->dev, "resume failed\n"); - return ret; -} - -static int mxr_runtime_suspend(struct device *dev) -{ - struct mxr_device *mdev = to_mdev(dev); - struct mxr_resources *res = &mdev->res; - mxr_dbg(mdev, "suspend - start\n"); - mutex_lock(&mdev->mutex); - /* turn clocks off */ - clk_disable_unprepare(res->sclk_mixer); - clk_disable_unprepare(res->vp); - clk_disable_unprepare(res->mixer); - mutex_unlock(&mdev->mutex); - mxr_dbg(mdev, "suspend - finished\n"); - return 0; -} - -static const struct dev_pm_ops mxr_pm_ops = { - .runtime_suspend = mxr_runtime_suspend, - .runtime_resume = mxr_runtime_resume, -}; - -/* --------- DRIVER INITIALIZATION ---------- */ - -static int mxr_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct mxr_platform_data *pdata = dev->platform_data; - struct mxr_device *mdev; - int ret; - - /* mdev does not exist yet so no mxr_dbg is used */ - dev_info(dev, "probe start\n"); - - mdev = kzalloc(sizeof(*mdev), GFP_KERNEL); - if (!mdev) { - dev_err(dev, "not enough memory.\n"); - ret = -ENOMEM; - goto fail; - } - - /* setup pointer to master device */ - mdev->dev = dev; - - mutex_init(&mdev->mutex); - spin_lock_init(&mdev->reg_slock); - init_waitqueue_head(&mdev->event_queue); - - /* acquire resources: regs, irqs, clocks, regulators */ - ret = mxr_acquire_resources(mdev, pdev); - if (ret) - goto fail_mem; - - /* configure resources for video output */ - ret = mxr_acquire_video(mdev, mxr_output_conf, - ARRAY_SIZE(mxr_output_conf)); - if (ret) - goto fail_resources; - - /* configure layers */ - ret = mxr_acquire_layers(mdev, pdata); - if (ret) - goto fail_video; - - pm_runtime_enable(dev); - - mxr_info(mdev, "probe successful\n"); - return 0; - -fail_video: - mxr_release_video(mdev); - -fail_resources: - mxr_release_resources(mdev); - -fail_mem: - kfree(mdev); - -fail: - dev_info(dev, "probe failed\n"); - return ret; -} - -static int mxr_remove(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct mxr_device *mdev = to_mdev(dev); - - pm_runtime_disable(dev); - - mxr_release_layers(mdev); - mxr_release_video(mdev); - mxr_release_resources(mdev); - - kfree(mdev); - - dev_info(dev, "remove successful\n"); - return 0; -} - -static struct platform_driver mxr_driver __refdata = { - .probe = mxr_probe, - .remove = mxr_remove, - .driver = { - .name = MXR_DRIVER_NAME, - .pm = &mxr_pm_ops, - } -}; - -static int __init mxr_init(void) -{ - int i, ret; - static const char banner[] __initconst = - "Samsung TV Mixer driver, " - "(c) 2010-2011 Samsung Electronics Co., Ltd.\n"; - pr_info("%s\n", banner); - - /* Loading auxiliary modules */ - for (i = 0; i < ARRAY_SIZE(mxr_output_conf); ++i) - request_module(mxr_output_conf[i].module_name); - - ret = platform_driver_register(&mxr_driver); - if (ret != 0) { - pr_err("s5p-tv: registration of MIXER driver failed\n"); - return -ENXIO; - } - - return 0; -} -module_init(mxr_init); - -static void __exit mxr_exit(void) -{ - platform_driver_unregister(&mxr_driver); -} -module_exit(mxr_exit); diff --git a/drivers/media/platform/s5p-tv/mixer_grp_layer.c b/drivers/media/platform/s5p-tv/mixer_grp_layer.c deleted file mode 100644 index d4d2564f7de7..000000000000 --- a/drivers/media/platform/s5p-tv/mixer_grp_layer.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Samsung TV Mixer driver - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * - * Tomasz Stanislawski, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundiation. either version 2 of the License, - * or (at your option) any later version - */ - -#include "mixer.h" - -#include - -/* FORMAT DEFINITIONS */ - -static const struct mxr_format mxr_fb_fmt_rgb565 = { - .name = "RGB565", - .fourcc = V4L2_PIX_FMT_RGB565, - .colorspace = V4L2_COLORSPACE_SRGB, - .num_planes = 1, - .plane = { - { .width = 1, .height = 1, .size = 2 }, - }, - .num_subframes = 1, - .cookie = 4, -}; - -static const struct mxr_format mxr_fb_fmt_argb1555 = { - .name = "ARGB1555", - .num_planes = 1, - .fourcc = V4L2_PIX_FMT_RGB555, - .colorspace = V4L2_COLORSPACE_SRGB, - .plane = { - { .width = 1, .height = 1, .size = 2 }, - }, - .num_subframes = 1, - .cookie = 5, -}; - -static const struct mxr_format mxr_fb_fmt_argb4444 = { - .name = "ARGB4444", - .num_planes = 1, - .fourcc = V4L2_PIX_FMT_RGB444, - .colorspace = V4L2_COLORSPACE_SRGB, - .plane = { - { .width = 1, .height = 1, .size = 2 }, - }, - .num_subframes = 1, - .cookie = 6, -}; - -static const struct mxr_format mxr_fb_fmt_argb8888 = { - .name = "ARGB8888", - .fourcc = V4L2_PIX_FMT_BGR32, - .colorspace = V4L2_COLORSPACE_SRGB, - .num_planes = 1, - .plane = { - { .width = 1, .height = 1, .size = 4 }, - }, - .num_subframes = 1, - .cookie = 7, -}; - -static const struct mxr_format *mxr_graph_format[] = { - &mxr_fb_fmt_rgb565, - &mxr_fb_fmt_argb1555, - &mxr_fb_fmt_argb4444, - &mxr_fb_fmt_argb8888, -}; - -/* AUXILIARY CALLBACKS */ - -static void mxr_graph_layer_release(struct mxr_layer *layer) -{ - mxr_base_layer_unregister(layer); - mxr_base_layer_release(layer); -} - -static void mxr_graph_buffer_set(struct mxr_layer *layer, - struct mxr_buffer *buf) -{ - dma_addr_t addr = 0; - - if (buf) - addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); - mxr_reg_graph_buffer(layer->mdev, layer->idx, addr); -} - -static void mxr_graph_stream_set(struct mxr_layer *layer, int en) -{ - mxr_reg_graph_layer_stream(layer->mdev, layer->idx, en); -} - -static void mxr_graph_format_set(struct mxr_layer *layer) -{ - mxr_reg_graph_format(layer->mdev, layer->idx, - layer->fmt, &layer->geo); -} - -static inline unsigned int closest(unsigned int x, unsigned int a, - unsigned int b, unsigned long flags) -{ - unsigned int mid = (a + b) / 2; - - /* choosing closest value with constraints according to table: - * -------------+-----+-----+-----+-------+ - * flags | 0 | LE | GE | LE|GE | - * -------------+-----+-----+-----+-------+ - * x <= a | a | a | a | a | - * a < x <= mid | a | a | b | a | - * mid < x < b | b | a | b | b | - * b <= x | b | b | b | b | - * -------------+-----+-----+-----+-------+ - */ - - /* remove all non-constraint flags */ - flags &= V4L2_SEL_FLAG_LE | V4L2_SEL_FLAG_GE; - - if (x <= a) - return a; - if (x >= b) - return b; - if (flags == V4L2_SEL_FLAG_LE) - return a; - if (flags == V4L2_SEL_FLAG_GE) - return b; - if (x <= mid) - return a; - return b; -} - -static inline unsigned int do_center(unsigned int center, - unsigned int size, unsigned int upper, unsigned int flags) -{ - unsigned int lower; - - if (flags & MXR_NO_OFFSET) - return 0; - - lower = center - min(center, size / 2); - return min(lower, upper - size); -} - -static void mxr_graph_fix_geometry(struct mxr_layer *layer, - enum mxr_geometry_stage stage, unsigned long flags) -{ - struct mxr_geometry *geo = &layer->geo; - struct mxr_crop *src = &geo->src; - struct mxr_crop *dst = &geo->dst; - unsigned int x_center, y_center; - - switch (stage) { - - case MXR_GEOMETRY_SINK: /* nothing to be fixed here */ - flags = 0; - /* fall through */ - - case MXR_GEOMETRY_COMPOSE: - /* remember center of the area */ - x_center = dst->x_offset + dst->width / 2; - y_center = dst->y_offset + dst->height / 2; - /* round up/down to 2 multiple depending on flags */ - if (flags & V4L2_SEL_FLAG_LE) { - dst->width = round_down(dst->width, 2); - dst->height = round_down(dst->height, 2); - } else { - dst->width = round_up(dst->width, 2); - dst->height = round_up(dst->height, 2); - } - /* assure that compose rect is inside display area */ - dst->width = min(dst->width, dst->full_width); - dst->height = min(dst->height, dst->full_height); - - /* ensure that compose is reachable using 2x scaling */ - dst->width = min(dst->width, 2 * src->full_width); - dst->height = min(dst->height, 2 * src->full_height); - - /* setup offsets */ - dst->x_offset = do_center(x_center, dst->width, - dst->full_width, flags); - dst->y_offset = do_center(y_center, dst->height, - dst->full_height, flags); - flags = 0; - /* fall through */ - - case MXR_GEOMETRY_CROP: - /* remember center of the area */ - x_center = src->x_offset + src->width / 2; - y_center = src->y_offset + src->height / 2; - /* ensure that cropping area lies inside the buffer */ - if (src->full_width < dst->width) - src->width = dst->width / 2; - else - src->width = closest(src->width, dst->width / 2, - dst->width, flags); - - if (src->width == dst->width) - geo->x_ratio = 0; - else - geo->x_ratio = 1; - - if (src->full_height < dst->height) - src->height = dst->height / 2; - else - src->height = closest(src->height, dst->height / 2, - dst->height, flags); - - if (src->height == dst->height) - geo->y_ratio = 0; - else - geo->y_ratio = 1; - - /* setup offsets */ - src->x_offset = do_center(x_center, src->width, - src->full_width, flags); - src->y_offset = do_center(y_center, src->height, - src->full_height, flags); - flags = 0; - /* fall through */ - case MXR_GEOMETRY_SOURCE: - src->full_width = clamp_val(src->full_width, - src->width + src->x_offset, 32767); - src->full_height = clamp_val(src->full_height, - src->height + src->y_offset, 2047); - } -} - -/* PUBLIC API */ - -struct mxr_layer *mxr_graph_layer_create(struct mxr_device *mdev, int idx) -{ - struct mxr_layer *layer; - int ret; - const struct mxr_layer_ops ops = { - .release = mxr_graph_layer_release, - .buffer_set = mxr_graph_buffer_set, - .stream_set = mxr_graph_stream_set, - .format_set = mxr_graph_format_set, - .fix_geometry = mxr_graph_fix_geometry, - }; - char name[32]; - - sprintf(name, "graph%d", idx); - - layer = mxr_base_layer_create(mdev, idx, name, &ops); - if (layer == NULL) { - mxr_err(mdev, "failed to initialize layer(%d) base\n", idx); - goto fail; - } - - layer->fmt_array = mxr_graph_format; - layer->fmt_array_size = ARRAY_SIZE(mxr_graph_format); - - ret = mxr_base_layer_register(layer); - if (ret) - goto fail_layer; - - return layer; - -fail_layer: - mxr_base_layer_release(layer); - -fail: - return NULL; -} - diff --git a/drivers/media/platform/s5p-tv/mixer_reg.c b/drivers/media/platform/s5p-tv/mixer_reg.c deleted file mode 100644 index a0ec14a1da13..000000000000 --- a/drivers/media/platform/s5p-tv/mixer_reg.c +++ /dev/null @@ -1,551 +0,0 @@ -/* - * Samsung TV Mixer driver - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * - * Tomasz Stanislawski, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundiation. either version 2 of the License, - * or (at your option) any later version - */ - -#include "mixer.h" -#include "regs-mixer.h" -#include "regs-vp.h" - -#include - -/* Register access subroutines */ - -static inline u32 vp_read(struct mxr_device *mdev, u32 reg_id) -{ - return readl(mdev->res.vp_regs + reg_id); -} - -static inline void vp_write(struct mxr_device *mdev, u32 reg_id, u32 val) -{ - writel(val, mdev->res.vp_regs + reg_id); -} - -static inline void vp_write_mask(struct mxr_device *mdev, u32 reg_id, - u32 val, u32 mask) -{ - u32 old = vp_read(mdev, reg_id); - - val = (val & mask) | (old & ~mask); - writel(val, mdev->res.vp_regs + reg_id); -} - -static inline u32 mxr_read(struct mxr_device *mdev, u32 reg_id) -{ - return readl(mdev->res.mxr_regs + reg_id); -} - -static inline void mxr_write(struct mxr_device *mdev, u32 reg_id, u32 val) -{ - writel(val, mdev->res.mxr_regs + reg_id); -} - -static inline void mxr_write_mask(struct mxr_device *mdev, u32 reg_id, - u32 val, u32 mask) -{ - u32 old = mxr_read(mdev, reg_id); - - val = (val & mask) | (old & ~mask); - writel(val, mdev->res.mxr_regs + reg_id); -} - -void mxr_vsync_set_update(struct mxr_device *mdev, int en) -{ - /* block update on vsync */ - mxr_write_mask(mdev, MXR_STATUS, en ? MXR_STATUS_SYNC_ENABLE : 0, - MXR_STATUS_SYNC_ENABLE); - vp_write(mdev, VP_SHADOW_UPDATE, en ? VP_SHADOW_UPDATE_ENABLE : 0); -} - -static void __mxr_reg_vp_reset(struct mxr_device *mdev) -{ - int tries = 100; - - vp_write(mdev, VP_SRESET, VP_SRESET_PROCESSING); - for (tries = 100; tries; --tries) { - /* waiting until VP_SRESET_PROCESSING is 0 */ - if (~vp_read(mdev, VP_SRESET) & VP_SRESET_PROCESSING) - break; - mdelay(10); - } - WARN(tries == 0, "failed to reset Video Processor\n"); -} - -static void mxr_reg_vp_default_filter(struct mxr_device *mdev); - -void mxr_reg_reset(struct mxr_device *mdev) -{ - unsigned long flags; - u32 val; /* value stored to register */ - - spin_lock_irqsave(&mdev->reg_slock, flags); - mxr_vsync_set_update(mdev, MXR_DISABLE); - - /* set output in RGB888 mode */ - mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888); - - /* 16 beat burst in DMA */ - mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST, - MXR_STATUS_BURST_MASK); - - /* setting default layer priority: layer1 > video > layer0 - * because typical usage scenario would be - * layer0 - framebuffer - * video - video overlay - * layer1 - OSD - */ - val = MXR_LAYER_CFG_GRP0_VAL(1); - val |= MXR_LAYER_CFG_VP_VAL(2); - val |= MXR_LAYER_CFG_GRP1_VAL(3); - mxr_write(mdev, MXR_LAYER_CFG, val); - - /* use dark gray background color */ - mxr_write(mdev, MXR_BG_COLOR0, 0x808080); - mxr_write(mdev, MXR_BG_COLOR1, 0x808080); - mxr_write(mdev, MXR_BG_COLOR2, 0x808080); - - /* setting graphical layers */ - - val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */ - val |= MXR_GRP_CFG_BLEND_PRE_MUL; /* premul mode */ - val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */ - - /* the same configuration for both layers */ - mxr_write(mdev, MXR_GRAPHIC_CFG(0), val); - mxr_write(mdev, MXR_GRAPHIC_CFG(1), val); - - /* configuration of Video Processor Registers */ - __mxr_reg_vp_reset(mdev); - mxr_reg_vp_default_filter(mdev); - - /* enable all interrupts */ - mxr_write_mask(mdev, MXR_INT_EN, ~0, MXR_INT_EN_ALL); - - mxr_vsync_set_update(mdev, MXR_ENABLE); - spin_unlock_irqrestore(&mdev->reg_slock, flags); -} - -void mxr_reg_graph_format(struct mxr_device *mdev, int idx, - const struct mxr_format *fmt, const struct mxr_geometry *geo) -{ - u32 val; - unsigned long flags; - - spin_lock_irqsave(&mdev->reg_slock, flags); - mxr_vsync_set_update(mdev, MXR_DISABLE); - - /* setup format */ - mxr_write_mask(mdev, MXR_GRAPHIC_CFG(idx), - MXR_GRP_CFG_FORMAT_VAL(fmt->cookie), MXR_GRP_CFG_FORMAT_MASK); - - /* setup geometry */ - mxr_write(mdev, MXR_GRAPHIC_SPAN(idx), geo->src.full_width); - val = MXR_GRP_WH_WIDTH(geo->src.width); - val |= MXR_GRP_WH_HEIGHT(geo->src.height); - val |= MXR_GRP_WH_H_SCALE(geo->x_ratio); - val |= MXR_GRP_WH_V_SCALE(geo->y_ratio); - mxr_write(mdev, MXR_GRAPHIC_WH(idx), val); - - /* setup offsets in source image */ - val = MXR_GRP_SXY_SX(geo->src.x_offset); - val |= MXR_GRP_SXY_SY(geo->src.y_offset); - mxr_write(mdev, MXR_GRAPHIC_SXY(idx), val); - - /* setup offsets in display image */ - val = MXR_GRP_DXY_DX(geo->dst.x_offset); - val |= MXR_GRP_DXY_DY(geo->dst.y_offset); - mxr_write(mdev, MXR_GRAPHIC_DXY(idx), val); - - mxr_vsync_set_update(mdev, MXR_ENABLE); - spin_unlock_irqrestore(&mdev->reg_slock, flags); -} - -void mxr_reg_vp_format(struct mxr_device *mdev, - const struct mxr_format *fmt, const struct mxr_geometry *geo) -{ - unsigned long flags; - - spin_lock_irqsave(&mdev->reg_slock, flags); - mxr_vsync_set_update(mdev, MXR_DISABLE); - - vp_write_mask(mdev, VP_MODE, fmt->cookie, VP_MODE_FMT_MASK); - - /* setting size of input image */ - vp_write(mdev, VP_IMG_SIZE_Y, VP_IMG_HSIZE(geo->src.full_width) | - VP_IMG_VSIZE(geo->src.full_height)); - /* chroma height has to reduced by 2 to avoid chroma distorions */ - vp_write(mdev, VP_IMG_SIZE_C, VP_IMG_HSIZE(geo->src.full_width) | - VP_IMG_VSIZE(geo->src.full_height / 2)); - - vp_write(mdev, VP_SRC_WIDTH, geo->src.width); - vp_write(mdev, VP_SRC_HEIGHT, geo->src.height); - vp_write(mdev, VP_SRC_H_POSITION, - VP_SRC_H_POSITION_VAL(geo->src.x_offset)); - vp_write(mdev, VP_SRC_V_POSITION, geo->src.y_offset); - - vp_write(mdev, VP_DST_WIDTH, geo->dst.width); - vp_write(mdev, VP_DST_H_POSITION, geo->dst.x_offset); - if (geo->dst.field == V4L2_FIELD_INTERLACED) { - vp_write(mdev, VP_DST_HEIGHT, geo->dst.height / 2); - vp_write(mdev, VP_DST_V_POSITION, geo->dst.y_offset / 2); - } else { - vp_write(mdev, VP_DST_HEIGHT, geo->dst.height); - vp_write(mdev, VP_DST_V_POSITION, geo->dst.y_offset); - } - - vp_write(mdev, VP_H_RATIO, geo->x_ratio); - vp_write(mdev, VP_V_RATIO, geo->y_ratio); - - vp_write(mdev, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE); - - mxr_vsync_set_update(mdev, MXR_ENABLE); - spin_unlock_irqrestore(&mdev->reg_slock, flags); - -} - -void mxr_reg_graph_buffer(struct mxr_device *mdev, int idx, dma_addr_t addr) -{ - u32 val = addr ? ~0 : 0; - unsigned long flags; - - spin_lock_irqsave(&mdev->reg_slock, flags); - mxr_vsync_set_update(mdev, MXR_DISABLE); - - if (idx == 0) - mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); - else - mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); - mxr_write(mdev, MXR_GRAPHIC_BASE(idx), addr); - - mxr_vsync_set_update(mdev, MXR_ENABLE); - spin_unlock_irqrestore(&mdev->reg_slock, flags); -} - -void mxr_reg_vp_buffer(struct mxr_device *mdev, - dma_addr_t luma_addr[2], dma_addr_t chroma_addr[2]) -{ - u32 val = luma_addr[0] ? ~0 : 0; - unsigned long flags; - - spin_lock_irqsave(&mdev->reg_slock, flags); - mxr_vsync_set_update(mdev, MXR_DISABLE); - - mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_VP_ENABLE); - vp_write_mask(mdev, VP_ENABLE, val, VP_ENABLE_ON); - /* TODO: fix tiled mode */ - vp_write(mdev, VP_TOP_Y_PTR, luma_addr[0]); - vp_write(mdev, VP_TOP_C_PTR, chroma_addr[0]); - vp_write(mdev, VP_BOT_Y_PTR, luma_addr[1]); - vp_write(mdev, VP_BOT_C_PTR, chroma_addr[1]); - - mxr_vsync_set_update(mdev, MXR_ENABLE); - spin_unlock_irqrestore(&mdev->reg_slock, flags); -} - -static void mxr_irq_layer_handle(struct mxr_layer *layer) -{ - struct list_head *head = &layer->enq_list; - struct mxr_buffer *done; - - /* skip non-existing layer */ - if (layer == NULL) - return; - - spin_lock(&layer->enq_slock); - if (layer->state == MXR_LAYER_IDLE) - goto done; - - done = layer->shadow_buf; - layer->shadow_buf = layer->update_buf; - - if (list_empty(head)) { - if (layer->state != MXR_LAYER_STREAMING) - layer->update_buf = NULL; - } else { - struct mxr_buffer *next; - next = list_first_entry(head, struct mxr_buffer, list); - list_del(&next->list); - layer->update_buf = next; - } - - layer->ops.buffer_set(layer, layer->update_buf); - - if (done && done != layer->shadow_buf) - vb2_buffer_done(&done->vb.vb2_buf, VB2_BUF_STATE_DONE); - -done: - spin_unlock(&layer->enq_slock); -} - -irqreturn_t mxr_irq_handler(int irq, void *dev_data) -{ - struct mxr_device *mdev = dev_data; - u32 i, val; - - spin_lock(&mdev->reg_slock); - val = mxr_read(mdev, MXR_INT_STATUS); - - /* wake up process waiting for VSYNC */ - if (val & MXR_INT_STATUS_VSYNC) { - set_bit(MXR_EVENT_VSYNC, &mdev->event_flags); - /* toggle TOP field event if working in interlaced mode */ - if (~mxr_read(mdev, MXR_CFG) & MXR_CFG_SCAN_PROGRASSIVE) - change_bit(MXR_EVENT_TOP, &mdev->event_flags); - wake_up(&mdev->event_queue); - /* vsync interrupt use different bit for read and clear */ - val &= ~MXR_INT_STATUS_VSYNC; - val |= MXR_INT_CLEAR_VSYNC; - } - - /* clear interrupts */ - mxr_write(mdev, MXR_INT_STATUS, val); - - spin_unlock(&mdev->reg_slock); - /* leave on non-vsync event */ - if (~val & MXR_INT_CLEAR_VSYNC) - return IRQ_HANDLED; - /* skip layer update on bottom field */ - if (!test_bit(MXR_EVENT_TOP, &mdev->event_flags)) - return IRQ_HANDLED; - for (i = 0; i < MXR_MAX_LAYERS; ++i) - mxr_irq_layer_handle(mdev->layer[i]); - return IRQ_HANDLED; -} - -void mxr_reg_s_output(struct mxr_device *mdev, int cookie) -{ - u32 val; - - val = cookie == 0 ? MXR_CFG_DST_SDO : MXR_CFG_DST_HDMI; - mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_DST_MASK); -} - -void mxr_reg_streamon(struct mxr_device *mdev) -{ - unsigned long flags; - - spin_lock_irqsave(&mdev->reg_slock, flags); - /* single write -> no need to block vsync update */ - - /* start MIXER */ - mxr_write_mask(mdev, MXR_STATUS, ~0, MXR_STATUS_REG_RUN); - set_bit(MXR_EVENT_TOP, &mdev->event_flags); - - spin_unlock_irqrestore(&mdev->reg_slock, flags); -} - -void mxr_reg_streamoff(struct mxr_device *mdev) -{ - unsigned long flags; - - spin_lock_irqsave(&mdev->reg_slock, flags); - /* single write -> no need to block vsync update */ - - /* stop MIXER */ - mxr_write_mask(mdev, MXR_STATUS, 0, MXR_STATUS_REG_RUN); - - spin_unlock_irqrestore(&mdev->reg_slock, flags); -} - -int mxr_reg_wait4vsync(struct mxr_device *mdev) -{ - long time_left; - - clear_bit(MXR_EVENT_VSYNC, &mdev->event_flags); - /* TODO: consider adding interruptible */ - time_left = wait_event_timeout(mdev->event_queue, - test_bit(MXR_EVENT_VSYNC, &mdev->event_flags), - msecs_to_jiffies(1000)); - if (time_left > 0) - return 0; - mxr_warn(mdev, "no vsync detected - timeout\n"); - return -ETIME; -} - -void mxr_reg_set_mbus_fmt(struct mxr_device *mdev, - struct v4l2_mbus_framefmt *fmt) -{ - u32 val = 0; - unsigned long flags; - - spin_lock_irqsave(&mdev->reg_slock, flags); - mxr_vsync_set_update(mdev, MXR_DISABLE); - - /* selecting colorspace accepted by output */ - if (fmt->colorspace == V4L2_COLORSPACE_JPEG) - val |= MXR_CFG_OUT_YUV444; - else - val |= MXR_CFG_OUT_RGB888; - - /* choosing between interlace and progressive mode */ - if (fmt->field == V4L2_FIELD_INTERLACED) - val |= MXR_CFG_SCAN_INTERLACE; - else - val |= MXR_CFG_SCAN_PROGRASSIVE; - - /* choosing between porper HD and SD mode */ - if (fmt->height == 480) - val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD; - else if (fmt->height == 576) - val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD; - else if (fmt->height == 720) - val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; - else if (fmt->height == 1080) - val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD; - else - WARN(1, "unrecognized mbus height %u!\n", fmt->height); - - mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK | - MXR_CFG_OUT_MASK); - - val = (fmt->field == V4L2_FIELD_INTERLACED) ? ~0 : 0; - vp_write_mask(mdev, VP_MODE, val, - VP_MODE_LINE_SKIP | VP_MODE_FIELD_ID_AUTO_TOGGLING); - - mxr_vsync_set_update(mdev, MXR_ENABLE); - spin_unlock_irqrestore(&mdev->reg_slock, flags); -} - -void mxr_reg_graph_layer_stream(struct mxr_device *mdev, int idx, int en) -{ - /* no extra actions need to be done */ -} - -void mxr_reg_vp_layer_stream(struct mxr_device *mdev, int en) -{ - /* no extra actions need to be done */ -} - -static const u8 filter_y_horiz_tap8[] = { - 0, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 0, 0, 0, - 0, 2, 4, 5, 6, 6, 6, 6, - 6, 5, 5, 4, 3, 2, 1, 1, - 0, -6, -12, -16, -18, -20, -21, -20, - -20, -18, -16, -13, -10, -8, -5, -2, - 127, 126, 125, 121, 114, 107, 99, 89, - 79, 68, 57, 46, 35, 25, 16, 8, -}; - -static const u8 filter_y_vert_tap4[] = { - 0, -3, -6, -8, -8, -8, -8, -7, - -6, -5, -4, -3, -2, -1, -1, 0, - 127, 126, 124, 118, 111, 102, 92, 81, - 70, 59, 48, 37, 27, 19, 11, 5, - 0, 5, 11, 19, 27, 37, 48, 59, - 70, 81, 92, 102, 111, 118, 124, 126, - 0, 0, -1, -1, -2, -3, -4, -5, - -6, -7, -8, -8, -8, -8, -6, -3, -}; - -static const u8 filter_cr_horiz_tap4[] = { - 0, -3, -6, -8, -8, -8, -8, -7, - -6, -5, -4, -3, -2, -1, -1, 0, - 127, 126, 124, 118, 111, 102, 92, 81, - 70, 59, 48, 37, 27, 19, 11, 5, -}; - -static inline void mxr_reg_vp_filter_set(struct mxr_device *mdev, - int reg_id, const u8 *data, unsigned int size) -{ - /* assure 4-byte align */ - BUG_ON(size & 3); - for (; size; size -= 4, reg_id += 4, data += 4) { - u32 val = (data[0] << 24) | (data[1] << 16) | - (data[2] << 8) | data[3]; - vp_write(mdev, reg_id, val); - } -} - -static void mxr_reg_vp_default_filter(struct mxr_device *mdev) -{ - mxr_reg_vp_filter_set(mdev, VP_POLY8_Y0_LL, - filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8)); - mxr_reg_vp_filter_set(mdev, VP_POLY4_Y0_LL, - filter_y_vert_tap4, sizeof(filter_y_vert_tap4)); - mxr_reg_vp_filter_set(mdev, VP_POLY4_C0_LL, - filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4)); -} - -static void mxr_reg_mxr_dump(struct mxr_device *mdev) -{ -#define DUMPREG(reg_id) \ -do { \ - mxr_dbg(mdev, #reg_id " = %08x\n", \ - (u32)readl(mdev->res.mxr_regs + reg_id)); \ -} while (0) - - DUMPREG(MXR_STATUS); - DUMPREG(MXR_CFG); - DUMPREG(MXR_INT_EN); - DUMPREG(MXR_INT_STATUS); - - DUMPREG(MXR_LAYER_CFG); - DUMPREG(MXR_VIDEO_CFG); - - DUMPREG(MXR_GRAPHIC0_CFG); - DUMPREG(MXR_GRAPHIC0_BASE); - DUMPREG(MXR_GRAPHIC0_SPAN); - DUMPREG(MXR_GRAPHIC0_WH); - DUMPREG(MXR_GRAPHIC0_SXY); - DUMPREG(MXR_GRAPHIC0_DXY); - - DUMPREG(MXR_GRAPHIC1_CFG); - DUMPREG(MXR_GRAPHIC1_BASE); - DUMPREG(MXR_GRAPHIC1_SPAN); - DUMPREG(MXR_GRAPHIC1_WH); - DUMPREG(MXR_GRAPHIC1_SXY); - DUMPREG(MXR_GRAPHIC1_DXY); -#undef DUMPREG -} - -static void mxr_reg_vp_dump(struct mxr_device *mdev) -{ -#define DUMPREG(reg_id) \ -do { \ - mxr_dbg(mdev, #reg_id " = %08x\n", \ - (u32) readl(mdev->res.vp_regs + reg_id)); \ -} while (0) - - - DUMPREG(VP_ENABLE); - DUMPREG(VP_SRESET); - DUMPREG(VP_SHADOW_UPDATE); - DUMPREG(VP_FIELD_ID); - DUMPREG(VP_MODE); - DUMPREG(VP_IMG_SIZE_Y); - DUMPREG(VP_IMG_SIZE_C); - DUMPREG(VP_PER_RATE_CTRL); - DUMPREG(VP_TOP_Y_PTR); - DUMPREG(VP_BOT_Y_PTR); - DUMPREG(VP_TOP_C_PTR); - DUMPREG(VP_BOT_C_PTR); - DUMPREG(VP_ENDIAN_MODE); - DUMPREG(VP_SRC_H_POSITION); - DUMPREG(VP_SRC_V_POSITION); - DUMPREG(VP_SRC_WIDTH); - DUMPREG(VP_SRC_HEIGHT); - DUMPREG(VP_DST_H_POSITION); - DUMPREG(VP_DST_V_POSITION); - DUMPREG(VP_DST_WIDTH); - DUMPREG(VP_DST_HEIGHT); - DUMPREG(VP_H_RATIO); - DUMPREG(VP_V_RATIO); - -#undef DUMPREG -} - -void mxr_reg_dump(struct mxr_device *mdev) -{ - mxr_reg_mxr_dump(mdev); - mxr_reg_vp_dump(mdev); -} - diff --git a/drivers/media/platform/s5p-tv/mixer_video.c b/drivers/media/platform/s5p-tv/mixer_video.c deleted file mode 100644 index ee74e2b44d69..000000000000 --- a/drivers/media/platform/s5p-tv/mixer_video.c +++ /dev/null @@ -1,1130 +0,0 @@ -/* - * Samsung TV Mixer driver - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * - * Tomasz Stanislawski, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundation. either version 2 of the License, - * or (at your option) any later version - */ - -#define pr_fmt(fmt) "s5p-tv (mixer): " fmt - -#include "mixer.h" - -#include -#include -#include -#include -#include -#include -#include - -static int find_reg_callback(struct device *dev, void *p) -{ - struct v4l2_subdev **sd = p; - - *sd = dev_get_drvdata(dev); - /* non-zero value stops iteration */ - return 1; -} - -static struct v4l2_subdev *find_and_register_subdev( - struct mxr_device *mdev, char *module_name) -{ - struct device_driver *drv; - struct v4l2_subdev *sd = NULL; - int ret; - - /* TODO: add waiting until probe is finished */ - drv = driver_find(module_name, &platform_bus_type); - if (!drv) { - mxr_warn(mdev, "module %s is missing\n", module_name); - return NULL; - } - /* driver refcnt is increased, it is safe to iterate over devices */ - ret = driver_for_each_device(drv, NULL, &sd, find_reg_callback); - /* ret == 0 means that find_reg_callback was never executed */ - if (sd == NULL) { - mxr_warn(mdev, "module %s provides no subdev!\n", module_name); - goto done; - } - /* v4l2_device_register_subdev detects if sd is NULL */ - ret = v4l2_device_register_subdev(&mdev->v4l2_dev, sd); - if (ret) { - mxr_warn(mdev, "failed to register subdev %s\n", sd->name); - sd = NULL; - } - -done: - return sd; -} - -int mxr_acquire_video(struct mxr_device *mdev, - struct mxr_output_conf *output_conf, int output_count) -{ - struct device *dev = mdev->dev; - struct v4l2_device *v4l2_dev = &mdev->v4l2_dev; - int i; - int ret = 0; - struct v4l2_subdev *sd; - - strlcpy(v4l2_dev->name, dev_name(mdev->dev), sizeof(v4l2_dev->name)); - /* prepare context for V4L2 device */ - ret = v4l2_device_register(dev, v4l2_dev); - if (ret) { - mxr_err(mdev, "could not register v4l2 device.\n"); - goto fail; - } - - vb2_dma_contig_set_max_seg_size(mdev->dev, DMA_BIT_MASK(32)); - - /* registering outputs */ - mdev->output_cnt = 0; - for (i = 0; i < output_count; ++i) { - struct mxr_output_conf *conf = &output_conf[i]; - struct mxr_output *out; - - sd = find_and_register_subdev(mdev, conf->module_name); - /* trying to register next output */ - if (sd == NULL) - continue; - out = kzalloc(sizeof(*out), GFP_KERNEL); - if (out == NULL) { - mxr_err(mdev, "no memory for '%s'\n", - conf->output_name); - ret = -ENOMEM; - /* registered subdevs are removed in fail_v4l2_dev */ - goto fail_output; - } - strlcpy(out->name, conf->output_name, sizeof(out->name)); - out->sd = sd; - out->cookie = conf->cookie; - mdev->output[mdev->output_cnt++] = out; - mxr_info(mdev, "added output '%s' from module '%s'\n", - conf->output_name, conf->module_name); - /* checking if maximal number of outputs is reached */ - if (mdev->output_cnt >= MXR_MAX_OUTPUTS) - break; - } - - if (mdev->output_cnt == 0) { - mxr_err(mdev, "failed to register any output\n"); - ret = -ENODEV; - /* skipping fail_output because there is nothing to free */ - goto fail_v4l2_dev; - } - - return 0; - -fail_output: - /* kfree is NULL-safe */ - for (i = 0; i < mdev->output_cnt; ++i) - kfree(mdev->output[i]); - memset(mdev->output, 0, sizeof(mdev->output)); - -fail_v4l2_dev: - /* NOTE: automatically unregister all subdevs */ - v4l2_device_unregister(v4l2_dev); - -fail: - return ret; -} - -void mxr_release_video(struct mxr_device *mdev) -{ - int i; - - /* kfree is NULL-safe */ - for (i = 0; i < mdev->output_cnt; ++i) - kfree(mdev->output[i]); - - vb2_dma_contig_clear_max_seg_size(mdev->dev); - v4l2_device_unregister(&mdev->v4l2_dev); -} - -static int mxr_querycap(struct file *file, void *priv, - struct v4l2_capability *cap) -{ - struct mxr_layer *layer = video_drvdata(file); - - mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__); - - strlcpy(cap->driver, MXR_DRIVER_NAME, sizeof(cap->driver)); - strlcpy(cap->card, layer->vfd.name, sizeof(cap->card)); - sprintf(cap->bus_info, "%d", layer->idx); - cap->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_OUTPUT_MPLANE; - cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; - - return 0; -} - -static void mxr_geometry_dump(struct mxr_device *mdev, struct mxr_geometry *geo) -{ - mxr_dbg(mdev, "src.full_size = (%u, %u)\n", - geo->src.full_width, geo->src.full_height); - mxr_dbg(mdev, "src.size = (%u, %u)\n", - geo->src.width, geo->src.height); - mxr_dbg(mdev, "src.offset = (%u, %u)\n", - geo->src.x_offset, geo->src.y_offset); - mxr_dbg(mdev, "dst.full_size = (%u, %u)\n", - geo->dst.full_width, geo->dst.full_height); - mxr_dbg(mdev, "dst.size = (%u, %u)\n", - geo->dst.width, geo->dst.height); - mxr_dbg(mdev, "dst.offset = (%u, %u)\n", - geo->dst.x_offset, geo->dst.y_offset); - mxr_dbg(mdev, "ratio = (%u, %u)\n", - geo->x_ratio, geo->y_ratio); -} - -static void mxr_layer_default_geo(struct mxr_layer *layer) -{ - struct mxr_device *mdev = layer->mdev; - struct v4l2_mbus_framefmt mbus_fmt; - - memset(&layer->geo, 0, sizeof(layer->geo)); - - mxr_get_mbus_fmt(mdev, &mbus_fmt); - - layer->geo.dst.full_width = mbus_fmt.width; - layer->geo.dst.full_height = mbus_fmt.height; - layer->geo.dst.width = layer->geo.dst.full_width; - layer->geo.dst.height = layer->geo.dst.full_height; - layer->geo.dst.field = mbus_fmt.field; - - layer->geo.src.full_width = mbus_fmt.width; - layer->geo.src.full_height = mbus_fmt.height; - layer->geo.src.width = layer->geo.src.full_width; - layer->geo.src.height = layer->geo.src.full_height; - - mxr_geometry_dump(mdev, &layer->geo); - layer->ops.fix_geometry(layer, MXR_GEOMETRY_SINK, 0); - mxr_geometry_dump(mdev, &layer->geo); -} - -static void mxr_layer_update_output(struct mxr_layer *layer) -{ - struct mxr_device *mdev = layer->mdev; - struct v4l2_mbus_framefmt mbus_fmt; - - mxr_get_mbus_fmt(mdev, &mbus_fmt); - /* checking if update is needed */ - if (layer->geo.dst.full_width == mbus_fmt.width && - layer->geo.dst.full_height == mbus_fmt.width) - return; - - layer->geo.dst.full_width = mbus_fmt.width; - layer->geo.dst.full_height = mbus_fmt.height; - layer->geo.dst.field = mbus_fmt.field; - layer->ops.fix_geometry(layer, MXR_GEOMETRY_SINK, 0); - - mxr_geometry_dump(mdev, &layer->geo); -} - -static const struct mxr_format *find_format_by_fourcc( - struct mxr_layer *layer, unsigned long fourcc); -static const struct mxr_format *find_format_by_index( - struct mxr_layer *layer, unsigned long index); - -static int mxr_enum_fmt(struct file *file, void *priv, - struct v4l2_fmtdesc *f) -{ - struct mxr_layer *layer = video_drvdata(file); - struct mxr_device *mdev = layer->mdev; - const struct mxr_format *fmt; - - mxr_dbg(mdev, "%s\n", __func__); - fmt = find_format_by_index(layer, f->index); - if (fmt == NULL) - return -EINVAL; - - strlcpy(f->description, fmt->name, sizeof(f->description)); - f->pixelformat = fmt->fourcc; - - return 0; -} - -static unsigned int divup(unsigned int divident, unsigned int divisor) -{ - return (divident + divisor - 1) / divisor; -} - -unsigned long mxr_get_plane_size(const struct mxr_block *blk, - unsigned int width, unsigned int height) -{ - unsigned int bl_width = divup(width, blk->width); - unsigned int bl_height = divup(height, blk->height); - - return bl_width * bl_height * blk->size; -} - -static void mxr_mplane_fill(struct v4l2_plane_pix_format *planes, - const struct mxr_format *fmt, u32 width, u32 height) -{ - int i; - - /* checking if nothing to fill */ - if (!planes) - return; - - memset(planes, 0, sizeof(*planes) * fmt->num_subframes); - for (i = 0; i < fmt->num_planes; ++i) { - struct v4l2_plane_pix_format *plane = planes - + fmt->plane2subframe[i]; - const struct mxr_block *blk = &fmt->plane[i]; - u32 bl_width = divup(width, blk->width); - u32 bl_height = divup(height, blk->height); - u32 sizeimage = bl_width * bl_height * blk->size; - u32 bytesperline = bl_width * blk->size / blk->height; - - plane->sizeimage += sizeimage; - plane->bytesperline = max(plane->bytesperline, bytesperline); - } -} - -static int mxr_g_fmt(struct file *file, void *priv, - struct v4l2_format *f) -{ - struct mxr_layer *layer = video_drvdata(file); - struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; - - mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__); - - pix->width = layer->geo.src.full_width; - pix->height = layer->geo.src.full_height; - pix->field = V4L2_FIELD_NONE; - pix->pixelformat = layer->fmt->fourcc; - pix->colorspace = layer->fmt->colorspace; - mxr_mplane_fill(pix->plane_fmt, layer->fmt, pix->width, pix->height); - - return 0; -} - -static int mxr_s_fmt(struct file *file, void *priv, - struct v4l2_format *f) -{ - struct mxr_layer *layer = video_drvdata(file); - const struct mxr_format *fmt; - struct v4l2_pix_format_mplane *pix; - struct mxr_device *mdev = layer->mdev; - struct mxr_geometry *geo = &layer->geo; - - mxr_dbg(mdev, "%s:%d\n", __func__, __LINE__); - - pix = &f->fmt.pix_mp; - fmt = find_format_by_fourcc(layer, pix->pixelformat); - if (fmt == NULL) { - mxr_warn(mdev, "not recognized fourcc: %08x\n", - pix->pixelformat); - return -EINVAL; - } - layer->fmt = fmt; - /* set source size to highest accepted value */ - geo->src.full_width = max(geo->dst.full_width, pix->width); - geo->src.full_height = max(geo->dst.full_height, pix->height); - layer->ops.fix_geometry(layer, MXR_GEOMETRY_SOURCE, 0); - mxr_geometry_dump(mdev, &layer->geo); - /* set cropping to total visible screen */ - geo->src.width = pix->width; - geo->src.height = pix->height; - geo->src.x_offset = 0; - geo->src.y_offset = 0; - /* assure consistency of geometry */ - layer->ops.fix_geometry(layer, MXR_GEOMETRY_CROP, MXR_NO_OFFSET); - mxr_geometry_dump(mdev, &layer->geo); - /* set full size to lowest possible value */ - geo->src.full_width = 0; - geo->src.full_height = 0; - layer->ops.fix_geometry(layer, MXR_GEOMETRY_SOURCE, 0); - mxr_geometry_dump(mdev, &layer->geo); - - /* returning results */ - mxr_g_fmt(file, priv, f); - - return 0; -} - -static int mxr_g_selection(struct file *file, void *fh, - struct v4l2_selection *s) -{ - struct mxr_layer *layer = video_drvdata(file); - struct mxr_geometry *geo = &layer->geo; - - mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__); - - if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && - s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) - return -EINVAL; - - switch (s->target) { - case V4L2_SEL_TGT_CROP: - s->r.left = geo->src.x_offset; - s->r.top = geo->src.y_offset; - s->r.width = geo->src.width; - s->r.height = geo->src.height; - break; - case V4L2_SEL_TGT_CROP_DEFAULT: - case V4L2_SEL_TGT_CROP_BOUNDS: - s->r.left = 0; - s->r.top = 0; - s->r.width = geo->src.full_width; - s->r.height = geo->src.full_height; - break; - case V4L2_SEL_TGT_COMPOSE: - case V4L2_SEL_TGT_COMPOSE_PADDED: - s->r.left = geo->dst.x_offset; - s->r.top = geo->dst.y_offset; - s->r.width = geo->dst.width; - s->r.height = geo->dst.height; - break; - case V4L2_SEL_TGT_COMPOSE_DEFAULT: - case V4L2_SEL_TGT_COMPOSE_BOUNDS: - s->r.left = 0; - s->r.top = 0; - s->r.width = geo->dst.full_width; - s->r.height = geo->dst.full_height; - break; - default: - return -EINVAL; - } - - return 0; -} - -/* returns 1 if rectangle 'a' is inside 'b' */ -static int mxr_is_rect_inside(struct v4l2_rect *a, struct v4l2_rect *b) -{ - if (a->left < b->left) - return 0; - if (a->top < b->top) - return 0; - if (a->left + a->width > b->left + b->width) - return 0; - if (a->top + a->height > b->top + b->height) - return 0; - return 1; -} - -static int mxr_s_selection(struct file *file, void *fh, - struct v4l2_selection *s) -{ - struct mxr_layer *layer = video_drvdata(file); - struct mxr_geometry *geo = &layer->geo; - struct mxr_crop *target = NULL; - enum mxr_geometry_stage stage; - struct mxr_geometry tmp; - struct v4l2_rect res; - - memset(&res, 0, sizeof(res)); - - mxr_dbg(layer->mdev, "%s: rect: %dx%d@%d,%d\n", __func__, - s->r.width, s->r.height, s->r.left, s->r.top); - - if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && - s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) - return -EINVAL; - - switch (s->target) { - /* ignore read-only targets */ - case V4L2_SEL_TGT_CROP_DEFAULT: - case V4L2_SEL_TGT_CROP_BOUNDS: - res.width = geo->src.full_width; - res.height = geo->src.full_height; - break; - - /* ignore read-only targets */ - case V4L2_SEL_TGT_COMPOSE_DEFAULT: - case V4L2_SEL_TGT_COMPOSE_BOUNDS: - res.width = geo->dst.full_width; - res.height = geo->dst.full_height; - break; - - case V4L2_SEL_TGT_CROP: - target = &geo->src; - stage = MXR_GEOMETRY_CROP; - break; - case V4L2_SEL_TGT_COMPOSE: - case V4L2_SEL_TGT_COMPOSE_PADDED: - target = &geo->dst; - stage = MXR_GEOMETRY_COMPOSE; - break; - default: - return -EINVAL; - } - /* apply change and update geometry if needed */ - if (target) { - /* backup current geometry if setup fails */ - memcpy(&tmp, geo, sizeof(tmp)); - - /* apply requested selection */ - target->x_offset = s->r.left; - target->y_offset = s->r.top; - target->width = s->r.width; - target->height = s->r.height; - - layer->ops.fix_geometry(layer, stage, s->flags); - - /* retrieve update selection rectangle */ - res.left = target->x_offset; - res.top = target->y_offset; - res.width = target->width; - res.height = target->height; - - mxr_geometry_dump(layer->mdev, &layer->geo); - } - - /* checking if the rectangle satisfies constraints */ - if ((s->flags & V4L2_SEL_FLAG_LE) && !mxr_is_rect_inside(&res, &s->r)) - goto fail; - if ((s->flags & V4L2_SEL_FLAG_GE) && !mxr_is_rect_inside(&s->r, &res)) - goto fail; - - /* return result rectangle */ - s->r = res; - - return 0; -fail: - /* restore old geometry, which is not touched if target is NULL */ - if (target) - memcpy(geo, &tmp, sizeof(tmp)); - return -ERANGE; -} - -static int mxr_enum_dv_timings(struct file *file, void *fh, - struct v4l2_enum_dv_timings *timings) -{ - struct mxr_layer *layer = video_drvdata(file); - struct mxr_device *mdev = layer->mdev; - int ret; - - timings->pad = 0; - - /* lock protects from changing sd_out */ - mutex_lock(&mdev->mutex); - ret = v4l2_subdev_call(to_outsd(mdev), pad, enum_dv_timings, timings); - mutex_unlock(&mdev->mutex); - - return ret ? -EINVAL : 0; -} - -static int mxr_s_dv_timings(struct file *file, void *fh, - struct v4l2_dv_timings *timings) -{ - struct mxr_layer *layer = video_drvdata(file); - struct mxr_device *mdev = layer->mdev; - int ret; - - /* lock protects from changing sd_out */ - mutex_lock(&mdev->mutex); - - /* timings change cannot be done while there is an entity - * dependent on output configuration - */ - if (mdev->n_output > 0) { - mutex_unlock(&mdev->mutex); - return -EBUSY; - } - - ret = v4l2_subdev_call(to_outsd(mdev), video, s_dv_timings, timings); - - mutex_unlock(&mdev->mutex); - - mxr_layer_update_output(layer); - - /* any failure should return EINVAL according to V4L2 doc */ - return ret ? -EINVAL : 0; -} - -static int mxr_g_dv_timings(struct file *file, void *fh, - struct v4l2_dv_timings *timings) -{ - struct mxr_layer *layer = video_drvdata(file); - struct mxr_device *mdev = layer->mdev; - int ret; - - /* lock protects from changing sd_out */ - mutex_lock(&mdev->mutex); - ret = v4l2_subdev_call(to_outsd(mdev), video, g_dv_timings, timings); - mutex_unlock(&mdev->mutex); - - return ret ? -EINVAL : 0; -} - -static int mxr_dv_timings_cap(struct file *file, void *fh, - struct v4l2_dv_timings_cap *cap) -{ - struct mxr_layer *layer = video_drvdata(file); - struct mxr_device *mdev = layer->mdev; - int ret; - - cap->pad = 0; - - /* lock protects from changing sd_out */ - mutex_lock(&mdev->mutex); - ret = v4l2_subdev_call(to_outsd(mdev), pad, dv_timings_cap, cap); - mutex_unlock(&mdev->mutex); - - return ret ? -EINVAL : 0; -} - -static int mxr_s_std(struct file *file, void *fh, v4l2_std_id norm) -{ - struct mxr_layer *layer = video_drvdata(file); - struct mxr_device *mdev = layer->mdev; - int ret; - - /* lock protects from changing sd_out */ - mutex_lock(&mdev->mutex); - - /* standard change cannot be done while there is an entity - * dependent on output configuration - */ - if (mdev->n_output > 0) { - mutex_unlock(&mdev->mutex); - return -EBUSY; - } - - ret = v4l2_subdev_call(to_outsd(mdev), video, s_std_output, norm); - - mutex_unlock(&mdev->mutex); - - mxr_layer_update_output(layer); - - return ret ? -EINVAL : 0; -} - -static int mxr_g_std(struct file *file, void *fh, v4l2_std_id *norm) -{ - struct mxr_layer *layer = video_drvdata(file); - struct mxr_device *mdev = layer->mdev; - int ret; - - /* lock protects from changing sd_out */ - mutex_lock(&mdev->mutex); - ret = v4l2_subdev_call(to_outsd(mdev), video, g_std_output, norm); - mutex_unlock(&mdev->mutex); - - return ret ? -EINVAL : 0; -} - -static int mxr_enum_output(struct file *file, void *fh, struct v4l2_output *a) -{ - struct mxr_layer *layer = video_drvdata(file); - struct mxr_device *mdev = layer->mdev; - struct mxr_output *out; - struct v4l2_subdev *sd; - - if (a->index >= mdev->output_cnt) - return -EINVAL; - out = mdev->output[a->index]; - BUG_ON(out == NULL); - sd = out->sd; - strlcpy(a->name, out->name, sizeof(a->name)); - - /* try to obtain supported tv norms */ - v4l2_subdev_call(sd, video, g_tvnorms_output, &a->std); - a->capabilities = 0; - if (sd->ops->video && sd->ops->video->s_dv_timings) - a->capabilities |= V4L2_OUT_CAP_DV_TIMINGS; - if (sd->ops->video && sd->ops->video->s_std_output) - a->capabilities |= V4L2_OUT_CAP_STD; - a->type = V4L2_OUTPUT_TYPE_ANALOG; - - return 0; -} - -static int mxr_s_output(struct file *file, void *fh, unsigned int i) -{ - struct video_device *vfd = video_devdata(file); - struct mxr_layer *layer = video_drvdata(file); - struct mxr_device *mdev = layer->mdev; - - if (i >= mdev->output_cnt || mdev->output[i] == NULL) - return -EINVAL; - - mutex_lock(&mdev->mutex); - if (mdev->n_output > 0) { - mutex_unlock(&mdev->mutex); - return -EBUSY; - } - mdev->current_output = i; - vfd->tvnorms = 0; - v4l2_subdev_call(to_outsd(mdev), video, g_tvnorms_output, - &vfd->tvnorms); - mutex_unlock(&mdev->mutex); - - /* update layers geometry */ - mxr_layer_update_output(layer); - - mxr_dbg(mdev, "tvnorms = %08llx\n", vfd->tvnorms); - - return 0; -} - -static int mxr_g_output(struct file *file, void *fh, unsigned int *p) -{ - struct mxr_layer *layer = video_drvdata(file); - struct mxr_device *mdev = layer->mdev; - - mutex_lock(&mdev->mutex); - *p = mdev->current_output; - mutex_unlock(&mdev->mutex); - - return 0; -} - -static int mxr_reqbufs(struct file *file, void *priv, - struct v4l2_requestbuffers *p) -{ - struct mxr_layer *layer = video_drvdata(file); - - mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__); - return vb2_reqbufs(&layer->vb_queue, p); -} - -static int mxr_querybuf(struct file *file, void *priv, struct v4l2_buffer *p) -{ - struct mxr_layer *layer = video_drvdata(file); - - mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__); - return vb2_querybuf(&layer->vb_queue, p); -} - -static int mxr_qbuf(struct file *file, void *priv, struct v4l2_buffer *p) -{ - struct mxr_layer *layer = video_drvdata(file); - - mxr_dbg(layer->mdev, "%s:%d(%d)\n", __func__, __LINE__, p->index); - return vb2_qbuf(&layer->vb_queue, p); -} - -static int mxr_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) -{ - struct mxr_layer *layer = video_drvdata(file); - - mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__); - return vb2_dqbuf(&layer->vb_queue, p, file->f_flags & O_NONBLOCK); -} - -static int mxr_expbuf(struct file *file, void *priv, - struct v4l2_exportbuffer *eb) -{ - struct mxr_layer *layer = video_drvdata(file); - - mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__); - return vb2_expbuf(&layer->vb_queue, eb); -} - -static int mxr_streamon(struct file *file, void *priv, enum v4l2_buf_type i) -{ - struct mxr_layer *layer = video_drvdata(file); - - mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__); - return vb2_streamon(&layer->vb_queue, i); -} - -static int mxr_streamoff(struct file *file, void *priv, enum v4l2_buf_type i) -{ - struct mxr_layer *layer = video_drvdata(file); - - mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__); - return vb2_streamoff(&layer->vb_queue, i); -} - -static const struct v4l2_ioctl_ops mxr_ioctl_ops = { - .vidioc_querycap = mxr_querycap, - /* format handling */ - .vidioc_enum_fmt_vid_out_mplane = mxr_enum_fmt, - .vidioc_s_fmt_vid_out_mplane = mxr_s_fmt, - .vidioc_g_fmt_vid_out_mplane = mxr_g_fmt, - /* buffer control */ - .vidioc_reqbufs = mxr_reqbufs, - .vidioc_querybuf = mxr_querybuf, - .vidioc_qbuf = mxr_qbuf, - .vidioc_dqbuf = mxr_dqbuf, - .vidioc_expbuf = mxr_expbuf, - /* Streaming control */ - .vidioc_streamon = mxr_streamon, - .vidioc_streamoff = mxr_streamoff, - /* DV Timings functions */ - .vidioc_enum_dv_timings = mxr_enum_dv_timings, - .vidioc_s_dv_timings = mxr_s_dv_timings, - .vidioc_g_dv_timings = mxr_g_dv_timings, - .vidioc_dv_timings_cap = mxr_dv_timings_cap, - /* analog TV standard functions */ - .vidioc_s_std = mxr_s_std, - .vidioc_g_std = mxr_g_std, - /* Output handling */ - .vidioc_enum_output = mxr_enum_output, - .vidioc_s_output = mxr_s_output, - .vidioc_g_output = mxr_g_output, - /* selection ioctls */ - .vidioc_g_selection = mxr_g_selection, - .vidioc_s_selection = mxr_s_selection, -}; - -static int mxr_video_open(struct file *file) -{ - struct mxr_layer *layer = video_drvdata(file); - struct mxr_device *mdev = layer->mdev; - int ret = 0; - - mxr_dbg(mdev, "%s:%d\n", __func__, __LINE__); - if (mutex_lock_interruptible(&layer->mutex)) - return -ERESTARTSYS; - /* assure device probe is finished */ - wait_for_device_probe(); - /* creating context for file descriptor */ - ret = v4l2_fh_open(file); - if (ret) { - mxr_err(mdev, "v4l2_fh_open failed\n"); - goto unlock; - } - - /* leaving if layer is already initialized */ - if (!v4l2_fh_is_singular_file(file)) - goto unlock; - - /* FIXME: should power be enabled on open? */ - ret = mxr_power_get(mdev); - if (ret) { - mxr_err(mdev, "power on failed\n"); - goto fail_fh_open; - } - - ret = vb2_queue_init(&layer->vb_queue); - if (ret != 0) { - mxr_err(mdev, "failed to initialize vb2 queue\n"); - goto fail_power; - } - /* set default format, first on the list */ - layer->fmt = layer->fmt_array[0]; - /* setup default geometry */ - mxr_layer_default_geo(layer); - mutex_unlock(&layer->mutex); - - return 0; - -fail_power: - mxr_power_put(mdev); - -fail_fh_open: - v4l2_fh_release(file); - -unlock: - mutex_unlock(&layer->mutex); - - return ret; -} - -static unsigned int -mxr_video_poll(struct file *file, struct poll_table_struct *wait) -{ - struct mxr_layer *layer = video_drvdata(file); - unsigned int res; - - mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__); - - mutex_lock(&layer->mutex); - res = vb2_poll(&layer->vb_queue, file, wait); - mutex_unlock(&layer->mutex); - return res; -} - -static int mxr_video_mmap(struct file *file, struct vm_area_struct *vma) -{ - struct mxr_layer *layer = video_drvdata(file); - int ret; - - mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__); - - if (mutex_lock_interruptible(&layer->mutex)) - return -ERESTARTSYS; - ret = vb2_mmap(&layer->vb_queue, vma); - mutex_unlock(&layer->mutex); - return ret; -} - -static int mxr_video_release(struct file *file) -{ - struct mxr_layer *layer = video_drvdata(file); - - mxr_dbg(layer->mdev, "%s:%d\n", __func__, __LINE__); - mutex_lock(&layer->mutex); - if (v4l2_fh_is_singular_file(file)) { - vb2_queue_release(&layer->vb_queue); - mxr_power_put(layer->mdev); - } - v4l2_fh_release(file); - mutex_unlock(&layer->mutex); - return 0; -} - -static const struct v4l2_file_operations mxr_fops = { - .owner = THIS_MODULE, - .open = mxr_video_open, - .poll = mxr_video_poll, - .mmap = mxr_video_mmap, - .release = mxr_video_release, - .unlocked_ioctl = video_ioctl2, -}; - -static int queue_setup(struct vb2_queue *vq, - unsigned int *nbuffers, unsigned int *nplanes, unsigned int sizes[], - struct device *alloc_devs[]) -{ - struct mxr_layer *layer = vb2_get_drv_priv(vq); - const struct mxr_format *fmt = layer->fmt; - int i; - struct mxr_device *mdev = layer->mdev; - struct v4l2_plane_pix_format planes[3]; - - mxr_dbg(mdev, "%s\n", __func__); - /* checking if format was configured */ - if (fmt == NULL) - return -EINVAL; - mxr_dbg(mdev, "fmt = %s\n", fmt->name); - mxr_mplane_fill(planes, fmt, layer->geo.src.full_width, - layer->geo.src.full_height); - - *nplanes = fmt->num_subframes; - for (i = 0; i < fmt->num_subframes; ++i) { - sizes[i] = planes[i].sizeimage; - mxr_dbg(mdev, "size[%d] = %08x\n", i, sizes[i]); - } - - if (*nbuffers == 0) - *nbuffers = 1; - - return 0; -} - -static void buf_queue(struct vb2_buffer *vb) -{ - struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); - struct mxr_buffer *buffer = container_of(vbuf, struct mxr_buffer, vb); - struct mxr_layer *layer = vb2_get_drv_priv(vb->vb2_queue); - struct mxr_device *mdev = layer->mdev; - unsigned long flags; - - spin_lock_irqsave(&layer->enq_slock, flags); - list_add_tail(&buffer->list, &layer->enq_list); - spin_unlock_irqrestore(&layer->enq_slock, flags); - - mxr_dbg(mdev, "queuing buffer\n"); -} - -static int start_streaming(struct vb2_queue *vq, unsigned int count) -{ - struct mxr_layer *layer = vb2_get_drv_priv(vq); - struct mxr_device *mdev = layer->mdev; - unsigned long flags; - - mxr_dbg(mdev, "%s\n", __func__); - - /* block any changes in output configuration */ - mxr_output_get(mdev); - - mxr_layer_update_output(layer); - layer->ops.format_set(layer); - /* enabling layer in hardware */ - spin_lock_irqsave(&layer->enq_slock, flags); - layer->state = MXR_LAYER_STREAMING; - spin_unlock_irqrestore(&layer->enq_slock, flags); - - layer->ops.stream_set(layer, MXR_ENABLE); - mxr_streamer_get(mdev); - - return 0; -} - -static void mxr_watchdog(unsigned long arg) -{ - struct mxr_layer *layer = (struct mxr_layer *) arg; - struct mxr_device *mdev = layer->mdev; - unsigned long flags; - - mxr_err(mdev, "watchdog fired for layer %s\n", layer->vfd.name); - - spin_lock_irqsave(&layer->enq_slock, flags); - - if (layer->update_buf == layer->shadow_buf) - layer->update_buf = NULL; - if (layer->update_buf) { - vb2_buffer_done(&layer->update_buf->vb.vb2_buf, - VB2_BUF_STATE_ERROR); - layer->update_buf = NULL; - } - if (layer->shadow_buf) { - vb2_buffer_done(&layer->shadow_buf->vb.vb2_buf, - VB2_BUF_STATE_ERROR); - layer->shadow_buf = NULL; - } - spin_unlock_irqrestore(&layer->enq_slock, flags); -} - -static void stop_streaming(struct vb2_queue *vq) -{ - struct mxr_layer *layer = vb2_get_drv_priv(vq); - struct mxr_device *mdev = layer->mdev; - unsigned long flags; - struct timer_list watchdog; - struct mxr_buffer *buf, *buf_tmp; - - mxr_dbg(mdev, "%s\n", __func__); - - spin_lock_irqsave(&layer->enq_slock, flags); - - /* reset list */ - layer->state = MXR_LAYER_STREAMING_FINISH; - - /* set all buffer to be done */ - list_for_each_entry_safe(buf, buf_tmp, &layer->enq_list, list) { - list_del(&buf->list); - vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); - } - - spin_unlock_irqrestore(&layer->enq_slock, flags); - - /* give 1 seconds to complete to complete last buffers */ - setup_timer_on_stack(&watchdog, mxr_watchdog, - (unsigned long)layer); - mod_timer(&watchdog, jiffies + msecs_to_jiffies(1000)); - - /* wait until all buffers are goes to done state */ - vb2_wait_for_all_buffers(vq); - - /* stop timer if all synchronization is done */ - del_timer_sync(&watchdog); - destroy_timer_on_stack(&watchdog); - - /* stopping hardware */ - spin_lock_irqsave(&layer->enq_slock, flags); - layer->state = MXR_LAYER_IDLE; - spin_unlock_irqrestore(&layer->enq_slock, flags); - - /* disabling layer in hardware */ - layer->ops.stream_set(layer, MXR_DISABLE); - /* remove one streamer */ - mxr_streamer_put(mdev); - /* allow changes in output configuration */ - mxr_output_put(mdev); -} - -static struct vb2_ops mxr_video_qops = { - .queue_setup = queue_setup, - .buf_queue = buf_queue, - .wait_prepare = vb2_ops_wait_prepare, - .wait_finish = vb2_ops_wait_finish, - .start_streaming = start_streaming, - .stop_streaming = stop_streaming, -}; - -/* FIXME: try to put this functions to mxr_base_layer_create */ -int mxr_base_layer_register(struct mxr_layer *layer) -{ - struct mxr_device *mdev = layer->mdev; - int ret; - - ret = video_register_device(&layer->vfd, VFL_TYPE_GRABBER, -1); - if (ret) - mxr_err(mdev, "failed to register video device\n"); - else - mxr_info(mdev, "registered layer %s as /dev/video%d\n", - layer->vfd.name, layer->vfd.num); - return ret; -} - -void mxr_base_layer_unregister(struct mxr_layer *layer) -{ - video_unregister_device(&layer->vfd); -} - -void mxr_layer_release(struct mxr_layer *layer) -{ - if (layer->ops.release) - layer->ops.release(layer); -} - -void mxr_base_layer_release(struct mxr_layer *layer) -{ - kfree(layer); -} - -static void mxr_vfd_release(struct video_device *vdev) -{ - pr_info("video device release\n"); -} - -struct mxr_layer *mxr_base_layer_create(struct mxr_device *mdev, - int idx, char *name, const struct mxr_layer_ops *ops) -{ - struct mxr_layer *layer; - - layer = kzalloc(sizeof(*layer), GFP_KERNEL); - if (layer == NULL) { - mxr_err(mdev, "not enough memory for layer.\n"); - goto fail; - } - - layer->mdev = mdev; - layer->idx = idx; - layer->ops = *ops; - - spin_lock_init(&layer->enq_slock); - INIT_LIST_HEAD(&layer->enq_list); - mutex_init(&layer->mutex); - - layer->vfd = (struct video_device) { - .minor = -1, - .release = mxr_vfd_release, - .fops = &mxr_fops, - .vfl_dir = VFL_DIR_TX, - .ioctl_ops = &mxr_ioctl_ops, - }; - strlcpy(layer->vfd.name, name, sizeof(layer->vfd.name)); - - video_set_drvdata(&layer->vfd, layer); - layer->vfd.lock = &layer->mutex; - layer->vfd.v4l2_dev = &mdev->v4l2_dev; - - layer->vb_queue = (struct vb2_queue) { - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - .io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF, - .drv_priv = layer, - .buf_struct_size = sizeof(struct mxr_buffer), - .ops = &mxr_video_qops, - .min_buffers_needed = 1, - .mem_ops = &vb2_dma_contig_memops, - .lock = &layer->mutex, - .dev = mdev->dev, - }; - - return layer; - -fail: - return NULL; -} - -static const struct mxr_format *find_format_by_fourcc( - struct mxr_layer *layer, unsigned long fourcc) -{ - int i; - - for (i = 0; i < layer->fmt_array_size; ++i) - if (layer->fmt_array[i]->fourcc == fourcc) - return layer->fmt_array[i]; - return NULL; -} - -static const struct mxr_format *find_format_by_index( - struct mxr_layer *layer, unsigned long index) -{ - if (index >= layer->fmt_array_size) - return NULL; - return layer->fmt_array[index]; -} - diff --git a/drivers/media/platform/s5p-tv/mixer_vp_layer.c b/drivers/media/platform/s5p-tv/mixer_vp_layer.c deleted file mode 100644 index 6fa6f673f53b..000000000000 --- a/drivers/media/platform/s5p-tv/mixer_vp_layer.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Samsung TV Mixer driver - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * - * Tomasz Stanislawski, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundiation. either version 2 of the License, - * or (at your option) any later version - */ - -#include "mixer.h" - -#include "regs-vp.h" - -#include - -/* FORMAT DEFINITIONS */ -static const struct mxr_format mxr_fmt_nv12 = { - .name = "NV12", - .fourcc = V4L2_PIX_FMT_NV12, - .colorspace = V4L2_COLORSPACE_JPEG, - .num_planes = 2, - .plane = { - { .width = 1, .height = 1, .size = 1 }, - { .width = 2, .height = 2, .size = 2 }, - }, - .num_subframes = 1, - .cookie = VP_MODE_NV12 | VP_MODE_MEM_LINEAR, -}; - -static const struct mxr_format mxr_fmt_nv21 = { - .name = "NV21", - .fourcc = V4L2_PIX_FMT_NV21, - .colorspace = V4L2_COLORSPACE_JPEG, - .num_planes = 2, - .plane = { - { .width = 1, .height = 1, .size = 1 }, - { .width = 2, .height = 2, .size = 2 }, - }, - .num_subframes = 1, - .cookie = VP_MODE_NV21 | VP_MODE_MEM_LINEAR, -}; - -static const struct mxr_format mxr_fmt_nv12m = { - .name = "NV12 (mplane)", - .fourcc = V4L2_PIX_FMT_NV12M, - .colorspace = V4L2_COLORSPACE_JPEG, - .num_planes = 2, - .plane = { - { .width = 1, .height = 1, .size = 1 }, - { .width = 2, .height = 2, .size = 2 }, - }, - .num_subframes = 2, - .plane2subframe = {0, 1}, - .cookie = VP_MODE_NV12 | VP_MODE_MEM_LINEAR, -}; - -static const struct mxr_format mxr_fmt_nv12mt = { - .name = "NV12 tiled (mplane)", - .fourcc = V4L2_PIX_FMT_NV12MT, - .colorspace = V4L2_COLORSPACE_JPEG, - .num_planes = 2, - .plane = { - { .width = 128, .height = 32, .size = 4096 }, - { .width = 128, .height = 32, .size = 2048 }, - }, - .num_subframes = 2, - .plane2subframe = {0, 1}, - .cookie = VP_MODE_NV12 | VP_MODE_MEM_TILED, -}; - -static const struct mxr_format *mxr_video_format[] = { - &mxr_fmt_nv12, - &mxr_fmt_nv21, - &mxr_fmt_nv12m, - &mxr_fmt_nv12mt, -}; - -/* AUXILIARY CALLBACKS */ - -static void mxr_vp_layer_release(struct mxr_layer *layer) -{ - mxr_base_layer_unregister(layer); - mxr_base_layer_release(layer); -} - -static void mxr_vp_buffer_set(struct mxr_layer *layer, - struct mxr_buffer *buf) -{ - dma_addr_t luma_addr[2] = {0, 0}; - dma_addr_t chroma_addr[2] = {0, 0}; - - if (buf == NULL) { - mxr_reg_vp_buffer(layer->mdev, luma_addr, chroma_addr); - return; - } - luma_addr[0] = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); - if (layer->fmt->num_subframes == 2) { - chroma_addr[0] = - vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 1); - } else { - /* FIXME: mxr_get_plane_size compute integer division, - * which is slow and should not be performed in interrupt */ - chroma_addr[0] = luma_addr[0] + mxr_get_plane_size( - &layer->fmt->plane[0], layer->geo.src.full_width, - layer->geo.src.full_height); - } - if (layer->fmt->cookie & VP_MODE_MEM_TILED) { - luma_addr[1] = luma_addr[0] + 0x40; - chroma_addr[1] = chroma_addr[0] + 0x40; - } else { - luma_addr[1] = luma_addr[0] + layer->geo.src.full_width; - chroma_addr[1] = chroma_addr[0]; - } - mxr_reg_vp_buffer(layer->mdev, luma_addr, chroma_addr); -} - -static void mxr_vp_stream_set(struct mxr_layer *layer, int en) -{ - mxr_reg_vp_layer_stream(layer->mdev, en); -} - -static void mxr_vp_format_set(struct mxr_layer *layer) -{ - mxr_reg_vp_format(layer->mdev, layer->fmt, &layer->geo); -} - -static inline unsigned int do_center(unsigned int center, - unsigned int size, unsigned int upper, unsigned int flags) -{ - unsigned int lower; - - if (flags & MXR_NO_OFFSET) - return 0; - - lower = center - min(center, size / 2); - return min(lower, upper - size); -} - -static void mxr_vp_fix_geometry(struct mxr_layer *layer, - enum mxr_geometry_stage stage, unsigned long flags) -{ - struct mxr_geometry *geo = &layer->geo; - struct mxr_crop *src = &geo->src; - struct mxr_crop *dst = &geo->dst; - unsigned long x_center, y_center; - - switch (stage) { - - case MXR_GEOMETRY_SINK: /* nothing to be fixed here */ - case MXR_GEOMETRY_COMPOSE: - /* remember center of the area */ - x_center = dst->x_offset + dst->width / 2; - y_center = dst->y_offset + dst->height / 2; - - /* ensure that compose is reachable using 16x scaling */ - dst->width = clamp(dst->width, 8U, 16 * src->full_width); - dst->height = clamp(dst->height, 1U, 16 * src->full_height); - - /* setup offsets */ - dst->x_offset = do_center(x_center, dst->width, - dst->full_width, flags); - dst->y_offset = do_center(y_center, dst->height, - dst->full_height, flags); - flags = 0; /* remove possible MXR_NO_OFFSET flag */ - /* fall through */ - case MXR_GEOMETRY_CROP: - /* remember center of the area */ - x_center = src->x_offset + src->width / 2; - y_center = src->y_offset + src->height / 2; - - /* ensure scaling is between 0.25x .. 16x */ - src->width = clamp(src->width, round_up(dst->width / 16, 4), - dst->width * 4); - src->height = clamp(src->height, round_up(dst->height / 16, 4), - dst->height * 4); - - /* hardware limits */ - src->width = clamp(src->width, 32U, 2047U); - src->height = clamp(src->height, 4U, 2047U); - - /* setup offsets */ - src->x_offset = do_center(x_center, src->width, - src->full_width, flags); - src->y_offset = do_center(y_center, src->height, - src->full_height, flags); - - /* setting scaling ratio */ - geo->x_ratio = (src->width << 16) / dst->width; - geo->y_ratio = (src->height << 16) / dst->height; - /* fall through */ - - case MXR_GEOMETRY_SOURCE: - src->full_width = clamp(src->full_width, - ALIGN(src->width + src->x_offset, 8), 8192U); - src->full_height = clamp(src->full_height, - src->height + src->y_offset, 8192U); - } -} - -/* PUBLIC API */ - -struct mxr_layer *mxr_vp_layer_create(struct mxr_device *mdev, int idx) -{ - struct mxr_layer *layer; - int ret; - const struct mxr_layer_ops ops = { - .release = mxr_vp_layer_release, - .buffer_set = mxr_vp_buffer_set, - .stream_set = mxr_vp_stream_set, - .format_set = mxr_vp_format_set, - .fix_geometry = mxr_vp_fix_geometry, - }; - char name[32]; - - sprintf(name, "video%d", idx); - - layer = mxr_base_layer_create(mdev, idx, name, &ops); - if (layer == NULL) { - mxr_err(mdev, "failed to initialize layer(%d) base\n", idx); - goto fail; - } - - layer->fmt_array = mxr_video_format; - layer->fmt_array_size = ARRAY_SIZE(mxr_video_format); - - ret = mxr_base_layer_register(layer); - if (ret) - goto fail_layer; - - return layer; - -fail_layer: - mxr_base_layer_release(layer); - -fail: - return NULL; -} - diff --git a/drivers/media/platform/s5p-tv/regs-hdmi.h b/drivers/media/platform/s5p-tv/regs-hdmi.h deleted file mode 100644 index a889d1f57f28..000000000000 --- a/drivers/media/platform/s5p-tv/regs-hdmi.h +++ /dev/null @@ -1,146 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/regs-hdmi.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * HDMI register header file for Samsung TVOUT driver - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef SAMSUNG_REGS_HDMI_H -#define SAMSUNG_REGS_HDMI_H - -/* - * Register part -*/ - -#define HDMI_CTRL_BASE(x) ((x) + 0x00000000) -#define HDMI_CORE_BASE(x) ((x) + 0x00010000) -#define HDMI_TG_BASE(x) ((x) + 0x00050000) - -/* Control registers */ -#define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) -#define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) -#define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) -#define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0014) -#define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0018) -#define HDMI_PHY_CMU HDMI_CTRL_BASE(0x001C) -#define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0020) - -/* Core registers */ -#define HDMI_CON_0 HDMI_CORE_BASE(0x0000) -#define HDMI_CON_1 HDMI_CORE_BASE(0x0004) -#define HDMI_CON_2 HDMI_CORE_BASE(0x0008) -#define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010) -#define HDMI_PHY_STATUS HDMI_CORE_BASE(0x0014) -#define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020) -#define HDMI_HPD HDMI_CORE_BASE(0x0030) -#define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040) -#define HDMI_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050) -#define HDMI_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054) -#define HDMI_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058) -#define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0) -#define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4) -#define HDMI_V_BLANK_0 HDMI_CORE_BASE(0x00B0) -#define HDMI_V_BLANK_1 HDMI_CORE_BASE(0x00B4) -#define HDMI_V_BLANK_2 HDMI_CORE_BASE(0x00B8) -#define HDMI_H_V_LINE_0 HDMI_CORE_BASE(0x00C0) -#define HDMI_H_V_LINE_1 HDMI_CORE_BASE(0x00C4) -#define HDMI_H_V_LINE_2 HDMI_CORE_BASE(0x00C8) -#define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4) -#define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8) -#define HDMI_V_BLANK_F_0 HDMI_CORE_BASE(0x0110) -#define HDMI_V_BLANK_F_1 HDMI_CORE_BASE(0x0114) -#define HDMI_V_BLANK_F_2 HDMI_CORE_BASE(0x0118) -#define HDMI_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120) -#define HDMI_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124) -#define HDMI_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128) -#define HDMI_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130) -#define HDMI_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134) -#define HDMI_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138) -#define HDMI_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140) -#define HDMI_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144) -#define HDMI_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148) -#define HDMI_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150) -#define HDMI_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154) -#define HDMI_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158) -#define HDMI_AVI_CON HDMI_CORE_BASE(0x0300) -#define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n)) -#define HDMI_DC_CONTROL HDMI_CORE_BASE(0x05C0) -#define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4) -#define HDMI_HPD_GEN HDMI_CORE_BASE(0x05C8) - -/* Timing generator registers */ -#define HDMI_TG_CMD HDMI_TG_BASE(0x0000) -#define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018) -#define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C) -#define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020) -#define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024) -#define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028) -#define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C) -#define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030) -#define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034) -#define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038) -#define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C) -#define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040) -#define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044) -#define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048) -#define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C) -#define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050) -#define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054) -#define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058) -#define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C) -#define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060) -#define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064) -#define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078) -#define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C) -#define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080) -#define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084) -#define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088) -#define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C) -#define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090) -#define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094) - -/* - * Bit definition part - */ - -/* HDMI_INTC_CON */ -#define HDMI_INTC_EN_GLOBAL (1 << 6) -#define HDMI_INTC_EN_HPD_PLUG (1 << 3) -#define HDMI_INTC_EN_HPD_UNPLUG (1 << 2) - -/* HDMI_INTC_FLAG */ -#define HDMI_INTC_FLAG_HPD_PLUG (1 << 3) -#define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2) - -/* HDMI_PHY_RSTOUT */ -#define HDMI_PHY_SW_RSTOUT (1 << 0) - -/* HDMI_CORE_RSTOUT */ -#define HDMI_CORE_SW_RSTOUT (1 << 0) - -/* HDMI_CON_0 */ -#define HDMI_BLUE_SCR_EN (1 << 5) -#define HDMI_EN (1 << 0) - -/* HDMI_CON_2 */ -#define HDMI_DVI_PERAMBLE_EN (1 << 5) -#define HDMI_DVI_BAND_EN (1 << 1) - -/* HDMI_PHY_STATUS */ -#define HDMI_PHY_STATUS_READY (1 << 0) - -/* HDMI_MODE_SEL */ -#define HDMI_MODE_HDMI_EN (1 << 1) -#define HDMI_MODE_DVI_EN (1 << 0) -#define HDMI_MODE_MASK (3 << 0) - -/* HDMI_TG_CMD */ -#define HDMI_TG_FIELD_EN (1 << 1) -#define HDMI_TG_EN (1 << 0) - -#endif /* SAMSUNG_REGS_HDMI_H */ diff --git a/drivers/media/platform/s5p-tv/regs-mixer.h b/drivers/media/platform/s5p-tv/regs-mixer.h deleted file mode 100644 index 158abb43d0a4..000000000000 --- a/drivers/media/platform/s5p-tv/regs-mixer.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Mixer register header file for Samsung Mixer driver - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ -#ifndef SAMSUNG_REGS_MIXER_H -#define SAMSUNG_REGS_MIXER_H - -/* - * Register part - */ -#define MXR_STATUS 0x0000 -#define MXR_CFG 0x0004 -#define MXR_INT_EN 0x0008 -#define MXR_INT_STATUS 0x000C -#define MXR_LAYER_CFG 0x0010 -#define MXR_VIDEO_CFG 0x0014 -#define MXR_GRAPHIC0_CFG 0x0020 -#define MXR_GRAPHIC0_BASE 0x0024 -#define MXR_GRAPHIC0_SPAN 0x0028 -#define MXR_GRAPHIC0_SXY 0x002C -#define MXR_GRAPHIC0_WH 0x0030 -#define MXR_GRAPHIC0_DXY 0x0034 -#define MXR_GRAPHIC0_BLANK 0x0038 -#define MXR_GRAPHIC1_CFG 0x0040 -#define MXR_GRAPHIC1_BASE 0x0044 -#define MXR_GRAPHIC1_SPAN 0x0048 -#define MXR_GRAPHIC1_SXY 0x004C -#define MXR_GRAPHIC1_WH 0x0050 -#define MXR_GRAPHIC1_DXY 0x0054 -#define MXR_GRAPHIC1_BLANK 0x0058 -#define MXR_BG_CFG 0x0060 -#define MXR_BG_COLOR0 0x0064 -#define MXR_BG_COLOR1 0x0068 -#define MXR_BG_COLOR2 0x006C - -/* for parametrized access to layer registers */ -#define MXR_GRAPHIC_CFG(i) (0x0020 + (i) * 0x20) -#define MXR_GRAPHIC_BASE(i) (0x0024 + (i) * 0x20) -#define MXR_GRAPHIC_SPAN(i) (0x0028 + (i) * 0x20) -#define MXR_GRAPHIC_SXY(i) (0x002C + (i) * 0x20) -#define MXR_GRAPHIC_WH(i) (0x0030 + (i) * 0x20) -#define MXR_GRAPHIC_DXY(i) (0x0034 + (i) * 0x20) - -/* - * Bit definition part - */ - -/* generates mask for range of bits */ -#define MXR_MASK(high_bit, low_bit) \ - (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit)) - -#define MXR_MASK_VAL(val, high_bit, low_bit) \ - (((val) << (low_bit)) & MXR_MASK(high_bit, low_bit)) - -/* bits for MXR_STATUS */ -#define MXR_STATUS_16_BURST (1 << 7) -#define MXR_STATUS_BURST_MASK (1 << 7) -#define MXR_STATUS_SYNC_ENABLE (1 << 2) -#define MXR_STATUS_REG_RUN (1 << 0) - -/* bits for MXR_CFG */ -#define MXR_CFG_OUT_YUV444 (0 << 8) -#define MXR_CFG_OUT_RGB888 (1 << 8) -#define MXR_CFG_OUT_MASK (1 << 8) -#define MXR_CFG_DST_SDO (0 << 7) -#define MXR_CFG_DST_HDMI (1 << 7) -#define MXR_CFG_DST_MASK (1 << 7) -#define MXR_CFG_SCAN_HD_720 (0 << 6) -#define MXR_CFG_SCAN_HD_1080 (1 << 6) -#define MXR_CFG_GRP1_ENABLE (1 << 5) -#define MXR_CFG_GRP0_ENABLE (1 << 4) -#define MXR_CFG_VP_ENABLE (1 << 3) -#define MXR_CFG_SCAN_INTERLACE (0 << 2) -#define MXR_CFG_SCAN_PROGRASSIVE (1 << 2) -#define MXR_CFG_SCAN_NTSC (0 << 1) -#define MXR_CFG_SCAN_PAL (1 << 1) -#define MXR_CFG_SCAN_SD (0 << 0) -#define MXR_CFG_SCAN_HD (1 << 0) -#define MXR_CFG_SCAN_MASK 0x47 - -/* bits for MXR_GRAPHICn_CFG */ -#define MXR_GRP_CFG_COLOR_KEY_DISABLE (1 << 21) -#define MXR_GRP_CFG_BLEND_PRE_MUL (1 << 20) -#define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8) -#define MXR_GRP_CFG_FORMAT_MASK MXR_GRP_CFG_FORMAT_VAL(~0) -#define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0) - -/* bits for MXR_GRAPHICn_WH */ -#define MXR_GRP_WH_H_SCALE(x) MXR_MASK_VAL(x, 28, 28) -#define MXR_GRP_WH_V_SCALE(x) MXR_MASK_VAL(x, 12, 12) -#define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16) -#define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0) - -/* bits for MXR_GRAPHICn_SXY */ -#define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16) -#define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0) - -/* bits for MXR_GRAPHICn_DXY */ -#define MXR_GRP_DXY_DX(x) MXR_MASK_VAL(x, 26, 16) -#define MXR_GRP_DXY_DY(x) MXR_MASK_VAL(x, 10, 0) - -/* bits for MXR_INT_EN */ -#define MXR_INT_EN_VSYNC (1 << 11) -#define MXR_INT_EN_ALL (0x0f << 8) - -/* bit for MXR_INT_STATUS */ -#define MXR_INT_CLEAR_VSYNC (1 << 11) -#define MXR_INT_STATUS_VSYNC (1 << 0) - -/* bit for MXR_LAYER_CFG */ -#define MXR_LAYER_CFG_GRP1_VAL(x) MXR_MASK_VAL(x, 11, 8) -#define MXR_LAYER_CFG_GRP0_VAL(x) MXR_MASK_VAL(x, 7, 4) -#define MXR_LAYER_CFG_VP_VAL(x) MXR_MASK_VAL(x, 3, 0) - -#endif /* SAMSUNG_REGS_MIXER_H */ - diff --git a/drivers/media/platform/s5p-tv/regs-sdo.h b/drivers/media/platform/s5p-tv/regs-sdo.h deleted file mode 100644 index 6f22fbfe2f6c..000000000000 --- a/drivers/media/platform/s5p-tv/regs-sdo.h +++ /dev/null @@ -1,63 +0,0 @@ -/* drivers/media/platform/s5p-tv/regs-sdo.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * SDO register description file - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef SAMSUNG_REGS_SDO_H -#define SAMSUNG_REGS_SDO_H - -/* - * Register part - */ - -#define SDO_CLKCON 0x0000 -#define SDO_CONFIG 0x0008 -#define SDO_VBI 0x0014 -#define SDO_DAC 0x003C -#define SDO_CCCON 0x0180 -#define SDO_IRQ 0x0280 -#define SDO_IRQMASK 0x0284 -#define SDO_VERSION 0x03D8 - -/* - * Bit definition part - */ - -/* SDO Clock Control Register (SDO_CLKCON) */ -#define SDO_TVOUT_SW_RESET (1 << 4) -#define SDO_TVOUT_CLOCK_READY (1 << 1) -#define SDO_TVOUT_CLOCK_ON (1 << 0) - -/* SDO Video Standard Configuration Register (SDO_CONFIG) */ -#define SDO_PROGRESSIVE (1 << 4) -#define SDO_NTSC_M 0 -#define SDO_PAL_M 1 -#define SDO_PAL_BGHID 2 -#define SDO_PAL_N 3 -#define SDO_PAL_NC 4 -#define SDO_NTSC_443 8 -#define SDO_PAL_60 9 -#define SDO_STANDARD_MASK 0xf - -/* SDO VBI Configuration Register (SDO_VBI) */ -#define SDO_CVBS_WSS_INS (1 << 14) -#define SDO_CVBS_CLOSED_CAPTION_MASK (3 << 12) - -/* SDO DAC Configuration Register (SDO_DAC) */ -#define SDO_POWER_ON_DAC (1 << 0) - -/* SDO Color Compensation On/Off Control (SDO_CCCON) */ -#define SDO_COMPENSATION_BHS_ADJ_OFF (1 << 4) -#define SDO_COMPENSATION_CVBS_COMP_OFF (1 << 0) - -/* SDO Interrupt Request Register (SDO_IRQ) */ -#define SDO_VSYNC_IRQ_PEND (1 << 0) - -#endif /* SAMSUNG_REGS_SDO_H */ diff --git a/drivers/media/platform/s5p-tv/regs-vp.h b/drivers/media/platform/s5p-tv/regs-vp.h deleted file mode 100644 index 6c63984e11e8..000000000000 --- a/drivers/media/platform/s5p-tv/regs-vp.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Video processor register header file for Samsung Mixer driver - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef SAMSUNG_REGS_VP_H -#define SAMSUNG_REGS_VP_H - -/* - * Register part - */ - -#define VP_ENABLE 0x0000 -#define VP_SRESET 0x0004 -#define VP_SHADOW_UPDATE 0x0008 -#define VP_FIELD_ID 0x000C -#define VP_MODE 0x0010 -#define VP_IMG_SIZE_Y 0x0014 -#define VP_IMG_SIZE_C 0x0018 -#define VP_PER_RATE_CTRL 0x001C -#define VP_TOP_Y_PTR 0x0028 -#define VP_BOT_Y_PTR 0x002C -#define VP_TOP_C_PTR 0x0030 -#define VP_BOT_C_PTR 0x0034 -#define VP_ENDIAN_MODE 0x03CC -#define VP_SRC_H_POSITION 0x0044 -#define VP_SRC_V_POSITION 0x0048 -#define VP_SRC_WIDTH 0x004C -#define VP_SRC_HEIGHT 0x0050 -#define VP_DST_H_POSITION 0x0054 -#define VP_DST_V_POSITION 0x0058 -#define VP_DST_WIDTH 0x005C -#define VP_DST_HEIGHT 0x0060 -#define VP_H_RATIO 0x0064 -#define VP_V_RATIO 0x0068 -#define VP_POLY8_Y0_LL 0x006C -#define VP_POLY4_Y0_LL 0x00EC -#define VP_POLY4_C0_LL 0x012C - -/* - * Bit definition part - */ - -/* generates mask for range of bits */ - -#define VP_MASK(high_bit, low_bit) \ - (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit)) - -#define VP_MASK_VAL(val, high_bit, low_bit) \ - (((val) << (low_bit)) & VP_MASK(high_bit, low_bit)) - - /* VP_ENABLE */ -#define VP_ENABLE_ON (1 << 0) - -/* VP_SRESET */ -#define VP_SRESET_PROCESSING (1 << 0) - -/* VP_SHADOW_UPDATE */ -#define VP_SHADOW_UPDATE_ENABLE (1 << 0) - -/* VP_MODE */ -#define VP_MODE_NV12 (0 << 6) -#define VP_MODE_NV21 (1 << 6) -#define VP_MODE_LINE_SKIP (1 << 5) -#define VP_MODE_MEM_LINEAR (0 << 4) -#define VP_MODE_MEM_TILED (1 << 4) -#define VP_MODE_FMT_MASK (5 << 4) -#define VP_MODE_FIELD_ID_AUTO_TOGGLING (1 << 2) -#define VP_MODE_2D_IPC (1 << 1) - -/* VP_IMG_SIZE_Y */ -/* VP_IMG_SIZE_C */ -#define VP_IMG_HSIZE(x) VP_MASK_VAL(x, 29, 16) -#define VP_IMG_VSIZE(x) VP_MASK_VAL(x, 13, 0) - -/* VP_SRC_H_POSITION */ -#define VP_SRC_H_POSITION_VAL(x) VP_MASK_VAL(x, 14, 4) - -/* VP_ENDIAN_MODE */ -#define VP_ENDIAN_MODE_LITTLE (1 << 0) - -#endif /* SAMSUNG_REGS_VP_H */ diff --git a/drivers/media/platform/s5p-tv/sdo_drv.c b/drivers/media/platform/s5p-tv/sdo_drv.c deleted file mode 100644 index c75d4354d182..000000000000 --- a/drivers/media/platform/s5p-tv/sdo_drv.c +++ /dev/null @@ -1,497 +0,0 @@ -/* - * Samsung Standard Definition Output (SDO) driver - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * - * Tomasz Stanislawski, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundiation. either version 2 of the License, - * or (at your option) any later version - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "regs-sdo.h" - -MODULE_AUTHOR("Tomasz Stanislawski, "); -MODULE_DESCRIPTION("Samsung Standard Definition Output (SDO)"); -MODULE_LICENSE("GPL"); - -#define SDO_DEFAULT_STD V4L2_STD_PAL - -struct sdo_format { - v4l2_std_id id; - /* all modes are 720 pixels wide */ - unsigned int height; - unsigned int cookie; -}; - -struct sdo_device { - /** pointer to device parent */ - struct device *dev; - /** base address of SDO registers */ - void __iomem *regs; - /** SDO interrupt */ - unsigned int irq; - /** DAC source clock */ - struct clk *sclk_dac; - /** DAC clock */ - struct clk *dac; - /** DAC physical interface */ - struct clk *dacphy; - /** clock for control of VPLL */ - struct clk *fout_vpll; - /** vpll rate before sdo stream was on */ - unsigned long vpll_rate; - /** regulator for SDO IP power */ - struct regulator *vdac; - /** regulator for SDO plug detection */ - struct regulator *vdet; - /** subdev used as device interface */ - struct v4l2_subdev sd; - /** current format */ - const struct sdo_format *fmt; -}; - -static inline struct sdo_device *sd_to_sdev(struct v4l2_subdev *sd) -{ - return container_of(sd, struct sdo_device, sd); -} - -static inline -void sdo_write_mask(struct sdo_device *sdev, u32 reg_id, u32 value, u32 mask) -{ - u32 old = readl(sdev->regs + reg_id); - value = (value & mask) | (old & ~mask); - writel(value, sdev->regs + reg_id); -} - -static inline -void sdo_write(struct sdo_device *sdev, u32 reg_id, u32 value) -{ - writel(value, sdev->regs + reg_id); -} - -static inline -u32 sdo_read(struct sdo_device *sdev, u32 reg_id) -{ - return readl(sdev->regs + reg_id); -} - -static irqreturn_t sdo_irq_handler(int irq, void *dev_data) -{ - struct sdo_device *sdev = dev_data; - - /* clear interrupt */ - sdo_write_mask(sdev, SDO_IRQ, ~0, SDO_VSYNC_IRQ_PEND); - return IRQ_HANDLED; -} - -static void sdo_reg_debug(struct sdo_device *sdev) -{ -#define DBGREG(reg_id) \ - dev_info(sdev->dev, #reg_id " = %08x\n", \ - sdo_read(sdev, reg_id)) - - DBGREG(SDO_CLKCON); - DBGREG(SDO_CONFIG); - DBGREG(SDO_VBI); - DBGREG(SDO_DAC); - DBGREG(SDO_IRQ); - DBGREG(SDO_IRQMASK); - DBGREG(SDO_VERSION); -} - -static const struct sdo_format sdo_format[] = { - { V4L2_STD_PAL_N, .height = 576, .cookie = SDO_PAL_N }, - { V4L2_STD_PAL_Nc, .height = 576, .cookie = SDO_PAL_NC }, - { V4L2_STD_PAL_M, .height = 480, .cookie = SDO_PAL_M }, - { V4L2_STD_PAL_60, .height = 480, .cookie = SDO_PAL_60 }, - { V4L2_STD_NTSC_443, .height = 480, .cookie = SDO_NTSC_443 }, - { V4L2_STD_PAL, .height = 576, .cookie = SDO_PAL_BGHID }, - { V4L2_STD_NTSC_M, .height = 480, .cookie = SDO_NTSC_M }, -}; - -static const struct sdo_format *sdo_find_format(v4l2_std_id id) -{ - int i; - for (i = 0; i < ARRAY_SIZE(sdo_format); ++i) - if (sdo_format[i].id & id) - return &sdo_format[i]; - return NULL; -} - -static int sdo_g_tvnorms_output(struct v4l2_subdev *sd, v4l2_std_id *std) -{ - *std = V4L2_STD_NTSC_M | V4L2_STD_PAL_M | V4L2_STD_PAL | - V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | - V4L2_STD_NTSC_443 | V4L2_STD_PAL_60; - return 0; -} - -static int sdo_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std) -{ - struct sdo_device *sdev = sd_to_sdev(sd); - const struct sdo_format *fmt; - fmt = sdo_find_format(std); - if (fmt == NULL) - return -EINVAL; - sdev->fmt = fmt; - return 0; -} - -static int sdo_g_std_output(struct v4l2_subdev *sd, v4l2_std_id *std) -{ - *std = sd_to_sdev(sd)->fmt->id; - return 0; -} - -static int sdo_get_fmt(struct v4l2_subdev *sd, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_format *format) -{ - struct v4l2_mbus_framefmt *fmt = &format->format; - struct sdo_device *sdev = sd_to_sdev(sd); - - if (!sdev->fmt) - return -ENXIO; - if (format->pad) - return -EINVAL; - /* all modes are 720 pixels wide */ - fmt->width = 720; - fmt->height = sdev->fmt->height; - fmt->code = MEDIA_BUS_FMT_FIXED; - fmt->field = V4L2_FIELD_INTERLACED; - fmt->colorspace = V4L2_COLORSPACE_JPEG; - return 0; -} - -static int sdo_s_power(struct v4l2_subdev *sd, int on) -{ - struct sdo_device *sdev = sd_to_sdev(sd); - struct device *dev = sdev->dev; - int ret; - - dev_info(dev, "sdo_s_power(%d)\n", on); - - if (on) - ret = pm_runtime_get_sync(dev); - else - ret = pm_runtime_put_sync(dev); - - /* only values < 0 indicate errors */ - return ret < 0 ? ret : 0; -} - -static int sdo_streamon(struct sdo_device *sdev) -{ - int ret; - - /* set proper clock for Timing Generator */ - sdev->vpll_rate = clk_get_rate(sdev->fout_vpll); - ret = clk_set_rate(sdev->fout_vpll, 54000000); - if (ret < 0) { - dev_err(sdev->dev, "Failed to set vpll rate\n"); - return ret; - } - dev_info(sdev->dev, "fout_vpll.rate = %lu\n", - clk_get_rate(sdev->fout_vpll)); - /* enable clock in SDO */ - sdo_write_mask(sdev, SDO_CLKCON, ~0, SDO_TVOUT_CLOCK_ON); - ret = clk_prepare_enable(sdev->dacphy); - if (ret < 0) { - dev_err(sdev->dev, "clk_prepare_enable(dacphy) failed\n"); - goto fail; - } - /* enable DAC */ - sdo_write_mask(sdev, SDO_DAC, ~0, SDO_POWER_ON_DAC); - sdo_reg_debug(sdev); - return 0; - -fail: - sdo_write_mask(sdev, SDO_CLKCON, 0, SDO_TVOUT_CLOCK_ON); - clk_set_rate(sdev->fout_vpll, sdev->vpll_rate); - return ret; -} - -static int sdo_streamoff(struct sdo_device *sdev) -{ - int tries; - - sdo_write_mask(sdev, SDO_DAC, 0, SDO_POWER_ON_DAC); - clk_disable_unprepare(sdev->dacphy); - sdo_write_mask(sdev, SDO_CLKCON, 0, SDO_TVOUT_CLOCK_ON); - for (tries = 100; tries; --tries) { - if (sdo_read(sdev, SDO_CLKCON) & SDO_TVOUT_CLOCK_READY) - break; - mdelay(1); - } - if (tries == 0) - dev_err(sdev->dev, "failed to stop streaming\n"); - clk_set_rate(sdev->fout_vpll, sdev->vpll_rate); - return tries ? 0 : -EIO; -} - -static int sdo_s_stream(struct v4l2_subdev *sd, int on) -{ - struct sdo_device *sdev = sd_to_sdev(sd); - return on ? sdo_streamon(sdev) : sdo_streamoff(sdev); -} - -static const struct v4l2_subdev_core_ops sdo_sd_core_ops = { - .s_power = sdo_s_power, -}; - -static const struct v4l2_subdev_video_ops sdo_sd_video_ops = { - .s_std_output = sdo_s_std_output, - .g_std_output = sdo_g_std_output, - .g_tvnorms_output = sdo_g_tvnorms_output, - .s_stream = sdo_s_stream, -}; - -static const struct v4l2_subdev_pad_ops sdo_sd_pad_ops = { - .get_fmt = sdo_get_fmt, -}; - -static const struct v4l2_subdev_ops sdo_sd_ops = { - .core = &sdo_sd_core_ops, - .video = &sdo_sd_video_ops, - .pad = &sdo_sd_pad_ops, -}; - -static int sdo_runtime_suspend(struct device *dev) -{ - struct v4l2_subdev *sd = dev_get_drvdata(dev); - struct sdo_device *sdev = sd_to_sdev(sd); - - dev_info(dev, "suspend\n"); - regulator_disable(sdev->vdet); - regulator_disable(sdev->vdac); - clk_disable_unprepare(sdev->sclk_dac); - return 0; -} - -static int sdo_runtime_resume(struct device *dev) -{ - struct v4l2_subdev *sd = dev_get_drvdata(dev); - struct sdo_device *sdev = sd_to_sdev(sd); - int ret; - - dev_info(dev, "resume\n"); - - ret = clk_prepare_enable(sdev->sclk_dac); - if (ret < 0) - return ret; - - ret = regulator_enable(sdev->vdac); - if (ret < 0) - goto dac_clk_dis; - - ret = regulator_enable(sdev->vdet); - if (ret < 0) - goto vdac_r_dis; - - /* software reset */ - sdo_write_mask(sdev, SDO_CLKCON, ~0, SDO_TVOUT_SW_RESET); - mdelay(10); - sdo_write_mask(sdev, SDO_CLKCON, 0, SDO_TVOUT_SW_RESET); - - /* setting TV mode */ - sdo_write_mask(sdev, SDO_CONFIG, sdev->fmt->cookie, SDO_STANDARD_MASK); - /* XXX: forcing interlaced mode using undocumented bit */ - sdo_write_mask(sdev, SDO_CONFIG, 0, SDO_PROGRESSIVE); - /* turn all VBI off */ - sdo_write_mask(sdev, SDO_VBI, 0, SDO_CVBS_WSS_INS | - SDO_CVBS_CLOSED_CAPTION_MASK); - /* turn all post processing off */ - sdo_write_mask(sdev, SDO_CCCON, ~0, SDO_COMPENSATION_BHS_ADJ_OFF | - SDO_COMPENSATION_CVBS_COMP_OFF); - sdo_reg_debug(sdev); - return 0; - -vdac_r_dis: - regulator_disable(sdev->vdac); -dac_clk_dis: - clk_disable_unprepare(sdev->sclk_dac); - return ret; -} - -static const struct dev_pm_ops sdo_pm_ops = { - .runtime_suspend = sdo_runtime_suspend, - .runtime_resume = sdo_runtime_resume, -}; - -static int sdo_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct sdo_device *sdev; - struct resource *res; - int ret = 0; - struct clk *sclk_vpll; - - dev_info(dev, "probe start\n"); - sdev = devm_kzalloc(&pdev->dev, sizeof(*sdev), GFP_KERNEL); - if (!sdev) { - dev_err(dev, "not enough memory.\n"); - ret = -ENOMEM; - goto fail; - } - sdev->dev = dev; - - /* mapping registers */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res == NULL) { - dev_err(dev, "get memory resource failed.\n"); - ret = -ENXIO; - goto fail; - } - - sdev->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); - if (sdev->regs == NULL) { - dev_err(dev, "register mapping failed.\n"); - ret = -ENXIO; - goto fail; - } - - /* acquiring interrupt */ - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (res == NULL) { - dev_err(dev, "get interrupt resource failed.\n"); - ret = -ENXIO; - goto fail; - } - ret = devm_request_irq(&pdev->dev, res->start, sdo_irq_handler, 0, - "s5p-sdo", sdev); - if (ret) { - dev_err(dev, "request interrupt failed.\n"); - goto fail; - } - sdev->irq = res->start; - - /* acquire clocks */ - sdev->sclk_dac = clk_get(dev, "sclk_dac"); - if (IS_ERR(sdev->sclk_dac)) { - dev_err(dev, "failed to get clock 'sclk_dac'\n"); - ret = PTR_ERR(sdev->sclk_dac); - goto fail; - } - sdev->dac = clk_get(dev, "dac"); - if (IS_ERR(sdev->dac)) { - dev_err(dev, "failed to get clock 'dac'\n"); - ret = PTR_ERR(sdev->dac); - goto fail_sclk_dac; - } - sdev->dacphy = clk_get(dev, "dacphy"); - if (IS_ERR(sdev->dacphy)) { - dev_err(dev, "failed to get clock 'dacphy'\n"); - ret = PTR_ERR(sdev->dacphy); - goto fail_dac; - } - sclk_vpll = clk_get(dev, "sclk_vpll"); - if (IS_ERR(sclk_vpll)) { - dev_err(dev, "failed to get clock 'sclk_vpll'\n"); - ret = PTR_ERR(sclk_vpll); - goto fail_dacphy; - } - clk_set_parent(sdev->sclk_dac, sclk_vpll); - clk_put(sclk_vpll); - sdev->fout_vpll = clk_get(dev, "fout_vpll"); - if (IS_ERR(sdev->fout_vpll)) { - dev_err(dev, "failed to get clock 'fout_vpll'\n"); - ret = PTR_ERR(sdev->fout_vpll); - goto fail_dacphy; - } - dev_info(dev, "fout_vpll.rate = %lu\n", clk_get_rate(sclk_vpll)); - - /* acquire regulator */ - sdev->vdac = devm_regulator_get(dev, "vdd33a_dac"); - if (IS_ERR(sdev->vdac)) { - dev_err(dev, "failed to get regulator 'vdac'\n"); - ret = PTR_ERR(sdev->vdac); - goto fail_fout_vpll; - } - sdev->vdet = devm_regulator_get(dev, "vdet"); - if (IS_ERR(sdev->vdet)) { - dev_err(dev, "failed to get regulator 'vdet'\n"); - ret = PTR_ERR(sdev->vdet); - goto fail_fout_vpll; - } - - /* enable gate for dac clock, because mixer uses it */ - ret = clk_prepare_enable(sdev->dac); - if (ret < 0) { - dev_err(dev, "clk_prepare_enable(dac) failed\n"); - goto fail_fout_vpll; - } - - /* configure power management */ - pm_runtime_enable(dev); - - /* configuration of interface subdevice */ - v4l2_subdev_init(&sdev->sd, &sdo_sd_ops); - sdev->sd.owner = THIS_MODULE; - strlcpy(sdev->sd.name, "s5p-sdo", sizeof(sdev->sd.name)); - - /* set default format */ - sdev->fmt = sdo_find_format(SDO_DEFAULT_STD); - BUG_ON(sdev->fmt == NULL); - - /* keeping subdev in device's private for use by other drivers */ - dev_set_drvdata(dev, &sdev->sd); - - dev_info(dev, "probe succeeded\n"); - return 0; - -fail_fout_vpll: - clk_put(sdev->fout_vpll); -fail_dacphy: - clk_put(sdev->dacphy); -fail_dac: - clk_put(sdev->dac); -fail_sclk_dac: - clk_put(sdev->sclk_dac); -fail: - dev_info(dev, "probe failed\n"); - return ret; -} - -static int sdo_remove(struct platform_device *pdev) -{ - struct v4l2_subdev *sd = dev_get_drvdata(&pdev->dev); - struct sdo_device *sdev = sd_to_sdev(sd); - - pm_runtime_disable(&pdev->dev); - clk_disable_unprepare(sdev->dac); - clk_put(sdev->fout_vpll); - clk_put(sdev->dacphy); - clk_put(sdev->dac); - clk_put(sdev->sclk_dac); - - dev_info(&pdev->dev, "remove successful\n"); - return 0; -} - -static struct platform_driver sdo_driver __refdata = { - .probe = sdo_probe, - .remove = sdo_remove, - .driver = { - .name = "s5p-sdo", - .pm = &sdo_pm_ops, - } -}; - -module_platform_driver(sdo_driver); diff --git a/drivers/media/platform/s5p-tv/sii9234_drv.c b/drivers/media/platform/s5p-tv/sii9234_drv.c deleted file mode 100644 index 0a97f9ab4f76..000000000000 --- a/drivers/media/platform/s5p-tv/sii9234_drv.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - * Samsung MHL interface driver - * - * Copyright (C) 2011 Samsung Electronics Co.Ltd - * Author: Tomasz Stanislawski - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -MODULE_AUTHOR("Tomasz Stanislawski "); -MODULE_DESCRIPTION("Samsung MHL interface driver"); -MODULE_LICENSE("GPL"); - -struct sii9234_context { - struct i2c_client *client; - struct regulator *power; - int gpio_n_reset; - struct v4l2_subdev sd; -}; - -static inline struct sii9234_context *sd_to_context(struct v4l2_subdev *sd) -{ - return container_of(sd, struct sii9234_context, sd); -} - -static inline int sii9234_readb(struct i2c_client *client, int addr) -{ - return i2c_smbus_read_byte_data(client, addr); -} - -static inline int sii9234_writeb(struct i2c_client *client, int addr, int value) -{ - return i2c_smbus_write_byte_data(client, addr, value); -} - -static inline int sii9234_writeb_mask(struct i2c_client *client, int addr, - int value, int mask) -{ - int ret; - - ret = i2c_smbus_read_byte_data(client, addr); - if (ret < 0) - return ret; - ret = (ret & ~mask) | (value & mask); - return i2c_smbus_write_byte_data(client, addr, ret); -} - -static inline int sii9234_readb_idx(struct i2c_client *client, int addr) -{ - int ret; - ret = i2c_smbus_write_byte_data(client, 0xbc, addr >> 8); - if (ret < 0) - return ret; - ret = i2c_smbus_write_byte_data(client, 0xbd, addr & 0xff); - if (ret < 0) - return ret; - return i2c_smbus_read_byte_data(client, 0xbe); -} - -static inline int sii9234_writeb_idx(struct i2c_client *client, int addr, - int value) -{ - int ret; - ret = i2c_smbus_write_byte_data(client, 0xbc, addr >> 8); - if (ret < 0) - return ret; - ret = i2c_smbus_write_byte_data(client, 0xbd, addr & 0xff); - if (ret < 0) - return ret; - ret = i2c_smbus_write_byte_data(client, 0xbe, value); - return ret; -} - -static inline int sii9234_writeb_idx_mask(struct i2c_client *client, int addr, - int value, int mask) -{ - int ret; - - ret = sii9234_readb_idx(client, addr); - if (ret < 0) - return ret; - ret = (ret & ~mask) | (value & mask); - return sii9234_writeb_idx(client, addr, ret); -} - -static int sii9234_reset(struct sii9234_context *ctx) -{ - struct i2c_client *client = ctx->client; - struct device *dev = &client->dev; - int ret, tries; - - gpio_direction_output(ctx->gpio_n_reset, 1); - mdelay(1); - gpio_direction_output(ctx->gpio_n_reset, 0); - mdelay(1); - gpio_direction_output(ctx->gpio_n_reset, 1); - mdelay(1); - - /* going to TTPI mode */ - ret = sii9234_writeb(client, 0xc7, 0); - if (ret < 0) { - dev_err(dev, "failed to set TTPI mode\n"); - return ret; - } - for (tries = 0; tries < 100 ; ++tries) { - ret = sii9234_readb(client, 0x1b); - if (ret > 0) - break; - if (ret < 0) { - dev_err(dev, "failed to reset device\n"); - return -EIO; - } - mdelay(1); - } - if (tries == 100) { - dev_err(dev, "maximal number of tries reached\n"); - return -EIO; - } - - return 0; -} - -static int sii9234_verify_version(struct i2c_client *client) -{ - struct device *dev = &client->dev; - int family, rev, tpi_rev, dev_id, sub_id, hdcp, id; - - family = sii9234_readb(client, 0x1b); - rev = sii9234_readb(client, 0x1c) & 0x0f; - tpi_rev = sii9234_readb(client, 0x1d) & 0x7f; - dev_id = sii9234_readb_idx(client, 0x0103); - sub_id = sii9234_readb_idx(client, 0x0102); - hdcp = sii9234_readb(client, 0x30); - - if (family < 0 || rev < 0 || tpi_rev < 0 || dev_id < 0 || - sub_id < 0 || hdcp < 0) { - dev_err(dev, "failed to read chip's version\n"); - return -EIO; - } - - id = (dev_id << 8) | sub_id; - - dev_info(dev, "chip: SiL%02x family: %02x, rev: %02x\n", - id, family, rev); - dev_info(dev, "tpi_rev:%02x, hdcp: %02x\n", tpi_rev, hdcp); - if (id != 0x9234) { - dev_err(dev, "not supported chip\n"); - return -ENODEV; - } - - return 0; -} - -static u8 data[][3] = { -/* setup from driver created by doonsoo45.kim */ - { 0x01, 0x05, 0x04 }, /* Enable Auto soft reset on SCDT = 0 */ - { 0x01, 0x08, 0x35 }, /* Power Up TMDS Tx Core */ - { 0x01, 0x0d, 0x1c }, /* HDMI Transcode mode enable */ - { 0x01, 0x2b, 0x01 }, /* Enable HDCP Compliance workaround */ - { 0x01, 0x79, 0x40 }, /* daniel test...MHL_INT */ - { 0x01, 0x80, 0x34 }, /* Enable Rx PLL Clock Value */ - { 0x01, 0x90, 0x27 }, /* Enable CBUS discovery */ - { 0x01, 0x91, 0xe5 }, /* Skip RGND detection */ - { 0x01, 0x92, 0x46 }, /* Force MHD mode */ - { 0x01, 0x93, 0xdc }, /* Disable CBUS pull-up during RGND measurement */ - { 0x01, 0x94, 0x66 }, /* 1.8V CBUS VTH & GND threshold */ - { 0x01, 0x95, 0x31 }, /* RGND block & single discovery attempt */ - { 0x01, 0x96, 0x22 }, /* use 1K and 2K setting */ - { 0x01, 0xa0, 0x10 }, /* SIMG: Term mode */ - { 0x01, 0xa1, 0xfc }, /* Disable internal Mobile HD driver */ - { 0x01, 0xa3, 0xfa }, /* SIMG: Output Swing default EB, 3x Clk Mult */ - { 0x01, 0xa5, 0x80 }, /* SIMG: RGND Hysterisis, 3x mode for Beast */ - { 0x01, 0xa6, 0x0c }, /* SIMG: Swing Offset */ - { 0x02, 0x3d, 0x3f }, /* Power up CVCC 1.2V core */ - { 0x03, 0x00, 0x00 }, /* SIMG: correcting HW default */ - { 0x03, 0x11, 0x01 }, /* Enable TxPLL Clock */ - { 0x03, 0x12, 0x15 }, /* Enable Tx Clock Path & Equalizer */ - { 0x03, 0x13, 0x60 }, /* SIMG: Set termination value */ - { 0x03, 0x14, 0xf0 }, /* SIMG: Change CKDT level */ - { 0x03, 0x17, 0x07 }, /* SIMG: PLL Calrefsel */ - { 0x03, 0x1a, 0x20 }, /* VCO Cal */ - { 0x03, 0x22, 0xe0 }, /* SIMG: Auto EQ */ - { 0x03, 0x23, 0xc0 }, /* SIMG: Auto EQ */ - { 0x03, 0x24, 0xa0 }, /* SIMG: Auto EQ */ - { 0x03, 0x25, 0x80 }, /* SIMG: Auto EQ */ - { 0x03, 0x26, 0x60 }, /* SIMG: Auto EQ */ - { 0x03, 0x27, 0x40 }, /* SIMG: Auto EQ */ - { 0x03, 0x28, 0x20 }, /* SIMG: Auto EQ */ - { 0x03, 0x29, 0x00 }, /* SIMG: Auto EQ */ - { 0x03, 0x31, 0x0b }, /* SIMG: Rx PLL BW value from I2C BW ~ 4MHz */ - { 0x03, 0x45, 0x06 }, /* SIMG: DPLL Mode */ - { 0x03, 0x4b, 0x06 }, /* SIMG: Correcting HW default */ - { 0x03, 0x4c, 0xa0 }, /* Manual zone control */ - { 0x03, 0x4d, 0x02 }, /* SIMG: PLL Mode Value (order is important) */ -}; - -static int sii9234_set_internal(struct sii9234_context *ctx) -{ - struct i2c_client *client = ctx->client; - int i, ret; - - for (i = 0; i < ARRAY_SIZE(data); ++i) { - int addr = (data[i][0] << 8) | data[i][1]; - ret = sii9234_writeb_idx(client, addr, data[i][2]); - if (ret < 0) - return ret; - } - return 0; -} - -static int sii9234_runtime_suspend(struct device *dev) -{ - struct v4l2_subdev *sd = dev_get_drvdata(dev); - struct sii9234_context *ctx = sd_to_context(sd); - struct i2c_client *client = ctx->client; - - dev_info(dev, "suspend start\n"); - - sii9234_writeb_mask(client, 0x1e, 3, 3); - regulator_disable(ctx->power); - - return 0; -} - -static int sii9234_runtime_resume(struct device *dev) -{ - struct v4l2_subdev *sd = dev_get_drvdata(dev); - struct sii9234_context *ctx = sd_to_context(sd); - struct i2c_client *client = ctx->client; - int ret; - - dev_info(dev, "resume start\n"); - ret = regulator_enable(ctx->power); - if (ret < 0) - return ret; - - ret = sii9234_reset(ctx); - if (ret) - goto fail; - - /* enable tpi */ - ret = sii9234_writeb_mask(client, 0x1e, 1, 0); - if (ret < 0) - goto fail; - ret = sii9234_set_internal(ctx); - if (ret < 0) - goto fail; - - return 0; - -fail: - dev_err(dev, "failed to resume\n"); - regulator_disable(ctx->power); - - return ret; -} - -static const struct dev_pm_ops sii9234_pm_ops = { - .runtime_suspend = sii9234_runtime_suspend, - .runtime_resume = sii9234_runtime_resume, -}; - -static int sii9234_s_power(struct v4l2_subdev *sd, int on) -{ - struct sii9234_context *ctx = sd_to_context(sd); - int ret; - - if (on) - ret = pm_runtime_get_sync(&ctx->client->dev); - else - ret = pm_runtime_put(&ctx->client->dev); - /* only values < 0 indicate errors */ - return ret < 0 ? ret : 0; -} - -static int sii9234_s_stream(struct v4l2_subdev *sd, int enable) -{ - struct sii9234_context *ctx = sd_to_context(sd); - - /* (dis/en)able TDMS output */ - sii9234_writeb_mask(ctx->client, 0x1a, enable ? 0 : ~0 , 1 << 4); - return 0; -} - -static const struct v4l2_subdev_core_ops sii9234_core_ops = { - .s_power = sii9234_s_power, -}; - -static const struct v4l2_subdev_video_ops sii9234_video_ops = { - .s_stream = sii9234_s_stream, -}; - -static const struct v4l2_subdev_ops sii9234_ops = { - .core = &sii9234_core_ops, - .video = &sii9234_video_ops, -}; - -static int sii9234_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct device *dev = &client->dev; - struct sii9234_platform_data *pdata = dev->platform_data; - struct sii9234_context *ctx; - int ret; - - ctx = devm_kzalloc(&client->dev, sizeof(*ctx), GFP_KERNEL); - if (!ctx) { - dev_err(dev, "out of memory\n"); - ret = -ENOMEM; - goto fail; - } - ctx->client = client; - - ctx->power = devm_regulator_get(dev, "hdmi-en"); - if (IS_ERR(ctx->power)) { - dev_err(dev, "failed to acquire regulator hdmi-en\n"); - return PTR_ERR(ctx->power); - } - - ctx->gpio_n_reset = pdata->gpio_n_reset; - ret = devm_gpio_request(dev, ctx->gpio_n_reset, "MHL_RST"); - if (ret) { - dev_err(dev, "failed to acquire MHL_RST gpio\n"); - return ret; - } - - v4l2_i2c_subdev_init(&ctx->sd, client, &sii9234_ops); - - pm_runtime_enable(dev); - - /* enable device */ - ret = pm_runtime_get_sync(dev); - if (ret) - goto fail_pm; - - /* verify chip version */ - ret = sii9234_verify_version(client); - if (ret) - goto fail_pm_get; - - /* stop processing */ - pm_runtime_put(dev); - - dev_info(dev, "probe successful\n"); - - return 0; - -fail_pm_get: - pm_runtime_put_sync(dev); - -fail_pm: - pm_runtime_disable(dev); - -fail: - dev_err(dev, "probe failed\n"); - - return ret; -} - -static int sii9234_remove(struct i2c_client *client) -{ - struct device *dev = &client->dev; - - pm_runtime_disable(dev); - - dev_info(dev, "remove successful\n"); - - return 0; -} - - -static const struct i2c_device_id sii9234_id[] = { - { "SII9234", 0 }, - { }, -}; - -MODULE_DEVICE_TABLE(i2c, sii9234_id); -static struct i2c_driver sii9234_driver = { - .driver = { - .name = "sii9234", - .pm = &sii9234_pm_ops, - }, - .probe = sii9234_probe, - .remove = sii9234_remove, - .id_table = sii9234_id, -}; - -module_i2c_driver(sii9234_driver); -- cgit v1.2.3 From 34d1324edd3154105b7a3985c6c4384d602f2ab6 Mon Sep 17 00:00:00 2001 From: Andrey Utkin Date: Wed, 20 Jul 2016 10:07:12 -0300 Subject: [media] pci: Add tw5864 driver Support for boards based on Techwell TW5864 chip which provides multichannel video & audio grabbing and encoding (H.264, MJPEG, ADPCM G.726). This submission implements only H.264 encoding of all channels at D1 resolution. Thanks to Mark Thompson for help, and for contribution of H.264 startcode emulation prevention code. Signed-off-by: Andrey Utkin Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 8 + drivers/media/pci/Kconfig | 1 + drivers/media/pci/Makefile | 1 + drivers/media/pci/tw5864/Kconfig | 11 + drivers/media/pci/tw5864/Makefile | 3 + drivers/media/pci/tw5864/tw5864-core.c | 359 ++++++ drivers/media/pci/tw5864/tw5864-h264.c | 259 ++++ drivers/media/pci/tw5864/tw5864-reg.h | 2133 +++++++++++++++++++++++++++++++ drivers/media/pci/tw5864/tw5864-util.c | 37 + drivers/media/pci/tw5864/tw5864-video.c | 1514 ++++++++++++++++++++++ drivers/media/pci/tw5864/tw5864.h | 205 +++ 11 files changed, 4531 insertions(+) create mode 100644 drivers/media/pci/tw5864/Kconfig create mode 100644 drivers/media/pci/tw5864/Makefile create mode 100644 drivers/media/pci/tw5864/tw5864-core.c create mode 100644 drivers/media/pci/tw5864/tw5864-h264.c create mode 100644 drivers/media/pci/tw5864/tw5864-reg.h create mode 100644 drivers/media/pci/tw5864/tw5864-util.c create mode 100644 drivers/media/pci/tw5864/tw5864-video.c create mode 100644 drivers/media/pci/tw5864/tw5864.h (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 998fd6b767f2..0a16a820fd56 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11839,6 +11839,14 @@ T: git git://linuxtv.org/media_tree.git S: Odd fixes F: drivers/media/usb/tm6000/ +TW5864 VIDEO4LINUX DRIVER +M: Bluecherry Maintainers +M: Andrey Utkin +M: Andrey Utkin +L: linux-media@vger.kernel.org +S: Supported +F: drivers/media/pci/tw5864/ + TW68 VIDEO4LINUX DRIVER M: Hans Verkuil L: linux-media@vger.kernel.org diff --git a/drivers/media/pci/Kconfig b/drivers/media/pci/Kconfig index 4f6467fbaeb4..da28e68c87d8 100644 --- a/drivers/media/pci/Kconfig +++ b/drivers/media/pci/Kconfig @@ -13,6 +13,7 @@ if MEDIA_CAMERA_SUPPORT source "drivers/media/pci/meye/Kconfig" source "drivers/media/pci/solo6x10/Kconfig" source "drivers/media/pci/sta2x11/Kconfig" +source "drivers/media/pci/tw5864/Kconfig" source "drivers/media/pci/tw68/Kconfig" source "drivers/media/pci/tw686x/Kconfig" source "drivers/media/pci/zoran/Kconfig" diff --git a/drivers/media/pci/Makefile b/drivers/media/pci/Makefile index 2e54c36441f7..a7e8af0f64a7 100644 --- a/drivers/media/pci/Makefile +++ b/drivers/media/pci/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_VIDEO_MEYE) += meye/ obj-$(CONFIG_STA2X11_VIP) += sta2x11/ obj-$(CONFIG_VIDEO_SOLO6X10) += solo6x10/ obj-$(CONFIG_VIDEO_COBALT) += cobalt/ +obj-$(CONFIG_VIDEO_TW5864) += tw5864/ diff --git a/drivers/media/pci/tw5864/Kconfig b/drivers/media/pci/tw5864/Kconfig new file mode 100644 index 000000000000..760fb11dfeae --- /dev/null +++ b/drivers/media/pci/tw5864/Kconfig @@ -0,0 +1,11 @@ +config VIDEO_TW5864 + tristate "Techwell TW5864 video/audio grabber and encoder" + depends on VIDEO_DEV && PCI && VIDEO_V4L2 + select VIDEOBUF2_DMA_CONTIG + ---help--- + Support for boards based on Techwell TW5864 chip which provides + multichannel video & audio grabbing and encoding (H.264, MJPEG, + ADPCM G.726). + + To compile this driver as a module, choose M here: the + module will be called tw5864. diff --git a/drivers/media/pci/tw5864/Makefile b/drivers/media/pci/tw5864/Makefile new file mode 100644 index 000000000000..4fc8b3b1a45a --- /dev/null +++ b/drivers/media/pci/tw5864/Makefile @@ -0,0 +1,3 @@ +tw5864-objs := tw5864-core.o tw5864-video.o tw5864-h264.o tw5864-util.o + +obj-$(CONFIG_VIDEO_TW5864) += tw5864.o diff --git a/drivers/media/pci/tw5864/tw5864-core.c b/drivers/media/pci/tw5864/tw5864-core.c new file mode 100644 index 000000000000..440cd7bb8d04 --- /dev/null +++ b/drivers/media/pci/tw5864/tw5864-core.c @@ -0,0 +1,359 @@ +/* + * TW5864 driver - core functions + * + * Copyright (C) 2016 Bluecherry, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tw5864.h" +#include "tw5864-reg.h" + +MODULE_DESCRIPTION("V4L2 driver module for tw5864-based multimedia capture & encoding devices"); +MODULE_AUTHOR("Bluecherry Maintainers "); +MODULE_AUTHOR("Andrey Utkin "); +MODULE_LICENSE("GPL"); + +/* + * BEWARE OF KNOWN ISSUES WITH VIDEO QUALITY + * + * This driver was developed by Bluecherry LLC by deducing behaviour of + * original manufacturer's driver, from both source code and execution traces. + * It is known that there are some artifacts on output video with this driver: + * - on all known hardware samples: random pixels of wrong color (mostly + * white, red or blue) appearing and disappearing on sequences of P-frames; + * - on some hardware samples (known with H.264 core version e006:2800): + * total madness on P-frames: blocks of wrong luminance; blocks of wrong + * colors "creeping" across the picture. + * There is a workaround for both issues: avoid P-frames by setting GOP size + * to 1. To do that, run this command on device files created by this driver: + * + * v4l2-ctl --device /dev/videoX --set-ctrl=video_gop_size=1 + * + * These issues are not decoding errors; all produced H.264 streams are decoded + * properly. Streams without P-frames don't have these artifacts so it's not + * analog-to-digital conversion issues nor internal memory errors; we conclude + * it's internal H.264 encoder issues. + * We cannot even check the original driver's behaviour because it has never + * worked properly at all in our development environment. So these issues may + * be actually related to firmware or hardware. However it may be that there's + * just some more register settings missing in the driver which would please + * the hardware. + * Manufacturer didn't help much on our inquiries, but feel free to disturb + * again the support of Intersil (owner of former Techwell). + */ + +/* take first free /dev/videoX indexes by default */ +static unsigned int video_nr[] = {[0 ... (TW5864_INPUTS - 1)] = -1 }; + +module_param_array(video_nr, int, NULL, 0444); +MODULE_PARM_DESC(video_nr, "video devices numbers array"); + +/* + * Please add any new PCI IDs to: http://pci-ids.ucw.cz. This keeps + * the PCI ID database up to date. Note that the entries must be + * added under vendor 0x1797 (Techwell Inc.) as subsystem IDs. + */ +static const struct pci_device_id tw5864_pci_tbl[] = { + {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_TECHWELL_5864)}, + {0,} +}; + +void tw5864_irqmask_apply(struct tw5864_dev *dev) +{ + tw_writel(TW5864_INTR_ENABLE_L, dev->irqmask & 0xffff); + tw_writel(TW5864_INTR_ENABLE_H, (dev->irqmask >> 16)); +} + +static void tw5864_interrupts_disable(struct tw5864_dev *dev) +{ + unsigned long flags; + + spin_lock_irqsave(&dev->slock, flags); + dev->irqmask = 0; + tw5864_irqmask_apply(dev); + spin_unlock_irqrestore(&dev->slock, flags); +} + +static void tw5864_timer_isr(struct tw5864_dev *dev); +static void tw5864_h264_isr(struct tw5864_dev *dev); + +static irqreturn_t tw5864_isr(int irq, void *dev_id) +{ + struct tw5864_dev *dev = dev_id; + u32 status; + + status = tw_readl(TW5864_INTR_STATUS_L) | + tw_readl(TW5864_INTR_STATUS_H) << 16; + if (!status) + return IRQ_NONE; + + tw_writel(TW5864_INTR_CLR_L, 0xffff); + tw_writel(TW5864_INTR_CLR_H, 0xffff); + + if (status & TW5864_INTR_VLC_DONE) + tw5864_h264_isr(dev); + + if (status & TW5864_INTR_TIMER) + tw5864_timer_isr(dev); + + if (!(status & (TW5864_INTR_TIMER | TW5864_INTR_VLC_DONE))) { + dev_dbg(&dev->pci->dev, "Unknown interrupt, status 0x%08X\n", + status); + } + + return IRQ_HANDLED; +} + +static void tw5864_h264_isr(struct tw5864_dev *dev) +{ + int channel = tw_readl(TW5864_DSP) & TW5864_DSP_ENC_CHN; + struct tw5864_input *input = &dev->inputs[channel]; + int cur_frame_index, next_frame_index; + struct tw5864_h264_frame *cur_frame, *next_frame; + unsigned long flags; + + spin_lock_irqsave(&dev->slock, flags); + + cur_frame_index = dev->h264_buf_w_index; + next_frame_index = (cur_frame_index + 1) % H264_BUF_CNT; + cur_frame = &dev->h264_buf[cur_frame_index]; + next_frame = &dev->h264_buf[next_frame_index]; + + if (next_frame_index != dev->h264_buf_r_index) { + cur_frame->vlc_len = tw_readl(TW5864_VLC_LENGTH) << 2; + cur_frame->checksum = tw_readl(TW5864_VLC_CRC_REG); + cur_frame->input = input; + cur_frame->timestamp = ktime_get_ns(); + cur_frame->seqno = input->frame_seqno; + cur_frame->gop_seqno = input->frame_gop_seqno; + + dev->h264_buf_w_index = next_frame_index; + tasklet_schedule(&dev->tasklet); + + cur_frame = next_frame; + + spin_lock_irqsave(&input->slock, flags); + input->frame_seqno++; + input->frame_gop_seqno++; + if (input->frame_gop_seqno >= input->gop) + input->frame_gop_seqno = 0; + spin_unlock_irqrestore(&input->slock, flags); + } else { + dev_err(&dev->pci->dev, + "Skipped frame on input %d because all buffers busy\n", + channel); + } + + dev->encoder_busy = 0; + + spin_unlock_irqrestore(&dev->slock, flags); + + tw_writel(TW5864_VLC_STREAM_BASE_ADDR, cur_frame->vlc.dma_addr); + tw_writel(TW5864_MV_STREAM_BASE_ADDR, cur_frame->mv.dma_addr); + + /* Additional ack for this interrupt */ + tw_writel(TW5864_VLC_DSP_INTR, 0x00000001); + tw_writel(TW5864_PCI_INTR_STATUS, TW5864_VLC_DONE_INTR); +} + +static void tw5864_input_deadline_update(struct tw5864_input *input) +{ + input->new_frame_deadline = jiffies + msecs_to_jiffies(1000); +} + +static void tw5864_timer_isr(struct tw5864_dev *dev) +{ + unsigned long flags; + int i; + int encoder_busy; + + /* Additional ack for this interrupt */ + tw_writel(TW5864_PCI_INTR_STATUS, TW5864_TIMER_INTR); + + spin_lock_irqsave(&dev->slock, flags); + encoder_busy = dev->encoder_busy; + spin_unlock_irqrestore(&dev->slock, flags); + + if (encoder_busy) + return; + + /* + * Traversing inputs in round-robin fashion, starting from next to the + * last processed one + */ + for (i = 0; i < TW5864_INPUTS; i++) { + int next_input = (i + dev->next_input) % TW5864_INPUTS; + struct tw5864_input *input = &dev->inputs[next_input]; + int raw_buf_id; /* id of internal buf with last raw frame */ + + spin_lock_irqsave(&input->slock, flags); + if (!input->enabled) + goto next; + + /* Check if new raw frame is available */ + raw_buf_id = tw_mask_shift_readl(TW5864_SENIF_ORG_FRM_PTR1, 0x3, + 2 * input->nr); + + if (input->buf_id != raw_buf_id) { + input->buf_id = raw_buf_id; + tw5864_input_deadline_update(input); + spin_unlock_irqrestore(&input->slock, flags); + + spin_lock_irqsave(&dev->slock, flags); + dev->encoder_busy = 1; + dev->next_input = (next_input + 1) % TW5864_INPUTS; + spin_unlock_irqrestore(&dev->slock, flags); + + tw5864_request_encoded_frame(input); + break; + } + + /* No new raw frame; check if channel is stuck */ + if (time_is_after_jiffies(input->new_frame_deadline)) { + /* If stuck, request new raw frames again */ + tw_mask_shift_writel(TW5864_ENC_BUF_PTR_REC1, 0x3, + 2 * input->nr, input->buf_id + 3); + tw5864_input_deadline_update(input); + } +next: + spin_unlock_irqrestore(&input->slock, flags); + } +} + +static int tw5864_initdev(struct pci_dev *pci_dev, + const struct pci_device_id *pci_id) +{ + struct tw5864_dev *dev; + int err; + + dev = devm_kzalloc(&pci_dev->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + snprintf(dev->name, sizeof(dev->name), "tw5864:%s", pci_name(pci_dev)); + + err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev); + if (err) + return err; + + /* pci init */ + dev->pci = pci_dev; + err = pci_enable_device(pci_dev); + if (err) { + dev_err(&dev->pci->dev, "pci_enable_device() failed\n"); + goto unreg_v4l2; + } + + pci_set_master(pci_dev); + + err = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32)); + if (err) { + dev_err(&dev->pci->dev, "32 bit PCI DMA is not supported\n"); + goto disable_pci; + } + + /* get mmio */ + err = pci_request_regions(pci_dev, dev->name); + if (err) { + dev_err(&dev->pci->dev, "Cannot request regions for MMIO\n"); + goto disable_pci; + } + dev->mmio = pci_ioremap_bar(pci_dev, 0); + if (!dev->mmio) { + err = -EIO; + dev_err(&dev->pci->dev, "can't ioremap() MMIO memory\n"); + goto release_mmio; + } + + spin_lock_init(&dev->slock); + + dev_info(&pci_dev->dev, "TW5864 hardware version: %04x\n", + tw_readl(TW5864_HW_VERSION)); + dev_info(&pci_dev->dev, "TW5864 H.264 core version: %04x:%04x\n", + tw_readl(TW5864_H264REV), + tw_readl(TW5864_UNDECLARED_H264REV_PART2)); + + err = tw5864_video_init(dev, video_nr); + if (err) + goto unmap_mmio; + + /* get irq */ + err = devm_request_irq(&pci_dev->dev, pci_dev->irq, tw5864_isr, + IRQF_SHARED, "tw5864", dev); + if (err < 0) { + dev_err(&dev->pci->dev, "can't get IRQ %d\n", pci_dev->irq); + goto fini_video; + } + + dev_info(&pci_dev->dev, "Note: there are known video quality issues. For details\n"); + dev_info(&pci_dev->dev, "see the comment in drivers/media/pci/tw5864/tw5864-core.c.\n"); + + return 0; + +fini_video: + tw5864_video_fini(dev); +unmap_mmio: + iounmap(dev->mmio); +release_mmio: + pci_release_regions(pci_dev); +disable_pci: + pci_disable_device(pci_dev); +unreg_v4l2: + v4l2_device_unregister(&dev->v4l2_dev); + return err; +} + +static void tw5864_finidev(struct pci_dev *pci_dev) +{ + struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); + struct tw5864_dev *dev = + container_of(v4l2_dev, struct tw5864_dev, v4l2_dev); + + /* shutdown subsystems */ + tw5864_interrupts_disable(dev); + + /* unregister */ + tw5864_video_fini(dev); + + /* release resources */ + iounmap(dev->mmio); + release_mem_region(pci_resource_start(pci_dev, 0), + pci_resource_len(pci_dev, 0)); + + v4l2_device_unregister(&dev->v4l2_dev); + devm_kfree(&pci_dev->dev, dev); +} + +static struct pci_driver tw5864_pci_driver = { + .name = "tw5864", + .id_table = tw5864_pci_tbl, + .probe = tw5864_initdev, + .remove = tw5864_finidev, +}; + +module_pci_driver(tw5864_pci_driver); diff --git a/drivers/media/pci/tw5864/tw5864-h264.c b/drivers/media/pci/tw5864/tw5864-h264.c new file mode 100644 index 000000000000..330d200f52cd --- /dev/null +++ b/drivers/media/pci/tw5864/tw5864-h264.c @@ -0,0 +1,259 @@ +/* + * TW5864 driver - H.264 headers generation functions + * + * Copyright (C) 2016 Bluecherry, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include "tw5864.h" + +static u8 marker[] = { 0x00, 0x00, 0x00, 0x01 }; + +/* + * Exponential-Golomb coding functions + * + * These functions are used for generation of H.264 bitstream headers. + * + * This code is derived from tw5864 reference driver by manufacturers, which + * itself apparently was derived from x264 project. + */ + +/* Bitstream writing context */ +struct bs { + u8 *buf; /* pointer to buffer beginning */ + u8 *buf_end; /* pointer to buffer end */ + u8 *ptr; /* pointer to current byte in buffer */ + unsigned int bits_left; /* number of available bits in current byte */ +}; + +static void bs_init(struct bs *s, void *buf, int size) +{ + s->buf = buf; + s->ptr = buf; + s->buf_end = s->ptr + size; + s->bits_left = 8; +} + +static int bs_len(struct bs *s) +{ + return s->ptr - s->buf; +} + +static void bs_write(struct bs *s, int count, u32 bits) +{ + if (s->ptr >= s->buf_end - 4) + return; + while (count > 0) { + if (count < 32) + bits &= (1 << count) - 1; + if (count < s->bits_left) { + *s->ptr = (*s->ptr << count) | bits; + s->bits_left -= count; + break; + } + *s->ptr = (*s->ptr << s->bits_left) | + (bits >> (count - s->bits_left)); + count -= s->bits_left; + s->ptr++; + s->bits_left = 8; + } +} + +static void bs_write1(struct bs *s, u32 bit) +{ + if (s->ptr < s->buf_end) { + *s->ptr <<= 1; + *s->ptr |= bit; + s->bits_left--; + if (s->bits_left == 0) { + s->ptr++; + s->bits_left = 8; + } + } +} + +static void bs_write_ue(struct bs *s, u32 val) +{ + if (val == 0) { + bs_write1(s, 1); + } else { + val++; + bs_write(s, 2 * fls(val) - 1, val); + } +} + +static void bs_write_se(struct bs *s, int val) +{ + bs_write_ue(s, val <= 0 ? -val * 2 : val * 2 - 1); +} + +static void bs_rbsp_trailing(struct bs *s) +{ + bs_write1(s, 1); + if (s->bits_left != 8) + bs_write(s, s->bits_left, 0x00); +} + +/* H.264 headers generation functions */ + +static int tw5864_h264_gen_sps_rbsp(u8 *buf, size_t size, int width, int height) +{ + struct bs bs, *s; + + s = &bs; + bs_init(s, buf, size); + bs_write(s, 8, 0x42); /* profile_idc, baseline */ + bs_write(s, 1, 1); /* constraint_set0_flag */ + bs_write(s, 1, 1); /* constraint_set1_flag */ + bs_write(s, 1, 0); /* constraint_set2_flag */ + bs_write(s, 5, 0); /* reserved_zero_5bits */ + bs_write(s, 8, 0x1e); /* level_idc */ + bs_write_ue(s, 0); /* seq_parameter_set_id */ + bs_write_ue(s, ilog2(MAX_GOP_SIZE) - 4); /* log2_max_frame_num_minus4 */ + bs_write_ue(s, 0); /* pic_order_cnt_type */ + /* log2_max_pic_order_cnt_lsb_minus4 */ + bs_write_ue(s, ilog2(MAX_GOP_SIZE) - 4); + bs_write_ue(s, 1); /* num_ref_frames */ + bs_write(s, 1, 0); /* gaps_in_frame_num_value_allowed_flag */ + bs_write_ue(s, width / 16 - 1); /* pic_width_in_mbs_minus1 */ + bs_write_ue(s, height / 16 - 1); /* pic_height_in_map_units_minus1 */ + bs_write(s, 1, 1); /* frame_mbs_only_flag */ + bs_write(s, 1, 0); /* direct_8x8_inference_flag */ + bs_write(s, 1, 0); /* frame_cropping_flag */ + bs_write(s, 1, 0); /* vui_parameters_present_flag */ + bs_rbsp_trailing(s); + return bs_len(s); +} + +static int tw5864_h264_gen_pps_rbsp(u8 *buf, size_t size, int qp) +{ + struct bs bs, *s; + + s = &bs; + bs_init(s, buf, size); + bs_write_ue(s, 0); /* pic_parameter_set_id */ + bs_write_ue(s, 0); /* seq_parameter_set_id */ + bs_write(s, 1, 0); /* entropy_coding_mode_flag */ + bs_write(s, 1, 0); /* pic_order_present_flag */ + bs_write_ue(s, 0); /* num_slice_groups_minus1 */ + bs_write_ue(s, 0); /* i_num_ref_idx_l0_active_minus1 */ + bs_write_ue(s, 0); /* i_num_ref_idx_l1_active_minus1 */ + bs_write(s, 1, 0); /* weighted_pred_flag */ + bs_write(s, 2, 0); /* weighted_bipred_idc */ + bs_write_se(s, qp - 26); /* pic_init_qp_minus26 */ + bs_write_se(s, qp - 26); /* pic_init_qs_minus26 */ + bs_write_se(s, 0); /* chroma_qp_index_offset */ + bs_write(s, 1, 0); /* deblocking_filter_control_present_flag */ + bs_write(s, 1, 0); /* constrained_intra_pred_flag */ + bs_write(s, 1, 0); /* redundant_pic_cnt_present_flag */ + bs_rbsp_trailing(s); + return bs_len(s); +} + +static int tw5864_h264_gen_slice_head(u8 *buf, size_t size, + unsigned int idr_pic_id, + unsigned int frame_gop_seqno, + int *tail_nb_bits, u8 *tail) +{ + struct bs bs, *s; + int is_i_frame = frame_gop_seqno == 0; + + s = &bs; + bs_init(s, buf, size); + bs_write_ue(s, 0); /* first_mb_in_slice */ + bs_write_ue(s, is_i_frame ? 2 : 5); /* slice_type - I or P */ + bs_write_ue(s, 0); /* pic_parameter_set_id */ + bs_write(s, ilog2(MAX_GOP_SIZE), frame_gop_seqno); /* frame_num */ + if (is_i_frame) + bs_write_ue(s, idr_pic_id); + + /* pic_order_cnt_lsb */ + bs_write(s, ilog2(MAX_GOP_SIZE), frame_gop_seqno); + + if (is_i_frame) { + bs_write1(s, 0); /* no_output_of_prior_pics_flag */ + bs_write1(s, 0); /* long_term_reference_flag */ + } else { + bs_write1(s, 0); /* num_ref_idx_active_override_flag */ + bs_write1(s, 0); /* ref_pic_list_reordering_flag_l0 */ + bs_write1(s, 0); /* adaptive_ref_pic_marking_mode_flag */ + } + + bs_write_se(s, 0); /* slice_qp_delta */ + + if (s->bits_left != 8) { + *tail = ((s->ptr[0]) << s->bits_left); + *tail_nb_bits = 8 - s->bits_left; + } else { + *tail = 0; + *tail_nb_bits = 0; + } + + return bs_len(s); +} + +void tw5864_h264_put_stream_header(u8 **buf, size_t *space_left, int qp, + int width, int height) +{ + int nal_len; + + /* SPS */ + memcpy(*buf, marker, sizeof(marker)); + *buf += 4; + *space_left -= 4; + + **buf = 0x67; /* SPS NAL header */ + *buf += 1; + *space_left -= 1; + + nal_len = tw5864_h264_gen_sps_rbsp(*buf, *space_left, width, height); + *buf += nal_len; + *space_left -= nal_len; + + /* PPS */ + memcpy(*buf, marker, sizeof(marker)); + *buf += 4; + *space_left -= 4; + + **buf = 0x68; /* PPS NAL header */ + *buf += 1; + *space_left -= 1; + + nal_len = tw5864_h264_gen_pps_rbsp(*buf, *space_left, qp); + *buf += nal_len; + *space_left -= nal_len; +} + +void tw5864_h264_put_slice_header(u8 **buf, size_t *space_left, + unsigned int idr_pic_id, + unsigned int frame_gop_seqno, + int *tail_nb_bits, u8 *tail) +{ + int nal_len; + + memcpy(*buf, marker, sizeof(marker)); + *buf += 4; + *space_left -= 4; + + /* Frame NAL header */ + **buf = (frame_gop_seqno == 0) ? 0x25 : 0x21; + *buf += 1; + *space_left -= 1; + + nal_len = tw5864_h264_gen_slice_head(*buf, *space_left, idr_pic_id, + frame_gop_seqno, tail_nb_bits, + tail); + *buf += nal_len; + *space_left -= nal_len; +} diff --git a/drivers/media/pci/tw5864/tw5864-reg.h b/drivers/media/pci/tw5864/tw5864-reg.h new file mode 100644 index 000000000000..92a1b077ef8a --- /dev/null +++ b/drivers/media/pci/tw5864/tw5864-reg.h @@ -0,0 +1,2133 @@ +/* + * TW5864 driver - registers description + * + * Copyright (C) 2016 Bluecherry, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */ + +/* Register Description - Direct Map Space */ +/* 0x0000 ~ 0x1ffc - H264 Register Map */ +/* [15:0] The Version register for H264 core (Read Only) */ +#define TW5864_H264REV 0x0000 + +#define TW5864_EMU 0x0004 +/* Define controls in register TW5864_EMU */ +/* DDR controller enabled */ +#define TW5864_EMU_EN_DDR BIT(0) +/* Enable bit for Inter module */ +#define TW5864_EMU_EN_ME BIT(1) +/* Enable bit for Sensor Interface module */ +#define TW5864_EMU_EN_SEN BIT(2) +/* Enable bit for Host Burst Access */ +#define TW5864_EMU_EN_BHOST BIT(3) +/* Enable bit for Loop Filter module */ +#define TW5864_EMU_EN_LPF BIT(4) +/* Enable bit for PLBK module */ +#define TW5864_EMU_EN_PLBK BIT(5) +/* + * Video Frame mapping in DDR + * 00 CIF + * 01 D1 + * 10 Reserved + * 11 Reserved + * + */ +#define TW5864_DSP_FRAME_TYPE (3 << 6) +#define TW5864_DSP_FRAME_TYPE_D1 BIT(6) + +#define TW5864_UNDECLARED_H264REV_PART2 0x0008 + +#define TW5864_SLICE 0x000c +/* Define controls in register TW5864_SLICE */ +/* VLC Slice end flag */ +#define TW5864_VLC_SLICE_END BIT(0) +/* Master Slice End Flag */ +#define TW5864_MAS_SLICE_END BIT(4) +/* Host to start a new slice Address */ +#define TW5864_START_NSLICE BIT(15) + +/* + * [15:0] Two bit for each channel (channel 0 ~ 7). Each two bits are the buffer + * pointer for the last encoded frame of the corresponding channel. + */ +#define TW5864_ENC_BUF_PTR_REC1 0x0010 + +/* [5:0] DSP_MB_QP and [15:10] DSP_LPF_OFFSET */ +#define TW5864_DSP_QP 0x0018 +/* Define controls in register TW5864_DSP_QP */ +/* [5:0] H264 QP Value for codec */ +#define TW5864_DSP_MB_QP 0x003f +/* + * [15:10] H264 LPF_OFFSET Address + * (Default 0) + */ +#define TW5864_DSP_LPF_OFFSET 0xfc00 + +#define TW5864_DSP_CODEC 0x001c +/* Define controls in register TW5864_DSP_CODEC */ +/* + * 0: Encode (TW5864 Default) + * 1: Decode + */ +#define TW5864_DSP_CODEC_MODE BIT(0) +/* + * 0->3 4 VLC data buffer in DDR (1M each) + * 0->7 8 VLC data buffer in DDR (512k each) + */ +#define TW5864_VLC_BUF_ID (7 << 2) +/* + * 0 4CIF in 1 MB + * 1 1CIF in 1 MB + */ +#define TW5864_CIF_MAP_MD BIT(6) +/* + * 0 2 falf D1 in 1 MB + * 1 1 half D1 in 1 MB + */ +#define TW5864_HD1_MAP_MD BIT(7) +/* VLC Stream valid */ +#define TW5864_VLC_VLD BIT(8) +/* MV Vector Valid */ +#define TW5864_MV_VECT_VLD BIT(9) +/* MV Flag Valid */ +#define TW5864_MV_FLAG_VLD BIT(10) + +#define TW5864_DSP_SEN 0x0020 +/* Define controls in register TW5864_DSP_SEN */ +/* Org Buffer Base for Luma (default 0) */ +#define TW5864_DSP_SEN_PIC_LU 0x000f +/* Org Buffer Base for Chroma (default 4) */ +#define TW5864_DSP_SEN_PIC_CHM 0x00f0 +/* Maximum Number of Buffers (default 4) */ +#define TW5864_DSP_SEN_PIC_MAX 0x0700 +/* + * Original Frame D1 or HD1 switch + * (Default 0) + */ +#define TW5864_DSP_SEN_HFULL 0x1000 + +#define TW5864_DSP_REF_PIC 0x0024 +/* Define controls in register TW5864_DSP_REF_PIC */ +/* Ref Buffer Base for Luma (default 0) */ +#define TW5864_DSP_REF_PIC_LU 0x000f +/* Ref Buffer Base for Chroma (default 4) */ +#define TW5864_DSP_REF_PIC_CHM 0x00f0 +/* Maximum Number of Buffers (default 4) */ +#define TW5864_DSP_REF_PIC_MAX 0x0700 + +/* [15:0] SEN_EN_CH[n] SENIF original frame capture enable for each channel */ +#define TW5864_SEN_EN_CH 0x0028 + +#define TW5864_DSP 0x002c +/* Define controls in register TW5864_DSP */ +/* The ID for channel selected for encoding operation */ +#define TW5864_DSP_ENC_CHN 0x000f +/* See DSP_MB_DELAY below */ +#define TW5864_DSP_MB_WAIT 0x0010 +/* + * DSP Chroma Switch + * 0 DDRB + * 1 DDRA + */ +#define TW5864_DSP_CHROM_SW 0x0020 +/* VLC Flow Control: 1 for enable */ +#define TW5864_DSP_FLW_CNTL 0x0040 +/* + * If DSP_MB_WAIT == 0, MB delay is DSP_MB_DELAY * 16 + * If DSP_MB_DELAY == 1, MB delay is DSP_MB_DELAY * 128 + */ +#define TW5864_DSP_MB_DELAY 0x0f00 + +#define TW5864_DDR 0x0030 +/* Define controls in register TW5864_DDR */ +/* DDR Single Access Page Number */ +#define TW5864_DDR_PAGE_CNTL 0x00ff +/* DDR-DPR Burst Read Enable */ +#define TW5864_DDR_BRST_EN BIT(13) +/* + * DDR A/B Select as HOST access + * 0 Select DDRA + * 1 Select DDRB + */ +#define TW5864_DDR_AB_SEL BIT(14) +/* + * DDR Access Mode Select + * 0 Single R/W Access (Host <-> DDR) + * 1 Burst R/W Access (Host <-> DPR) + */ +#define TW5864_DDR_MODE BIT(15) + +/* The original frame capture pointer. Two bits for each channel */ +/* SENIF_ORG_FRM_PTR [15:0] */ +#define TW5864_SENIF_ORG_FRM_PTR1 0x0038 +/* SENIF_ORG_FRM_PTR [31:16] */ +#define TW5864_SENIF_ORG_FRM_PTR2 0x003c + +#define TW5864_DSP_SEN_MODE 0x0040 +/* Define controls in register TW5864_DSP_SEN_MODE */ +#define TW5864_DSP_SEN_MODE_CH0 0x000f +#define TW5864_DSP_SEN_MODE_CH1 0x00f0 + +/* + * [15:0]: ENC_BUF_PTR_REC[31:16] Two bit for each channel (channel 8 ~ 15). + * Each two bits are the buffer pointer for the last encoded frame of a channel + */ +#define TW5864_ENC_BUF_PTR_REC2 0x004c + +/* Current MV Flag Status Pointer for Channel n. (Read only) */ +/* + * [1:0] CH0_MV_PTR, ..., [15:14] CH7_MV_PTR + */ +#define TW5864_CH_MV_PTR1 0x0060 +/* + * [1:0] CH8_MV_PTR, ..., [15:14] CH15_MV_PTR + */ +#define TW5864_CH_MV_PTR2 0x0064 + +/* + * [15:0] Reset Current MV Flag Status Pointer for Channel n (one bit each) + */ +#define TW5864_RST_MV_PTR 0x0068 +#define TW5864_INTERLACING 0x0200 +/* Define controls in register TW5864_INTERLACING */ +/* + * Inter_Mode Start. 2-nd bit? A guess. Missing in datasheet. Without this bit + * set, the output video is interlaced (stripy). + */ +#define TW5864_DSP_INTER_ST BIT(1) +/* Deinterlacer Enable */ +#define TW5864_DI_EN BIT(2) +/* + * De-interlacer Mode + * 1 Shuffled frame + * 0 Normal Un-Shuffled Frame + */ +#define TW5864_DI_MD BIT(3) +/* + * Down scale original frame in X direction + * 11: Un-used + * 10: down-sample to 1/4 + * 01: down-sample to 1/2 + * 00: down-sample disabled + */ +#define TW5864_DSP_DWN_X (3 << 4) +/* + * Down scale original frame in Y direction + * 11: Un-used + * 10: down-sample to 1/4 + * 01: down-sample to 1/2 + * 00: down-sample disabled + */ +#define TW5864_DSP_DWN_Y (3 << 6) +/* + * 1 Dual Stream + * 0 Single Stream + */ +#define TW5864_DUAL_STR BIT(8) + +#define TW5864_DSP_REF 0x0204 +/* Define controls in register TW5864_DSP_REF */ +/* Number of reference frame (Default 1 for TW5864B) */ +#define TW5864_DSP_REF_FRM 0x000f +/* Window size */ +#define TW5864_DSP_WIN_SIZE 0x02f0 + +#define TW5864_DSP_SKIP 0x0208 +/* Define controls in register TW5864_DSP_SKIP */ +/* + * Skip Offset Enable bit + * 0 DSP_SKIP_OFFSET value is not used (default 8) + * 1 DSP_SKIP_OFFSET value is used in HW + */ +#define TW5864_DSP_SKIP_OFEN 0x0080 +/* Skip mode cost offset (default 8) */ +#define TW5864_DSP_SKIP_OFFSET 0x007f + +#define TW5864_MOTION_SEARCH_ETC 0x020c +/* Define controls in register TW5864_MOTION_SEARCH_ETC */ +/* Enable quarter pel search mode */ +#define TW5864_QPEL_EN BIT(0) +/* Enable half pel search mode */ +#define TW5864_HPEL_EN BIT(1) +/* Enable motion search mode */ +#define TW5864_ME_EN BIT(2) +/* Enable Intra mode */ +#define TW5864_INTRA_EN BIT(3) +/* Enable Skip Mode */ +#define TW5864_SKIP_EN BIT(4) +/* Search Option (Default 2"b01) */ +#define TW5864_SRCH_OPT (3 << 5) + +#define TW5864_DSP_ENC_REC 0x0210 +/* Define controls in register TW5864_DSP_ENC_REC */ +/* Reference Buffer Pointer for encoding */ +#define TW5864_DSP_ENC_REF_PTR 0x0007 +/* Reconstruct Buffer pointer */ +#define TW5864_DSP_REC_BUF_PTR 0x7000 + +/* [15:0] Lambda Value for H264 */ +#define TW5864_DSP_REF_MVP_LAMBDA 0x0214 + +#define TW5864_DSP_PIC_MAX_MB 0x0218 +/* Define controls in register TW5864_DSP_PIC_MAX_MB */ +/* The MB number in Y direction for a frame */ +#define TW5864_DSP_PIC_MAX_MB_Y 0x007f +/* The MB number in X direction for a frame */ +#define TW5864_DSP_PIC_MAX_MB_X 0x7f00 + +/* The original frame pointer for encoding */ +#define TW5864_DSP_ENC_ORG_PTR_REG 0x021c +/* Mask to use with TW5864_DSP_ENC_ORG_PTR */ +#define TW5864_DSP_ENC_ORG_PTR_MASK 0x7000 +/* Number of bits to shift with TW5864_DSP_ENC_ORG_PTR */ +#define TW5864_DSP_ENC_ORG_PTR_SHIFT 12 + +/* DDR base address of OSD rectangle attribute data */ +#define TW5864_DSP_OSD_ATTRI_BASE 0x0220 +/* OSD enable bit for each channel */ +#define TW5864_DSP_OSD_ENABLE 0x0228 + +/* 0x0280 ~ 0x029c – Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */ +#define TW5864_ME_MV_VEC1 0x0280 +/* 0x02a0 ~ 0x02bc – Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */ +#define TW5864_ME_MV_VEC2 0x02a0 +/* 0x02c0 ~ 0x02dc – Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */ +#define TW5864_ME_MV_VEC3 0x02c0 +/* 0x02e0 ~ 0x02fc – Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */ +#define TW5864_ME_MV_VEC4 0x02e0 + +/* + * [5:0] + * if (intra16x16_cost < (intra4x4_cost+dsp_i4x4_offset)) + * Intra_mode = intra16x16_mode + * Else + * Intra_mode = intra4x4_mode + */ +#define TW5864_DSP_I4x4_OFFSET 0x040c + +/* + * [6:4] + * 0x5 Only 4x4 + * 0x6 Only 16x16 + * 0x7 16x16 & 4x4 + */ +#define TW5864_DSP_INTRA_MODE 0x0410 +#define TW5864_DSP_INTRA_MODE_SHIFT 4 +#define TW5864_DSP_INTRA_MODE_MASK (7 << 4) +#define TW5864_DSP_INTRA_MODE_4x4 0x5 +#define TW5864_DSP_INTRA_MODE_16x16 0x6 +#define TW5864_DSP_INTRA_MODE_4x4_AND_16x16 0x7 +/* + * [5:0] WEIGHT Factor for I4x4 cost calculation (QP dependent) + */ +#define TW5864_DSP_I4x4_WEIGHT 0x0414 + +/* + * [7:0] Offset used to affect Intra/ME model decision + * If (me_cost < intra_cost + dsp_resid_mode_offset) + * Pred_Mode = me_mode + * Else + * Pred_mode = intra_mode + */ +#define TW5864_DSP_RESID_MODE_OFFSET 0x0604 + +/* 0x0800 ~ 0x09ff - Quantization TABLE Values */ +#define TW5864_QUAN_TAB 0x0800 + +/* Valid channel value [0; f], frame value [0; 3] */ +#define TW5864_RT_CNTR_CH_FRM(channel, frame) \ + (0x0c00 | (channel << 4) | (frame << 2)) + +#define TW5864_FRAME_BUS1 0x0d00 +/* + * 1 Progressive in part A in bus n + * 0 Interlaced in part A in bus n + */ +#define TW5864_PROG_A BIT(0) +/* + * 1 Progressive in part B in bus n + * 0 Interlaced in part B in bus n + */ +#define TW5864_PROG_B BIT(1) +/* + * 1 Frame Mode in bus n + * 0 Field Mode in bus n + */ +#define TW5864_FRAME BIT(2) +/* + * 0 4CIF in bus n + * 1 1D1 + 4 CIF in bus n + * 2 2D1 in bus n + */ +#define TW5864_BUS_D1 (3 << 3) +/* Bus 1 goes in TW5864_FRAME_BUS1 in [4:0] */ +/* Bus 2 goes in TW5864_FRAME_BUS1 in [12:8] */ +#define TW5864_FRAME_BUS2 0x0d04 +/* Bus 3 goes in TW5864_FRAME_BUS2 in [4:0] */ +/* Bus 4 goes in TW5864_FRAME_BUS2 in [12:8] */ + +/* [15:0] Horizontal Mirror for channel n */ +#define TW5864_SENIF_HOR_MIR 0x0d08 +/* [15:0] Vertical Mirror for channel n */ +#define TW5864_SENIF_VER_MIR 0x0d0c + +/* + * FRAME_WIDTH_BUSn_A + * 0x15f: 4 CIF + * 0x2cf: 1 D1 + 3 CIF + * 0x2cf: 2 D1 + * FRAME_WIDTH_BUSn_B + * 0x15f: 4 CIF + * 0x2cf: 1 D1 + 3 CIF + * 0x2cf: 2 D1 + * FRAME_HEIGHT_BUSn_A + * 0x11f: 4CIF (PAL) + * 0x23f: 1D1 + 3CIF (PAL) + * 0x23f: 2 D1 (PAL) + * 0x0ef: 4CIF (NTSC) + * 0x1df: 1D1 + 3CIF (NTSC) + * 0x1df: 2 D1 (NTSC) + * FRAME_HEIGHT_BUSn_B + * 0x11f: 4CIF (PAL) + * 0x23f: 1D1 + 3CIF (PAL) + * 0x23f: 2 D1 (PAL) + * 0x0ef: 4CIF (NTSC) + * 0x1df: 1D1 + 3CIF (NTSC) + * 0x1df: 2 D1 (NTSC) + */ +#define TW5864_FRAME_WIDTH_BUS_A(bus) (0x0d10 + 0x0010 * bus) +#define TW5864_FRAME_WIDTH_BUS_B(bus) (0x0d14 + 0x0010 * bus) +#define TW5864_FRAME_HEIGHT_BUS_A(bus) (0x0d18 + 0x0010 * bus) +#define TW5864_FRAME_HEIGHT_BUS_B(bus) (0x0d1c + 0x0010 * bus) + +/* + * 1: the bus mapped Channel n Full D1 + * 0: the bus mapped Channel n Half D1 + */ +#define TW5864_FULL_HALF_FLAG 0x0d50 + +/* + * 0 The bus mapped Channel select partA Mode + * 1 The bus mapped Channel select partB Mode + */ +#define TW5864_FULL_HALF_MODE_SEL 0x0d54 + +#define TW5864_VLC 0x1000 +/* Define controls in register TW5864_VLC */ +/* QP Value used by H264 CAVLC */ +#define TW5864_VLC_SLICE_QP 0x003f +/* + * Swap byte order of VLC stream in d-word. + * 1 Normal (VLC output= [31:0]) + * 0 Swap (VLC output={[23:16],[31:24],[7:0], [15:8]}) + */ +#define TW5864_VLC_BYTE_SWP BIT(6) +/* Enable Adding 03 circuit for VLC stream */ +#define TW5864_VLC_ADD03_EN BIT(7) +/* Number of bit for VLC bit Align */ +#define TW5864_VLC_BIT_ALIGN_SHIFT 8 +#define TW5864_VLC_BIT_ALIGN_MASK (0x1f << 8) +/* + * Synchronous Interface select for VLC Stream + * 1 CDC_VLCS_MAS read VLC stream + * 0 CPU read VLC stream + */ +#define TW5864_VLC_INF_SEL BIT(13) +/* Enable VLC overflow control */ +#define TW5864_VLC_OVFL_CNTL BIT(14) +/* + * 1 PCI Master Mode + * 0 Non PCI Master Mode + */ +#define TW5864_VLC_PCI_SEL BIT(15) +/* + * 0 Enable Adding 03 to VLC header and stream + * 1 Disable Adding 03 to VLC header of "00000001" + */ +#define TW5864_VLC_A03_DISAB BIT(16) +/* + * Status of VLC stream in DDR (one bit for each buffer) + * 1 VLC is ready in buffer n (HW set) + * 0 VLC is not ready in buffer n (SW clear) + */ +#define TW5864_VLC_BUF_RDY_SHIFT 24 +#define TW5864_VLC_BUF_RDY_MASK (0xff << 24) + +/* Total number of bit in the slice */ +#define TW5864_SLICE_TOTAL_BIT 0x1004 +/* Total number of bit in the residue */ +#define TW5864_RES_TOTAL_BIT 0x1008 + +#define TW5864_VLC_BUF 0x100c +/* Define controls in register TW5864_VLC_BUF */ +/* VLC BK0 full status, write ‘1’ to clear */ +#define TW5864_VLC_BK0_FULL BIT(0) +/* VLC BK1 full status, write ‘1’ to clear */ +#define TW5864_VLC_BK1_FULL BIT(1) +/* VLC end slice status, write ‘1’ to clear */ +#define TW5864_VLC_END_SLICE BIT(2) +/* VLC Buffer overflow status, write ‘1’ to clear */ +#define TW5864_DSP_RD_OF BIT(3) +/* VLC string length in either buffer 0 or 1 at end of frame */ +#define TW5864_VLC_STREAM_LEN_SHIFT 4 +#define TW5864_VLC_STREAM_LEN_MASK (0x1ff << 4) + +/* [15:0] Total coefficient number in a frame */ +#define TW5864_TOTAL_COEF_NO 0x1010 +/* [0] VLC Encoder Interrupt. Write ‘1’ to clear */ +#define TW5864_VLC_DSP_INTR 0x1014 +/* [31:0] VLC stream CRC checksum */ +#define TW5864_VLC_STREAM_CRC 0x1018 + +#define TW5864_VLC_RD 0x101c +/* Define controls in register TW5864_VLC_RD */ +/* + * 1 Read VLC lookup Memory + * 0 Read VLC Stream Memory + */ +#define TW5864_VLC_RD_MEM BIT(0) +/* + * 1 Read VLC Stream Memory in burst mode + * 0 Read VLC Stream Memory in single mode + */ +#define TW5864_VLC_RD_BRST BIT(1) + +/* 0x2000 ~ 0x2ffc -- H264 Stream Memory Map */ +/* + * A word is 4 bytes. I.e., + * VLC_STREAM_MEM[0] address: 0x2000 + * VLC_STREAM_MEM[1] address: 0x2004 + * ... + * VLC_STREAM_MEM[3FF] address: 0x2ffc + */ +#define TW5864_VLC_STREAM_MEM_START 0x2000 +#define TW5864_VLC_STREAM_MEM_MAX_OFFSET 0x3ff +#define TW5864_VLC_STREAM_MEM(offset) (TW5864_VLC_STREAM_MEM_START + 4 * offset) + +/* 0x4000 ~ 0x4ffc -- Audio Register Map */ +/* [31:0] config 1ms cnt = Realtime clk/1000 */ +#define TW5864_CFG_1MS_CNT 0x4000 + +#define TW5864_ADPCM 0x4004 +/* Define controls in register TW5864_ADPCM */ +/* ADPCM decoder enable */ +#define TW5864_ADPCM_DEC BIT(0) +/* ADPCM input data enable */ +#define TW5864_ADPCM_IN_DATA BIT(1) +/* ADPCM encoder enable */ +#define TW5864_ADPCM_ENC BIT(2) + +#define TW5864_AUD 0x4008 +/* Define controls in register TW5864_AUD */ +/* Record path PCM Audio enable bit for each channel */ +#define TW5864_AUD_ORG_CH_EN 0x00ff +/* Speaker path PCM Audio Enable */ +#define TW5864_SPK_ORG_EN BIT(16) +/* + * 0 16bit + * 1 8bit + */ +#define TW5864_AD_BIT_MODE BIT(17) +#define TW5864_AUD_TYPE_SHIFT 18 +/* + * 0 PCM + * 3 ADPCM + */ +#define TW5864_AUD_TYPE (0xf << 18) +#define TW5864_AUD_SAMPLE_RATE_SHIFT 22 +/* + * 0 8K + * 1 16K + */ +#define TW5864_AUD_SAMPLE_RATE (3 << 22) +/* Channel ID used to select audio channel (0 to 16) for loopback */ +#define TW5864_TESTLOOP_CHID_SHIFT 24 +#define TW5864_TESTLOOP_CHID (0x1f << 24) +/* Enable AD Loopback Test */ +#define TW5864_TEST_ADLOOP_EN BIT(30) +/* + * 0 Asynchronous Mode or PCI target mode + * 1 PCI Initiator Mode + */ +#define TW5864_AUD_MODE BIT(31) + +#define TW5864_AUD_ADPCM 0x400c +/* Define controls in register TW5864_AUD_ADPCM */ +/* Record path ADPCM audio channel enable, one bit for each */ +#define TW5864_AUD_ADPCM_CH_EN 0x00ff +/* Speaker path ADPCM audio channel enable */ +#define TW5864_SPK_ADPCM_EN BIT(16) + +#define TW5864_PC_BLOCK_ADPCM_RD_NO 0x4018 +#define TW5864_PC_BLOCK_ADPCM_RD_NO_MASK 0x1f + +/* + * For ADPCM_ENC_WR_PTR, ADPCM_ENC_RD_PTR (see below): + * Bit[2:0] ch0 + * Bit[5:3] ch1 + * Bit[8:6] ch2 + * Bit[11:9] ch3 + * Bit[14:12] ch4 + * Bit[17:15] ch5 + * Bit[20:18] ch6 + * Bit[23:21] ch7 + * Bit[26:24] ch8 + * Bit[29:27] ch9 + * Bit[32:30] ch10 + * Bit[35:33] ch11 + * Bit[38:36] ch12 + * Bit[41:39] ch13 + * Bit[44:42] ch14 + * Bit[47:45] ch15 + * Bit[50:48] ch16 + */ +#define TW5864_ADPCM_ENC_XX_MASK 0x3fff +#define TW5864_ADPCM_ENC_XX_PTR2_SHIFT 30 +/* ADPCM_ENC_WR_PTR[29:0] */ +#define TW5864_ADPCM_ENC_WR_PTR1 0x401c +/* ADPCM_ENC_WR_PTR[50:30] */ +#define TW5864_ADPCM_ENC_WR_PTR2 0x4020 + +/* ADPCM_ENC_RD_PTR[29:0] */ +#define TW5864_ADPCM_ENC_RD_PTR1 0x4024 +/* ADPCM_ENC_RD_PTR[50:30] */ +#define TW5864_ADPCM_ENC_RD_PTR2 0x4028 + +/* [3:0] rd ch0, [7:4] rd ch1, [11:8] wr ch0, [15:12] wr ch1 */ +#define TW5864_ADPCM_DEC_RD_WR_PTR 0x402c + +/* + * For TW5864_AD_ORIG_WR_PTR, TW5864_AD_ORIG_RD_PTR: + * Bit[3:0] ch0 + * Bit[7:4] ch1 + * Bit[11:8] ch2 + * Bit[15:12] ch3 + * Bit[19:16] ch4 + * Bit[23:20] ch5 + * Bit[27:24] ch6 + * Bit[31:28] ch7 + * Bit[35:32] ch8 + * Bit[39:36] ch9 + * Bit[43:40] ch10 + * Bit[47:44] ch11 + * Bit[51:48] ch12 + * Bit[55:52] ch13 + * Bit[59:56] ch14 + * Bit[63:60] ch15 + * Bit[67:64] ch16 + */ +/* AD_ORIG_WR_PTR[31:0] */ +#define TW5864_AD_ORIG_WR_PTR1 0x4030 +/* AD_ORIG_WR_PTR[63:32] */ +#define TW5864_AD_ORIG_WR_PTR2 0x4034 +/* AD_ORIG_WR_PTR[67:64] */ +#define TW5864_AD_ORIG_WR_PTR3 0x4038 + +/* AD_ORIG_RD_PTR[31:0] */ +#define TW5864_AD_ORIG_RD_PTR1 0x403c +/* AD_ORIG_RD_PTR[63:32] */ +#define TW5864_AD_ORIG_RD_PTR2 0x4040 +/* AD_ORIG_RD_PTR[67:64] */ +#define TW5864_AD_ORIG_RD_PTR3 0x4044 + +#define TW5864_PC_BLOCK_ORIG_RD_NO 0x4048 +#define TW5864_PC_BLOCK_ORIG_RD_NO_MASK 0x1f + +#define TW5864_PCI_AUD 0x404c +/* Define controls in register TW5864_PCI_AUD */ +/* + * The register is applicable to PCI initiator mode only. Used to select PCM(0) + * or ADPCM(1) audio data sent to PC. One bit for each channel + */ +#define TW5864_PCI_DATA_SEL 0xffff +/* + * Audio flow control mode selection bit. + * 0 Flow control disabled. TW5864 continuously sends audio frame to PC + * (initiator mode) + * 1 Flow control enabled + */ +#define TW5864_PCI_FLOW_EN BIT(16) +/* + * When PCI_FLOW_EN is set, PCI need to toggle this bit to send an audio frame + * to PC. One toggle to send one frame. + */ +#define TW5864_PCI_AUD_FRM_EN BIT(17) + +/* [1:0] CS valid to data valid CLK cycles when writing operation */ +#define TW5864_CS2DAT_CNT 0x8000 +/* [2:0] Data valid signal width by system clock cycles */ +#define TW5864_DATA_VLD_WIDTH 0x8004 + +#define TW5864_SYNC 0x8008 +/* Define controls in register TW5864_SYNC */ +/* + * 0 vlc stream to syncrous port + * 1 vlc stream to ddr buffers + */ +#define TW5864_SYNC_CFG BIT(7) +/* + * 0 SYNC Address sampled on Rising edge + * 1 SYNC Address sampled on Falling edge + */ +#define TW5864_SYNC_ADR_EDGE BIT(0) +#define TW5864_VLC_STR_DELAY_SHIFT 1 +/* + * 0 No system delay + * 1 One system clock delay + * 2 Two system clock delay + * 3 Three system clock delay + */ +#define TW5864_VLC_STR_DELAY (3 << 1) +/* + * 0 Rising edge output + * 1 Falling edge output + */ +#define TW5864_VLC_OUT_EDGE BIT(3) + +/* + * [1:0] + * 2’b00 phase set to 180 degree + * 2’b01 phase set to 270 degree + * 2’b10 phase set to 0 degree + * 2’b11 phase set to 90 degree + */ +#define TW5864_I2C_PHASE_CFG 0x800c + +/* + * The system / DDR clock (166 MHz) is generated with an on-chip system clock + * PLL (SYSPLL) using input crystal clock of 27 MHz. The system clock PLL + * frequency is controlled with the following equation. + * CLK_OUT = CLK_IN * (M+1) / ((N+1) * P) + * SYSPLL_M M parameter + * SYSPLL_N N parameter + * SYSPLL_P P parameter + */ +/* SYSPLL_M[7:0] */ +#define TW5864_SYSPLL1 0x8018 +/* Define controls in register TW5864_SYSPLL1 */ +#define TW5864_SYSPLL_M_LOW 0x00ff + +/* [2:0]: SYSPLL_M[10:8], [7:3]: SYSPLL_N[4:0] */ +#define TW5864_SYSPLL2 0x8019 +/* Define controls in register TW5864_SYSPLL2 */ +#define TW5864_SYSPLL_M_HI 0x07 +#define TW5864_SYSPLL_N_LOW_SHIFT 3 +#define TW5864_SYSPLL_N_LOW (0x1f << 3) + +/* + * [1:0]: SYSPLL_N[6:5], [3:2]: SYSPLL_P, [4]: SYSPLL_IREF, [7:5]: SYSPLL_CP_SEL + */ +#define TW5864_SYSPLL3 0x8020 +/* Define controls in register TW5864_SYSPLL3 */ +#define TW5864_SYSPLL_N_HI 0x03 +#define TW5864_SYSPLL_P_SHIFT 2 +#define TW5864_SYSPLL_P (0x03 << 2) +/* + * SYSPLL bias current control + * 0 Lower current (default) + * 1 30% higher current + */ +#define TW5864_SYSPLL_IREF BIT(4) +/* + * SYSPLL charge pump current selection + * 0 1,5 uA + * 1 4 uA + * 2 9 uA + * 3 19 uA + * 4 39 uA + * 5 79 uA + * 6 159 uA + * 7 319 uA + */ +#define TW5864_SYSPLL_CP_SEL_SHIFT 5 +#define TW5864_SYSPLL_CP_SEL (0x07 << 5) + +/* + * [1:0]: SYSPLL_VCO, [3:2]: SYSPLL_LP_X8, [5:4]: SYSPLL_ICP_SEL, + * [6]: SYSPLL_LPF_5PF, [7]: SYSPLL_ED_SEL + */ +#define TW5864_SYSPLL4 0x8021 +/* Define controls in register TW5864_SYSPLL4 */ +/* + * SYSPLL_VCO VCO Range selection + * 00 5 ~ 75 MHz + * 01 50 ~ 140 MHz + * 10 110 ~ 320 MHz + * 11 270 ~ 700 MHz + */ +#define TW5864_SYSPLL_VCO 0x03 +#define TW5864_SYSPLL_LP_X8_SHIFT 2 +/* + * Loop resister + * 0 38.5K ohms + * 1 6.6K ohms (default) + * 2 2.2K ohms + * 3 1.1K ohms + */ +#define TW5864_SYSPLL_LP_X8 (0x03 << 2) +#define TW5864_SYSPLL_ICP_SEL_SHIFT 4 +/* + * PLL charge pump fine tune + * 00 x1 (default) + * 01 x1/2 + * 10 x1/7 + * 11 x1/8 + */ +#define TW5864_SYSPLL_ICP_SEL (0x03 << 4) +/* + * PLL low pass filter phase margin adjustment + * 0 no 5pF (default) + * 1 5pF added + */ +#define TW5864_SYSPLL_LPF_5PF BIT(6) +/* + * PFD select edge for detection + * 0 Falling edge (default) + * 1 Rising edge + */ +#define TW5864_SYSPLL_ED_SEL BIT(7) + +/* [0]: SYSPLL_RST, [4]: SYSPLL_PD */ +#define TW5864_SYSPLL5 0x8024 +/* Define controls in register TW5864_SYSPLL5 */ +/* Reset SYSPLL */ +#define TW5864_SYSPLL_RST BIT(0) +/* Power down SYSPLL */ +#define TW5864_SYSPLL_PD BIT(4) + +#define TW5864_PLL_CFG 0x801c +/* Define controls in register TW5864_PLL_CFG */ +/* + * Issue Soft Reset from Async Host Interface / PCI Interface clock domain. + * Become valid after sync to the xtal clock domain. This bit is set only if + * LOAD register bit is also set to 1. + */ +#define TW5864_SRST BIT(0) +/* + * Issue SYSPLL (166 MHz) configuration latch from Async host interface / PCI + * Interface clock domain. The configuration setting becomes effective only if + * LOAD register bit is also set to 1. + */ +#define TW5864_SYSPLL_CFG BIT(2) +/* + * Issue SPLL (108 MHz) configuration load from Async host interface / PCI + * Interface clock domain. The configuration setting becomes effective only if + * the LOAD register bit is also set to 1. + */ +#define TW5864_SPLL_CFG BIT(4) +/* + * Set this bit to latch the SRST, SYSPLL_CFG, SPLL_CFG setting into the xtal + * clock domain to restart the PLL. This bit is self cleared. + */ +#define TW5864_LOAD BIT(3) + +/* SPLL_IREF, SPLL_LPX4, SPLL_CPX4, SPLL_PD, SPLL_DBG */ +#define TW5864_SPLL 0x8028 + +/* 0x8800 ~ 0x88fc -- Interrupt Register Map */ +/* + * Trigger mode of interrupt source 0 ~ 15 + * 1 Edge trigger mode + * 0 Level trigger mode + */ +#define TW5864_TRIGGER_MODE_L 0x8800 +/* Trigger mode of interrupt source 16 ~ 31 */ +#define TW5864_TRIGGER_MODE_H 0x8804 +/* Enable of interrupt source 0 ~ 15 */ +#define TW5864_INTR_ENABLE_L 0x8808 +/* Enable of interrupt source 16 ~ 31 */ +#define TW5864_INTR_ENABLE_H 0x880c +/* Clear interrupt command of interrupt source 0 ~ 15 */ +#define TW5864_INTR_CLR_L 0x8810 +/* Clear interrupt command of interrupt source 16 ~ 31 */ +#define TW5864_INTR_CLR_H 0x8814 +/* + * Assertion of interrupt source 0 ~ 15 + * 1 High level or pos-edge is assertion + * 0 Low level or neg-edge is assertion + */ +#define TW5864_INTR_ASSERT_L 0x8818 +/* Assertion of interrupt source 16 ~ 31 */ +#define TW5864_INTR_ASSERT_H 0x881c +/* + * Output level of interrupt + * 1 Interrupt output is high assertion + * 0 Interrupt output is low assertion + */ +#define TW5864_INTR_OUT_LEVEL 0x8820 +/* + * Status of interrupt source 0 ~ 15 + * Bit[0]: VLC 4k RAM interrupt + * Bit[1]: BURST DDR RAM interrupt + * Bit[2]: MV DSP interrupt + * Bit[3]: video lost interrupt + * Bit[4]: gpio 0 interrupt + * Bit[5]: gpio 1 interrupt + * Bit[6]: gpio 2 interrupt + * Bit[7]: gpio 3 interrupt + * Bit[8]: gpio 4 interrupt + * Bit[9]: gpio 5 interrupt + * Bit[10]: gpio 6 interrupt + * Bit[11]: gpio 7 interrupt + * Bit[12]: JPEG interrupt + * Bit[13:15]: Reserved + */ +#define TW5864_INTR_STATUS_L 0x8838 +/* + * Status of interrupt source 16 ~ 31 + * Bit[0]: Reserved + * Bit[1]: VLC done interrupt + * Bit[2]: Reserved + * Bit[3]: AD Vsync interrupt + * Bit[4]: Preview eof interrupt + * Bit[5]: Preview overflow interrupt + * Bit[6]: Timer interrupt + * Bit[7]: Reserved + * Bit[8]: Audio eof interrupt + * Bit[9]: I2C done interrupt + * Bit[10]: AD interrupt + * Bit[11:15]: Reserved + */ +#define TW5864_INTR_STATUS_H 0x883c + +/* Defines of interrupt bits, united for both low and high word registers */ +#define TW5864_INTR_VLC_RAM BIT(0) +#define TW5864_INTR_BURST BIT(1) +#define TW5864_INTR_MV_DSP BIT(2) +#define TW5864_INTR_VIN_LOST BIT(3) +/* n belongs to [0; 7] */ +#define TW5864_INTR_GPIO(n) (1 << (4 + n)) +#define TW5864_INTR_JPEG BIT(12) +#define TW5864_INTR_VLC_DONE BIT(17) +#define TW5864_INTR_AD_VSYNC BIT(19) +#define TW5864_INTR_PV_EOF BIT(20) +#define TW5864_INTR_PV_OVERFLOW BIT(21) +#define TW5864_INTR_TIMER BIT(22) +#define TW5864_INTR_AUD_EOF BIT(24) +#define TW5864_INTR_I2C_DONE BIT(25) +#define TW5864_INTR_AD BIT(26) + +/* 0x9000 ~ 0x920c -- Video Capture (VIF) Register Map */ +/* + * H264EN_CH_STATUS[n] Status of Vsync synchronized H264EN_CH_EN (Read Only) + * 1 Channel Enabled + * 0 Channel Disabled + */ +#define TW5864_H264EN_CH_STATUS 0x9000 +/* + * [15:0] H264EN_CH_EN[n] H264 Encoding Path Enable for channel + * 1 Channel Enabled + * 0 Channel Disabled + */ +#define TW5864_H264EN_CH_EN 0x9004 +/* + * H264EN_CH_DNS[n] H264 Encoding Path Downscale Video Decoder Input for + * channel n + * 1 Downscale Y to 1/2 + * 0 Does not downscale + */ +#define TW5864_H264EN_CH_DNS 0x9008 +/* + * H264EN_CH_PROG[n] H264 Encoding Path channel n is progressive + * 1 Progressive (Not valid for TW5864) + * 0 Interlaced (TW5864 default) + */ +#define TW5864_H264EN_CH_PROG 0x900c +/* + * [3:0] H264EN_BUS_MAX_CH[n] + * H264 Encoding Path maximum number of channel on BUS n + * 0 Max 4 channels + * 1 Max 2 channels + */ +#define TW5864_H264EN_BUS_MAX_CH 0x9010 + +/* + * H264EN_RATE_MAX_LINE_n H264 Encoding path Rate Mapping Maximum Line Number + * on Bus n + */ +#define TW5864_H264EN_RATE_MAX_LINE_EVEN 0x1f +#define TW5864_H264EN_RATE_MAX_LINE_ODD_SHIFT 5 +#define TW5864_H264EN_RATE_MAX_LINE_ODD (0x1f << 5) +/* + * [4:0] H264EN_RATE_MAX_LINE_0 + * [9:5] H264EN_RATE_MAX_LINE_1 + */ +#define TW5864_H264EN_RATE_MAX_LINE_REG1 0x9014 +/* + * [4:0] H264EN_RATE_MAX_LINE_2 + * [9:5] H264EN_RATE_MAX_LINE_3 + */ +#define TW5864_H264EN_RATE_MAX_LINE_REG2 0x9018 + +/* + * H264EN_CHn_FMT H264 Encoding Path Format configuration of Channel n + * 00 D1 (For D1 and hD1 frame) + * 01 (Reserved) + * 10 (Reserved) + * 11 D1 with 1/2 size in X (for CIF frame) + * Note: To be used with 0x9008 register to configure the frame size + */ +/* + * [1:0]: H264EN_CH0_FMT, + * ..., [15:14]: H264EN_CH7_FMT + */ +#define TW5864_H264EN_CH_FMT_REG1 0x9020 +/* + * [1:0]: H264EN_CH8_FMT (?), + * ..., [15:14]: H264EN_CH15_FMT (?) + */ +#define TW5864_H264EN_CH_FMT_REG2 0x9024 + +/* + * H264EN_RATE_CNTL_BUSm_CHn H264 Encoding Path BUS m Rate Control for Channel n + */ +#define TW5864_H264EN_RATE_CNTL_LO_WORD(bus, channel) \ + (0x9100 + bus * 0x20 + channel * 0x08) +#define TW5864_H264EN_RATE_CNTL_HI_WORD(bus, channel) \ + (0x9104 + bus * 0x20 + channel * 0x08) + +/* + * H264EN_BUSm_MAP_CHn The 16-to-1 MUX configuration register for each encoding + * channel (total of 16 channels). Four bits for each channel. + */ +#define TW5864_H264EN_BUS0_MAP 0x9200 +#define TW5864_H264EN_BUS1_MAP 0x9204 +#define TW5864_H264EN_BUS2_MAP 0x9208 +#define TW5864_H264EN_BUS3_MAP 0x920c + +/* This register is not defined in datasheet, but used in reference driver */ +#define TW5864_UNDECLARED_ERROR_FLAGS_0x9218 0x9218 + +#define TW5864_GPIO1 0x9800 +#define TW5864_GPIO2 0x9804 +/* Define controls in registers TW5864_GPIO1, TW5864_GPIO2 */ +/* GPIO DATA of Group n */ +#define TW5864_GPIO_DATA 0x00ff +#define TW5864_GPIO_OEN_SHIFT 8 +/* GPIO Output Enable of Group n */ +#define TW5864_GPIO_OEN (0xff << 8) + +/* 0xa000 ~ 0xa8ff – DDR Controller Register Map */ +/* DDR Controller A */ +/* + * [2:0] Data valid counter after read command to DDR. This is the delay value + * to show how many cycles the data will be back from DDR after we issue a read + * command. + */ +#define TW5864_RD_ACK_VLD_MUX 0xa000 + +#define TW5864_DDR_PERIODS 0xa004 +/* Define controls in register TW5864_DDR_PERIODS */ +/* + * Tras value, the minimum cycle of active to precharge command period, + * default is 7 + */ +#define TW5864_TRAS_CNT_MAX 0x000f +/* + * Trfc value, the minimum cycle of refresh to active or refresh command period, + * default is 4"hf + */ +#define TW5864_RFC_CNT_MAX_SHIFT 8 +#define TW5864_RFC_CNT_MAX (0x0f << 8) +/* + * Trcd value, the minimum cycle of active to internal read/write command + * period, default is 4"h2 + */ +#define TW5864_TCD_CNT_MAX_SHIFT 4 +#define TW5864_TCD_CNT_MAX (0x0f << 4) +/* Twr value, write recovery time, default is 4"h3 */ +#define TW5864_TWR_CNT_MAX_SHIFT 12 +#define TW5864_TWR_CNT_MAX (0x0f << 12) + +/* + * [2:0] CAS latency, the delay cycle between internal read command and the + * availability of the first bit of output data, default is 3 + */ +#define TW5864_CAS_LATENCY 0xa008 +/* + * [15:0] Maximum average periodic refresh, the value is based on the current + * frequency to match 7.8mcs + */ +#define TW5864_DDR_REF_CNTR_MAX 0xa00c +/* + * DDR_ON_CHIP_MAP [1:0] + * 0 256M DDR on board + * 1 512M DDR on board + * 2 1G DDR on board + * DDR_ON_CHIP_MAP [2] + * 0 Only one DDR chip + * 1 Two DDR chips + */ +#define TW5864_DDR_ON_CHIP_MAP 0xa01c +#define TW5864_DDR_SELFTEST_MODE 0xa020 +/* Define controls in register TW5864_DDR_SELFTEST_MODE */ +/* + * 0 Common read/write mode + * 1 DDR self-test mode + */ +#define TW5864_MASTER_MODE BIT(0) +/* + * 0 DDR self-test single read/write + * 1 DDR self-test burst read/write + */ +#define TW5864_SINGLE_PROC BIT(1) +/* + * 0 DDR self-test write command + * 1 DDR self-test read command + */ +#define TW5864_WRITE_FLAG BIT(2) +#define TW5864_DATA_MODE_SHIFT 4 +/* + * 0 write 32'haaaa5555 to DDR + * 1 write 32'hffffffff to DDR + * 2 write 32'hha5a55a5a to DDR + * 3 write increasing data to DDR + */ +#define TW5864_DATA_MODE (0x3 << 4) + +/* [7:0] The maximum data of one burst in DDR self-test mode */ +#define TW5864_BURST_CNTR_MAX 0xa024 +/* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */ +#define TW5864_DDR_PROC_CNTR_MAX_L 0xa028 +/* The maximum burst counter (bit 31~16) in DDR self-test mode */ +#define TW5864_DDR_PROC_CNTR_MAX_H 0xa02c +/* [0]: Start one DDR self-test */ +#define TW5864_DDR_SELF_TEST_CMD 0xa030 +/* The maximum error counter (bit 15 ~ 0) in DDR self-test */ +#define TW5864_ERR_CNTR_L 0xa034 + +#define TW5864_ERR_CNTR_H_AND_FLAG 0xa038 +/* Define controls in register TW5864_ERR_CNTR_H_AND_FLAG */ +/* The maximum error counter (bit 30 ~ 16) in DDR self-test */ +#define TW5864_ERR_CNTR_H_MASK 0x3fff +/* DDR self-test end flag */ +#define TW5864_END_FLAG 0x8000 + +/* + * DDR Controller B: same as 0xa000 ~ 0xa038, but add TW5864_DDR_B_OFFSET to all + * addresses + */ +#define TW5864_DDR_B_OFFSET 0x0800 + +/* 0xb004 ~ 0xb018 – HW version/ARB12 Register Map */ +/* [15:0] Default is C013 */ +#define TW5864_HW_VERSION 0xb004 + +#define TW5864_REQS_ENABLE 0xb010 +/* Define controls in register TW5864_REQS_ENABLE */ +/* Audio data in to DDR enable (default 1) */ +#define TW5864_AUD_DATA_IN_ENB BIT(0) +/* Audio encode request to DDR enable (default 1) */ +#define TW5864_AUD_ENC_REQ_ENB BIT(1) +/* Audio decode request0 to DDR enable (default 1) */ +#define TW5864_AUD_DEC_REQ0_ENB BIT(2) +/* Audio decode request1 to DDR enable (default 1) */ +#define TW5864_AUD_DEC_REQ1_ENB BIT(3) +/* VLC stream request to DDR enable (default 1) */ +#define TW5864_VLC_STRM_REQ_ENB BIT(4) +/* H264 MV request to DDR enable (default 1) */ +#define TW5864_DVM_MV_REQ_ENB BIT(5) +/* mux_core MVD request to DDR enable (default 1) */ +#define TW5864_MVD_REQ_ENB BIT(6) +/* mux_core MVD temp data request to DDR enable (default 1) */ +#define TW5864_MVD_TMP_REQ_ENB BIT(7) +/* JPEG request to DDR enable (default 1) */ +#define TW5864_JPEG_REQ_ENB BIT(8) +/* mv_flag request to DDR enable (default 1) */ +#define TW5864_MV_FLAG_REQ_ENB BIT(9) + +#define TW5864_ARB12 0xb018 +/* Define controls in register TW5864_ARB12 */ +/* ARB12 Enable (default 1) */ +#define TW5864_ARB12_ENB BIT(15) +/* ARB12 maximum value of time out counter (default 15"h1FF) */ +#define TW5864_ARB12_TIME_OUT_CNT 0x7fff + +/* 0xb800 ~ 0xb80c -- Indirect Access Register Map */ +/* + * Spec says: + * In order to access the indirect register space, the following procedure is + * followed. + * But reference driver implementation, and current driver, too, does it + * differently. + * + * Write Registers: + * (1) Write IND_DATA at 0xb804 ~ 0xb807 + * (2) Read BUSY flag from 0xb803. Wait until BUSY signal is 0. + * (3) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "1", ENABLE to "1" + * Read Registers: + * (1) Read BUSY flag from 0xb803. Wait until BUSY signal is 0. + * (2) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "0", ENABLE to "1" + * (3) Read BUSY flag from 0xb803. Wait until BUSY signal is 0. + * (4) Read IND_DATA from 0xb804 ~ 0xb807 + */ +#define TW5864_IND_CTL 0xb800 +/* Define controls in register TW5864_IND_CTL */ +/* Address used to access indirect register space */ +#define TW5864_IND_ADDR 0x0000ffff +/* Wait until this bit is "0" before using indirect access */ +#define TW5864_BUSY BIT(31) +/* Activate the indirect access. This bit is self cleared */ +#define TW5864_ENABLE BIT(25) +/* Read/Write command */ +#define TW5864_RW BIT(24) + +/* [31:0] Data used to read/write indirect register space */ +#define TW5864_IND_DATA 0xb804 + +/* 0xc000 ~ 0xc7fc -- Preview Register Map */ +/* Mostly skipped this section. */ +/* + * [15:0] Status of Vsync Synchronized PCI_PV_CH_EN (Read Only) + * 1 Channel Enabled + * 0 Channel Disabled + */ +#define TW5864_PCI_PV_CH_STATUS 0xc000 +/* + * [15:0] PCI Preview Path Enable for channel n + * 1 Channel Enable + * 0 Channel Disable + */ +#define TW5864_PCI_PV_CH_EN 0xc004 + +/* 0xc800 ~ 0xc804 -- JPEG Capture Register Map */ +/* Skipped. */ +/* 0xd000 ~ 0xd0fc -- JPEG Control Register Map */ +/* Skipped. */ + +/* 0xe000 ~ 0xfc04 – Motion Vector Register Map */ + +/* ME Motion Vector data (Four Byte Each) 0xe000 ~ 0xe7fc */ +#define TW5864_ME_MV_VEC_START 0xe000 +#define TW5864_ME_MV_VEC_MAX_OFFSET 0x1ff +#define TW5864_ME_MV_VEC(offset) (TW5864_ME_MV_VEC_START + 4 * offset) + +#define TW5864_MV 0xfc00 +/* Define controls in register TW5864_MV */ +/* mv bank0 full status , write "1" to clear */ +#define TW5864_MV_BK0_FULL BIT(0) +/* mv bank1 full status , write "1" to clear */ +#define TW5864_MV_BK1_FULL BIT(1) +/* slice end status; write "1" to clear */ +#define TW5864_MV_EOF BIT(2) +/* mv encode interrupt status; write "1" to clear */ +#define TW5864_MV_DSP_INTR BIT(3) +/* mv write memory overflow, write "1" to clear */ +#define TW5864_DSP_WR_OF BIT(4) +#define TW5864_MV_LEN_SHIFT 5 +/* mv stream length */ +#define TW5864_MV_LEN (0xff << 5) +/* The configured status bit written into bit 15 of 0xfc04 */ +#define TW5864_MPI_DDR_SEL BIT(13) + +#define TW5864_MPI_DDR_SEL_REG 0xfc04 +/* Define controls in register TW5864_MPI_DDR_SEL_REG */ +/* + * SW configure register + * 0 MV is saved in internal DPR + * 1 MV is saved in DDR + */ +#define TW5864_MPI_DDR_SEL2 BIT(15) + +/* 0x18000 ~ 0x181fc – PCI Master/Slave Control Map */ +#define TW5864_PCI_INTR_STATUS 0x18000 +/* Define controls in register TW5864_PCI_INTR_STATUS */ +/* vlc done */ +#define TW5864_VLC_DONE_INTR BIT(1) +/* ad vsync */ +#define TW5864_AD_VSYNC_INTR BIT(3) +/* preview eof */ +#define TW5864_PREV_EOF_INTR BIT(4) +/* preview overflow interrupt */ +#define TW5864_PREV_OVERFLOW_INTR BIT(5) +/* timer interrupt */ +#define TW5864_TIMER_INTR BIT(6) +/* audio eof */ +#define TW5864_AUDIO_EOF_INTR BIT(8) +/* IIC done */ +#define TW5864_IIC_DONE_INTR BIT(24) +/* ad interrupt (e.g.: video lost, video format changed) */ +#define TW5864_AD_INTR_REG BIT(25) + +#define TW5864_PCI_INTR_CTL 0x18004 +/* Define controls in register TW5864_PCI_INTR_CTL */ +/* master enable */ +#define TW5864_PCI_MAST_ENB BIT(0) +/* mvd&vlc master enable */ +#define TW5864_MVD_VLC_MAST_ENB 0x06 +/* (Need to set 0 in TW5864A) */ +#define TW5864_AD_MAST_ENB BIT(3) +/* preview master enable */ +#define TW5864_PREV_MAST_ENB BIT(4) +/* preview overflow enable */ +#define TW5864_PREV_OVERFLOW_ENB BIT(5) +/* timer interrupt enable */ +#define TW5864_TIMER_INTR_ENB BIT(6) +/* JPEG master (push mode) enable */ +#define TW5864_JPEG_MAST_ENB BIT(7) +#define TW5864_AU_MAST_ENB_CHN_SHIFT 8 +/* audio master channel enable */ +#define TW5864_AU_MAST_ENB_CHN (0xffff << 8) +/* IIC interrupt enable */ +#define TW5864_IIC_INTR_ENB BIT(24) +/* ad interrupt enable */ +#define TW5864_AD_INTR_ENB BIT(25) +/* target burst enable */ +#define TW5864_PCI_TAR_BURST_ENB BIT(26) +/* vlc stream burst enable */ +#define TW5864_PCI_VLC_BURST_ENB BIT(27) +/* ddr burst enable (1 enable, and must set DDR_BRST_EN) */ +#define TW5864_PCI_DDR_BURST_ENB BIT(28) + +/* + * Because preview and audio have 16 channels separately, so using this + * registers to indicate interrupt status for every channels. This is secondary + * interrupt status register. OR operating of the PREV_INTR_REG is + * PREV_EOF_INTR, OR operating of the AU_INTR_REG bits is AUDIO_EOF_INTR + */ +#define TW5864_PREV_AND_AU_INTR 0x18008 +/* Define controls in register TW5864_PREV_AND_AU_INTR */ +/* preview eof interrupt flag */ +#define TW5864_PREV_INTR_REG 0x0000ffff +#define TW5864_AU_INTR_REG_SHIFT 16 +/* audio eof interrupt flag */ +#define TW5864_AU_INTR_REG (0xffff << 16) + +#define TW5864_MASTER_ENB_REG 0x1800c +/* Define controls in register TW5864_MASTER_ENB_REG */ +/* master enable */ +#define TW5864_PCI_VLC_INTR_ENB BIT(1) +/* mvd and vlc master enable */ +#define TW5864_PCI_PREV_INTR_ENB BIT(4) +/* ad vsync master enable */ +#define TW5864_PCI_PREV_OF_INTR_ENB BIT(5) +/* jpeg master enable */ +#define TW5864_PCI_JPEG_INTR_ENB BIT(7) +/* preview master enable */ +#define TW5864_PCI_AUD_INTR_ENB BIT(8) + +/* + * Every channel of preview and audio have ping-pong buffers in system memory, + * this register is the buffer flag to notify software which buffer is been + * operated. + */ +#define TW5864_PREV_AND_AU_BUF_FLAG 0x18010 +/* Define controls in register TW5864_PREV_AND_AU_BUF_FLAG */ +/* preview buffer A/B flag */ +#define TW5864_PREV_BUF_FLAG 0xffff +#define TW5864_AUDIO_BUF_FLAG_SHIFT 16 +/* audio buffer A/B flag */ +#define TW5864_AUDIO_BUF_FLAG (0xffff << 16) + +#define TW5864_IIC 0x18014 +/* Define controls in register TW5864_IIC */ +/* register data */ +#define TW5864_IIC_DATA 0x00ff +#define TW5864_IIC_REG_ADDR_SHIFT 8 +/* register addr */ +#define TW5864_IIC_REG_ADDR (0xff << 8) +/* rd/wr flag rd=1,wr=0 */ +#define TW5864_IIC_RW BIT(16) +#define TW5864_IIC_DEV_ADDR_SHIFT 17 +/* device addr */ +#define TW5864_IIC_DEV_ADDR (0x7f << 17) +/* + * iic done, software kick off one time iic transaction through setting this + * bit to 1. Then poll this bit, value 1 indicate iic transaction have + * completed, if read, valid data have been stored in iic_data + */ +#define TW5864_IIC_DONE BIT(24) + +#define TW5864_RST_AND_IF_INFO 0x18018 +/* Define controls in register TW5864_RST_AND_IF_INFO */ +/* application software soft reset */ +#define TW5864_APP_SOFT_RST BIT(0) +#define TW5864_PCI_INF_VERSION_SHIFT 16 +/* PCI interface version, read only */ +#define TW5864_PCI_INF_VERSION (0xffff << 16) + +/* vlc stream crc value, it is calculated in pci module */ +#define TW5864_VLC_CRC_REG 0x1801c +/* + * vlc max length, it is defined by software based on software assign memory + * space for vlc + */ +#define TW5864_VLC_MAX_LENGTH 0x18020 +/* vlc length of one frame */ +#define TW5864_VLC_LENGTH 0x18024 +/* vlc original crc value */ +#define TW5864_VLC_INTRA_CRC_I_REG 0x18028 +/* vlc original crc value */ +#define TW5864_VLC_INTRA_CRC_O_REG 0x1802c +/* mv stream crc value, it is calculated in pci module */ +#define TW5864_VLC_PAR_CRC_REG 0x18030 +/* mv length */ +#define TW5864_VLC_PAR_LENGTH_REG 0x18034 +/* mv original crc value */ +#define TW5864_VLC_PAR_I_REG 0x18038 +/* mv original crc value */ +#define TW5864_VLC_PAR_O_REG 0x1803c + +/* + * Configuration register for 9[or 10] CIFs or 1D1+15QCIF Preview mode. + * PREV_PCI_ENB_CHN[0] Enable 9th preview channel (9CIF prev) or 1D1 channel in + * (1D1+15QCIF prev) + * PREV_PCI_ENB_CHN[1] Enable 10th preview channel + */ +#define TW5864_PREV_PCI_ENB_CHN 0x18040 +/* Description skipped. */ +#define TW5864_PREV_FRAME_FORMAT_IN 0x18044 +/* IIC enable */ +#define TW5864_IIC_ENB 0x18048 +/* + * Timer interrupt interval + * 0 1ms + * 1 2ms + * 2 4ms + * 3 8ms + */ +#define TW5864_PCI_INTTM_SCALE 0x1804c + +/* + * The above register is pci base address registers. Application software will + * initialize them to tell chip where the corresponding stream will be dumped + * to. Application software will select appropriate base address interval based + * on the stream length. + */ +/* VLC stream base address */ +#define TW5864_VLC_STREAM_BASE_ADDR 0x18080 +/* MV stream base address */ +#define TW5864_MV_STREAM_BASE_ADDR 0x18084 +/* 0x180a0 – 0x180bc: audio burst base address. Skipped. */ +/* 0x180c0 ~ 0x180dc – JPEG Push Mode Buffer Base Address. Skipped. */ +/* 0x18100 – 0x1817c: preview burst base address. Skipped. */ + +/* 0x80000 ~ 0x87fff -- DDR Burst RW Register Map */ +#define TW5864_DDR_CTL 0x80000 +/* Define controls in register TW5864_DDR_CTL */ +#define TW5864_BRST_LENGTH_SHIFT 2 +/* Length of 32-bit data burst */ +#define TW5864_BRST_LENGTH (0x3fff << 2) +/* + * Burst Read/Write + * 0 Read Burst from DDR + * 1 Write Burst to DDR + */ +#define TW5864_BRST_RW BIT(16) +/* Begin a new DDR Burst. This bit is self cleared */ +#define TW5864_NEW_BRST_CMD BIT(17) +/* DDR Burst End Flag */ +#define TW5864_BRST_END BIT(24) +/* Enable Error Interrupt for Single DDR Access */ +#define TW5864_SING_ERR_INTR BIT(25) +/* Enable Error Interrupt for Burst DDR Access */ +#define TW5864_BRST_ERR_INTR BIT(26) +/* Enable Interrupt for End of DDR Burst Access */ +#define TW5864_BRST_END_INTR BIT(27) +/* DDR Single Access Error Flag */ +#define TW5864_SINGLE_ERR BIT(28) +/* DDR Single Access Busy Flag */ +#define TW5864_SINGLE_BUSY BIT(29) +/* DDR Burst Access Error Flag */ +#define TW5864_BRST_ERR BIT(30) +/* DDR Burst Access Busy Flag */ +#define TW5864_BRST_BUSY BIT(31) + +/* [27:0] DDR Access Address. Bit [1:0] has to be 0 */ +#define TW5864_DDR_ADDR 0x80004 +/* DDR Access Internal Buffer Address. Bit [1:0] has to be 0 */ +#define TW5864_DPR_BUF_ADDR 0x80008 +/* SRAM Buffer MPI Access Space. Totally 16 KB */ +#define TW5864_DPR_BUF_START 0x84000 +/* 0x84000 - 0x87ffc */ +#define TW5864_DPR_BUF_SIZE 0x4000 + +/* Indirect Map Space */ +/* + * The indirect space is accessed through 0xb800 ~ 0xb807 registers in direct + * access space + */ +/* Analog Video / Audio Decoder / Encoder */ +/* Allowed channel values: [0; 3] */ +/* Read-only register */ +#define TW5864_INDIR_VIN_0(channel) (0x000 + channel * 0x010) +/* Define controls in register TW5864_INDIR_VIN_0 */ +/* + * 1 Video not present. (sync is not detected in number of consecutive line + * periods specified by MISSCNT register) + * 0 Video detected. + */ +#define TW5864_INDIR_VIN_0_VDLOSS BIT(7) +/* + * 1 Horizontal sync PLL is locked to the incoming video source. + * 0 Horizontal sync PLL is not locked. + */ +#define TW5864_INDIR_VIN_0_HLOCK BIT(6) +/* + * 1 Sub-carrier PLL is locked to the incoming video source. + * 0 Sub-carrier PLL is not locked. + */ +#define TW5864_INDIR_VIN_0_SLOCK BIT(5) +/* + * 1 Even field is being decoded. + * 0 Odd field is being decoded. + */ +#define TW5864_INDIR_VIN_0_FLD BIT(4) +/* + * 1 Vertical logic is locked to the incoming video source. + * 0 Vertical logic is not locked. + */ +#define TW5864_INDIR_VIN_0_VLOCK BIT(3) +/* + * 1 No color burst signal detected. + * 0 Color burst signal detected. + */ +#define TW5864_INDIR_VIN_0_MONO BIT(1) +/* + * 0 60Hz source detected + * 1 50Hz source detected + * The actual vertical scanning frequency depends on the current standard + * invoked. + */ +#define TW5864_INDIR_VIN_0_DET50 BIT(0) + +#define TW5864_INDIR_VIN_1(channel) (0x001 + channel * 0x010) +/* VCR signal indicator. Read-only. */ +#define TW5864_INDIR_VIN_1_VCR BIT(7) +/* Weak signal indicator 2. Read-only. */ +#define TW5864_INDIR_VIN_1_WKAIR BIT(6) +/* Weak signal indicator controlled by WKTH. Read-only. */ +#define TW5864_INDIR_VIN_1_WKAIR1 BIT(5) +/* + * 1 = Standard signal + * 0 = Non-standard signal + * Read-only + */ +#define TW5864_INDIR_VIN_1_VSTD BIT(4) +/* + * 1 = Non-interlaced signal + * 0 = interlaced signal + * Read-only + */ +#define TW5864_INDIR_VIN_1_NINTL BIT(3) +/* + * Vertical Sharpness Control. Writable. + * 0 = None (default) + * 7 = Highest + * **Note: VSHP must be set to ‘0’ if COMB = 0 + */ +#define TW5864_INDIR_VIN_1_VSHP 0x07 + +/* HDELAY_XY[7:0] */ +#define TW5864_INDIR_VIN_2_HDELAY_XY_LO(channel) (0x002 + channel * 0x010) +/* HACTIVE_XY[7:0] */ +#define TW5864_INDIR_VIN_3_HACTIVE_XY_LO(channel) (0x003 + channel * 0x010) +/* VDELAY_XY[7:0] */ +#define TW5864_INDIR_VIN_4_VDELAY_XY_LO(channel) (0x004 + channel * 0x010) +/* VACTIVE_XY[7:0] */ +#define TW5864_INDIR_VIN_5_VACTIVE_XY_LO(channel) (0x005 + channel * 0x010) + +#define TW5864_INDIR_VIN_6(channel) (0x006 + channel * 0x010) +/* Define controls in register TW5864_INDIR_VIN_6 */ +#define TW5864_INDIR_VIN_6_HDELAY_XY_HI 0x03 +#define TW5864_INDIR_VIN_6_HACTIVE_XY_HI_SHIFT 2 +#define TW5864_INDIR_VIN_6_HACTIVE_XY_HI (0x03 << 2) +#define TW5864_INDIR_VIN_6_VDELAY_XY_HI BIT(4) +#define TW5864_INDIR_VIN_6_VACTIVE_XY_HI BIT(5) + +/* + * HDELAY_XY This 10bit register defines the starting location of horizontal + * active pixel for display / record path. A unit is 1 pixel. The default value + * is 0x00f for NTSC and 0x00a for PAL. + * + * HACTIVE_XY This 10bit register defines the number of horizontal active pixel + * for display / record path. A unit is 1 pixel. The default value is decimal + * 720. + * + * VDELAY_XY This 9bit register defines the starting location of vertical + * active for display / record path. A unit is 1 line. The default value is + * decimal 6. + * + * VACTIVE_XY This 9bit register defines the number of vertical active lines + * for display / record path. A unit is 1 line. The default value is decimal + * 240. + */ + +/* HUE These bits control the color hue as 2's complement number. They have + * value from +36o (7Fh) to -36o (80h) with an increment of 2.8o. The 2 LSB has + * no effect. The positive value gives greenish tone and negative value gives + * purplish tone. The default value is 0o (00h). This is effective only on NTSC + * system. The default is 00h. + */ +#define TW5864_INDIR_VIN_7_HUE(channel) (0x007 + channel * 0x010) + +#define TW5864_INDIR_VIN_8(channel) (0x008 + channel * 0x010) +/* Define controls in register TW5864_INDIR_VIN_8 */ +/* + * This bit controls the center frequency of the peaking filter. + * The corresponding gain adjustment is HFLT. + * 0 Low + * 1 center + */ +#define TW5864_INDIR_VIN_8_SCURVE BIT(7) +/* CTI level selection. The default is 1. + * 0 None + * 3 Highest + */ +#define TW5864_INDIR_VIN_8_CTI_SHIFT 4 +#define TW5864_INDIR_VIN_8_CTI (0x03 << 4) + +/* + * These bits control the amount of sharpness enhancement on the luminance + * signals. There are 16 levels of control with "0" having no effect on the + * output image. 1 through 15 provides sharpness enhancement with "F" being the + * strongest. The default is 1. + */ +#define TW5864_INDIR_VIN_8_SHARPNESS 0x0f + +/* + * These bits control the luminance contrast gain. A value of 100 (64h) has a + * gain of 1. The range adjustment is from 0% to 255% at 1% per step. The + * default is 64h. + */ +#define TW5864_INDIR_VIN_9_CNTRST(channel) (0x009 + channel * 0x010) + +/* + * These bits control the brightness. They have value of –128 to 127 in 2's + * complement form. Positive value increases brightness. A value 0 has no + * effect on the data. The default is 00h. + */ +#define TW5864_INDIR_VIN_A_BRIGHT(channel) (0x00a + channel * 0x010) + +/* + * These bits control the digital gain adjustment to the U (or Cb) component of + * the digital video signal. The color saturation can be adjusted by adjusting + * the U and V color gain components by the same amount in the normal + * situation. The U and V can also be adjusted independently to provide greater + * flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has + * gain of 100%. The default is 80h. + */ +#define TW5864_INDIR_VIN_B_SAT_U(channel) (0x00b + channel * 0x010) + +/* + * These bits control the digital gain adjustment to the V (or Cr) component of + * the digital video signal. The color saturation can be adjusted by adjusting + * the U and V color gain components by the same amount in the normal + * situation. The U and V can also be adjusted independently to provide greater + * flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has + * gain of 100%. The default is 80h. + */ +#define TW5864_INDIR_VIN_C_SAT_V(channel) (0x00c + channel * 0x010) + +/* Read-only */ +#define TW5864_INDIR_VIN_D(channel) (0x00d + channel * 0x010) +/* Define controls in register TW5864_INDIR_VIN_D */ +/* Macrovision color stripe detection may be un-reliable */ +#define TW5864_INDIR_VIN_D_CSBAD BIT(3) +/* Macrovision AGC pulse detected */ +#define TW5864_INDIR_VIN_D_MCVSN BIT(2) +/* Macrovision color stripe protection burst detected */ +#define TW5864_INDIR_VIN_D_CSTRIPE BIT(1) +/* + * This bit is valid only when color stripe protection is detected, i.e. if + * CSTRIPE=1, + * 1 Type 2 color stripe protection + * 0 Type 3 color stripe protection + */ +#define TW5864_INDIR_VIN_D_CTYPE2 BIT(0) + +/* Read-only */ +#define TW5864_INDIR_VIN_E(channel) (0x00e + channel * 0x010) +/* Define controls in register TW5864_INDIR_VIN_E */ +/* + * Read-only. + * 0 Idle + * 1 Detection in progress + */ +#define TW5864_INDIR_VIN_E_DETSTUS BIT(7) +/* + * STDNOW Current standard invoked + * 0 NTSC (M) + * 1 PAL (B, D, G, H, I) + * 2 SECAM + * 3 NTSC4.43 + * 4 PAL (M) + * 5 PAL (CN) + * 6 PAL 60 + * 7 Not valid + */ +#define TW5864_INDIR_VIN_E_STDNOW_SHIFT 4 +#define TW5864_INDIR_VIN_E_STDNOW (0x07 << 4) + +/* + * 1 Disable the shadow registers + * 0 Enable VACTIVE and HDELAY shadow registers value depending on STANDARD. + * (Default) + */ +#define TW5864_INDIR_VIN_E_ATREG BIT(3) +/* + * STANDARD Standard selection + * 0 NTSC (M) + * 1 PAL (B, D, G, H, I) + * 2 SECAM + * 3 NTSC4.43 + * 4 PAL (M) + * 5 PAL (CN) + * 6 PAL 60 + * 7 Auto detection (Default) + */ +#define TW5864_INDIR_VIN_E_STANDARD 0x07 + +#define TW5864_INDIR_VIN_F(channel) (0x00f + channel * 0x010) +/* Define controls in register TW5864_INDIR_VIN_F */ +/* + * 1 Writing 1 to this bit will manually initiate the auto format detection + * process. This bit is a self-clearing bit + * 0 Manual initiation of auto format detection is done. (Default) + */ +#define TW5864_INDIR_VIN_F_ATSTART BIT(7) +/* Enable recognition of PAL60 (Default) */ +#define TW5864_INDIR_VIN_F_PAL60EN BIT(6) +/* Enable recognition of PAL (CN). (Default) */ +#define TW5864_INDIR_VIN_F_PALCNEN BIT(5) +/* Enable recognition of PAL (M). (Default) */ +#define TW5864_INDIR_VIN_F_PALMEN BIT(4) +/* Enable recognition of NTSC 4.43. (Default) */ +#define TW5864_INDIR_VIN_F_NTSC44EN BIT(3) +/* Enable recognition of SECAM. (Default) */ +#define TW5864_INDIR_VIN_F_SECAMEN BIT(2) +/* Enable recognition of PAL (B, D, G, H, I). (Default) */ +#define TW5864_INDIR_VIN_F_PALBEN BIT(1) +/* Enable recognition of NTSC (M). (Default) */ +#define TW5864_INDIR_VIN_F_NTSCEN BIT(0) + +/* Some registers skipped. */ + +/* Use falling edge to sample VD1-VD4 from 54 MHz to 108 MHz */ +#define TW5864_INDIR_VD_108_POL 0x041 +#define TW5864_INDIR_VD_108_POL_VD12 BIT(0) +#define TW5864_INDIR_VD_108_POL_VD34 BIT(1) +#define TW5864_INDIR_VD_108_POL_BOTH \ + (TW5864_INDIR_VD_108_POL_VD12 | TW5864_INDIR_VD_108_POL_VD34) + +/* Some registers skipped. */ + +/* + * Audio Input ADC gain control + * 0 0.25 + * 1 0.31 + * 2 0.38 + * 3 0.44 + * 4 0.50 + * 5 0.63 + * 6 0.75 + * 7 0.88 + * 8 1.00 (default) + * 9 1.25 + * 10 1.50 + * 11 1.75 + * 12 2.00 + * 13 2.25 + * 14 2.50 + * 15 2.75 + */ +/* [3:0] channel 0, [7:4] channel 1 */ +#define TW5864_INDIR_AIGAIN1 0x060 +/* [3:0] channel 2, [7:4] channel 3 */ +#define TW5864_INDIR_AIGAIN2 0x061 + +/* Some registers skipped */ + +#define TW5864_INDIR_AIN_0x06D 0x06d +/* Define controls in register TW5864_INDIR_AIN_0x06D */ +/* + * LAWMD Select u-Law/A-Law/PCM/SB data output format on ADATR and ADATM pin. + * 0 PCM output (default) + * 1 SB (Signed MSB bit in PCM data is inverted) output + * 2 u-Law output + * 3 A-Law output + */ +#define TW5864_INDIR_AIN_LAWMD_SHIFT 6 +#define TW5864_INDIR_AIN_LAWMD (0x03 << 6) +/* + * Disable the mixing ratio value for all audio. + * 0 Apply individual mixing ratio value for each audio (default) + * 1 Apply nominal value for all audio commonly + */ +#define TW5864_INDIR_AIN_MIX_DERATIO BIT(5) +/* + * Enable the mute function for audio channel AINn when n is 0 to 3. It effects + * only for mixing. When n = 4, it enable the mute function of the playback + * audio input. It effects only for single chip or the last stage chip + * 0 Normal + * 1 Muted (default) + */ +#define TW5864_INDIR_AIN_MIX_MUTE 0x1f + +/* Some registers skipped */ + +#define TW5864_INDIR_AIN_0x0E3 0x0e3 +/* Define controls in register TW5864_INDIR_AIN_0x0E3 */ +/* + * ADATP signal is coming from external ADPCM decoder, instead of on-chip ADPCM + * decoder + */ +#define TW5864_INDIR_AIN_0x0E3_EXT_ADATP BIT(7) +/* ACLKP output signal polarity inverse */ +#define TW5864_INDIR_AIN_0x0E3_ACLKPPOLO BIT(6) +/* + * ACLKR input signal polarity inverse. + * 0 Not inversed (Default) + * 1 Inversed + */ +#define TW5864_INDIR_AIN_0x0E3_ACLKRPOL BIT(5) +/* + * ACLKP input signal polarity inverse. + * 0 Not inversed (Default) + * 1 Inversed + */ +#define TW5864_INDIR_AIN_0x0E3_ACLKPPOLI BIT(4) +/* + * ACKI [21:0] control automatic set up with AFMD registers + * This mode is only effective when ACLKRMASTER=1 + * 0 ACKI [21:0] registers set up ACKI control + * 1 ACKI control is automatically set up by AFMD register values + */ +#define TW5864_INDIR_AIN_0x0E3_AFAUTO BIT(3) +/* + * AFAUTO control mode + * 0 8kHz setting (Default) + * 1 16kHz setting + * 2 32kHz setting + * 3 44.1kHz setting + * 4 48kHz setting + */ +#define TW5864_INDIR_AIN_0x0E3_AFMD 0x07 + +#define TW5864_INDIR_AIN_0x0E4 0x0e4 +/* Define controls in register TW5864_INDIR_AIN_0x0ED */ +/* + * 8bit I2S Record output mode. + * 0 L/R half length separated output (Default). + * 1 One continuous packed output equal to DSP output format. + */ +#define TW5864_INDIR_AIN_0x0E4_I2S8MODE BIT(7) +/* + * Audio Clock Master ACLKR output wave format. + * 0 High periods is one 27MHz clock period (default). + * 1 Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two + * times bigger number value need to be set up on the ACKI register. If + * AFAUTO=1, ACKI control is automatically set up even if MASCKMD=1. + */ +#define TW5864_INDIR_AIN_0x0E4_MASCKMD BIT(6) +/* Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping */ +#define TW5864_INDIR_AIN_0x0E4_PBINSWAP BIT(5) +/* + * ASYNR input signal delay. + * 0 No delay + * 1 Add one 27MHz period delay in ASYNR signal input + */ +#define TW5864_INDIR_AIN_0x0E4_ASYNRDLY BIT(4) +/* + * ASYNP input signal delay. + * 0 no delay + * 1 add one 27MHz period delay in ASYNP signal input + */ +#define TW5864_INDIR_AIN_0x0E4_ASYNPDLY BIT(3) +/* + * ADATP input data delay by one ACLKP clock. + * 0 No delay (Default). This is for I2S type 1T delay input interface. + * 1 Add 1 ACLKP clock delay in ADATP input data. This is for left-justified + * type 0T delay input interface. + */ +#define TW5864_INDIR_AIN_0x0E4_ADATPDLY BIT(2) +/* + * Select u-Law/A-Law/PCM/SB data input format on ADATP pin. + * 0 PCM input (Default) + * 1 SB (Signed MSB bit in PCM data is inverted) input + * 2 u-Law input + * 3 A-Law input + */ +#define TW5864_INDIR_AIN_0x0E4_INLAWMD 0x03 + +/* + * Enable state register updating and interrupt request of audio AIN5 detection + * for each input + */ +#define TW5864_INDIR_AIN_A5DETENA 0x0e5 + +/* Some registers skipped */ + +/* + * [7:3]: DEV_ID The TW5864 product ID code is 01000 + * [2:0]: REV_ID The revision number is 0h + */ +#define TW5864_INDIR_ID 0x0fe + +#define TW5864_INDIR_IN_PIC_WIDTH(channel) (0x200 + 4 * channel) +#define TW5864_INDIR_IN_PIC_HEIGHT(channel) (0x201 + 4 * channel) +#define TW5864_INDIR_OUT_PIC_WIDTH(channel) (0x202 + 4 * channel) +#define TW5864_INDIR_OUT_PIC_HEIGHT(channel) (0x203 + 4 * channel) +/* + * Interrupt status register from the front-end. Write "1" to each bit to clear + * the interrupt + * 15:0 Motion detection interrupt for channel 0 ~ 15 + * 31:16 Night detection interrupt for channel 0 ~ 15 + * 47:32 Blind detection interrupt for channel 0 ~ 15 + * 63:48 No video interrupt for channel 0 ~ 15 + * 79:64 Line mode underflow interrupt for channel 0 ~ 15 + * 95:80 Line mode overflow interrupt for channel 0 ~ 15 + */ +/* 0x2d0~0x2d7: [63:0] bits */ +#define TW5864_INDIR_INTERRUPT1 0x2d0 +/* 0x2e0~0x2e3: [95:64] bits */ +#define TW5864_INDIR_INTERRUPT2 0x2e0 + +/* + * Interrupt mask register for interrupts in 0x2d0 ~ 0x2d7 + * 15:0 Motion detection interrupt for channel 0 ~ 15 + * 31:16 Night detection interrupt for channel 0 ~ 15 + * 47:32 Blind detection interrupt for channel 0 ~ 15 + * 63:48 No video interrupt for channel 0 ~ 15 + * 79:64 Line mode underflow interrupt for channel 0 ~ 15 + * 95:80 Line mode overflow interrupt for channel 0 ~ 15 + */ +/* 0x2d8~0x2df: [63:0] bits */ +#define TW5864_INDIR_INTERRUPT_MASK1 0x2d8 +/* 0x2e8~0x2eb: [95:64] bits */ +#define TW5864_INDIR_INTERRUPT_MASK2 0x2e8 + +/* [11:0]: Interrupt summary register for interrupts & interrupt mask from in + * 0x2d0 ~ 0x2d7 and 0x2d8 ~ 0x2df + * bit 0: interrupt occurs in 0x2d0 & 0x2d8 + * bit 1: interrupt occurs in 0x2d1 & 0x2d9 + * bit 2: interrupt occurs in 0x2d2 & 0x2da + * bit 3: interrupt occurs in 0x2d3 & 0x2db + * bit 4: interrupt occurs in 0x2d4 & 0x2dc + * bit 5: interrupt occurs in 0x2d5 & 0x2dd + * bit 6: interrupt occurs in 0x2d6 & 0x2de + * bit 7: interrupt occurs in 0x2d7 & 0x2df + * bit 8: interrupt occurs in 0x2e0 & 0x2e8 + * bit 9: interrupt occurs in 0x2e1 & 0x2e9 + * bit 10: interrupt occurs in 0x2e2 & 0x2ea + * bit 11: interrupt occurs in 0x2e3 & 0x2eb + */ +#define TW5864_INDIR_INTERRUPT_SUMMARY 0x2f0 + +/* Motion / Blind / Night Detection */ +/* valid value for channel is [0:15] */ +#define TW5864_INDIR_DETECTION_CTL0(channel) (0x300 + channel * 0x08) +/* Define controls in register TW5864_INDIR_DETECTION_CTL0 */ +/* + * Disable the motion and blind detection. + * 0 Enable motion and blind detection (default) + * 1 Disable motion and blind detection + */ +#define TW5864_INDIR_DETECTION_CTL0_MD_DIS BIT(5) +/* + * Request to start motion detection on manual trigger mode + * 0 None Operation (default) + * 1 Request to start motion detection + */ +#define TW5864_INDIR_DETECTION_CTL0_MD_STRB BIT(3) +/* + * Select the trigger mode of motion detection + * 0 Automatic trigger mode of motion detection (default) + * 1 Manual trigger mode for motion detection + */ +#define TW5864_INDIR_DETECTION_CTL0_MD_STRB_EN BIT(2) +/* + * Define the threshold of cell for blind detection. + * 0 Low threshold (More sensitive) (default) + * : : + * 3 High threshold (Less sensitive) + */ +#define TW5864_INDIR_DETECTION_CTL0_BD_CELSENS 0x03 + +#define TW5864_INDIR_DETECTION_CTL1(channel) (0x301 + channel * 0x08) +/* Define controls in register TW5864_INDIR_DETECTION_CTL1 */ +/* + * Control the temporal sensitivity of motion detector. + * 0 More Sensitive (default) + * : : + * 15 Less Sensitive + */ +#define TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS_SHIFT 4 +#define TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS (0x0f << 4) +/* + * Adjust the horizontal starting position for motion detection + * 0 0 pixel (default) + * : : + * 15 15 pixels + */ +#define TW5864_INDIR_DETECTION_CTL1_MD_PIXEL_OS 0x0f + +#define TW5864_INDIR_DETECTION_CTL2(channel) (0x302 + channel * 0x08) +/* Define controls in register TW5864_INDIR_DETECTION_CTL2 */ +/* + * Control the updating time of reference field for motion detection. + * 0 Update reference field every field (default) + * 1 Update reference field according to MD_SPEED + */ +#define TW5864_INDIR_DETECTION_CTL2_MD_REFFLD BIT(7) +/* + * Select the field for motion detection. + * 0 Detecting motion for only odd field (default) + * 1 Detecting motion for only even field + * 2 Detecting motion for any field + * 3 Detecting motion for both odd and even field + */ +#define TW5864_INDIR_DETECTION_CTL2_MD_FIELD_SHIFT 5 +#define TW5864_INDIR_DETECTION_CTL2_MD_FIELD (0x03 << 5) +/* + * Control the level sensitivity of motion detector. + * 0 More sensitive (default) + * : : + * 15 Less sensitive + */ +#define TW5864_INDIR_DETECTION_CTL2_MD_LVSENS 0x1f + +#define TW5864_INDIR_DETECTION_CTL3(channel) (0x303 + channel * 0x08) +/* Define controls in register TW5864_INDIR_DETECTION_CTL3 */ +/* + * Define the threshold of sub-cell number for motion detection. + * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default) + * 1 Motion is detected if 2 sub-cells have motion + * 2 Motion is detected if 3 sub-cells have motion + * 3 Motion is detected if 4 sub-cells have motion (Less sensitive) + */ +#define TW5864_INDIR_DETECTION_CTL3_MD_CELSENS_SHIFT 6 +#define TW5864_INDIR_DETECTION_CTL3_MD_CELSENS (0x03 << 6) +/* + * Control the velocity of motion detector. + * Large value is suitable for slow motion detection. + * In MD_DUAL_EN = 1, MD_SPEED should be limited to 0 ~ 31. + * 0 1 field intervals (default) + * 1 2 field intervals + * : : + * 61 62 field intervals + * 62 63 field intervals + * 63 Not supported + */ +#define TW5864_INDIR_DETECTION_CTL3_MD_SPEED 0x3f + +#define TW5864_INDIR_DETECTION_CTL4(channel) (0x304 + channel * 0x08) +/* Define controls in register TW5864_INDIR_DETECTION_CTL4 */ +/* + * Control the spatial sensitivity of motion detector. + * 0 More Sensitive (default) + * : : + * 15 Less Sensitive + */ +#define TW5864_INDIR_DETECTION_CTL4_MD_SPSENS_SHIFT 4 +#define TW5864_INDIR_DETECTION_CTL4_MD_SPSENS (0x0f << 4) +/* + * Define the threshold of level for blind detection. + * 0 Low threshold (More sensitive) (default) + * : : + * 15 High threshold (Less sensitive) + */ +#define TW5864_INDIR_DETECTION_CTL4_BD_LVSENS 0x0f + +#define TW5864_INDIR_DETECTION_CTL5(channel) (0x305 + channel * 0x08) +/* + * Define the threshold of temporal sensitivity for night detection. + * 0 Low threshold (More sensitive) (default) + * : : + * 15 High threshold (Less sensitive) + */ +#define TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS_SHIFT 4 +#define TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS (0x0f << 4) +/* + * Define the threshold of level for night detection. + * 0 Low threshold (More sensitive) (default) + * : : + * 3 High threshold (Less sensitive) + */ +#define TW5864_INDIR_DETECTION_CTL5_ND_LVSENS 0x0f + +/* + * [11:0] The base address of the motion detection buffer. This address is in + * unit of 64K bytes. The generated DDR address will be {MD_BASE_ADDR, + * 16"h0000}. The default value should be 12"h000 + */ +#define TW5864_INDIR_MD_BASE_ADDR 0x380 + +/* + * This controls the channel of the motion detection result shown in register + * 0x3a0 ~ 0x3b7. Before reading back motion result, always set this first. + */ +#define TW5864_INDIR_RGR_MOTION_SEL 0x382 + +/* [15:0] MD strobe has been performed at channel n (read only) */ +#define TW5864_INDIR_MD_STRB 0x386 +/* NO_VIDEO Detected from channel n (read only) */ +#define TW5864_INDIR_NOVID_DET 0x388 +/* Motion Detected from channel n (read only) */ +#define TW5864_INDIR_MD_DET 0x38a +/* Blind Detected from channel n (read only) */ +#define TW5864_INDIR_BD_DET 0x38c +/* Night Detected from channel n (read only) */ +#define TW5864_INDIR_ND_DET 0x38e + +/* 192 bit motion flag of the channel specified by RGR_MOTION_SEL in 0x382 */ +#define TW5864_INDIR_MOTION_FLAG 0x3a0 +#define TW5864_INDIR_MOTION_FLAG_BYTE_COUNT 24 + +/* + * [9:0] The motion cell count of a specific channel selected by 0x382. This is + * for DI purpose + */ +#define TW5864_INDIR_MD_DI_CNT 0x3b8 +/* The motion detection cell sensitivity for DI purpose */ +#define TW5864_INDIR_MD_DI_CELLSENS 0x3ba +/* The motion detection threshold level for DI purpose */ +#define TW5864_INDIR_MD_DI_LVSENS 0x3bb + +/* 192 bit motion mask of the channel specified by MASK_CH_SEL in 0x3fe */ +#define TW5864_INDIR_MOTION_MASK 0x3e0 +#define TW5864_INDIR_MOTION_MASK_BYTE_COUNT 24 + +/* [4:0] The channel selection to access masks in 0x3e0 ~ 0x3f7 */ +#define TW5864_INDIR_MASK_CH_SEL 0x3fe + +/* Clock PLL / Analog IP Control */ +/* Some registers skipped */ + +#define TW5864_INDIR_DDRA_DLL_DQS_SEL0 0xee6 +#define TW5864_INDIR_DDRA_DLL_DQS_SEL1 0xee7 +#define TW5864_INDIR_DDRA_DLL_CLK90_SEL 0xee8 +#define TW5864_INDIR_DDRA_DLL_TEST_SEL_AND_TAP_S 0xee9 + +#define TW5864_INDIR_DDRB_DLL_DQS_SEL0 0xeeb +#define TW5864_INDIR_DDRB_DLL_DQS_SEL1 0xeec +#define TW5864_INDIR_DDRB_DLL_CLK90_SEL 0xeed +#define TW5864_INDIR_DDRB_DLL_TEST_SEL_AND_TAP_S 0xeee + +#define TW5864_INDIR_RESET 0xef0 +#define TW5864_INDIR_RESET_VD BIT(7) +#define TW5864_INDIR_RESET_DLL BIT(6) +#define TW5864_INDIR_RESET_MUX_CORE BIT(5) + +#define TW5864_INDIR_PV_VD_CK_POL 0xefd +#define TW5864_INDIR_PV_VD_CK_POL_PV(channel) BIT(channel) +#define TW5864_INDIR_PV_VD_CK_POL_VD(channel) BIT(channel + 4) + +#define TW5864_INDIR_CLK0_SEL 0xefe +#define TW5864_INDIR_CLK0_SEL_VD_SHIFT 0 +#define TW5864_INDIR_CLK0_SEL_VD_MASK 0x3 +#define TW5864_INDIR_CLK0_SEL_PV_SHIFT 2 +#define TW5864_INDIR_CLK0_SEL_PV_MASK (0x3 << 2) +#define TW5864_INDIR_CLK0_SEL_PV2_SHIFT 4 +#define TW5864_INDIR_CLK0_SEL_PV2_MASK (0x3 << 4) diff --git a/drivers/media/pci/tw5864/tw5864-util.c b/drivers/media/pci/tw5864/tw5864-util.c new file mode 100644 index 000000000000..771eef235755 --- /dev/null +++ b/drivers/media/pci/tw5864/tw5864-util.c @@ -0,0 +1,37 @@ +#include "tw5864.h" + +void tw5864_indir_writeb(struct tw5864_dev *dev, u16 addr, u8 data) +{ + int retries = 30000; + + while (tw_readl(TW5864_IND_CTL) & BIT(31) && --retries) + ; + if (!retries) + dev_err(&dev->pci->dev, + "tw_indir_writel() retries exhausted before writing\n"); + + tw_writel(TW5864_IND_DATA, data); + tw_writel(TW5864_IND_CTL, addr << 2 | TW5864_RW | TW5864_ENABLE); +} + +u8 tw5864_indir_readb(struct tw5864_dev *dev, u16 addr) +{ + int retries = 30000; + + while (tw_readl(TW5864_IND_CTL) & BIT(31) && --retries) + ; + if (!retries) + dev_err(&dev->pci->dev, + "tw_indir_readl() retries exhausted before reading\n"); + + tw_writel(TW5864_IND_CTL, addr << 2 | TW5864_ENABLE); + + retries = 30000; + while (tw_readl(TW5864_IND_CTL) & BIT(31) && --retries) + ; + if (!retries) + dev_err(&dev->pci->dev, + "tw_indir_readl() retries exhausted at reading\n"); + + return tw_readl(TW5864_IND_DATA); +} diff --git a/drivers/media/pci/tw5864/tw5864-video.c b/drivers/media/pci/tw5864/tw5864-video.c new file mode 100644 index 000000000000..3461ba9162e7 --- /dev/null +++ b/drivers/media/pci/tw5864/tw5864-video.c @@ -0,0 +1,1514 @@ +/* + * TW5864 driver - video encoding functions + * + * Copyright (C) 2016 Bluecherry, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "tw5864.h" +#include "tw5864-reg.h" + +#define QUANTIZATION_TABLE_LEN 96 +#define VLC_LOOKUP_TABLE_LEN 1024 + +static const u16 forward_quantization_table[QUANTIZATION_TABLE_LEN] = { + 0x3333, 0x1f82, 0x3333, 0x1f82, 0x1f82, 0x147b, 0x1f82, 0x147b, + 0x3333, 0x1f82, 0x3333, 0x1f82, 0x1f82, 0x147b, 0x1f82, 0x147b, + 0x2e8c, 0x1d42, 0x2e8c, 0x1d42, 0x1d42, 0x1234, 0x1d42, 0x1234, + 0x2e8c, 0x1d42, 0x2e8c, 0x1d42, 0x1d42, 0x1234, 0x1d42, 0x1234, + 0x2762, 0x199a, 0x2762, 0x199a, 0x199a, 0x1062, 0x199a, 0x1062, + 0x2762, 0x199a, 0x2762, 0x199a, 0x199a, 0x1062, 0x199a, 0x1062, + 0x2492, 0x16c1, 0x2492, 0x16c1, 0x16c1, 0x0e3f, 0x16c1, 0x0e3f, + 0x2492, 0x16c1, 0x2492, 0x16c1, 0x16c1, 0x0e3f, 0x16c1, 0x0e3f, + 0x2000, 0x147b, 0x2000, 0x147b, 0x147b, 0x0d1b, 0x147b, 0x0d1b, + 0x2000, 0x147b, 0x2000, 0x147b, 0x147b, 0x0d1b, 0x147b, 0x0d1b, + 0x1c72, 0x11cf, 0x1c72, 0x11cf, 0x11cf, 0x0b4d, 0x11cf, 0x0b4d, + 0x1c72, 0x11cf, 0x1c72, 0x11cf, 0x11cf, 0x0b4d, 0x11cf, 0x0b4d +}; + +static const u16 inverse_quantization_table[QUANTIZATION_TABLE_LEN] = { + 0x800a, 0x800d, 0x800a, 0x800d, 0x800d, 0x8010, 0x800d, 0x8010, + 0x800a, 0x800d, 0x800a, 0x800d, 0x800d, 0x8010, 0x800d, 0x8010, + 0x800b, 0x800e, 0x800b, 0x800e, 0x800e, 0x8012, 0x800e, 0x8012, + 0x800b, 0x800e, 0x800b, 0x800e, 0x800e, 0x8012, 0x800e, 0x8012, + 0x800d, 0x8010, 0x800d, 0x8010, 0x8010, 0x8014, 0x8010, 0x8014, + 0x800d, 0x8010, 0x800d, 0x8010, 0x8010, 0x8014, 0x8010, 0x8014, + 0x800e, 0x8012, 0x800e, 0x8012, 0x8012, 0x8017, 0x8012, 0x8017, + 0x800e, 0x8012, 0x800e, 0x8012, 0x8012, 0x8017, 0x8012, 0x8017, + 0x8010, 0x8014, 0x8010, 0x8014, 0x8014, 0x8019, 0x8014, 0x8019, + 0x8010, 0x8014, 0x8010, 0x8014, 0x8014, 0x8019, 0x8014, 0x8019, + 0x8012, 0x8017, 0x8012, 0x8017, 0x8017, 0x801d, 0x8017, 0x801d, + 0x8012, 0x8017, 0x8012, 0x8017, 0x8017, 0x801d, 0x8017, 0x801d +}; + +static const u16 encoder_vlc_lookup_table[VLC_LOOKUP_TABLE_LEN] = { + 0x011, 0x000, 0x000, 0x000, 0x065, 0x021, 0x000, 0x000, 0x087, 0x064, + 0x031, 0x000, 0x097, 0x086, 0x075, 0x053, 0x0a7, 0x096, 0x085, 0x063, + 0x0b7, 0x0a6, 0x095, 0x074, 0x0df, 0x0b6, 0x0a5, 0x084, 0x0db, 0x0de, + 0x0b5, 0x094, 0x0d8, 0x0da, 0x0dd, 0x0a4, 0x0ef, 0x0ee, 0x0d9, 0x0b4, + 0x0eb, 0x0ea, 0x0ed, 0x0dc, 0x0ff, 0x0fe, 0x0e9, 0x0ec, 0x0fb, 0x0fa, + 0x0fd, 0x0e8, 0x10f, 0x0f1, 0x0f9, 0x0fc, 0x10b, 0x10e, 0x10d, 0x0f8, + 0x107, 0x10a, 0x109, 0x10c, 0x104, 0x106, 0x105, 0x108, 0x023, 0x000, + 0x000, 0x000, 0x06b, 0x022, 0x000, 0x000, 0x067, 0x057, 0x033, 0x000, + 0x077, 0x06a, 0x069, 0x045, 0x087, 0x066, 0x065, 0x044, 0x084, 0x076, + 0x075, 0x056, 0x097, 0x086, 0x085, 0x068, 0x0bf, 0x096, 0x095, 0x064, + 0x0bb, 0x0be, 0x0bd, 0x074, 0x0cf, 0x0ba, 0x0b9, 0x094, 0x0cb, 0x0ce, + 0x0cd, 0x0bc, 0x0c8, 0x0ca, 0x0c9, 0x0b8, 0x0df, 0x0de, 0x0dd, 0x0cc, + 0x0db, 0x0da, 0x0d9, 0x0dc, 0x0d7, 0x0eb, 0x0d6, 0x0d8, 0x0e9, 0x0e8, + 0x0ea, 0x0d1, 0x0e7, 0x0e6, 0x0e5, 0x0e4, 0x04f, 0x000, 0x000, 0x000, + 0x06f, 0x04e, 0x000, 0x000, 0x06b, 0x05f, 0x04d, 0x000, 0x068, 0x05c, + 0x05e, 0x04c, 0x07f, 0x05a, 0x05b, 0x04b, 0x07b, 0x058, 0x059, 0x04a, + 0x079, 0x06e, 0x06d, 0x049, 0x078, 0x06a, 0x069, 0x048, 0x08f, 0x07e, + 0x07d, 0x05d, 0x08b, 0x08e, 0x07a, 0x06c, 0x09f, 0x08a, 0x08d, 0x07c, + 0x09b, 0x09e, 0x089, 0x08c, 0x098, 0x09a, 0x09d, 0x088, 0x0ad, 0x097, + 0x099, 0x09c, 0x0a9, 0x0ac, 0x0ab, 0x0aa, 0x0a5, 0x0a8, 0x0a7, 0x0a6, + 0x0a1, 0x0a4, 0x0a3, 0x0a2, 0x021, 0x000, 0x000, 0x000, 0x067, 0x011, + 0x000, 0x000, 0x064, 0x066, 0x031, 0x000, 0x063, 0x073, 0x072, 0x065, + 0x062, 0x083, 0x082, 0x070, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x011, 0x010, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x011, 0x021, 0x020, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x023, 0x022, 0x021, 0x020, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x023, 0x022, 0x021, 0x031, + 0x030, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x023, 0x022, 0x033, 0x032, 0x031, 0x030, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x023, 0x030, + 0x031, 0x033, 0x032, 0x035, 0x034, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x037, 0x036, 0x035, 0x034, 0x033, 0x032, + 0x031, 0x041, 0x051, 0x061, 0x071, 0x081, 0x091, 0x0a1, 0x0b1, 0x000, + 0x002, 0x000, 0x0e4, 0x011, 0x0f4, 0x002, 0x024, 0x003, 0x005, 0x012, + 0x034, 0x013, 0x065, 0x024, 0x013, 0x063, 0x015, 0x022, 0x075, 0x034, + 0x044, 0x023, 0x023, 0x073, 0x054, 0x033, 0x033, 0x004, 0x043, 0x014, + 0x011, 0x043, 0x014, 0x001, 0x025, 0x015, 0x035, 0x025, 0x064, 0x055, + 0x045, 0x035, 0x074, 0x065, 0x085, 0x0d5, 0x012, 0x095, 0x055, 0x045, + 0x095, 0x0e5, 0x084, 0x075, 0x022, 0x0a5, 0x094, 0x085, 0x032, 0x0b5, + 0x003, 0x0c5, 0x001, 0x044, 0x0a5, 0x032, 0x0b5, 0x094, 0x0c5, 0x0a4, + 0x0a4, 0x054, 0x0d5, 0x0b4, 0x0b4, 0x064, 0x0f5, 0x0f5, 0x053, 0x0d4, + 0x0e5, 0x0c4, 0x105, 0x105, 0x0c4, 0x074, 0x063, 0x0e4, 0x0d4, 0x084, + 0x073, 0x0f4, 0x004, 0x005, 0x000, 0x053, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x011, 0x021, 0x031, 0x030, 0x011, 0x021, 0x020, 0x000, + 0x011, 0x010, 0x000, 0x000, 0x011, 0x033, 0x032, 0x043, 0x042, 0x053, + 0x052, 0x063, 0x062, 0x073, 0x072, 0x083, 0x082, 0x093, 0x092, 0x091, + 0x037, 0x036, 0x035, 0x034, 0x033, 0x045, 0x044, 0x043, 0x042, 0x053, + 0x052, 0x063, 0x062, 0x061, 0x060, 0x000, 0x045, 0x037, 0x036, 0x035, + 0x044, 0x043, 0x034, 0x033, 0x042, 0x053, 0x052, 0x061, 0x051, 0x060, + 0x000, 0x000, 0x053, 0x037, 0x045, 0x044, 0x036, 0x035, 0x034, 0x043, + 0x033, 0x042, 0x052, 0x051, 0x050, 0x000, 0x000, 0x000, 0x045, 0x044, + 0x043, 0x037, 0x036, 0x035, 0x034, 0x033, 0x042, 0x051, 0x041, 0x050, + 0x000, 0x000, 0x000, 0x000, 0x061, 0x051, 0x037, 0x036, 0x035, 0x034, + 0x033, 0x032, 0x041, 0x031, 0x060, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x061, 0x051, 0x035, 0x034, 0x033, 0x023, 0x032, 0x041, 0x031, 0x060, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x061, 0x041, 0x051, 0x033, + 0x023, 0x022, 0x032, 0x031, 0x060, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x061, 0x060, 0x041, 0x023, 0x022, 0x031, 0x021, 0x051, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x051, 0x050, + 0x031, 0x023, 0x022, 0x021, 0x041, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x040, 0x041, 0x031, 0x032, 0x011, 0x033, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x040, 0x041, 0x021, 0x011, 0x031, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x030, 0x031, 0x011, 0x021, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x020, 0x021, 0x011, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x010, 0x011, + 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000 +}; + +static const unsigned int lambda_lookup_table[] = { + 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, + 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, + 0x0040, 0x0040, 0x0040, 0x0040, 0x0060, 0x0060, 0x0060, 0x0080, + 0x0080, 0x0080, 0x00a0, 0x00c0, 0x00c0, 0x00e0, 0x0100, 0x0120, + 0x0140, 0x0160, 0x01a0, 0x01c0, 0x0200, 0x0240, 0x0280, 0x02e0, + 0x0320, 0x03a0, 0x0400, 0x0480, 0x0500, 0x05a0, 0x0660, 0x0720, + 0x0800, 0x0900, 0x0a20, 0x0b60 +}; + +static const unsigned int intra4x4_lambda3[] = { + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 2, 2, 2, 2, 3, 3, 3, 4, + 4, 4, 5, 6, 6, 7, 8, 9, + 10, 11, 13, 14, 16, 18, 20, 23, + 25, 29, 32, 36, 40, 45, 51, 57, + 64, 72, 81, 91 +}; + +static v4l2_std_id tw5864_get_v4l2_std(enum tw5864_vid_std std); +static enum tw5864_vid_std tw5864_from_v4l2_std(v4l2_std_id v4l2_std); + +static void tw5864_handle_frame_task(unsigned long data); +static void tw5864_handle_frame(struct tw5864_h264_frame *frame); +static void tw5864_frame_interval_set(struct tw5864_input *input); + +static int tw5864_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, + unsigned int *num_planes, unsigned int sizes[], + struct device *alloc_ctxs[]) +{ + if (*num_planes) + return sizes[0] < H264_VLC_BUF_SIZE ? -EINVAL : 0; + + sizes[0] = H264_VLC_BUF_SIZE; + *num_planes = 1; + + return 0; +} + +static void tw5864_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vb2_queue *vq = vb->vb2_queue; + struct tw5864_input *dev = vb2_get_drv_priv(vq); + struct tw5864_buf *buf = container_of(vbuf, struct tw5864_buf, vb); + unsigned long flags; + + spin_lock_irqsave(&dev->slock, flags); + list_add_tail(&buf->list, &dev->active); + spin_unlock_irqrestore(&dev->slock, flags); +} + +static int tw5864_input_std_get(struct tw5864_input *input, + enum tw5864_vid_std *std) +{ + struct tw5864_dev *dev = input->root; + u8 std_reg = tw_indir_readb(TW5864_INDIR_VIN_E(input->nr)); + + *std = (std_reg & 0x70) >> 4; + + if (std_reg & 0x80) { + dev_dbg(&dev->pci->dev, + "Video format detection is in progress, please wait\n"); + return -EAGAIN; + } + + return 0; +} + +static int tw5864_enable_input(struct tw5864_input *input) +{ + struct tw5864_dev *dev = input->root; + int nr = input->nr; + unsigned long flags; + int d1_width = 720; + int d1_height; + int frame_width_bus_value = 0; + int frame_height_bus_value = 0; + int reg_frame_bus = 0x1c; + int fmt_reg_value = 0; + int downscale_enabled = 0; + + dev_dbg(&dev->pci->dev, "Enabling channel %d\n", nr); + + input->frame_seqno = 0; + input->frame_gop_seqno = 0; + input->h264_idr_pic_id = 0; + + input->reg_dsp_qp = input->qp; + input->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp]; + input->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp]; + input->reg_emu = TW5864_EMU_EN_LPF | TW5864_EMU_EN_BHOST + | TW5864_EMU_EN_SEN | TW5864_EMU_EN_ME | TW5864_EMU_EN_DDR; + input->reg_dsp = nr /* channel id */ + | TW5864_DSP_CHROM_SW + | ((0xa << 8) & TW5864_DSP_MB_DELAY) + ; + + input->resolution = D1; + + d1_height = (input->std == STD_NTSC) ? 480 : 576; + + input->width = d1_width; + input->height = d1_height; + + input->reg_interlacing = 0x4; + + switch (input->resolution) { + case D1: + frame_width_bus_value = 0x2cf; + frame_height_bus_value = input->height - 1; + reg_frame_bus = 0x1c; + fmt_reg_value = 0; + downscale_enabled = 0; + input->reg_dsp_codec |= TW5864_CIF_MAP_MD | TW5864_HD1_MAP_MD; + input->reg_emu |= TW5864_DSP_FRAME_TYPE_D1; + input->reg_interlacing = TW5864_DI_EN | TW5864_DSP_INTER_ST; + + tw_setl(TW5864_FULL_HALF_FLAG, 1 << nr); + break; + case HD1: + input->height /= 2; + input->width /= 2; + frame_width_bus_value = 0x2cf; + frame_height_bus_value = input->height * 2 - 1; + reg_frame_bus = 0x1c; + fmt_reg_value = 0; + downscale_enabled = 0; + input->reg_dsp_codec |= TW5864_HD1_MAP_MD; + input->reg_emu |= TW5864_DSP_FRAME_TYPE_D1; + + tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr); + + break; + case CIF: + input->height /= 4; + input->width /= 2; + frame_width_bus_value = 0x15f; + frame_height_bus_value = input->height * 2 - 1; + reg_frame_bus = 0x07; + fmt_reg_value = 1; + downscale_enabled = 1; + input->reg_dsp_codec |= TW5864_CIF_MAP_MD; + + tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr); + break; + case QCIF: + input->height /= 4; + input->width /= 4; + frame_width_bus_value = 0x15f; + frame_height_bus_value = input->height * 2 - 1; + reg_frame_bus = 0x07; + fmt_reg_value = 1; + downscale_enabled = 1; + input->reg_dsp_codec |= TW5864_CIF_MAP_MD; + + tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr); + break; + } + + /* analog input width / 4 */ + tw_indir_writeb(TW5864_INDIR_IN_PIC_WIDTH(nr), d1_width / 4); + tw_indir_writeb(TW5864_INDIR_IN_PIC_HEIGHT(nr), d1_height / 4); + + /* output width / 4 */ + tw_indir_writeb(TW5864_INDIR_OUT_PIC_WIDTH(nr), input->width / 4); + tw_indir_writeb(TW5864_INDIR_OUT_PIC_HEIGHT(nr), input->height / 4); + + tw_writel(TW5864_DSP_PIC_MAX_MB, + ((input->width / 16) << 8) | (input->height / 16)); + + tw_writel(TW5864_FRAME_WIDTH_BUS_A(nr), + frame_width_bus_value); + tw_writel(TW5864_FRAME_WIDTH_BUS_B(nr), + frame_width_bus_value); + tw_writel(TW5864_FRAME_HEIGHT_BUS_A(nr), + frame_height_bus_value); + tw_writel(TW5864_FRAME_HEIGHT_BUS_B(nr), + (frame_height_bus_value + 1) / 2 - 1); + + tw5864_frame_interval_set(input); + + if (downscale_enabled) + tw_setl(TW5864_H264EN_CH_DNS, 1 << nr); + + tw_mask_shift_writel(TW5864_H264EN_CH_FMT_REG1, 0x3, 2 * nr, + fmt_reg_value); + + tw_mask_shift_writel((nr < 2 + ? TW5864_H264EN_RATE_MAX_LINE_REG1 + : TW5864_H264EN_RATE_MAX_LINE_REG2), + 0x1f, 5 * (nr % 2), + input->std == STD_NTSC ? 29 : 24); + + tw_mask_shift_writel((nr < 2) ? TW5864_FRAME_BUS1 : + TW5864_FRAME_BUS2, 0xff, (nr % 2) * 8, + reg_frame_bus); + + spin_lock_irqsave(&dev->slock, flags); + input->enabled = 1; + spin_unlock_irqrestore(&dev->slock, flags); + + return 0; +} + +void tw5864_request_encoded_frame(struct tw5864_input *input) +{ + struct tw5864_dev *dev = input->root; + u32 enc_buf_id_new; + + tw_setl(TW5864_DSP_CODEC, TW5864_CIF_MAP_MD | TW5864_HD1_MAP_MD); + tw_writel(TW5864_EMU, input->reg_emu); + tw_writel(TW5864_INTERLACING, input->reg_interlacing); + tw_writel(TW5864_DSP, input->reg_dsp); + + tw_writel(TW5864_DSP_QP, input->reg_dsp_qp); + tw_writel(TW5864_DSP_REF_MVP_LAMBDA, input->reg_dsp_ref_mvp_lambda); + tw_writel(TW5864_DSP_I4x4_WEIGHT, input->reg_dsp_i4x4_weight); + tw_mask_shift_writel(TW5864_DSP_INTRA_MODE, TW5864_DSP_INTRA_MODE_MASK, + TW5864_DSP_INTRA_MODE_SHIFT, + TW5864_DSP_INTRA_MODE_16x16); + + if (input->frame_gop_seqno == 0) { + /* Produce I-frame */ + tw_writel(TW5864_MOTION_SEARCH_ETC, TW5864_INTRA_EN); + input->h264_idr_pic_id++; + input->h264_idr_pic_id &= TW5864_DSP_REF_FRM; + } else { + /* Produce P-frame */ + tw_writel(TW5864_MOTION_SEARCH_ETC, TW5864_INTRA_EN | + TW5864_ME_EN | BIT(5) /* SRCH_OPT default */); + } + tw5864_prepare_frame_headers(input); + tw_writel(TW5864_VLC, + TW5864_VLC_PCI_SEL | + ((input->tail_nb_bits + 24) << TW5864_VLC_BIT_ALIGN_SHIFT) | + input->reg_dsp_qp); + + enc_buf_id_new = tw_mask_shift_readl(TW5864_ENC_BUF_PTR_REC1, 0x3, + 2 * input->nr); + tw_writel(TW5864_DSP_ENC_ORG_PTR_REG, + enc_buf_id_new << TW5864_DSP_ENC_ORG_PTR_SHIFT); + tw_writel(TW5864_DSP_ENC_REC, + enc_buf_id_new << 12 | ((enc_buf_id_new + 3) & 3)); + + tw_writel(TW5864_SLICE, TW5864_START_NSLICE); + tw_writel(TW5864_SLICE, 0); +} + +static int tw5864_disable_input(struct tw5864_input *input) +{ + struct tw5864_dev *dev = input->root; + unsigned long flags; + + dev_dbg(&dev->pci->dev, "Disabling channel %d\n", input->nr); + + spin_lock_irqsave(&dev->slock, flags); + input->enabled = 0; + spin_unlock_irqrestore(&dev->slock, flags); + return 0; +} + +static int tw5864_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct tw5864_input *input = vb2_get_drv_priv(q); + int ret; + + ret = tw5864_enable_input(input); + if (!ret) + return 0; + + while (!list_empty(&input->active)) { + struct tw5864_buf *buf = list_entry(input->active.next, + struct tw5864_buf, list); + + list_del(&buf->list); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); + } + return ret; +} + +static void tw5864_stop_streaming(struct vb2_queue *q) +{ + unsigned long flags; + struct tw5864_input *input = vb2_get_drv_priv(q); + + tw5864_disable_input(input); + + spin_lock_irqsave(&input->slock, flags); + if (input->vb) { + vb2_buffer_done(&input->vb->vb.vb2_buf, VB2_BUF_STATE_ERROR); + input->vb = NULL; + } + while (!list_empty(&input->active)) { + struct tw5864_buf *buf = list_entry(input->active.next, + struct tw5864_buf, list); + + list_del(&buf->list); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + } + spin_unlock_irqrestore(&input->slock, flags); +} + +static struct vb2_ops tw5864_video_qops = { + .queue_setup = tw5864_queue_setup, + .buf_queue = tw5864_buf_queue, + .start_streaming = tw5864_start_streaming, + .stop_streaming = tw5864_stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; + +static int tw5864_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct tw5864_input *input = + container_of(ctrl->handler, struct tw5864_input, hdl); + struct tw5864_dev *dev = input->root; + unsigned long flags; + + switch (ctrl->id) { + case V4L2_CID_BRIGHTNESS: + tw_indir_writeb(TW5864_INDIR_VIN_A_BRIGHT(input->nr), + (u8)ctrl->val); + break; + case V4L2_CID_HUE: + tw_indir_writeb(TW5864_INDIR_VIN_7_HUE(input->nr), + (u8)ctrl->val); + break; + case V4L2_CID_CONTRAST: + tw_indir_writeb(TW5864_INDIR_VIN_9_CNTRST(input->nr), + (u8)ctrl->val); + break; + case V4L2_CID_SATURATION: + tw_indir_writeb(TW5864_INDIR_VIN_B_SAT_U(input->nr), + (u8)ctrl->val); + tw_indir_writeb(TW5864_INDIR_VIN_C_SAT_V(input->nr), + (u8)ctrl->val); + break; + case V4L2_CID_MPEG_VIDEO_GOP_SIZE: + input->gop = ctrl->val; + return 0; + case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: + spin_lock_irqsave(&input->slock, flags); + input->qp = ctrl->val; + input->reg_dsp_qp = input->qp; + input->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp]; + input->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp]; + spin_unlock_irqrestore(&input->slock, flags); + return 0; + case V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD: + memset(input->md_threshold_grid_values, ctrl->val, + sizeof(input->md_threshold_grid_values)); + return 0; + case V4L2_CID_DETECT_MD_MODE: + return 0; + case V4L2_CID_DETECT_MD_THRESHOLD_GRID: + /* input->md_threshold_grid_ctrl->p_new.p_u16 contains data */ + memcpy(input->md_threshold_grid_values, + input->md_threshold_grid_ctrl->p_new.p_u16, + sizeof(input->md_threshold_grid_values)); + return 0; + } + return 0; +} + +static int tw5864_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct tw5864_input *input = video_drvdata(file); + + f->fmt.pix.width = 720; + switch (input->std) { + default: + WARN_ON_ONCE(1); + case STD_NTSC: + f->fmt.pix.height = 480; + break; + case STD_PAL: + case STD_SECAM: + f->fmt.pix.height = 576; + break; + } + f->fmt.pix.field = V4L2_FIELD_INTERLACED; + f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264; + f->fmt.pix.sizeimage = H264_VLC_BUF_SIZE; + f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; + return 0; +} + +static int tw5864_enum_input(struct file *file, void *priv, + struct v4l2_input *i) +{ + struct tw5864_input *input = video_drvdata(file); + struct tw5864_dev *dev = input->root; + + u8 indir_0x000 = tw_indir_readb(TW5864_INDIR_VIN_0(input->nr)); + u8 indir_0x00d = tw_indir_readb(TW5864_INDIR_VIN_D(input->nr)); + u8 v1 = indir_0x000; + u8 v2 = indir_0x00d; + + if (i->index) + return -EINVAL; + + i->type = V4L2_INPUT_TYPE_CAMERA; + snprintf(i->name, sizeof(i->name), "Encoder %d", input->nr); + i->std = TW5864_NORMS; + if (v1 & (1 << 7)) + i->status |= V4L2_IN_ST_NO_SYNC; + if (!(v1 & (1 << 6))) + i->status |= V4L2_IN_ST_NO_H_LOCK; + if (v1 & (1 << 2)) + i->status |= V4L2_IN_ST_NO_SIGNAL; + if (v1 & (1 << 1)) + i->status |= V4L2_IN_ST_NO_COLOR; + if (v2 & (1 << 2)) + i->status |= V4L2_IN_ST_MACROVISION; + + return 0; +} + +static int tw5864_g_input(struct file *file, void *priv, unsigned int *i) +{ + *i = 0; + return 0; +} + +static int tw5864_s_input(struct file *file, void *priv, unsigned int i) +{ + if (i) + return -EINVAL; + return 0; +} + +static int tw5864_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct tw5864_input *input = video_drvdata(file); + + strcpy(cap->driver, "tw5864"); + snprintf(cap->card, sizeof(cap->card), "TW5864 Encoder %d", + input->nr); + sprintf(cap->bus_info, "PCI:%s", pci_name(input->root->pci)); + return 0; +} + +static int tw5864_querystd(struct file *file, void *priv, v4l2_std_id *std) +{ + struct tw5864_input *input = video_drvdata(file); + enum tw5864_vid_std tw_std; + int ret; + + ret = tw5864_input_std_get(input, &tw_std); + if (ret) + return ret; + *std = tw5864_get_v4l2_std(tw_std); + + return 0; +} + +static int tw5864_g_std(struct file *file, void *priv, v4l2_std_id *std) +{ + struct tw5864_input *input = video_drvdata(file); + + *std = input->v4l2_std; + return 0; +} + +static int tw5864_s_std(struct file *file, void *priv, v4l2_std_id std) +{ + struct tw5864_input *input = video_drvdata(file); + struct tw5864_dev *dev = input->root; + + input->v4l2_std = std; + input->std = tw5864_from_v4l2_std(std); + tw_indir_writeb(TW5864_INDIR_VIN_E(input->nr), input->std); + return 0; +} + +static int tw5864_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + if (f->index) + return -EINVAL; + + f->pixelformat = V4L2_PIX_FMT_H264; + + return 0; +} + +static int tw5864_subscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + switch (sub->type) { + case V4L2_EVENT_CTRL: + return v4l2_ctrl_subscribe_event(fh, sub); + case V4L2_EVENT_MOTION_DET: + /* + * Allow for up to 30 events (1 second for NTSC) to be stored. + */ + return v4l2_event_subscribe(fh, sub, 30, NULL); + } + return -EINVAL; +} + +static void tw5864_frame_interval_set(struct tw5864_input *input) +{ + /* + * This register value seems to follow such approach: In each second + * interval, when processing Nth frame, it checks Nth bit of register + * value and, if the bit is 1, it processes the frame, otherwise the + * frame is discarded. + * So unary representation would work, but more or less equal gaps + * between the frames should be preserved. + * + * For 1 FPS - 0x00000001 + * 00000000 00000000 00000000 00000001 + * + * For max FPS - set all 25/30 lower bits: + * 00111111 11111111 11111111 11111111 (NTSC) + * 00000001 11111111 11111111 11111111 (PAL) + * + * For half of max FPS - use such pattern: + * 00010101 01010101 01010101 01010101 (NTSC) + * 00000001 01010101 01010101 01010101 (PAL) + * + * Et cetera. + * + * The value supplied to hardware is capped by mask of 25/30 lower bits. + */ + struct tw5864_dev *dev = input->root; + u32 unary_framerate = 0; + int shift = 0; + int std_max_fps = input->std == STD_NTSC ? 30 : 25; + + for (shift = 0; shift < std_max_fps; shift += input->frame_interval) + unary_framerate |= 0x00000001 << shift; + + tw_writel(TW5864_H264EN_RATE_CNTL_LO_WORD(input->nr, 0), + unary_framerate >> 16); + tw_writel(TW5864_H264EN_RATE_CNTL_HI_WORD(input->nr, 0), + unary_framerate & 0xffff); +} + +static int tw5864_frameinterval_get(struct tw5864_input *input, + struct v4l2_fract *frameinterval) +{ + switch (input->std) { + case STD_NTSC: + frameinterval->numerator = 1001; + frameinterval->denominator = 30000; + break; + case STD_PAL: + case STD_SECAM: + frameinterval->numerator = 1; + frameinterval->denominator = 25; + break; + default: + WARN(1, "tw5864_frameinterval_get requested for unknown std %d\n", + input->std); + return -EINVAL; + } + + return 0; +} + +static int tw5864_enum_framesizes(struct file *file, void *priv, + struct v4l2_frmsizeenum *fsize) +{ + struct tw5864_input *input = video_drvdata(file); + + if (fsize->index > 0) + return -EINVAL; + if (fsize->pixel_format != V4L2_PIX_FMT_H264) + return -EINVAL; + + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; + fsize->discrete.width = 720; + fsize->discrete.height = input->std == STD_NTSC ? 480 : 576; + + return 0; +} + +static int tw5864_enum_frameintervals(struct file *file, void *priv, + struct v4l2_frmivalenum *fintv) +{ + struct tw5864_input *input = video_drvdata(file); + struct v4l2_fract frameinterval; + int std_max_fps = input->std == STD_NTSC ? 30 : 25; + struct v4l2_frmsizeenum fsize = { .index = fintv->index, + .pixel_format = fintv->pixel_format }; + int ret; + + ret = tw5864_enum_framesizes(file, priv, &fsize); + if (ret) + return ret; + + if (fintv->width != fsize.discrete.width || + fintv->height != fsize.discrete.height) + return -EINVAL; + + fintv->type = V4L2_FRMIVAL_TYPE_STEPWISE; + + ret = tw5864_frameinterval_get(input, &frameinterval); + fintv->stepwise.step = frameinterval; + fintv->stepwise.min = frameinterval; + fintv->stepwise.max = frameinterval; + fintv->stepwise.max.numerator *= std_max_fps; + + return ret; +} + +static int tw5864_g_parm(struct file *file, void *priv, + struct v4l2_streamparm *sp) +{ + struct tw5864_input *input = video_drvdata(file); + struct v4l2_captureparm *cp = &sp->parm.capture; + int ret; + + cp->capability = V4L2_CAP_TIMEPERFRAME; + + ret = tw5864_frameinterval_get(input, &cp->timeperframe); + cp->timeperframe.numerator *= input->frame_interval; + cp->capturemode = 0; + cp->readbuffers = 2; + + return ret; +} + +static int tw5864_s_parm(struct file *file, void *priv, + struct v4l2_streamparm *sp) +{ + struct tw5864_input *input = video_drvdata(file); + struct v4l2_fract *t = &sp->parm.capture.timeperframe; + struct v4l2_fract time_base; + int ret; + + ret = tw5864_frameinterval_get(input, &time_base); + if (ret) + return ret; + + if (!t->numerator || !t->denominator) { + t->numerator = time_base.numerator * input->frame_interval; + t->denominator = time_base.denominator; + } else if (t->denominator != time_base.denominator) { + t->numerator = t->numerator * time_base.denominator / + t->denominator; + t->denominator = time_base.denominator; + } + + input->frame_interval = t->numerator / time_base.numerator; + if (input->frame_interval < 1) + input->frame_interval = 1; + tw5864_frame_interval_set(input); + return tw5864_g_parm(file, priv, sp); +} + +static const struct v4l2_ctrl_ops tw5864_ctrl_ops = { + .s_ctrl = tw5864_s_ctrl, +}; + +static const struct v4l2_file_operations video_fops = { + .owner = THIS_MODULE, + .open = v4l2_fh_open, + .release = vb2_fop_release, + .read = vb2_fop_read, + .poll = vb2_fop_poll, + .mmap = vb2_fop_mmap, + .unlocked_ioctl = video_ioctl2, +}; + +#ifdef CONFIG_VIDEO_ADV_DEBUG + +#define INDIR_SPACE_MAP_SHIFT 0x100000 + +static int tw5864_g_reg(struct file *file, void *fh, + struct v4l2_dbg_register *reg) +{ + struct tw5864_input *input = video_drvdata(file); + struct tw5864_dev *dev = input->root; + + if (reg->reg < INDIR_SPACE_MAP_SHIFT) { + if (reg->reg > 0x87fff) + return -EINVAL; + reg->size = 4; + reg->val = tw_readl(reg->reg); + } else { + __u64 indir_addr = reg->reg - INDIR_SPACE_MAP_SHIFT; + + if (indir_addr > 0xefe) + return -EINVAL; + reg->size = 1; + reg->val = tw_indir_readb(reg->reg); + } + return 0; +} + +static int tw5864_s_reg(struct file *file, void *fh, + const struct v4l2_dbg_register *reg) +{ + struct tw5864_input *input = video_drvdata(file); + struct tw5864_dev *dev = input->root; + + if (reg->reg < INDIR_SPACE_MAP_SHIFT) { + if (reg->reg > 0x87fff) + return -EINVAL; + tw_writel(reg->reg, reg->val); + } else { + __u64 indir_addr = reg->reg - INDIR_SPACE_MAP_SHIFT; + + if (indir_addr > 0xefe) + return -EINVAL; + tw_indir_writeb(reg->reg, reg->val); + } + return 0; +} +#endif + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = tw5864_querycap, + .vidioc_enum_fmt_vid_cap = tw5864_enum_fmt_vid_cap, + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_querystd = tw5864_querystd, + .vidioc_s_std = tw5864_s_std, + .vidioc_g_std = tw5864_g_std, + .vidioc_enum_input = tw5864_enum_input, + .vidioc_g_input = tw5864_g_input, + .vidioc_s_input = tw5864_s_input, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, + .vidioc_try_fmt_vid_cap = tw5864_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = tw5864_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = tw5864_fmt_vid_cap, + .vidioc_log_status = v4l2_ctrl_log_status, + .vidioc_subscribe_event = tw5864_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, + .vidioc_enum_framesizes = tw5864_enum_framesizes, + .vidioc_enum_frameintervals = tw5864_enum_frameintervals, + .vidioc_s_parm = tw5864_s_parm, + .vidioc_g_parm = tw5864_g_parm, +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = tw5864_g_reg, + .vidioc_s_register = tw5864_s_reg, +#endif +}; + +static struct video_device tw5864_video_template = { + .name = "tw5864_video", + .fops = &video_fops, + .ioctl_ops = &video_ioctl_ops, + .release = video_device_release_empty, + .tvnorms = TW5864_NORMS, + .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | + V4L2_CAP_STREAMING, +}; + +/* Motion Detection Threshold matrix */ +static const struct v4l2_ctrl_config tw5864_md_thresholds = { + .ops = &tw5864_ctrl_ops, + .id = V4L2_CID_DETECT_MD_THRESHOLD_GRID, + .dims = {MD_CELLS_HOR, MD_CELLS_VERT}, + .def = 14, + /* See tw5864_md_metric_from_mvd() */ + .max = 2 * 0x0f, + .step = 1, +}; + +static int tw5864_video_input_init(struct tw5864_input *dev, int video_nr); +static void tw5864_video_input_fini(struct tw5864_input *dev); +static void tw5864_encoder_tables_upload(struct tw5864_dev *dev); + +int tw5864_video_init(struct tw5864_dev *dev, int *video_nr) +{ + int i; + int ret; + unsigned long flags; + int last_dma_allocated = -1; + int last_input_nr_registered = -1; + + for (i = 0; i < H264_BUF_CNT; i++) { + struct tw5864_h264_frame *frame = &dev->h264_buf[i]; + + frame->vlc.addr = dma_alloc_coherent(&dev->pci->dev, + H264_VLC_BUF_SIZE, + &frame->vlc.dma_addr, + GFP_KERNEL | GFP_DMA32); + if (!frame->vlc.addr) { + dev_err(&dev->pci->dev, "dma alloc fail\n"); + ret = -ENOMEM; + goto free_dma; + } + frame->mv.addr = dma_alloc_coherent(&dev->pci->dev, + H264_MV_BUF_SIZE, + &frame->mv.dma_addr, + GFP_KERNEL | GFP_DMA32); + if (!frame->mv.addr) { + dev_err(&dev->pci->dev, "dma alloc fail\n"); + ret = -ENOMEM; + dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE, + frame->vlc.addr, frame->vlc.dma_addr); + goto free_dma; + } + last_dma_allocated = i; + } + + tw5864_encoder_tables_upload(dev); + + /* Picture is distorted without this block */ + /* use falling edge to sample 54M to 108M */ + tw_indir_writeb(TW5864_INDIR_VD_108_POL, TW5864_INDIR_VD_108_POL_BOTH); + tw_indir_writeb(TW5864_INDIR_CLK0_SEL, 0x00); + + tw_indir_writeb(TW5864_INDIR_DDRA_DLL_DQS_SEL0, 0x02); + tw_indir_writeb(TW5864_INDIR_DDRA_DLL_DQS_SEL1, 0x02); + tw_indir_writeb(TW5864_INDIR_DDRA_DLL_CLK90_SEL, 0x02); + tw_indir_writeb(TW5864_INDIR_DDRB_DLL_DQS_SEL0, 0x02); + tw_indir_writeb(TW5864_INDIR_DDRB_DLL_DQS_SEL1, 0x02); + tw_indir_writeb(TW5864_INDIR_DDRB_DLL_CLK90_SEL, 0x02); + + /* video input reset */ + tw_indir_writeb(TW5864_INDIR_RESET, 0); + tw_indir_writeb(TW5864_INDIR_RESET, TW5864_INDIR_RESET_VD | + TW5864_INDIR_RESET_DLL | TW5864_INDIR_RESET_MUX_CORE); + msleep(20); + + /* + * Select Part A mode for all channels. + * tw_setl instead of tw_clearl for Part B mode. + * + * I guess "Part B" is primarily for downscaled version of same channel + * which goes in Part A of same bus + */ + tw_writel(TW5864_FULL_HALF_MODE_SEL, 0); + + tw_indir_writeb(TW5864_INDIR_PV_VD_CK_POL, + TW5864_INDIR_PV_VD_CK_POL_VD(0) | + TW5864_INDIR_PV_VD_CK_POL_VD(1) | + TW5864_INDIR_PV_VD_CK_POL_VD(2) | + TW5864_INDIR_PV_VD_CK_POL_VD(3)); + + spin_lock_irqsave(&dev->slock, flags); + dev->encoder_busy = 0; + dev->h264_buf_r_index = 0; + dev->h264_buf_w_index = 0; + tw_writel(TW5864_VLC_STREAM_BASE_ADDR, + dev->h264_buf[dev->h264_buf_w_index].vlc.dma_addr); + tw_writel(TW5864_MV_STREAM_BASE_ADDR, + dev->h264_buf[dev->h264_buf_w_index].mv.dma_addr); + spin_unlock_irqrestore(&dev->slock, flags); + + tw_writel(TW5864_SEN_EN_CH, 0x000f); + tw_writel(TW5864_H264EN_CH_EN, 0x000f); + + tw_writel(TW5864_H264EN_BUS0_MAP, 0x00000000); + tw_writel(TW5864_H264EN_BUS1_MAP, 0x00001111); + tw_writel(TW5864_H264EN_BUS2_MAP, 0x00002222); + tw_writel(TW5864_H264EN_BUS3_MAP, 0x00003333); + + /* + * Quote from Intersil (manufacturer): + * 0x0038 is managed by HW, and by default it won't pass the pointer set + * at 0x0010. So if you don't do encoding, 0x0038 should stay at '3' + * (with 4 frames in buffer). If you encode one frame and then move + * 0x0010 to '1' for example, HW will take one more frame and set it to + * buffer #0, and then you should see 0x0038 is set to '0'. There is + * only one HW encoder engine, so 4 channels cannot get encoded + * simultaneously. But each channel does have its own buffer (for + * original frames and reconstructed frames). So there is no problem to + * manage encoding for 4 channels at same time and no need to force + * I-frames in switching channels. + * End of quote. + * + * If we set 0x0010 (TW5864_ENC_BUF_PTR_REC1) to 0 (for any channel), we + * have no "rolling" (until we change this value). + * If we set 0x0010 (TW5864_ENC_BUF_PTR_REC1) to 0x3, it starts to roll + * continuously together with 0x0038. + */ + tw_writel(TW5864_ENC_BUF_PTR_REC1, 0x00ff); + tw_writel(TW5864_PCI_INTTM_SCALE, 0); + + tw_writel(TW5864_INTERLACING, TW5864_DI_EN); + tw_writel(TW5864_MASTER_ENB_REG, TW5864_PCI_VLC_INTR_ENB); + tw_writel(TW5864_PCI_INTR_CTL, + TW5864_TIMER_INTR_ENB | TW5864_PCI_MAST_ENB | + TW5864_MVD_VLC_MAST_ENB); + + dev->irqmask |= TW5864_INTR_VLC_DONE | TW5864_INTR_TIMER; + tw5864_irqmask_apply(dev); + + tasklet_init(&dev->tasklet, tw5864_handle_frame_task, + (unsigned long)dev); + + for (i = 0; i < TW5864_INPUTS; i++) { + dev->inputs[i].root = dev; + dev->inputs[i].nr = i; + ret = tw5864_video_input_init(&dev->inputs[i], video_nr[i]); + if (ret) + goto fini_video_inputs; + last_input_nr_registered = i; + } + + return 0; + +fini_video_inputs: + for (i = last_input_nr_registered; i >= 0; i--) + tw5864_video_input_fini(&dev->inputs[i]); + + tasklet_kill(&dev->tasklet); + +free_dma: + for (i = last_dma_allocated; i >= 0; i--) { + dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE, + dev->h264_buf[i].vlc.addr, + dev->h264_buf[i].vlc.dma_addr); + dma_free_coherent(&dev->pci->dev, H264_MV_BUF_SIZE, + dev->h264_buf[i].mv.addr, + dev->h264_buf[i].mv.dma_addr); + } + + return ret; +} + +static int tw5864_video_input_init(struct tw5864_input *input, int video_nr) +{ + struct tw5864_dev *dev = input->root; + int ret; + struct v4l2_ctrl_handler *hdl = &input->hdl; + + mutex_init(&input->lock); + spin_lock_init(&input->slock); + + /* setup video buffers queue */ + INIT_LIST_HEAD(&input->active); + input->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + input->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + input->vidq.io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF; + input->vidq.ops = &tw5864_video_qops; + input->vidq.mem_ops = &vb2_dma_contig_memops; + input->vidq.drv_priv = input; + input->vidq.gfp_flags = 0; + input->vidq.buf_struct_size = sizeof(struct tw5864_buf); + input->vidq.lock = &input->lock; + input->vidq.min_buffers_needed = 2; + input->vidq.dev = &input->root->pci->dev; + ret = vb2_queue_init(&input->vidq); + if (ret) + goto free_mutex; + + input->vdev = tw5864_video_template; + input->vdev.v4l2_dev = &input->root->v4l2_dev; + input->vdev.lock = &input->lock; + input->vdev.queue = &input->vidq; + video_set_drvdata(&input->vdev, input); + + /* Initialize the device control structures */ + v4l2_ctrl_handler_init(hdl, 6); + v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, + V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); + v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, + V4L2_CID_CONTRAST, 0, 255, 1, 100); + v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, + V4L2_CID_SATURATION, 0, 255, 1, 128); + v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, V4L2_CID_HUE, -128, 127, 1, 0); + v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, V4L2_CID_MPEG_VIDEO_GOP_SIZE, + 1, MAX_GOP_SIZE, 1, GOP_SIZE); + v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_MIN_QP, 28, 51, 1, QP_VALUE); + v4l2_ctrl_new_std_menu(hdl, &tw5864_ctrl_ops, + V4L2_CID_DETECT_MD_MODE, + V4L2_DETECT_MD_MODE_THRESHOLD_GRID, 0, + V4L2_DETECT_MD_MODE_DISABLED); + v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, + V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD, + tw5864_md_thresholds.min, tw5864_md_thresholds.max, + tw5864_md_thresholds.step, tw5864_md_thresholds.def); + input->md_threshold_grid_ctrl = + v4l2_ctrl_new_custom(hdl, &tw5864_md_thresholds, NULL); + if (hdl->error) { + ret = hdl->error; + goto free_v4l2_hdl; + } + input->vdev.ctrl_handler = hdl; + v4l2_ctrl_handler_setup(hdl); + + input->qp = QP_VALUE; + input->gop = GOP_SIZE; + input->frame_interval = 1; + + ret = video_register_device(&input->vdev, VFL_TYPE_GRABBER, video_nr); + if (ret) + goto free_v4l2_hdl; + + dev_info(&input->root->pci->dev, "Registered video device %s\n", + video_device_node_name(&input->vdev)); + + /* + * Set default video standard. Doesn't matter which, the detected value + * will be found out by VIDIOC_QUERYSTD handler. + */ + input->v4l2_std = V4L2_STD_NTSC_M; + input->std = STD_NTSC; + + tw_indir_writeb(TW5864_INDIR_VIN_E(video_nr), 0x07); + /* to initiate auto format recognition */ + tw_indir_writeb(TW5864_INDIR_VIN_F(video_nr), 0xff); + + return 0; + +free_v4l2_hdl: + v4l2_ctrl_handler_free(hdl); + vb2_queue_release(&input->vidq); +free_mutex: + mutex_destroy(&input->lock); + + return ret; +} + +static void tw5864_video_input_fini(struct tw5864_input *dev) +{ + video_unregister_device(&dev->vdev); + v4l2_ctrl_handler_free(&dev->hdl); + vb2_queue_release(&dev->vidq); +} + +void tw5864_video_fini(struct tw5864_dev *dev) +{ + int i; + + tasklet_kill(&dev->tasklet); + + for (i = 0; i < TW5864_INPUTS; i++) + tw5864_video_input_fini(&dev->inputs[i]); + + for (i = 0; i < H264_BUF_CNT; i++) { + dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE, + dev->h264_buf[i].vlc.addr, + dev->h264_buf[i].vlc.dma_addr); + dma_free_coherent(&dev->pci->dev, H264_MV_BUF_SIZE, + dev->h264_buf[i].mv.addr, + dev->h264_buf[i].mv.dma_addr); + } +} + +void tw5864_prepare_frame_headers(struct tw5864_input *input) +{ + struct tw5864_buf *vb = input->vb; + u8 *dst; + size_t dst_space; + unsigned long flags; + u8 *sl_hdr; + unsigned long space_before_sl_hdr; + + if (!vb) { + spin_lock_irqsave(&input->slock, flags); + if (list_empty(&input->active)) { + spin_unlock_irqrestore(&input->slock, flags); + input->vb = NULL; + return; + } + vb = list_first_entry(&input->active, struct tw5864_buf, list); + list_del(&vb->list); + spin_unlock_irqrestore(&input->slock, flags); + } + + dst = vb2_plane_vaddr(&vb->vb.vb2_buf, 0); + dst_space = vb2_plane_size(&vb->vb.vb2_buf, 0); + + /* + * Low-level bitstream writing functions don't have a fine way to say + * correctly that supplied buffer is too small. So we just check there + * and warn, and don't care at lower level. + * Currently all headers take below 32 bytes. + * The buffer is supposed to have plenty of free space at this point, + * anyway. + */ + if (WARN_ON_ONCE(dst_space < 128)) + return; + + /* + * Generate H264 headers: + * If this is first frame, put SPS and PPS + */ + if (input->frame_gop_seqno == 0) + tw5864_h264_put_stream_header(&dst, &dst_space, input->qp, + input->width, input->height); + + /* Put slice header */ + sl_hdr = dst; + space_before_sl_hdr = dst_space; + tw5864_h264_put_slice_header(&dst, &dst_space, input->h264_idr_pic_id, + input->frame_gop_seqno, + &input->tail_nb_bits, &input->tail); + input->vb = vb; + input->buf_cur_ptr = dst; + input->buf_cur_space_left = dst_space; +} + +/* + * Returns heuristic motion detection metric value from known components of + * hardware-provided Motion Vector Data. + */ +static unsigned int tw5864_md_metric_from_mvd(u32 mvd) +{ + /* + * Format of motion vector data exposed by tw5864, according to + * manufacturer: + * mv_x 10 bits + * mv_y 10 bits + * non_zero_members 8 bits + * mb_type 3 bits + * reserved 1 bit + * + * non_zero_members: number of non-zero residuals in each macro block + * after quantization + * + * unsigned int reserved = mvd >> 31; + * unsigned int mb_type = (mvd >> 28) & 0x7; + * unsigned int non_zero_members = (mvd >> 20) & 0xff; + */ + unsigned int mv_y = (mvd >> 10) & 0x3ff; + unsigned int mv_x = mvd & 0x3ff; + + /* heuristic: */ + mv_x &= 0x0f; + mv_y &= 0x0f; + + return mv_y + mv_x; +} + +static int tw5864_is_motion_triggered(struct tw5864_h264_frame *frame) +{ + struct tw5864_input *input = frame->input; + u32 *mv = (u32 *)frame->mv.addr; + int i; + int detected = 0; + + for (i = 0; i < MD_CELLS; i++) { + const u16 thresh = input->md_threshold_grid_values[i]; + const unsigned int metric = tw5864_md_metric_from_mvd(mv[i]); + + if (metric > thresh) + detected = 1; + + if (detected) + break; + } + return detected; +} + +static void tw5864_handle_frame_task(unsigned long data) +{ + struct tw5864_dev *dev = (struct tw5864_dev *)data; + unsigned long flags; + int batch_size = H264_BUF_CNT; + + spin_lock_irqsave(&dev->slock, flags); + while (dev->h264_buf_r_index != dev->h264_buf_w_index && batch_size--) { + struct tw5864_h264_frame *frame = + &dev->h264_buf[dev->h264_buf_r_index]; + + spin_unlock_irqrestore(&dev->slock, flags); + dma_sync_single_for_cpu(&dev->pci->dev, frame->vlc.dma_addr, + H264_VLC_BUF_SIZE, DMA_FROM_DEVICE); + dma_sync_single_for_cpu(&dev->pci->dev, frame->mv.dma_addr, + H264_MV_BUF_SIZE, DMA_FROM_DEVICE); + tw5864_handle_frame(frame); + dma_sync_single_for_device(&dev->pci->dev, frame->vlc.dma_addr, + H264_VLC_BUF_SIZE, DMA_FROM_DEVICE); + dma_sync_single_for_device(&dev->pci->dev, frame->mv.dma_addr, + H264_MV_BUF_SIZE, DMA_FROM_DEVICE); + spin_lock_irqsave(&dev->slock, flags); + + dev->h264_buf_r_index++; + dev->h264_buf_r_index %= H264_BUF_CNT; + } + spin_unlock_irqrestore(&dev->slock, flags); +} + +#ifdef DEBUG +static u32 tw5864_vlc_checksum(u32 *data, int len) +{ + u32 val, count_len = len; + + val = *data++; + while (((count_len >> 2) - 1) > 0) { + val ^= *data++; + count_len -= 4; + } + val ^= htonl((len >> 2)); + return val; +} +#endif + +static void tw5864_handle_frame(struct tw5864_h264_frame *frame) +{ +#define SKIP_VLCBUF_BYTES 3 + struct tw5864_input *input = frame->input; + struct tw5864_dev *dev = input->root; + struct tw5864_buf *vb; + struct vb2_v4l2_buffer *v4l2_buf; + int frame_len = frame->vlc_len - SKIP_VLCBUF_BYTES; + u8 *dst = input->buf_cur_ptr; + u8 tail_mask, vlc_mask = 0; + int i; + u8 vlc_first_byte = ((u8 *)(frame->vlc.addr + SKIP_VLCBUF_BYTES))[0]; + unsigned long flags; + int zero_run; + u8 *src; + u8 *src_end; + +#ifdef DEBUG + if (frame->checksum != + tw5864_vlc_checksum((u32 *)frame->vlc.addr, frame_len)) + dev_err(&dev->pci->dev, + "Checksum of encoded frame doesn't match!\n"); +#endif + + spin_lock_irqsave(&input->slock, flags); + vb = input->vb; + input->vb = NULL; + spin_unlock_irqrestore(&input->slock, flags); + + v4l2_buf = to_vb2_v4l2_buffer(&vb->vb.vb2_buf); + + if (!vb) { /* Gone because of disabling */ + dev_dbg(&dev->pci->dev, "vb is empty, dropping frame\n"); + return; + } + + /* + * Check for space. + * Mind the overhead of startcode emulation prevention. + */ + if (input->buf_cur_space_left < frame_len * 5 / 4) { + dev_err_once(&dev->pci->dev, + "Left space in vb2 buffer, %d bytes, is less than considered safely enough to put frame of length %d. Dropping this frame.\n", + input->buf_cur_space_left, frame_len); + return; + } + + for (i = 0; i < 8 - input->tail_nb_bits; i++) + vlc_mask |= 1 << i; + tail_mask = (~vlc_mask) & 0xff; + + dst[0] = (input->tail & tail_mask) | (vlc_first_byte & vlc_mask); + frame_len--; + dst++; + + /* H.264 startcode emulation prevention */ + src = frame->vlc.addr + SKIP_VLCBUF_BYTES + 1; + src_end = src + frame_len; + zero_run = 0; + for (; src < src_end; src++) { + if (zero_run < 2) { + if (*src == 0) + ++zero_run; + else + zero_run = 0; + } else { + if ((*src & ~0x03) == 0) + *dst++ = 0x03; + zero_run = *src == 0; + } + *dst++ = *src; + } + + vb2_set_plane_payload(&vb->vb.vb2_buf, 0, + dst - (u8 *)vb2_plane_vaddr(&vb->vb.vb2_buf, 0)); + + vb->vb.vb2_buf.timestamp = frame->timestamp; + v4l2_buf->field = V4L2_FIELD_INTERLACED; + v4l2_buf->sequence = frame->seqno; + + /* Check for motion flags */ + if (frame->gop_seqno /* P-frame */ && + tw5864_is_motion_triggered(frame)) { + struct v4l2_event ev = { + .type = V4L2_EVENT_MOTION_DET, + .u.motion_det = { + .flags = V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ, + .frame_sequence = v4l2_buf->sequence, + }, + }; + + v4l2_event_queue(&input->vdev, &ev); + } + + vb2_buffer_done(&vb->vb.vb2_buf, VB2_BUF_STATE_DONE); +} + +static v4l2_std_id tw5864_get_v4l2_std(enum tw5864_vid_std std) +{ + switch (std) { + case STD_NTSC: return V4L2_STD_NTSC_M; + case STD_PAL: return V4L2_STD_PAL_B; + case STD_SECAM: return V4L2_STD_SECAM_B; + case STD_NTSC443: return V4L2_STD_NTSC_443; + case STD_PAL_M: return V4L2_STD_PAL_M; + case STD_PAL_CN: return V4L2_STD_PAL_Nc; + case STD_PAL_60: return V4L2_STD_PAL_60; + case STD_INVALID: return V4L2_STD_UNKNOWN; + } + return 0; +} + +static enum tw5864_vid_std tw5864_from_v4l2_std(v4l2_std_id v4l2_std) +{ + if (v4l2_std & V4L2_STD_NTSC_M) + return STD_NTSC; + if (v4l2_std & V4L2_STD_PAL_B) + return STD_PAL; + if (v4l2_std & V4L2_STD_SECAM_B) + return STD_SECAM; + if (v4l2_std & V4L2_STD_NTSC_443) + return STD_NTSC443; + if (v4l2_std & V4L2_STD_PAL_M) + return STD_PAL_M; + if (v4l2_std & V4L2_STD_PAL_Nc) + return STD_PAL_CN; + if (v4l2_std & V4L2_STD_PAL_60) + return STD_PAL_60; + + return STD_INVALID; +} + +static void tw5864_encoder_tables_upload(struct tw5864_dev *dev) +{ + int i; + + tw_writel(TW5864_VLC_RD, 0x1); + for (i = 0; i < VLC_LOOKUP_TABLE_LEN; i++) { + tw_writel((TW5864_VLC_STREAM_MEM_START + i * 4), + encoder_vlc_lookup_table[i]); + } + tw_writel(TW5864_VLC_RD, 0x0); + + for (i = 0; i < QUANTIZATION_TABLE_LEN; i++) { + tw_writel((TW5864_QUAN_TAB + i * 4), + forward_quantization_table[i]); + } + + for (i = 0; i < QUANTIZATION_TABLE_LEN; i++) { + tw_writel((TW5864_QUAN_TAB + i * 4), + inverse_quantization_table[i]); + } +} diff --git a/drivers/media/pci/tw5864/tw5864.h b/drivers/media/pci/tw5864/tw5864.h new file mode 100644 index 000000000000..f5de9f6ef119 --- /dev/null +++ b/drivers/media/pci/tw5864/tw5864.h @@ -0,0 +1,205 @@ +/* + * TW5864 driver - common header file + * + * Copyright (C) 2016 Bluecherry, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "tw5864-reg.h" + +#define PCI_DEVICE_ID_TECHWELL_5864 0x5864 + +#define TW5864_NORMS V4L2_STD_ALL + +/* ----------------------------------------------------------- */ +/* card configuration */ + +#define TW5864_INPUTS 4 + +/* The TW5864 uses 192 (16x12) detection cells in full screen for motion + * detection. Each detection cell is composed of 44 pixels and 20 lines for + * NTSC and 24 lines for PAL. + */ +#define MD_CELLS_HOR 16 +#define MD_CELLS_VERT 12 +#define MD_CELLS (MD_CELLS_HOR * MD_CELLS_VERT) + +#define H264_VLC_BUF_SIZE 0x80000 +#define H264_MV_BUF_SIZE 0x2000 /* device writes 5396 bytes */ +#define QP_VALUE 28 +#define MAX_GOP_SIZE 255 +#define GOP_SIZE MAX_GOP_SIZE + +enum resolution { + D1 = 1, + HD1 = 2, /* half d1 - 360x(240|288) */ + CIF = 3, + QCIF = 4, +}; + +/* ----------------------------------------------------------- */ +/* device / file handle status */ + +struct tw5864_dev; /* forward delclaration */ + +/* buffer for one video/vbi/ts frame */ +struct tw5864_buf { + struct vb2_v4l2_buffer vb; + struct list_head list; + + unsigned int size; +}; + +struct tw5864_dma_buf { + void *addr; + dma_addr_t dma_addr; +}; + +enum tw5864_vid_std { + STD_NTSC = 0, /* NTSC (M) */ + STD_PAL = 1, /* PAL (B, D, G, H, I) */ + STD_SECAM = 2, /* SECAM */ + STD_NTSC443 = 3, /* NTSC4.43 */ + STD_PAL_M = 4, /* PAL (M) */ + STD_PAL_CN = 5, /* PAL (CN) */ + STD_PAL_60 = 6, /* PAL 60 */ + STD_INVALID = 7, + STD_AUTO = 7, +}; + +struct tw5864_input { + int nr; /* input number */ + struct tw5864_dev *root; + struct mutex lock; /* used for vidq and vdev */ + spinlock_t slock; /* used for sync between ISR, tasklet & V4L2 API */ + struct video_device vdev; + struct v4l2_ctrl_handler hdl; + struct vb2_queue vidq; + struct list_head active; + enum resolution resolution; + unsigned int width, height; + unsigned int frame_seqno; + unsigned int frame_gop_seqno; + unsigned int h264_idr_pic_id; + int enabled; + enum tw5864_vid_std std; + v4l2_std_id v4l2_std; + int tail_nb_bits; + u8 tail; + u8 *buf_cur_ptr; + int buf_cur_space_left; + + u32 reg_interlacing; + u32 reg_vlc; + u32 reg_dsp_codec; + u32 reg_dsp; + u32 reg_emu; + u32 reg_dsp_qp; + u32 reg_dsp_ref_mvp_lambda; + u32 reg_dsp_i4x4_weight; + u32 buf_id; + + struct tw5864_buf *vb; + + struct v4l2_ctrl *md_threshold_grid_ctrl; + u16 md_threshold_grid_values[12 * 16]; + int qp; + int gop; + + /* + * In (1/MAX_FPS) units. + * For max FPS (default), set to 1. + * For 1 FPS, set to e.g. 32. + */ + int frame_interval; + unsigned long new_frame_deadline; +}; + +struct tw5864_h264_frame { + struct tw5864_dma_buf vlc; + struct tw5864_dma_buf mv; + int vlc_len; + u32 checksum; + struct tw5864_input *input; + u64 timestamp; + unsigned int seqno; + unsigned int gop_seqno; +}; + +/* global device status */ +struct tw5864_dev { + spinlock_t slock; /* used for sync between ISR, tasklet & V4L2 API */ + struct v4l2_device v4l2_dev; + struct tw5864_input inputs[TW5864_INPUTS]; +#define H264_BUF_CNT 4 + struct tw5864_h264_frame h264_buf[H264_BUF_CNT]; + int h264_buf_r_index; + int h264_buf_w_index; + + struct tasklet_struct tasklet; + + int encoder_busy; + /* Input number to check next for ready raw picture (in RR fashion) */ + int next_input; + + /* pci i/o */ + char name[64]; + struct pci_dev *pci; + void __iomem *mmio; + u32 irqmask; +}; + +#define tw_readl(reg) readl(dev->mmio + reg) +#define tw_mask_readl(reg, mask) \ + (tw_readl(reg) & (mask)) +#define tw_mask_shift_readl(reg, mask, shift) \ + (tw_mask_readl((reg), ((mask) << (shift))) >> (shift)) + +#define tw_writel(reg, value) writel((value), dev->mmio + reg) +#define tw_mask_writel(reg, mask, value) \ + tw_writel(reg, (tw_readl(reg) & ~(mask)) | ((value) & (mask))) +#define tw_mask_shift_writel(reg, mask, shift, value) \ + tw_mask_writel((reg), ((mask) << (shift)), ((value) << (shift))) + +#define tw_setl(reg, bit) tw_writel((reg), tw_readl(reg) | (bit)) +#define tw_clearl(reg, bit) tw_writel((reg), tw_readl(reg) & ~(bit)) + +u8 tw5864_indir_readb(struct tw5864_dev *dev, u16 addr); +#define tw_indir_readb(addr) tw5864_indir_readb(dev, addr) +void tw5864_indir_writeb(struct tw5864_dev *dev, u16 addr, u8 data); +#define tw_indir_writeb(addr, data) tw5864_indir_writeb(dev, addr, data) + +void tw5864_irqmask_apply(struct tw5864_dev *dev); +int tw5864_video_init(struct tw5864_dev *dev, int *video_nr); +void tw5864_video_fini(struct tw5864_dev *dev); +void tw5864_prepare_frame_headers(struct tw5864_input *input); +void tw5864_h264_put_stream_header(u8 **buf, size_t *space_left, int qp, + int width, int height); +void tw5864_h264_put_slice_header(u8 **buf, size_t *space_left, + unsigned int idr_pic_id, + unsigned int frame_gop_seqno, + int *tail_nb_bits, u8 *tail); +void tw5864_request_encoded_frame(struct tw5864_input *input); -- cgit v1.2.3 From fe713d608bcb5de7b709ddebceced9f047e3d506 Mon Sep 17 00:00:00 2001 From: Jean-Christophe Trotin Date: Mon, 5 Sep 2016 12:31:29 -0300 Subject: [media] st-hva: update MAINTAINERS Add entry for the HVA driver to the MAINTAINERS file. Signed-off-by: Jean-Christophe Trotin Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 0a16a820fd56..9015f04208a7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5626,6 +5626,14 @@ M: Nadia Yvette Chambers S: Maintained F: fs/hugetlbfs/ +HVA ST MEDIA DRIVER +M: Jean-Christophe Trotin +L: linux-media@vger.kernel.org +T: git git://linuxtv.org/media_tree.git +W: https://linuxtv.org +S: Supported +F: drivers/media/platform/sti/hva + Hyper-V CORE AND DRIVERS M: "K. Y. Srinivasan" M: Haiyang Zhang -- cgit v1.2.3 From 49fc9361db78a598c53134d083b84f15492da3bc Mon Sep 17 00:00:00 2001 From: Benjamin Gaignard Date: Thu, 15 Sep 2016 04:37:46 -0300 Subject: [media] add maintainer for stih-cec driver Signed-off-by: Benjamin Gaignard Acked-by: Peter Griffin Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 9015f04208a7..22feb294de5d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10282,6 +10282,13 @@ S: Maintained F: Documentation/devicetree/bindings/serial/ F: drivers/tty/serial/ +STI CEC DRIVER +M: Benjamin Gaignard +L: kernel@stlinux.com +S: Maintained +F: drivers/staging/media/st-cec/ +F: Documentation/devicetree/bindings/media/stih-cec.txt + SYNOPSYS DESIGNWARE DMAC DRIVER M: Viresh Kumar M: Andy Shevchenko -- cgit v1.2.3 From 618cd932cd38b65d89eb31a5271999b6ccc59b2e Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 12 Sep 2016 12:48:54 -0300 Subject: MAINTAINERS: update documentation for media subsystem With ReST conversion, the media subsystem documentation is now located on different directories. Update them. Suggested-by: Joe Perches Cc: LKML Cc: linux-doc Cc: Jonathan Corbet Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 22feb294de5d..de23660823b8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2755,7 +2755,7 @@ L: linux-media@vger.kernel.org W: https://linuxtv.org T: git git://linuxtv.org/media_tree.git S: Odd fixes -F: Documentation/video4linux/bttv/ +F: Documentation/media/v4l-drivers/bttv* F: drivers/media/pci/bt8xx/bttv* BUSLOGIC SCSI DRIVER @@ -2800,7 +2800,7 @@ M: Jonathan Corbet L: linux-media@vger.kernel.org T: git git://linuxtv.org/media_tree.git S: Maintained -F: Documentation/video4linux/cafe_ccic +F: Documentation/media/v4l-drivers/cafe_ccic* F: drivers/media/platform/marvell-ccic/ CAIF NETWORK LAYER @@ -2894,7 +2894,7 @@ T: git git://linuxtv.org/media_tree.git W: http://linuxtv.org S: Supported F: Documentation/cec.txt -F: Documentation/DocBook/media/v4l/cec* +F: Documentation/media/uapi/cec F: drivers/staging/media/cec/ F: drivers/media/cec-edid.c F: drivers/media/rc/keymaps/rc-cec.c @@ -3380,7 +3380,7 @@ T: git git://linuxtv.org/media_tree.git W: https://linuxtv.org W: http://www.ivtvdriver.org/index.php/Cx18 S: Maintained -F: Documentation/video4linux/cx18.txt +F: Documentation/media/v4l-drivers/cx18* F: drivers/media/pci/cx18/ F: include/uapi/linux/ivtv* @@ -3409,7 +3409,7 @@ L: linux-media@vger.kernel.org W: https://linuxtv.org T: git git://linuxtv.org/media_tree.git S: Odd fixes -F: Documentation/video4linux/cx88/ +F: Documentation/media/v4l-drivers/cx88* F: drivers/media/pci/cx88/ CXD2820R MEDIA DRIVER @@ -3882,7 +3882,7 @@ X: Documentation/devicetree/ X: Documentation/acpi X: Documentation/power X: Documentation/spi -X: Documentation/DocBook/media +X: Documentation/media T: git git://git.lwn.net/linux.git docs-next DOUBLETALK DRIVER @@ -4577,6 +4577,7 @@ W: https://linuxtv.org T: git git://linuxtv.org/media_tree.git S: Maintained F: drivers/media/usb/em28xx/ +F: Documentation/media/v4l-drivers/em28xx* EMBEDDED LINUX M: Paul Gortmaker @@ -6503,7 +6504,7 @@ L: linux-media@vger.kernel.org T: git git://linuxtv.org/media_tree.git W: http://www.ivtvdriver.org S: Maintained -F: Documentation/video4linux/*.ivtv +F: Documentation/media/v4l-drivers/ivtv* F: drivers/media/pci/ivtv/ F: include/uapi/linux/ivtv* @@ -7583,9 +7584,7 @@ W: https://linuxtv.org Q: http://patchwork.kernel.org/project/linux-media/list/ T: git git://linuxtv.org/media_tree.git S: Maintained -F: Documentation/dvb/ -F: Documentation/video4linux/ -F: Documentation/DocBook/media/ +F: Documentation/media/ F: drivers/media/ F: drivers/staging/media/ F: include/linux/platform_data/media/ @@ -7854,7 +7853,7 @@ F: kernel/module.c MOTION EYE VAIO PICTUREBOOK CAMERA DRIVER W: http://popies.net/meye/ S: Orphan -F: Documentation/video4linux/meye.txt +F: Documentation/media/v4l-drivers/meye* F: drivers/media/pci/meye/ F: include/uapi/linux/meye.h @@ -9498,7 +9497,7 @@ L: linux-media@vger.kernel.org W: http://www.isely.net/pvrusb2/ T: git git://linuxtv.org/media_tree.git S: Maintained -F: Documentation/video4linux/README.pvrusb2 +F: Documentation/media/v4l-drivers/pvrusb2* F: drivers/media/usb/pvrusb2/ PWC WEBCAM DRIVER @@ -10152,7 +10151,7 @@ L: linux-media@vger.kernel.org W: https://linuxtv.org T: git git://linuxtv.org/media_tree.git S: Odd fixes -F: Documentation/video4linux/*.saa7134 +F: Documentation/media/v4l-drivers/saa7134* F: drivers/media/pci/saa7134/ SAA7146 VIDEO4LINUX-2 DRIVER @@ -11853,6 +11852,7 @@ W: https://linuxtv.org T: git git://linuxtv.org/media_tree.git S: Odd fixes F: drivers/media/usb/tm6000/ +F: Documentation/media/v4l-drivers/tm6000* TW5864 VIDEO4LINUX DRIVER M: Bluecherry Maintainers @@ -12357,7 +12357,7 @@ L: linux-media@vger.kernel.org T: git git://linuxtv.org/media_tree.git W: http://royale.zerezo.com/zr364xx/ S: Maintained -F: Documentation/video4linux/zr364xx.txt +F: Documentation/media/v4l-drivers/zr364xx* F: drivers/media/usb/zr364xx/ ULPI BUS -- cgit v1.2.3 From 7aae6e2df127f9f7a96c21e21a277dd7ff063e6a Mon Sep 17 00:00:00 2001 From: Charles-Antoine Couret Date: Thu, 15 Sep 2016 12:29:51 -0300 Subject: [media] Add GS1662 driver, a video serializer You can read datasheet here: http://www.c-dis.net/media/871/GS1662_Datasheet.pdf It's a component which supports HD and SD CEA or SDI formats to SDI output. It's configured through SPI bus. GS1662 driver is implemented as v4l2 subdev. Signed-off-by: Charles-Antoine Couret Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 7 + drivers/media/Kconfig | 1 + drivers/media/Makefile | 2 +- drivers/media/spi/Kconfig | 9 + drivers/media/spi/Makefile | 1 + drivers/media/spi/gs1662.c | 472 +++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 491 insertions(+), 1 deletion(-) create mode 100644 drivers/media/spi/Kconfig create mode 100644 drivers/media/spi/Makefile create mode 100644 drivers/media/spi/gs1662.c (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index de23660823b8..5678e50fc13a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5259,6 +5259,13 @@ L: netdev@vger.kernel.org S: Maintained F: drivers/net/ethernet/aeroflex/ +GS1662 VIDEO SERIALIZER +M: Charles-Antoine Couret +L: linux-media@vger.kernel.org +T: git git://linuxtv.org/media_tree.git +S: Maintained +F: drivers/media/spi/gs1662.c + GSPCA FINEPIX SUBDRIVER M: Frank Zago L: linux-media@vger.kernel.org diff --git a/drivers/media/Kconfig b/drivers/media/Kconfig index 962f2a9a6614..6600e59eb3c0 100644 --- a/drivers/media/Kconfig +++ b/drivers/media/Kconfig @@ -218,5 +218,6 @@ config MEDIA_ATTACH source "drivers/media/i2c/Kconfig" source "drivers/media/tuners/Kconfig" source "drivers/media/dvb-frontends/Kconfig" +source "drivers/media/spi/Kconfig" endif # MEDIA_SUPPORT diff --git a/drivers/media/Makefile b/drivers/media/Makefile index 081a7866fd44..0deaa93efdee 100644 --- a/drivers/media/Makefile +++ b/drivers/media/Makefile @@ -32,6 +32,6 @@ obj-y += rc/ # Finally, merge the drivers that require the core # -obj-y += common/ platform/ pci/ usb/ mmc/ firewire/ +obj-y += common/ platform/ pci/ usb/ mmc/ firewire/ spi/ obj-$(CONFIG_VIDEO_DEV) += radio/ diff --git a/drivers/media/spi/Kconfig b/drivers/media/spi/Kconfig new file mode 100644 index 000000000000..fa47c90f857d --- /dev/null +++ b/drivers/media/spi/Kconfig @@ -0,0 +1,9 @@ +if VIDEO_V4L2 + +config VIDEO_GS1662 + tristate "Gennum Serializers video" + depends on SPI && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API + ---help--- + Enable the GS1662 driver which serializes video streams. + +endif diff --git a/drivers/media/spi/Makefile b/drivers/media/spi/Makefile new file mode 100644 index 000000000000..ea64013d16cc --- /dev/null +++ b/drivers/media/spi/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_VIDEO_GS1662) += gs1662.o diff --git a/drivers/media/spi/gs1662.c b/drivers/media/spi/gs1662.c new file mode 100644 index 000000000000..f74342339e5a --- /dev/null +++ b/drivers/media/spi/gs1662.c @@ -0,0 +1,472 @@ +/* + * GS1662 device registration. + * + * Copyright (C) 2015-2016 Nexvision + * Author: Charles-Antoine Couret + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define REG_STATUS 0x04 +#define REG_FORCE_FMT 0x06 +#define REG_LINES_PER_FRAME 0x12 +#define REG_WORDS_PER_LINE 0x13 +#define REG_WORDS_PER_ACT_LINE 0x14 +#define REG_ACT_LINES_PER_FRAME 0x15 + +#define MASK_H_LOCK 0x001 +#define MASK_V_LOCK 0x002 +#define MASK_STD_LOCK 0x004 +#define MASK_FORCE_STD 0x020 +#define MASK_STD_STATUS 0x3E0 + +#define GS_WIDTH_MIN 720 +#define GS_WIDTH_MAX 2048 +#define GS_HEIGHT_MIN 487 +#define GS_HEIGHT_MAX 1080 +#define GS_PIXELCLOCK_MIN 10519200 +#define GS_PIXELCLOCK_MAX 74250000 + +struct gs { + struct spi_device *pdev; + struct v4l2_subdev sd; + struct v4l2_dv_timings current_timings; + int enabled; +}; + +struct gs_reg_fmt { + u16 reg_value; + struct v4l2_dv_timings format; +}; + +struct gs_reg_fmt_custom { + u16 reg_value; + __u32 width; + __u32 height; + __u64 pixelclock; + __u32 interlaced; +}; + +static const struct spi_device_id gs_id[] = { + { "gs1662", 0 }, + { } +}; +MODULE_DEVICE_TABLE(spi, gs_id); + +static const struct v4l2_dv_timings fmt_cap[] = { + V4L2_DV_BT_SDI_720X487I60, + V4L2_DV_BT_CEA_720X576P50, + V4L2_DV_BT_CEA_1280X720P24, + V4L2_DV_BT_CEA_1280X720P25, + V4L2_DV_BT_CEA_1280X720P30, + V4L2_DV_BT_CEA_1280X720P50, + V4L2_DV_BT_CEA_1280X720P60, + V4L2_DV_BT_CEA_1920X1080P24, + V4L2_DV_BT_CEA_1920X1080P25, + V4L2_DV_BT_CEA_1920X1080P30, + V4L2_DV_BT_CEA_1920X1080I50, + V4L2_DV_BT_CEA_1920X1080I60, +}; + +static const struct gs_reg_fmt reg_fmt[] = { + { 0x00, V4L2_DV_BT_CEA_1280X720P60 }, + { 0x01, V4L2_DV_BT_CEA_1280X720P60 }, + { 0x02, V4L2_DV_BT_CEA_1280X720P30 }, + { 0x03, V4L2_DV_BT_CEA_1280X720P30 }, + { 0x04, V4L2_DV_BT_CEA_1280X720P50 }, + { 0x05, V4L2_DV_BT_CEA_1280X720P50 }, + { 0x06, V4L2_DV_BT_CEA_1280X720P25 }, + { 0x07, V4L2_DV_BT_CEA_1280X720P25 }, + { 0x08, V4L2_DV_BT_CEA_1280X720P24 }, + { 0x09, V4L2_DV_BT_CEA_1280X720P24 }, + { 0x0A, V4L2_DV_BT_CEA_1920X1080I60 }, + { 0x0B, V4L2_DV_BT_CEA_1920X1080P30 }, + + /* Default value: keep this field before 0xC */ + { 0x14, V4L2_DV_BT_CEA_1920X1080I50 }, + { 0x0C, V4L2_DV_BT_CEA_1920X1080I50 }, + { 0x0D, V4L2_DV_BT_CEA_1920X1080P25 }, + { 0x0E, V4L2_DV_BT_CEA_1920X1080P25 }, + { 0x10, V4L2_DV_BT_CEA_1920X1080P24 }, + { 0x12, V4L2_DV_BT_CEA_1920X1080P24 }, + { 0x16, V4L2_DV_BT_SDI_720X487I60 }, + { 0x19, V4L2_DV_BT_SDI_720X487I60 }, + { 0x18, V4L2_DV_BT_CEA_720X576P50 }, + { 0x1A, V4L2_DV_BT_CEA_720X576P50 }, + + /* Implement following timings before enable it. + * Because of we don't have access to these theoretical timings yet. + * Workaround: use functions to get and set registers for these formats. + */ +#if 0 + { 0x0F, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */ + { 0x11, V4L2_DV_BT_XXX_1920X1080I24 }, /* SMPTE 274M */ + { 0x13, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */ + { 0x15, V4L2_DV_BT_XXX_1920X1035I60 }, /* SMPTE 260M */ + { 0x17, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */ + { 0x1B, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */ + { 0x1C, V4L2_DV_BT_XXX_2048X1080P25 }, /* SMPTE 428.1M */ +#endif +}; + +static const struct v4l2_dv_timings_cap gs_timings_cap = { + .type = V4L2_DV_BT_656_1120, + /* keep this initialization for compatibility with GCC < 4.4.6 */ + .reserved = { 0 }, + V4L2_INIT_BT_TIMINGS(GS_WIDTH_MIN, GS_WIDTH_MAX, GS_HEIGHT_MIN, + GS_HEIGHT_MAX, GS_PIXELCLOCK_MIN, GS_PIXELCLOCK_MAX, + V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_SDI, + V4L2_DV_BT_CAP_PROGRESSIVE + | V4L2_DV_BT_CAP_INTERLACED) +}; + +static int gs_read_register(struct spi_device *spi, u16 addr, u16 *value) +{ + int ret; + u16 buf_addr = (0x8000 | (0x0FFF & addr)); + u16 buf_value = 0; + struct spi_message msg; + struct spi_transfer tx[] = { + { + .tx_buf = &buf_addr, + .len = 2, + .delay_usecs = 1, + }, { + .rx_buf = &buf_value, + .len = 2, + .delay_usecs = 1, + }, + }; + + spi_message_init(&msg); + spi_message_add_tail(&tx[0], &msg); + spi_message_add_tail(&tx[1], &msg); + ret = spi_sync(spi, &msg); + + *value = buf_value; + + return ret; +} + +static int gs_write_register(struct spi_device *spi, u16 addr, u16 value) +{ + int ret; + u16 buf_addr = addr; + u16 buf_value = value; + struct spi_message msg; + struct spi_transfer tx[] = { + { + .tx_buf = &buf_addr, + .len = 2, + .delay_usecs = 1, + }, { + .tx_buf = &buf_value, + .len = 2, + .delay_usecs = 1, + }, + }; + + spi_message_init(&msg); + spi_message_add_tail(&tx[0], &msg); + spi_message_add_tail(&tx[1], &msg); + ret = spi_sync(spi, &msg); + + return ret; +} + +#ifdef CONFIG_VIDEO_ADV_DEBUG +static int gs_g_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) +{ + struct spi_device *spi = v4l2_get_subdevdata(sd); + u16 val; + int ret; + + ret = gs_read_register(spi, reg->reg & 0xFFFF, &val); + reg->val = val; + reg->size = 2; + return ret; +} + +static int gs_s_register(struct v4l2_subdev *sd, + const struct v4l2_dbg_register *reg) +{ + struct spi_device *spi = v4l2_get_subdevdata(sd); + + return gs_write_register(spi, reg->reg & 0xFFFF, reg->val & 0xFFFF); +} +#endif + +static int gs_status_format(u16 status, struct v4l2_dv_timings *timings) +{ + int std = (status & MASK_STD_STATUS) >> 5; + int i; + + for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) { + if (reg_fmt[i].reg_value == std) { + *timings = reg_fmt[i].format; + return 0; + } + } + + return -ERANGE; +} + +static u16 get_register_timings(struct v4l2_dv_timings *timings) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) { + if (v4l2_match_dv_timings(timings, ®_fmt[i].format, 0, false)) + return reg_fmt[i].reg_value | MASK_FORCE_STD; + } + + return 0x0; +} + +static inline struct gs *to_gs(struct v4l2_subdev *sd) +{ + return container_of(sd, struct gs, sd); +} + +static int gs_s_dv_timings(struct v4l2_subdev *sd, + struct v4l2_dv_timings *timings) +{ + struct gs *gs = to_gs(sd); + int reg_value; + + reg_value = get_register_timings(timings); + if (reg_value == 0x0) + return -EINVAL; + + gs->current_timings = *timings; + return 0; +} + +static int gs_g_dv_timings(struct v4l2_subdev *sd, + struct v4l2_dv_timings *timings) +{ + struct gs *gs = to_gs(sd); + + *timings = gs->current_timings; + return 0; +} + +static int gs_query_dv_timings(struct v4l2_subdev *sd, + struct v4l2_dv_timings *timings) +{ + struct gs *gs = to_gs(sd); + struct v4l2_dv_timings fmt; + u16 reg_value, i; + int ret; + + if (gs->enabled) + return -EBUSY; + + /* Check if the component detect a line, a frame or something else + * which looks like a video signal activity.*/ + for (i = 0; i < 4; i++) { + gs_read_register(gs->pdev, REG_LINES_PER_FRAME + i, ®_value); + if (reg_value) + break; + } + + /* If no register reports a video signal */ + if (i >= 4) + return -ENOLINK; + + gs_read_register(gs->pdev, REG_STATUS, ®_value); + if (!(reg_value & MASK_H_LOCK) || !(reg_value & MASK_V_LOCK)) + return -ENOLCK; + if (!(reg_value & MASK_STD_LOCK)) + return -ERANGE; + + ret = gs_status_format(reg_value, &fmt); + + if (ret < 0) + return ret; + + *timings = fmt; + return 0; +} + +static int gs_enum_dv_timings(struct v4l2_subdev *sd, + struct v4l2_enum_dv_timings *timings) +{ + if (timings->index >= ARRAY_SIZE(fmt_cap)) + return -EINVAL; + + if (timings->pad != 0) + return -EINVAL; + + timings->timings = fmt_cap[timings->index]; + return 0; +} + +static int gs_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct gs *gs = to_gs(sd); + int reg_value; + + if (gs->enabled == enable) + return 0; + + gs->enabled = enable; + + if (enable) { + /* To force the specific format */ + reg_value = get_register_timings(&gs->current_timings); + return gs_write_register(gs->pdev, REG_FORCE_FMT, reg_value); + } else { + /* To renable auto-detection mode */ + return gs_write_register(gs->pdev, REG_FORCE_FMT, 0x0); + } +} + +static int gs_g_input_status(struct v4l2_subdev *sd, u32 *status) +{ + struct gs *gs = to_gs(sd); + u16 reg_value, i; + int ret; + + /* Check if the component detect a line, a frame or something else + * which looks like a video signal activity.*/ + for (i = 0; i < 4; i++) { + ret = gs_read_register(gs->pdev, + REG_LINES_PER_FRAME + i, ®_value); + if (reg_value) + break; + if (ret) { + *status = V4L2_IN_ST_NO_POWER; + return ret; + } + } + + /* If no register reports a video signal */ + if (i >= 4) + *status |= V4L2_IN_ST_NO_SIGNAL; + + ret = gs_read_register(gs->pdev, REG_STATUS, ®_value); + if (!(reg_value & MASK_H_LOCK)) + *status |= V4L2_IN_ST_NO_H_LOCK; + if (!(reg_value & MASK_V_LOCK)) + *status |= V4L2_IN_ST_NO_V_LOCK; + if (!(reg_value & MASK_STD_LOCK)) + *status |= V4L2_IN_ST_NO_STD_LOCK; + + return ret; +} + +static int gs_dv_timings_cap(struct v4l2_subdev *sd, + struct v4l2_dv_timings_cap *cap) +{ + if (cap->pad != 0) + return -EINVAL; + + *cap = gs_timings_cap; + return 0; +} + +/* V4L2 core operation handlers */ +static const struct v4l2_subdev_core_ops gs_core_ops = { +#ifdef CONFIG_VIDEO_ADV_DEBUG + .g_register = gs_g_register, + .s_register = gs_s_register, +#endif +}; + +static const struct v4l2_subdev_video_ops gs_video_ops = { + .s_dv_timings = gs_s_dv_timings, + .g_dv_timings = gs_g_dv_timings, + .s_stream = gs_s_stream, + .g_input_status = gs_g_input_status, + .query_dv_timings = gs_query_dv_timings, +}; + +static const struct v4l2_subdev_pad_ops gs_pad_ops = { + .enum_dv_timings= gs_enum_dv_timings, + .dv_timings_cap = gs_dv_timings_cap, +}; + +/* V4L2 top level operation handlers */ +static const struct v4l2_subdev_ops gs_ops = { + .core = &gs_core_ops, + .video = &gs_video_ops, + .pad = &gs_pad_ops, +}; + +static int gs_probe(struct spi_device *spi) +{ + int ret; + struct gs *gs; + struct v4l2_subdev *sd; + + gs = devm_kzalloc(&spi->dev, sizeof(struct gs), GFP_KERNEL); + if (!gs) + return -ENOMEM; + + gs->pdev = spi; + sd = &gs->sd; + + spi->mode = SPI_MODE_0; + spi->irq = -1; + spi->max_speed_hz = 10000000; + spi->bits_per_word = 16; + ret = spi_setup(spi); + v4l2_spi_subdev_init(sd, spi, &gs_ops); + + gs->current_timings = reg_fmt[0].format; + gs->enabled = 0; + + /* Set H_CONFIG to SMPTE timings */ + gs_write_register(spi, 0x0, 0x300); + + return ret; +} + +static int gs_remove(struct spi_device *spi) +{ + struct v4l2_subdev *sd = spi_get_drvdata(spi); + struct gs *gs = to_gs(sd); + + v4l2_device_unregister_subdev(sd); + kfree(gs); + return 0; +} + +static struct spi_driver gs_driver = { + .driver = { + .name = "gs1662", + .owner = THIS_MODULE, + }, + + .probe = gs_probe, + .remove = gs_remove, + .id_table = gs_id, +}; + +module_spi_driver(gs_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Charles-Antoine Couret "); +MODULE_DESCRIPTION("Gennum GS1662 HD/SD-SDI Serializer driver"); -- cgit v1.2.3 From 474cde669dfe49da07eed8e9c2d8c30016fa701c Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Thu, 15 Sep 2016 09:18:36 -0300 Subject: [media] MAINTAINERS: Add entry for the Renesas VIN driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The driver is maintained and supported, document it as such. Signed-off-by: Niklas Söderlund Acked-by: Laurent Pinchart Acked-by: Simon Horman Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 5678e50fc13a..d5c793b0f30f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7514,6 +7514,15 @@ F: Documentation/devicetree/bindings/media/renesas,fcp.txt F: drivers/media/platform/rcar-fcp.c F: include/media/rcar-fcp.h +MEDIA DRIVERS FOR RENESAS - VIN +M: Niklas Söderlund +L: linux-media@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +T: git git://linuxtv.org/media_tree.git +S: Supported +F: Documentation/devicetree/bindings/media/rcar_vin.txt +F: drivers/media/platform/rcar-vin/ + MEDIA DRIVERS FOR RENESAS - VSP1 M: Laurent Pinchart L: linux-media@vger.kernel.org -- cgit v1.2.3