From 1f6ccfff6314672743ad7252160654709e997a2a Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 13 May 2013 18:30:41 +0530 Subject: ARCv2: Support for ARCv2 ISA and HS38x cores The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta --- arch/arc/include/asm/ptrace.h | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch/arc/include/asm/ptrace.h') diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h index 1bfeec2c0558..91755972b9a2 100644 --- a/arch/arc/include/asm/ptrace.h +++ b/arch/arc/include/asm/ptrace.h @@ -16,6 +16,7 @@ /* THE pt_regs: Defines how regs are saved during entry into kernel */ +#ifdef CONFIG_ISA_ARCOMPACT struct pt_regs { /* Real registers */ @@ -56,6 +57,48 @@ struct pt_regs { long user_r25; }; +#else + +struct pt_regs { + + long orig_r0; + + union { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned long state:8, ecr_vec:8, + ecr_cause:8, ecr_param:8; +#else + unsigned long ecr_param:8, ecr_cause:8, + ecr_vec:8, state:8; +#endif + }; + unsigned long event; + }; + + long bta; /* bta_l1, bta_l2, erbta */ + + long user_r25; + + long r26; /* gp */ + long fp; + long sp; /* user/kernel sp depending on where we came from */ + + long r12; + + /*------- Below list auto saved by h/w -----------*/ + long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11; + + long blink; + long lp_end, lp_start, lp_count; + + long ei, ldi, jli; + + long ret; + long status32; +}; + +#endif /* Callee saved registers - need to be saved only when you are scheduled out */ -- cgit v1.2.3