From 9d0412680e6c7b685ee466842047bcfb924d6dc5 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Mon, 5 Feb 2007 11:42:07 +0100 Subject: [ARM] 4124/1: Rename mach-at91rm9200 and arch-at91rm9200 directories Now that Linux includes support for the Atmel AT91SAM9260 and AT91SAM9261 processors in addition to the original Atmel AT91RM9200 (with support for more AT91 processors pending), the "mach-at91rm9200" and "arch-at91rm9200" directories should be renamed to indicate their more generic nature. The following git commands should be run BEFORE applying this patch: git-mv arch/arm/mach-at91rm9200 arch/arm/mach-at91 git-mv include/asm-arm/arch-at91rm9200 include/asm-arm/arch-at91 Signed-off-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/Makefile') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 000f1100b553..0205547fa45c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -124,7 +124,7 @@ endif machine-$(CONFIG_ARCH_H720X) := h720x machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 machine-$(CONFIG_ARCH_REALVIEW) := realview - machine-$(CONFIG_ARCH_AT91) := at91rm9200 + machine-$(CONFIG_ARCH_AT91) := at91 machine-$(CONFIG_ARCH_EP93XX) := ep93xx machine-$(CONFIG_ARCH_PNX4008) := pnx4008 machine-$(CONFIG_ARCH_NETX) := netx -- cgit v1.2.3 From a21765a70ec06be175d3997320a83fa66fcc8955 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 11 Feb 2007 18:31:01 +0100 Subject: [ARM] 4157/2: S3C24XX: move arch/arch/mach-s3c2410 into cpu components The following patch and script moves the arch/arm/mach-s3c2410 directory into arch/arm/plat-s3c24xx for the generic core code and inti arch/arm/mach-s3c{cpu} for the cpu/machine support files Include directory include/asm-arm/plat-s3c24xx is added for the core include files. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/Kconfig | 8 + arch/arm/Makefile | 7 +- arch/arm/mach-s3c2400/Kconfig | 13 + arch/arm/mach-s3c2400/Makefile | 15 + arch/arm/mach-s3c2400/gpio.c | 42 + arch/arm/mach-s3c2410/Kconfig | 356 ++----- arch/arm/mach-s3c2410/Makefile | 95 +- arch/arm/mach-s3c2410/bast-irq.c | 2 +- arch/arm/mach-s3c2410/bast.h | 2 +- arch/arm/mach-s3c2410/clock.c | 565 ++++------ arch/arm/mach-s3c2410/clock.h | 63 -- arch/arm/mach-s3c2410/common-smdk.c | 200 ---- arch/arm/mach-s3c2410/common-smdk.h | 15 - arch/arm/mach-s3c2410/cpu.c | 357 ------- arch/arm/mach-s3c2410/cpu.h | 69 -- arch/arm/mach-s3c2410/devs.c | 585 ----------- arch/arm/mach-s3c2410/devs.h | 51 - arch/arm/mach-s3c2410/dma.c | 1528 +++------------------------- arch/arm/mach-s3c2410/dma.h | 45 - arch/arm/mach-s3c2410/gpio.c | 165 +-- arch/arm/mach-s3c2410/irq.c | 775 +------------- arch/arm/mach-s3c2410/irq.h | 107 -- arch/arm/mach-s3c2410/mach-amlm5900.c | 6 +- arch/arm/mach-s3c2410/mach-anubis.c | 325 ------ arch/arm/mach-s3c2410/mach-bast.c | 6 +- arch/arm/mach-s3c2410/mach-h1940.c | 8 +- arch/arm/mach-s3c2410/mach-n30.c | 8 +- arch/arm/mach-s3c2410/mach-nexcoder.c | 158 --- arch/arm/mach-s3c2410/mach-osiris.c | 303 ------ arch/arm/mach-s3c2410/mach-otom.c | 8 +- arch/arm/mach-s3c2410/mach-rx3715.c | 244 ----- arch/arm/mach-s3c2410/mach-smdk2410.c | 8 +- arch/arm/mach-s3c2410/mach-smdk2413.c | 140 --- arch/arm/mach-s3c2410/mach-smdk2440.c | 208 ---- arch/arm/mach-s3c2410/mach-vr1000.c | 6 +- arch/arm/mach-s3c2410/mach-vstms.c | 169 --- arch/arm/mach-s3c2410/pm-simtec.c | 66 -- arch/arm/mach-s3c2410/pm.c | 653 ++---------- arch/arm/mach-s3c2410/pm.h | 73 -- arch/arm/mach-s3c2410/s3c2400-gpio.c | 42 - arch/arm/mach-s3c2410/s3c2400.h | 31 - arch/arm/mach-s3c2410/s3c2410-clock.c | 276 ----- arch/arm/mach-s3c2410/s3c2410-dma.c | 161 --- arch/arm/mach-s3c2410/s3c2410-gpio.c | 71 -- arch/arm/mach-s3c2410/s3c2410-irq.c | 48 - arch/arm/mach-s3c2410/s3c2410-pm.c | 156 --- arch/arm/mach-s3c2410/s3c2410-sleep.S | 68 -- arch/arm/mach-s3c2410/s3c2410.c | 8 +- arch/arm/mach-s3c2410/s3c2410.h | 31 - arch/arm/mach-s3c2410/s3c2412-clock.c | 716 ------------- arch/arm/mach-s3c2410/s3c2412-dma.c | 161 --- arch/arm/mach-s3c2410/s3c2412-irq.c | 133 --- arch/arm/mach-s3c2410/s3c2412-pm.c | 128 --- arch/arm/mach-s3c2410/s3c2412.c | 181 ---- arch/arm/mach-s3c2410/s3c2412.h | 29 - arch/arm/mach-s3c2410/s3c2440-clock.c | 170 ---- arch/arm/mach-s3c2410/s3c2440-dma.c | 165 --- arch/arm/mach-s3c2410/s3c2440-dsc.c | 54 - arch/arm/mach-s3c2410/s3c2440-irq.c | 130 --- arch/arm/mach-s3c2410/s3c2440.c | 52 - arch/arm/mach-s3c2410/s3c2440.h | 17 - arch/arm/mach-s3c2410/s3c2442-clock.c | 171 ---- arch/arm/mach-s3c2410/s3c2442.c | 34 - arch/arm/mach-s3c2410/s3c2442.h | 17 - arch/arm/mach-s3c2410/s3c244x-irq.c | 146 --- arch/arm/mach-s3c2410/s3c244x.c | 184 ---- arch/arm/mach-s3c2410/s3c244x.h | 25 - arch/arm/mach-s3c2410/sleep.S | 151 +-- arch/arm/mach-s3c2410/time.c | 262 ----- arch/arm/mach-s3c2410/usb-simtec.c | 2 +- arch/arm/mach-s3c2412/Kconfig | 58 ++ arch/arm/mach-s3c2412/Makefile | 21 + arch/arm/mach-s3c2412/clock.c | 716 +++++++++++++ arch/arm/mach-s3c2412/dma.c | 161 +++ arch/arm/mach-s3c2412/irq.c | 133 +++ arch/arm/mach-s3c2412/mach-smdk2413.c | 140 +++ arch/arm/mach-s3c2412/mach-vstms.c | 169 +++ arch/arm/mach-s3c2412/pm.c | 128 +++ arch/arm/mach-s3c2412/s3c2412.c | 181 ++++ arch/arm/mach-s3c2440/Kconfig | 71 ++ arch/arm/mach-s3c2440/Makefile | 23 + arch/arm/mach-s3c2440/clock.c | 170 ++++ arch/arm/mach-s3c2440/dma.c | 165 +++ arch/arm/mach-s3c2440/dsc.c | 54 + arch/arm/mach-s3c2440/irq.c | 130 +++ arch/arm/mach-s3c2440/mach-anubis.c | 325 ++++++ arch/arm/mach-s3c2440/mach-nexcoder.c | 158 +++ arch/arm/mach-s3c2440/mach-osiris.c | 303 ++++++ arch/arm/mach-s3c2440/mach-rx3715.c | 244 +++++ arch/arm/mach-s3c2440/mach-smdk2440.c | 208 ++++ arch/arm/mach-s3c2440/s3c2440.c | 52 + arch/arm/mach-s3c2442/Kconfig | 27 + arch/arm/mach-s3c2442/Makefile | 16 + arch/arm/mach-s3c2442/clock.c | 171 ++++ arch/arm/mach-s3c2442/s3c2442.c | 34 + arch/arm/plat-s3c24xx/Kconfig | 96 ++ arch/arm/plat-s3c24xx/Makefile | 30 + arch/arm/plat-s3c24xx/clock.c | 449 ++++++++ arch/arm/plat-s3c24xx/common-smdk.c | 200 ++++ arch/arm/plat-s3c24xx/cpu.c | 357 +++++++ arch/arm/plat-s3c24xx/devs.c | 585 +++++++++++ arch/arm/plat-s3c24xx/dma.c | 1441 ++++++++++++++++++++++++++ arch/arm/plat-s3c24xx/gpio.c | 188 ++++ arch/arm/plat-s3c24xx/irq.c | 801 +++++++++++++++ arch/arm/plat-s3c24xx/pm-simtec.c | 66 ++ arch/arm/plat-s3c24xx/pm.c | 659 ++++++++++++ arch/arm/plat-s3c24xx/s3c244x-irq.c | 146 +++ arch/arm/plat-s3c24xx/s3c244x.c | 184 ++++ arch/arm/plat-s3c24xx/s3c244x.h | 25 + arch/arm/plat-s3c24xx/sleep.S | 159 +++ arch/arm/plat-s3c24xx/time.c | 262 +++++ include/asm-arm/plat-s3c24xx/clock.h | 63 ++ include/asm-arm/plat-s3c24xx/common-smdk.h | 15 + include/asm-arm/plat-s3c24xx/cpu.h | 69 ++ include/asm-arm/plat-s3c24xx/devs.h | 51 + include/asm-arm/plat-s3c24xx/dma.h | 45 + include/asm-arm/plat-s3c24xx/irq.h | 107 ++ include/asm-arm/plat-s3c24xx/pm.h | 73 ++ include/asm-arm/plat-s3c24xx/s3c2400.h | 31 + include/asm-arm/plat-s3c24xx/s3c2410.h | 31 + include/asm-arm/plat-s3c24xx/s3c2412.h | 29 + include/asm-arm/plat-s3c24xx/s3c2440.h | 17 + include/asm-arm/plat-s3c24xx/s3c2442.h | 17 + 123 files changed, 10711 insertions(+), 10617 deletions(-) create mode 100644 arch/arm/mach-s3c2400/Kconfig create mode 100644 arch/arm/mach-s3c2400/Makefile create mode 100644 arch/arm/mach-s3c2400/gpio.c delete mode 100644 arch/arm/mach-s3c2410/clock.h delete mode 100644 arch/arm/mach-s3c2410/common-smdk.c delete mode 100644 arch/arm/mach-s3c2410/common-smdk.h delete mode 100644 arch/arm/mach-s3c2410/cpu.c delete mode 100644 arch/arm/mach-s3c2410/cpu.h delete mode 100644 arch/arm/mach-s3c2410/devs.c delete mode 100644 arch/arm/mach-s3c2410/devs.h delete mode 100644 arch/arm/mach-s3c2410/dma.h delete mode 100644 arch/arm/mach-s3c2410/irq.h delete mode 100644 arch/arm/mach-s3c2410/mach-anubis.c delete mode 100644 arch/arm/mach-s3c2410/mach-nexcoder.c delete mode 100644 arch/arm/mach-s3c2410/mach-osiris.c delete mode 100644 arch/arm/mach-s3c2410/mach-rx3715.c delete mode 100644 arch/arm/mach-s3c2410/mach-smdk2413.c delete mode 100644 arch/arm/mach-s3c2410/mach-smdk2440.c delete mode 100644 arch/arm/mach-s3c2410/mach-vstms.c delete mode 100644 arch/arm/mach-s3c2410/pm-simtec.c delete mode 100644 arch/arm/mach-s3c2410/pm.h delete mode 100644 arch/arm/mach-s3c2410/s3c2400-gpio.c delete mode 100644 arch/arm/mach-s3c2410/s3c2400.h delete mode 100644 arch/arm/mach-s3c2410/s3c2410-clock.c delete mode 100644 arch/arm/mach-s3c2410/s3c2410-dma.c delete mode 100644 arch/arm/mach-s3c2410/s3c2410-gpio.c delete mode 100644 arch/arm/mach-s3c2410/s3c2410-irq.c delete mode 100644 arch/arm/mach-s3c2410/s3c2410-pm.c delete mode 100644 arch/arm/mach-s3c2410/s3c2410-sleep.S delete mode 100644 arch/arm/mach-s3c2410/s3c2410.h delete mode 100644 arch/arm/mach-s3c2410/s3c2412-clock.c delete mode 100644 arch/arm/mach-s3c2410/s3c2412-dma.c delete mode 100644 arch/arm/mach-s3c2410/s3c2412-irq.c delete mode 100644 arch/arm/mach-s3c2410/s3c2412-pm.c delete mode 100644 arch/arm/mach-s3c2410/s3c2412.c delete mode 100644 arch/arm/mach-s3c2410/s3c2412.h delete mode 100644 arch/arm/mach-s3c2410/s3c2440-clock.c delete mode 100644 arch/arm/mach-s3c2410/s3c2440-dma.c delete mode 100644 arch/arm/mach-s3c2410/s3c2440-dsc.c delete mode 100644 arch/arm/mach-s3c2410/s3c2440-irq.c delete mode 100644 arch/arm/mach-s3c2410/s3c2440.c delete mode 100644 arch/arm/mach-s3c2410/s3c2440.h delete mode 100644 arch/arm/mach-s3c2410/s3c2442-clock.c delete mode 100644 arch/arm/mach-s3c2410/s3c2442.c delete mode 100644 arch/arm/mach-s3c2410/s3c2442.h delete mode 100644 arch/arm/mach-s3c2410/s3c244x-irq.c delete mode 100644 arch/arm/mach-s3c2410/s3c244x.c delete mode 100644 arch/arm/mach-s3c2410/s3c244x.h delete mode 100644 arch/arm/mach-s3c2410/time.c create mode 100644 arch/arm/mach-s3c2412/Kconfig create mode 100644 arch/arm/mach-s3c2412/Makefile create mode 100644 arch/arm/mach-s3c2412/clock.c create mode 100644 arch/arm/mach-s3c2412/dma.c create mode 100644 arch/arm/mach-s3c2412/irq.c create mode 100644 arch/arm/mach-s3c2412/mach-smdk2413.c create mode 100644 arch/arm/mach-s3c2412/mach-vstms.c create mode 100644 arch/arm/mach-s3c2412/pm.c create mode 100644 arch/arm/mach-s3c2412/s3c2412.c create mode 100644 arch/arm/mach-s3c2440/Kconfig create mode 100644 arch/arm/mach-s3c2440/Makefile create mode 100644 arch/arm/mach-s3c2440/clock.c create mode 100644 arch/arm/mach-s3c2440/dma.c create mode 100644 arch/arm/mach-s3c2440/dsc.c create mode 100644 arch/arm/mach-s3c2440/irq.c create mode 100644 arch/arm/mach-s3c2440/mach-anubis.c create mode 100644 arch/arm/mach-s3c2440/mach-nexcoder.c create mode 100644 arch/arm/mach-s3c2440/mach-osiris.c create mode 100644 arch/arm/mach-s3c2440/mach-rx3715.c create mode 100644 arch/arm/mach-s3c2440/mach-smdk2440.c create mode 100644 arch/arm/mach-s3c2440/s3c2440.c create mode 100644 arch/arm/mach-s3c2442/Kconfig create mode 100644 arch/arm/mach-s3c2442/Makefile create mode 100644 arch/arm/mach-s3c2442/clock.c create mode 100644 arch/arm/mach-s3c2442/s3c2442.c create mode 100644 arch/arm/plat-s3c24xx/Kconfig create mode 100644 arch/arm/plat-s3c24xx/Makefile create mode 100644 arch/arm/plat-s3c24xx/clock.c create mode 100644 arch/arm/plat-s3c24xx/common-smdk.c create mode 100644 arch/arm/plat-s3c24xx/cpu.c create mode 100644 arch/arm/plat-s3c24xx/devs.c create mode 100644 arch/arm/plat-s3c24xx/dma.c create mode 100644 arch/arm/plat-s3c24xx/gpio.c create mode 100644 arch/arm/plat-s3c24xx/irq.c create mode 100644 arch/arm/plat-s3c24xx/pm-simtec.c create mode 100644 arch/arm/plat-s3c24xx/pm.c create mode 100644 arch/arm/plat-s3c24xx/s3c244x-irq.c create mode 100644 arch/arm/plat-s3c24xx/s3c244x.c create mode 100644 arch/arm/plat-s3c24xx/s3c244x.h create mode 100644 arch/arm/plat-s3c24xx/sleep.S create mode 100644 arch/arm/plat-s3c24xx/time.c create mode 100644 include/asm-arm/plat-s3c24xx/clock.h create mode 100644 include/asm-arm/plat-s3c24xx/common-smdk.h create mode 100644 include/asm-arm/plat-s3c24xx/cpu.h create mode 100644 include/asm-arm/plat-s3c24xx/devs.h create mode 100644 include/asm-arm/plat-s3c24xx/dma.h create mode 100644 include/asm-arm/plat-s3c24xx/irq.h create mode 100644 include/asm-arm/plat-s3c24xx/pm.h create mode 100644 include/asm-arm/plat-s3c24xx/s3c2400.h create mode 100644 include/asm-arm/plat-s3c24xx/s3c2410.h create mode 100644 include/asm-arm/plat-s3c24xx/s3c2412.h create mode 100644 include/asm-arm/plat-s3c24xx/s3c2440.h create mode 100644 include/asm-arm/plat-s3c24xx/s3c2442.h (limited to 'arch/arm/Makefile') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6783c2e5512d..51ee13e7c74c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -363,7 +363,15 @@ source "arch/arm/mach-omap1/Kconfig" source "arch/arm/mach-omap2/Kconfig" +source "arch/arm/plat-s3c24xx/Kconfig" + +if ARCH_S3C2410 +source "arch/arm/mach-s3c2400/Kconfig" source "arch/arm/mach-s3c2410/Kconfig" +source "arch/arm/mach-s3c2412/Kconfig" +source "arch/arm/mach-s3c2440/Kconfig" +source "arch/arm/mach-s3c2442/Kconfig" +endif source "arch/arm/mach-lh7a40x/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 000f1100b553..2df1ea0a0c2d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -149,7 +149,7 @@ MACHINE := arch/arm/mach-$(machine-y)/ else MACHINE := endif - + export TEXT_OFFSET GZFLAGS MMUEXT # Do we have FASTFPE? @@ -161,6 +161,10 @@ endif # If we have a machine-specific directory, then include it in the build. core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ core-y += $(MACHINE) +core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2400/ +core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2412/ +core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2440/ +core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2442/ core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/ core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ) core-$(CONFIG_VFP) += arch/arm/vfp/ @@ -168,6 +172,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/ # If we have a common platform directory, then include it in the build. core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/ core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/ +core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/ drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/ diff --git a/arch/arm/mach-s3c2400/Kconfig b/arch/arm/mach-s3c2400/Kconfig new file mode 100644 index 000000000000..deab0722836e --- /dev/null +++ b/arch/arm/mach-s3c2400/Kconfig @@ -0,0 +1,13 @@ +# arch/arm/mach-s3c2400/Kconfig +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + + + +menu "S3C2400 Machines" + + +endmenu + diff --git a/arch/arm/mach-s3c2400/Makefile b/arch/arm/mach-s3c2400/Makefile new file mode 100644 index 000000000000..7e23f4e13766 --- /dev/null +++ b/arch/arm/mach-s3c2400/Makefile @@ -0,0 +1,15 @@ +# arch/arm/mach-s3c2400/Makefile +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +obj-$(CONFIG_CPU_S3C2400) += gpio.o + +# Machine support + diff --git a/arch/arm/mach-s3c2400/gpio.c b/arch/arm/mach-s3c2400/gpio.c new file mode 100644 index 000000000000..758e160410e9 --- /dev/null +++ b/arch/arm/mach-s3c2400/gpio.c @@ -0,0 +1,42 @@ +/* linux/arch/arm/mach-s3c2400/gpio.c + * + * Copyright (c) 2006 Lucas Correia Villa Real + * + * S3C2400 GPIO support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +int s3c2400_gpio_getirq(unsigned int pin) +{ + if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7) + return -1; /* not valid interrupts */ + + return (pin - S3C2410_GPE0) + IRQ_EINT0; +} + +EXPORT_SYMBOL(s3c2400_gpio_getirq); diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 0ab590ec4582..016b53f5d6fc 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -1,54 +1,51 @@ -if ARCH_S3C2410 +# arch/arm/mach-s3c2410/Kconfig +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 -menu "S3C24XX Implementations" +config CPU_S3C2410 + bool + depends on ARCH_S3C2410 + select S3C2410_CLOCK + select S3C2410_GPIO + select S3C2410_PM if PM + help + Support for S3C2410 and S3C2410A family from the S3C24XX line + of Samsung Mobile CPUs. -config MACH_AML_M5900 - bool "AML M5900 Series" - select CPU_S3C2410 - select PM_SIMTEC if PM +config CPU_S3C2410_DMA + bool + depends on S3C2410_DMA && (CPU_S3C2410 || CPU_S3C2442) + default y if CPU_S3C2410 || CPU_S3C2442 help - Say Y here if you are using the American Microsystems M5900 Series - + DMA device selection for S3C2410 and compatible CPUs -config MACH_ANUBIS - bool "Simtec Electronics ANUBIS" - select CPU_S3C2440 - select PM_SIMTEC if PM +config S3C2410_PM + bool help - Say Y here if you are using the Simtec Electronics ANUBIS - development system + Power Management code common to S3C2410 and better -config MACH_OSIRIS - bool "Simtec IM2440D20 (OSIRIS) module" - select CPU_S3C2440 - select PM_SIMTEC if PM +config S3C2410_GPIO + bool help - Say Y here if you are using the Simtec IM2440D20 module, also - known as the Osiris. + GPIO code for S3C2410 and similar processors -config ARCH_BAST - bool "Simtec Electronics BAST (EB2410ITX)" - select CPU_S3C2410 - select PM_SIMTEC if PM - select ISA +config S3C2410_CLOCK + bool help - Say Y here if you are using the Simtec Electronics EB2410ITX - development board (also known as BAST) + Clock code for the S3C2410, and similar processors - Product page: . -config BAST_PC104_IRQ - bool "BAST PC104 IRQ support" - depends on ARCH_BAST - default y - help - Say Y here to enable the PC104 IRQ routing on the - Simtec BAST (EB2410ITX) +menu "S3C2410 Machines" -config PM_H1940 - bool +config ARCH_SMDK2410 + bool "SMDK2410/A9M2410" + select CPU_S3C2410 + select MACH_SMDK help - Internal node for H1940 and related PM + Say Y here if you are using the SMDK2410 or the derived module A9M2410 + config ARCH_H1940 bool "IPAQ H1940" @@ -57,7 +54,10 @@ config ARCH_H1940 help Say Y here if you are using the HP IPAQ H1940 - . +config PM_H1940 + bool + help + Internal node for H1940 and related PM config MACH_N30 bool "Acer N30" @@ -65,53 +65,36 @@ config MACH_N30 help Say Y here if you are using the Acer N30 - . - -config MACH_SMDK - bool - help - Common machine code for SMDK2410 and SMDK2440 - -config ARCH_SMDK2410 - bool "SMDK2410/A9M2410" +config ARCH_BAST + bool "Simtec Electronics BAST (EB2410ITX)" select CPU_S3C2410 - select MACH_SMDK + select PM_SIMTEC if PM + select ISA help - Say Y here if you are using the SMDK2410 or the derived module A9M2410 - + Say Y here if you are using the Simtec Electronics EB2410ITX + development board (also known as BAST) -config ARCH_S3C2440 - bool "SMDK2440" - select CPU_S3C2440 - select MACH_SMDK +config MACH_OTOM + bool "NexVision OTOM Board" + select CPU_S3C2410 help - Say Y here if you are using the SMDK2440. - -config SMDK2440_CPU2440 - bool "SMDK2440 with S3C2440 CPU module" - depends on ARCH_S3C2440 - default y if ARCH_S3C2440 - select CPU_S3C2440 - -config SMDK2440_CPU2442 - bool "SMDM2440 with S3C2442 CPU module" - depends on ARCH_S3C2440 - select CPU_S3C2442 + Say Y here if you are using the Nex Vision OTOM board -config MACH_S3C2413 - bool +config MACH_AML_M5900 + bool "AML M5900 Series" + select CPU_S3C2410 + select PM_SIMTEC if PM help - Internal node for S3C2413 version of SMDK2413, so that - machine_is_s3c2413() will work when MACH_SMDK2413 is - selected + Say Y here if you are using the American Microsystems M5900 Series + -config MACH_SMDK2413 - bool "SMDK2413" - select CPU_S3C2412 - select MACH_S3C2413 - select MACH_SMDK +config BAST_PC104_IRQ + bool "BAST PC104 IRQ support" + depends on ARCH_BAST + default y help - Say Y here if you are using an SMDK2413 + Say Y here to enable the PC104 IRQ routing on the + Simtec BAST (EB2410ITX) config MACH_VR1000 bool "Thorcom VR1000" @@ -120,223 +103,6 @@ config MACH_VR1000 help Say Y here if you are using the Thorcom VR1000 board. - This linux port is currently being maintained by Simtec, on behalf - of Thorcom. Any queries, please contact Thorcom first. - -config MACH_RX3715 - bool "HP iPAQ rx3715" - select CPU_S3C2440 - select PM_H1940 if PM - help - Say Y here if you are using the HP iPAQ rx3715. - - See for more - information on this project - -config MACH_OTOM - bool "NexVision OTOM Board" - select CPU_S3C2410 - help - Say Y here if you are using the Nex Vision OTOM board - -config MACH_NEXCODER_2440 - bool "NexVision NEXCODER 2440 Light Board" - select CPU_S3C2440 - help - Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board - -config MACH_VSTMS - bool "VMSTMS" - select CPU_S3C2412 - help - Say Y here if you are using an VSTMS board endmenu -config S3C2410_CLOCK - bool - help - Clock code for the S3C2410, and similar processors - -config S3C2410_GPIO - bool - help - GPIO code for S3C2410 and similar processors - -config S3C2410_PM - bool - help - Power Management code common to S3C2410 and better - -config CPU_S3C2410_DMA - bool - depends on S3C2410_DMA && (CPU_S3C2410 || CPU_S3C2442) - default y if CPU_S3C2410 || CPU_S3C2442 - help - DMA device selection for S3C2410 and compatible CPUs - -config CPU_S3C2410 - bool - depends on ARCH_S3C2410 - select S3C2410_CLOCK - select S3C2410_GPIO - select S3C2410_PM if PM - help - Support for S3C2410 and S3C2410A family from the S3C24XX line - of Samsung Mobile CPUs. - -# internal node to signify if we are only dealing with an S3C2412 - -config CPU_S3C2412_ONLY - bool - depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \ - !CPU_S3C2440 && !CPU_S3C2442 && CPU_S3C2412 - default y if CPU_S3C2412 - -config S3C2412_PM - bool - help - Internal config node to apply S3C2412 power management - -config S3C2412_DMA - bool - depends on CPU_S3C2412 - help - Internal config node for S3C2412 DMA support - -config CPU_S3C2412 - bool - depends on ARCH_S3C2410 - select S3C2412_PM if PM - select S3C2412_DMA if S3C2410_DMA - help - Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line - -config CPU_S3C244X - bool - depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442) - help - Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems. - -config S3C2440_DMA - bool - depends on ARCH_S3C2410 && CPU_S3C24405B - help - Support for S3C2440 specific DMA code5A - -config CPU_S3C2440 - bool - depends on ARCH_S3C2410 - select S3C2410_CLOCK - select S3C2410_PM if PM - select S3C2410_GPIO - select S3C2440_DMA if S3C2410_DMA - select CPU_S3C244X - help - Support for S3C2440 Samsung Mobile CPU based systems. - -config CPU_S3C2442 - bool - depends on ARCH_S3C2420 - select S3C2410_CLOCK - select S3C2410_GPIO - select S3C2410_PM if PM - select CPU_S3C244X - help - Support for S3C2442 Samsung Mobile CPU based systems. - -comment "S3C2410 Boot" - -config S3C2410_BOOT_WATCHDOG - bool "S3C2410 Initialisation watchdog" - depends on ARCH_S3C2410 && S3C2410_WATCHDOG - help - Say y to enable the watchdog during the kernel decompression - stage. If the kernel fails to uncompress, then the watchdog - will trigger a reset and the system should restart. - - Although this uses the same hardware unit as the kernel watchdog - driver, it is not a replacement for it. If you use this option, - you will have to use the watchdg driver to either stop the timeout - or restart it. If you do not, then your kernel will reboot after - startup. - - The driver uses a fixed timeout value, so the exact time till the - system resets depends on the value of PCLK. The timeout on an - 200MHz s3c2410 should be about 30 seconds. - -config S3C2410_BOOT_ERROR_RESET - bool "S3C2410 Reboot on decompression error" - depends on ARCH_S3C2410 - help - Say y here to use the watchdog to reset the system if the - kernel decompressor detects an error during decompression. - - -comment "S3C2410 Setup" - -config S3C2410_DMA - bool "S3C2410 DMA support" - depends on ARCH_S3C2410 - help - S3C2410 DMA support. This is needed for drivers like sound which - use the S3C2410's DMA system to move data to and from the - peripheral blocks. - -config S3C2410_DMA_DEBUG - bool "S3C2410 DMA support debug" - depends on ARCH_S3C2410 && S3C2410_DMA - help - Enable debugging output for the DMA code. This option sends info - to the kernel log, at priority KERN_DEBUG. - - Note, it is easy to create and fill the log buffer in a small - amount of time, as well as using an significant percentage of - the CPU time doing so. - -config S3C2410_PM_DEBUG - bool "S3C2410 PM Suspend debug" - depends on ARCH_S3C2410 && PM - help - Say Y here if you want verbose debugging from the PM Suspend and - Resume code. See - for more information. - -config S3C2410_PM_CHECK - bool "S3C2410 PM Suspend Memory CRC" - depends on ARCH_S3C2410 && PM && CRC32 - help - Enable the PM code's memory area checksum over sleep. This option - will generate CRCs of all blocks of memory, and store them before - going to sleep. The blocks are then checked on resume for any - errors. - -config S3C2410_PM_CHECK_CHUNKSIZE - int "S3C2410 PM Suspend CRC Chunksize (KiB)" - depends on ARCH_S3C2410 && PM && S3C2410_PM_CHECK - default 64 - help - Set the chunksize in Kilobytes of the CRC for checking memory - corruption over suspend and resume. A smaller value will mean that - the CRC data block will take more memory, but wil identify any - faults with better precision. - -config PM_SIMTEC - bool - help - Common power management code for systems that are - compatible with the Simtec style of power management - -config S3C2410_LOWLEVEL_UART_PORT - int "S3C2410 UART to use for low-level messages" - default 0 - help - Choice of which UART port to use for the low-level messages, - such as the `Uncompressing...` at start time. The value of - this configuration should be between zero and two. The port - must have been initialised by the boot-loader before use. - - Note, this does not affect the port used by the debug messages, - which is a separate configuration. - -endif diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 1cc5febdaabd..b33ac5b84773 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile @@ -1,85 +1,30 @@ - +# arch/arm/mach-s3c2410/Makefile # -# Makefile for the linux kernel. +# Copyright 2007 Simtec Electronics # +# Licensed under GPLv2 -# Object file lists. - -obj-y := cpu.o irq.o time.o gpio.o clock.o devs.o -obj-m := -obj-n := -obj- := - -# DMA -obj-$(CONFIG_S3C2410_DMA) += dma.o - -# S3C2400 support files -obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o - -# S3C2410 support files +obj-y := +obj-m := +obj-n := +obj- := obj-$(CONFIG_CPU_S3C2410) += s3c2410.o -obj-$(CONFIG_CPU_S3C2410) += s3c2410-irq.o - -obj-$(CONFIG_S3C2410_PM) += s3c2410-pm.o s3c2410-sleep.o -obj-$(CONFIG_S3C2410_GPIO) += s3c2410-gpio.o -obj-$(CONFIG_CPU_S3C2410_DMA) += s3c2410-dma.o - -# Power Management support - -obj-$(CONFIG_PM) += pm.o sleep.o -obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o -obj-$(CONFIG_PM_H1940) += pm-h1940.o - -# S3C2412 support -obj-$(CONFIG_CPU_S3C2412) += s3c2412.o -obj-$(CONFIG_CPU_S3C2412) += s3c2412-irq.o -obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o - -obj-$(CONFIG_S3C2412_PM) += s3c2412-pm.o -obj-$(CONFIG_S3C2412_DMA) += s3c2412-dma.o - -# -# S3C244X support - -obj-$(CONFIG_CPU_S3C244X) += s3c244x.o -obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o - -# Clock control - -obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o - -# S3C2440 support +obj-$(CONFIG_CPU_S3C2410) += irq.o +obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o +obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o +obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o +obj-$(CONFIG_S3C2410_GPIO) += gpio.o +obj-$(CONFIG_S3C2410_CLOCK) += clock.o -obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o -obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o -obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o -obj-$(CONFIG_S3C2440_DMA) += s3c2440-dma.o +# Machine support -# S3C2442 support - -obj-$(CONFIG_CPU_S3C2442) += s3c2442.o -obj-$(CONFIG_CPU_S3C2442) += s3c2442-clock.o - -# bast extras - -obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o - -# machine specific support - -obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o -obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o -obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o -obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o +obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o obj-$(CONFIG_ARCH_H1940) += mach-h1940.o +obj-$(CONFIG_PM_H1940) += pm-h1940.o obj-$(CONFIG_MACH_N30) += mach-n30.o -obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o -obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o -obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o -obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o -obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o +obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o obj-$(CONFIG_MACH_OTOM) += mach-otom.o -obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o -obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o - -obj-$(CONFIG_MACH_SMDK) += common-smdk.o \ No newline at end of file +obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o +obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o +obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c index 379efe70778c..daeba427d781 100644 --- a/arch/arm/mach-s3c2410/bast-irq.c +++ b/arch/arm/mach-s3c2410/bast-irq.c @@ -39,7 +39,7 @@ #include #include -#include "irq.h" +#include #if 0 #include diff --git a/arch/arm/mach-s3c2410/bast.h b/arch/arm/mach-s3c2410/bast.h index e5d03311752c..e98543742eb9 100644 --- a/arch/arm/mach-s3c2410/bast.h +++ b/arch/arm/mach-s3c2410/bast.h @@ -1,2 +1,2 @@ - +/* linux/arch/arm/mach-s3c2410/bast.h extern void bast_init_irq(void); diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c index e13fb6778890..5b4831c4c1d8 100644 --- a/arch/arm/mach-s3c2410/clock.c +++ b/arch/arm/mach-s3c2410/clock.c @@ -1,15 +1,9 @@ /* linux/arch/arm/mach-s3c2410/clock.c * - * Copyright (c) 2004-2005 Simtec Electronics + * Copyright (c) 2006 Simtec Electronics * Ben Dooks * - * S3C24XX Core clock control support - * - * Based on, and code from linux/arch/arm/mach-versatile/clock.c - ** - ** Copyright (C) 2004 ARM Limited. - ** Written by Deep Blue Solutions Limited. - * + * S3C2410,S3C2440,S3C2442 Clock control support * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,418 +26,251 @@ #include #include #include -#include #include -#include -#include #include #include #include +#include + +#include #include -#include #include +#include #include #include -#include "clock.h" -#include "cpu.h" - -/* clock information */ +#include +#include +#include -static LIST_HEAD(clocks); - -DEFINE_MUTEX(clocks_mutex); - -/* enable and disable calls for use with the clk struct */ - -static int clk_null_enable(struct clk *clk, int enable) +int s3c2410_clkcon_enable(struct clk *clk, int enable) { - return 0; -} - -/* Clock API calls */ + unsigned int clocks = clk->ctrlbit; + unsigned long clkcon; -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p; - struct clk *clk = ERR_PTR(-ENOENT); - int idno; + clkcon = __raw_readl(S3C2410_CLKCON); - if (dev == NULL || dev->bus != &platform_bus_type) - idno = -1; + if (enable) + clkcon |= clocks; else - idno = to_platform_device(dev)->id; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(p, &clocks, list) { - if (p->id == idno && - strcmp(id, p->name) == 0 && - try_module_get(p->owner)) { - clk = p; - break; - } - } - - /* check for the case where a device was supplied, but the - * clock that was being searched for is not device specific */ - - if (IS_ERR(clk)) { - list_for_each_entry(p, &clocks, list) { - if (p->id == -1 && strcmp(id, p->name) == 0 && - try_module_get(p->owner)) { - clk = p; - break; - } - } - } + clkcon &= ~clocks; - mutex_unlock(&clocks_mutex); - return clk; -} + /* ensure none of the special function bits set */ + clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER); -void clk_put(struct clk *clk) -{ - module_put(clk->owner); -} + __raw_writel(clkcon, S3C2410_CLKCON); -int clk_enable(struct clk *clk) -{ - if (IS_ERR(clk) || clk == NULL) - return -EINVAL; - - clk_enable(clk->parent); - - mutex_lock(&clocks_mutex); - - if ((clk->usage++) == 0) - (clk->enable)(clk, 1); - - mutex_unlock(&clocks_mutex); return 0; } -void clk_disable(struct clk *clk) -{ - if (IS_ERR(clk) || clk == NULL) - return; - - mutex_lock(&clocks_mutex); - - if ((--clk->usage) == 0) - (clk->enable)(clk, 0); - - mutex_unlock(&clocks_mutex); - clk_disable(clk->parent); -} - - -unsigned long clk_get_rate(struct clk *clk) -{ - if (IS_ERR(clk)) - return 0; - - if (clk->rate != 0) - return clk->rate; - - if (clk->get_rate != NULL) - return (clk->get_rate)(clk); - - if (clk->parent != NULL) - return clk_get_rate(clk->parent); - - return clk->rate; -} - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (!IS_ERR(clk) && clk->round_rate) - return (clk->round_rate)(clk, rate); - - return rate; -} - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret; - - if (IS_ERR(clk)) - return -EINVAL; - - mutex_lock(&clocks_mutex); - ret = (clk->set_rate)(clk, rate); - mutex_unlock(&clocks_mutex); - - return ret; -} - -struct clk *clk_get_parent(struct clk *clk) +static int s3c2410_upll_enable(struct clk *clk, int enable) { - return clk->parent; -} - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int ret = 0; - - if (IS_ERR(clk)) - return -EINVAL; - - mutex_lock(&clocks_mutex); - - if (clk->set_parent) - ret = (clk->set_parent)(clk, parent); - - mutex_unlock(&clocks_mutex); - - return ret; -} - -EXPORT_SYMBOL(clk_get); -EXPORT_SYMBOL(clk_put); -EXPORT_SYMBOL(clk_enable); -EXPORT_SYMBOL(clk_disable); -EXPORT_SYMBOL(clk_get_rate); -EXPORT_SYMBOL(clk_round_rate); -EXPORT_SYMBOL(clk_set_rate); -EXPORT_SYMBOL(clk_get_parent); -EXPORT_SYMBOL(clk_set_parent); - -/* base clocks */ - -struct clk clk_xtal = { - .name = "xtal", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, -}; - -struct clk clk_mpll = { - .name = "mpll", - .id = -1, -}; - -struct clk clk_upll = { - .name = "upll", - .id = -1, - .parent = NULL, - .ctrlbit = 0, -}; - -struct clk clk_f = { - .name = "fclk", - .id = -1, - .rate = 0, - .parent = &clk_mpll, - .ctrlbit = 0, -}; - -struct clk clk_h = { - .name = "hclk", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, -}; - -struct clk clk_p = { - .name = "pclk", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, -}; - -struct clk clk_usb_bus = { - .name = "usb-bus", - .id = -1, - .rate = 0, - .parent = &clk_upll, -}; - -/* clocks that could be registered by external code */ - -static int s3c24xx_dclk_enable(struct clk *clk, int enable) -{ - unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON); + unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); + unsigned long orig = clkslow; if (enable) - dclkcon |= clk->ctrlbit; + clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF; else - dclkcon &= ~clk->ctrlbit; + clkslow |= S3C2410_CLKSLOW_UCLK_OFF; - __raw_writel(dclkcon, S3C24XX_DCLKCON); + __raw_writel(clkslow, S3C2410_CLKSLOW); - return 0; -} + /* if we started the UPLL, then allow to settle */ -static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) -{ - unsigned long dclkcon; - unsigned int uclk; - - if (parent == &clk_upll) - uclk = 1; - else if (parent == &clk_p) - uclk = 0; - else - return -EINVAL; - - clk->parent = parent; - - dclkcon = __raw_readl(S3C24XX_DCLKCON); - - if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) { - if (uclk) - dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK; - else - dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK; - } else { - if (uclk) - dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK; - else - dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK; - } - - __raw_writel(dclkcon, S3C24XX_DCLKCON); + if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF)) + udelay(200); return 0; } - -static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) -{ - unsigned long mask; - unsigned long source; - - /* calculate the MISCCR setting for the clock */ - - if (parent == &clk_xtal) - source = S3C2410_MISCCR_CLK0_MPLL; - else if (parent == &clk_upll) - source = S3C2410_MISCCR_CLK0_UPLL; - else if (parent == &clk_f) - source = S3C2410_MISCCR_CLK0_FCLK; - else if (parent == &clk_h) - source = S3C2410_MISCCR_CLK0_HCLK; - else if (parent == &clk_p) - source = S3C2410_MISCCR_CLK0_PCLK; - else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0) - source = S3C2410_MISCCR_CLK0_DCLK0; - else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1) - source = S3C2410_MISCCR_CLK0_DCLK0; - else - return -EINVAL; - - clk->parent = parent; - - if (clk == &s3c24xx_dclk0) - mask = S3C2410_MISCCR_CLK0_MASK; - else { - source <<= 4; - mask = S3C2410_MISCCR_CLK1_MASK; +/* standard clock definitions */ + +static struct clk init_clocks_disable[] = { + { + .name = "nand", + .id = -1, + .parent = &clk_h, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_NAND, + }, { + .name = "sdi", + .id = -1, + .parent = &clk_p, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_SDI, + }, { + .name = "adc", + .id = -1, + .parent = &clk_p, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_ADC, + }, { + .name = "i2c", + .id = -1, + .parent = &clk_p, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_IIC, + }, { + .name = "iis", + .id = -1, + .parent = &clk_p, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_IIS, + }, { + .name = "spi", + .id = -1, + .parent = &clk_p, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_SPI, } - - s3c2410_modify_misccr(mask, source); - return 0; -} - -/* external clock definitions */ - -struct clk s3c24xx_dclk0 = { - .name = "dclk0", - .id = -1, - .ctrlbit = S3C2410_DCLKCON_DCLK0EN, - .enable = s3c24xx_dclk_enable, - .set_parent = s3c24xx_dclk_setparent, -}; - -struct clk s3c24xx_dclk1 = { - .name = "dclk1", - .id = -1, - .ctrlbit = S3C2410_DCLKCON_DCLK0EN, - .enable = s3c24xx_dclk_enable, - .set_parent = s3c24xx_dclk_setparent, }; -struct clk s3c24xx_clkout0 = { - .name = "clkout0", - .id = -1, - .set_parent = s3c24xx_clkout_setparent, +static struct clk init_clocks[] = { + { + .name = "lcd", + .id = -1, + .parent = &clk_h, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_LCDC, + }, { + .name = "gpio", + .id = -1, + .parent = &clk_p, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_GPIO, + }, { + .name = "usb-host", + .id = -1, + .parent = &clk_h, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_USBH, + }, { + .name = "usb-device", + .id = -1, + .parent = &clk_h, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_USBD, + }, { + .name = "timers", + .id = -1, + .parent = &clk_p, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_PWMT, + }, { + .name = "uart", + .id = 0, + .parent = &clk_p, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_UART0, + }, { + .name = "uart", + .id = 1, + .parent = &clk_p, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_UART1, + }, { + .name = "uart", + .id = 2, + .parent = &clk_p, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_UART2, + }, { + .name = "rtc", + .id = -1, + .parent = &clk_p, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2410_CLKCON_RTC, + }, { + .name = "watchdog", + .id = -1, + .parent = &clk_p, + .ctrlbit = 0, + }, { + .name = "usb-bus-host", + .id = -1, + .parent = &clk_usb_bus, + }, { + .name = "usb-bus-gadget", + .id = -1, + .parent = &clk_usb_bus, + }, }; -struct clk s3c24xx_clkout1 = { - .name = "clkout1", - .id = -1, - .set_parent = s3c24xx_clkout_setparent, -}; - -struct clk s3c24xx_uclk = { - .name = "uclk", - .id = -1, -}; - -/* initialise the clock system */ - -int s3c24xx_register_clock(struct clk *clk) -{ - clk->owner = THIS_MODULE; - - if (clk->enable == NULL) - clk->enable = clk_null_enable; - - /* add to the list of available clocks */ - - mutex_lock(&clocks_mutex); - list_add(&clk->list, &clocks); - mutex_unlock(&clocks_mutex); - - return 0; -} - -/* initalise all the clocks */ +/* s3c2410_baseclk_add() + * + * Add all the clocks used by the s3c2410 or compatible CPUs + * such as the S3C2440 and S3C2442. + * + * We cannot use a system device as we are needed before any + * of the init-calls that initialise the devices are actually + * done. +*/ -int __init s3c24xx_setup_clocks(unsigned long xtal, - unsigned long fclk, - unsigned long hclk, - unsigned long pclk) +int __init s3c2410_baseclk_add(void) { - printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); + unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); + unsigned long clkcon = __raw_readl(S3C2410_CLKCON); + struct clk *clkp; + struct clk *xtal; + int ret; + int ptr; - /* initialise the main system clocks */ + clk_upll.enable = s3c2410_upll_enable; - clk_xtal.rate = xtal; - clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal); + if (s3c24xx_register_clock(&clk_usb_bus) < 0) + printk(KERN_ERR "failed to register usb bus clock\n"); - clk_mpll.rate = fclk; - clk_h.rate = hclk; - clk_p.rate = pclk; - clk_f.rate = fclk; + /* register clocks from clock array */ - /* assume uart clocks are correctly setup */ + clkp = init_clocks; + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { + /* ensure that we note the clock state */ - /* register our clocks */ + clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0; - if (s3c24xx_register_clock(&clk_xtal) < 0) - printk(KERN_ERR "failed to register master xtal\n"); + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + } - if (s3c24xx_register_clock(&clk_mpll) < 0) - printk(KERN_ERR "failed to register mpll clock\n"); + /* We must be careful disabling the clocks we are not intending to + * be using at boot time, as subsytems such as the LCD which do + * their own DMA requests to the bus can cause the system to lockup + * if they where in the middle of requesting bus access. + * + * Disabling the LCD clock if the LCD is active is very dangerous, + * and therefore the bootloader should be careful to not enable + * the LCD clock if it is not needed. + */ + + /* install (and disable) the clocks we do not need immediately */ + + clkp = init_clocks_disable; + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { + + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } - if (s3c24xx_register_clock(&clk_upll) < 0) - printk(KERN_ERR "failed to register upll clock\n"); + s3c2410_clkcon_enable(clkp, 0); + } - if (s3c24xx_register_clock(&clk_f) < 0) - printk(KERN_ERR "failed to register cpu fclk\n"); + /* show the clock-slow value */ - if (s3c24xx_register_clock(&clk_h) < 0) - printk(KERN_ERR "failed to register cpu hclk\n"); + xtal = clk_get(NULL, "xtal"); - if (s3c24xx_register_clock(&clk_p) < 0) - printk(KERN_ERR "failed to register cpu pclk\n"); + printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n", + print_mhz(clk_get_rate(xtal) / + ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))), + (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast", + (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", + (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); return 0; } diff --git a/arch/arm/mach-s3c2410/clock.h b/arch/arm/mach-s3c2410/clock.h deleted file mode 100644 index 7f0ea03e1d49..000000000000 --- a/arch/arm/mach-s3c2410/clock.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * linux/arch/arm/mach-s3c2410/clock.h - * - * Copyright (c) 2004-2005 Simtec Electronics - * http://www.simtec.co.uk/products/SWLINUX/ - * Written by Ben Dooks, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct clk { - struct list_head list; - struct module *owner; - struct clk *parent; - const char *name; - int id; - int usage; - unsigned long rate; - unsigned long ctrlbit; - - int (*enable)(struct clk *, int enable); - int (*set_rate)(struct clk *c, unsigned long rate); - unsigned long (*get_rate)(struct clk *c); - unsigned long (*round_rate)(struct clk *c, unsigned long rate); - int (*set_parent)(struct clk *c, struct clk *parent); -}; - -/* other clocks which may be registered by board support */ - -extern struct clk s3c24xx_dclk0; -extern struct clk s3c24xx_dclk1; -extern struct clk s3c24xx_clkout0; -extern struct clk s3c24xx_clkout1; -extern struct clk s3c24xx_uclk; - -extern struct clk clk_usb_bus; - -/* core clock support */ - -extern struct clk clk_f; -extern struct clk clk_h; -extern struct clk clk_p; -extern struct clk clk_mpll; -extern struct clk clk_upll; -extern struct clk clk_xtal; - -/* exports for arch/arm/mach-s3c2410 - * - * Please DO NOT use these outside of arch/arm/mach-s3c2410 -*/ - -extern struct mutex clocks_mutex; - -extern int s3c2410_clkcon_enable(struct clk *clk, int enable); - -extern int s3c24xx_register_clock(struct clk *clk); - -extern int s3c24xx_setup_clocks(unsigned long xtal, - unsigned long fclk, - unsigned long hclk, - unsigned long pclk); diff --git a/arch/arm/mach-s3c2410/common-smdk.c b/arch/arm/mach-s3c2410/common-smdk.c deleted file mode 100644 index a40eaa656177..000000000000 --- a/arch/arm/mach-s3c2410/common-smdk.c +++ /dev/null @@ -1,200 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/common-smdk.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * Common code for SMDK2410 and SMDK2440 boards - * - * http://www.fluff.org/ben/smdk2440/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include - -#include "common-smdk.h" -#include "devs.h" -#include "pm.h" - -/* LED devices */ - -static struct s3c24xx_led_platdata smdk_pdata_led4 = { - .gpio = S3C2410_GPF4, - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, - .name = "led4", - .def_trigger = "timer", -}; - -static struct s3c24xx_led_platdata smdk_pdata_led5 = { - .gpio = S3C2410_GPF5, - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, - .name = "led5", - .def_trigger = "nand-disk", -}; - -static struct s3c24xx_led_platdata smdk_pdata_led6 = { - .gpio = S3C2410_GPF6, - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, - .name = "led6", -}; - -static struct s3c24xx_led_platdata smdk_pdata_led7 = { - .gpio = S3C2410_GPF7, - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, - .name = "led7", -}; - -static struct platform_device smdk_led4 = { - .name = "s3c24xx_led", - .id = 0, - .dev = { - .platform_data = &smdk_pdata_led4, - }, -}; - -static struct platform_device smdk_led5 = { - .name = "s3c24xx_led", - .id = 1, - .dev = { - .platform_data = &smdk_pdata_led5, - }, -}; - -static struct platform_device smdk_led6 = { - .name = "s3c24xx_led", - .id = 2, - .dev = { - .platform_data = &smdk_pdata_led6, - }, -}; - -static struct platform_device smdk_led7 = { - .name = "s3c24xx_led", - .id = 3, - .dev = { - .platform_data = &smdk_pdata_led7, - }, -}; - -/* NAND parititon from 2.4.18-swl5 */ - -static struct mtd_partition smdk_default_nand_part[] = { - [0] = { - .name = "Boot Agent", - .size = SZ_16K, - .offset = 0, - }, - [1] = { - .name = "S3C2410 flash partition 1", - .offset = 0, - .size = SZ_2M, - }, - [2] = { - .name = "S3C2410 flash partition 2", - .offset = SZ_4M, - .size = SZ_4M, - }, - [3] = { - .name = "S3C2410 flash partition 3", - .offset = SZ_8M, - .size = SZ_2M, - }, - [4] = { - .name = "S3C2410 flash partition 4", - .offset = SZ_1M * 10, - .size = SZ_4M, - }, - [5] = { - .name = "S3C2410 flash partition 5", - .offset = SZ_1M * 14, - .size = SZ_1M * 10, - }, - [6] = { - .name = "S3C2410 flash partition 6", - .offset = SZ_1M * 24, - .size = SZ_1M * 24, - }, - [7] = { - .name = "S3C2410 flash partition 7", - .offset = SZ_1M * 48, - .size = SZ_16M, - } -}; - -static struct s3c2410_nand_set smdk_nand_sets[] = { - [0] = { - .name = "NAND", - .nr_chips = 1, - .nr_partitions = ARRAY_SIZE(smdk_default_nand_part), - .partitions = smdk_default_nand_part, - }, -}; - -/* choose a set of timings which should suit most 512Mbit - * chips and beyond. -*/ - -static struct s3c2410_platform_nand smdk_nand_info = { - .tacls = 20, - .twrph0 = 60, - .twrph1 = 20, - .nr_sets = ARRAY_SIZE(smdk_nand_sets), - .sets = smdk_nand_sets, -}; - -/* devices we initialise */ - -static struct platform_device __initdata *smdk_devs[] = { - &s3c_device_nand, - &smdk_led4, - &smdk_led5, - &smdk_led6, - &smdk_led7, -}; - -void __init smdk_machine_init(void) -{ - /* Configure the LEDs (even if we have no LED support)*/ - - s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP); - s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP); - s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP); - s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP); - - s3c2410_gpio_setpin(S3C2410_GPF4, 1); - s3c2410_gpio_setpin(S3C2410_GPF5, 1); - s3c2410_gpio_setpin(S3C2410_GPF6, 1); - s3c2410_gpio_setpin(S3C2410_GPF7, 1); - - s3c_device_nand.dev.platform_data = &smdk_nand_info; - - platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); - - s3c2410_pm_init(); -} diff --git a/arch/arm/mach-s3c2410/common-smdk.h b/arch/arm/mach-s3c2410/common-smdk.h deleted file mode 100644 index 0e3a3be330a3..000000000000 --- a/arch/arm/mach-s3c2410/common-smdk.h +++ /dev/null @@ -1,15 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/common-smdk.h - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * Common code for SMDK2410 and SMDK2440 boards - * - * http://www.fluff.org/ben/smdk2440/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -extern void smdk_machine_init(void); diff --git a/arch/arm/mach-s3c2410/cpu.c b/arch/arm/mach-s3c2410/cpu.c deleted file mode 100644 index ae1f5bb63f7a..000000000000 --- a/arch/arm/mach-s3c2410/cpu.c +++ /dev/null @@ -1,357 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/cpu.c - * - * Copyright (c) 2004-2005 Simtec Electronics - * http://www.simtec.co.uk/products/SWLINUX/ - * Ben Dooks - * - * S3C24XX CPU Support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include "cpu.h" -#include "devs.h" -#include "clock.h" -#include "s3c2400.h" -#include "s3c2410.h" -#include "s3c2412.h" -#include "s3c244x.h" -#include "s3c2440.h" -#include "s3c2442.h" - -struct cpu_table { - unsigned long idcode; - unsigned long idmask; - void (*map_io)(struct map_desc *mach_desc, int size); - void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); - void (*init_clocks)(int xtal); - int (*init)(void); - const char *name; -}; - -/* table of supported CPUs */ - -static const char name_s3c2400[] = "S3C2400"; -static const char name_s3c2410[] = "S3C2410"; -static const char name_s3c2412[] = "S3C2412"; -static const char name_s3c2440[] = "S3C2440"; -static const char name_s3c2442[] = "S3C2442"; -static const char name_s3c2410a[] = "S3C2410A"; -static const char name_s3c2440a[] = "S3C2440A"; - -static struct cpu_table cpu_ids[] __initdata = { - { - .idcode = 0x32410000, - .idmask = 0xffffffff, - .map_io = s3c2410_map_io, - .init_clocks = s3c2410_init_clocks, - .init_uarts = s3c2410_init_uarts, - .init = s3c2410_init, - .name = name_s3c2410 - }, - { - .idcode = 0x32410002, - .idmask = 0xffffffff, - .map_io = s3c2410_map_io, - .init_clocks = s3c2410_init_clocks, - .init_uarts = s3c2410_init_uarts, - .init = s3c2410_init, - .name = name_s3c2410a - }, - { - .idcode = 0x32440000, - .idmask = 0xffffffff, - .map_io = s3c244x_map_io, - .init_clocks = s3c244x_init_clocks, - .init_uarts = s3c244x_init_uarts, - .init = s3c2440_init, - .name = name_s3c2440 - }, - { - .idcode = 0x32440001, - .idmask = 0xffffffff, - .map_io = s3c244x_map_io, - .init_clocks = s3c244x_init_clocks, - .init_uarts = s3c244x_init_uarts, - .init = s3c2440_init, - .name = name_s3c2440a - }, - { - .idcode = 0x32440aaa, - .idmask = 0xffffffff, - .map_io = s3c244x_map_io, - .init_clocks = s3c244x_init_clocks, - .init_uarts = s3c244x_init_uarts, - .init = s3c2442_init, - .name = name_s3c2442 - }, - { - .idcode = 0x32412001, - .idmask = 0xffffffff, - .map_io = s3c2412_map_io, - .init_clocks = s3c2412_init_clocks, - .init_uarts = s3c2412_init_uarts, - .init = s3c2412_init, - .name = name_s3c2412, - }, - { /* a newer version of the s3c2412 */ - .idcode = 0x32412003, - .idmask = 0xffffffff, - .map_io = s3c2412_map_io, - .init_clocks = s3c2412_init_clocks, - .init_uarts = s3c2412_init_uarts, - .init = s3c2412_init, - .name = name_s3c2412, - }, - { - .idcode = 0x0, /* S3C2400 doesn't have an idcode */ - .idmask = 0xffffffff, - .map_io = s3c2400_map_io, - .init_clocks = s3c2400_init_clocks, - .init_uarts = s3c2400_init_uarts, - .init = s3c2400_init, - .name = name_s3c2400 - }, -}; - -/* minimal IO mapping */ - -static struct map_desc s3c_iodesc[] __initdata = { - IODESC_ENT(GPIO), - IODESC_ENT(IRQ), - IODESC_ENT(MEMCTRL), - IODESC_ENT(UART) -}; - - -static struct cpu_table * -s3c_lookup_cpu(unsigned long idcode) -{ - struct cpu_table *tab; - int count; - - tab = cpu_ids; - for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) { - if ((idcode & tab->idmask) == tab->idcode) - return tab; - } - - return NULL; -} - -/* board information */ - -static struct s3c24xx_board *board; - -void s3c24xx_set_board(struct s3c24xx_board *b) -{ - int i; - - board = b; - - if (b->clocks_count != 0) { - struct clk **ptr = b->clocks; - - for (i = b->clocks_count; i > 0; i--, ptr++) - s3c24xx_register_clock(*ptr); - } -} - -/* cpu information */ - -static struct cpu_table *cpu; - -static unsigned long s3c24xx_read_idcode_v5(void) -{ -#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) - return __raw_readl(S3C2412_GSTATUS1); -#else - return 1UL; /* don't look like an 2400 */ -#endif -} - -static unsigned long s3c24xx_read_idcode_v4(void) -{ -#ifndef CONFIG_CPU_S3C2400 - return __raw_readl(S3C2410_GSTATUS1); -#else - return 0UL; -#endif -} - -void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) -{ - unsigned long idcode = 0x0; - - /* initialise the io descriptors we need for initialisation */ - iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); - - if (cpu_architecture() >= CPU_ARCH_ARMv5) { - idcode = s3c24xx_read_idcode_v5(); - } else { - idcode = s3c24xx_read_idcode_v4(); - } - - cpu = s3c_lookup_cpu(idcode); - - if (cpu == NULL) { - printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); - panic("Unknown S3C24XX CPU"); - } - - printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); - - if (cpu->map_io == NULL || cpu->init == NULL) { - printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); - panic("Unsupported S3C24XX CPU"); - } - - (cpu->map_io)(mach_desc, size); -} - -/* s3c24xx_init_clocks - * - * Initialise the clock subsystem and associated information from the - * given master crystal value. - * - * xtal = 0 -> use default PLL crystal value (normally 12MHz) - * != 0 -> PLL crystal value in Hz -*/ - -void __init s3c24xx_init_clocks(int xtal) -{ - if (xtal == 0) - xtal = 12*1000*1000; - - if (cpu == NULL) - panic("s3c24xx_init_clocks: no cpu setup?\n"); - - if (cpu->init_clocks == NULL) - panic("s3c24xx_init_clocks: cpu has no clock init\n"); - else - (cpu->init_clocks)(xtal); -} - -/* uart management */ - -static int nr_uarts __initdata = 0; - -static struct s3c2410_uartcfg uart_cfgs[3]; - -/* s3c24xx_init_uartdevs - * - * copy the specified platform data and configuration into our central - * set of devices, before the data is thrown away after the init process. - * - * This also fills in the array passed to the serial driver for the - * early initialisation of the console. -*/ - -void __init s3c24xx_init_uartdevs(char *name, - struct s3c24xx_uart_resources *res, - struct s3c2410_uartcfg *cfg, int no) -{ - struct platform_device *platdev; - struct s3c2410_uartcfg *cfgptr = uart_cfgs; - struct s3c24xx_uart_resources *resp; - int uart; - - memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no); - - for (uart = 0; uart < no; uart++, cfg++, cfgptr++) { - platdev = s3c24xx_uart_src[cfgptr->hwport]; - - resp = res + cfgptr->hwport; - - s3c24xx_uart_devs[uart] = platdev; - - platdev->name = name; - platdev->resource = resp->resources; - platdev->num_resources = resp->nr_resources; - - platdev->dev.platform_data = cfgptr; - } - - nr_uarts = no; -} - -void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) -{ - if (cpu == NULL) - return; - - if (cpu->init_uarts == NULL) { - printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); - } else - (cpu->init_uarts)(cfg, no); -} - -static int __init s3c_arch_init(void) -{ - int ret; - - // do the correct init for cpu - - if (cpu == NULL) - panic("s3c_arch_init: NULL cpu\n"); - - ret = (cpu->init)(); - if (ret != 0) - return ret; - - ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); - if (ret != 0) - return ret; - - if (board != NULL) { - struct platform_device **ptr = board->devices; - int i; - - for (i = 0; i < board->devices_count; i++, ptr++) { - ret = platform_device_register(*ptr); - - if (ret) { - printk(KERN_ERR "s3c24xx: failed to add board device %s (%d) @%p\n", (*ptr)->name, ret, *ptr); - } - } - - /* mask any error, we may not need all these board - * devices */ - ret = 0; - } - - return ret; -} - -arch_initcall(s3c_arch_init); diff --git a/arch/arm/mach-s3c2410/cpu.h b/arch/arm/mach-s3c2410/cpu.h deleted file mode 100644 index be42e4032a6d..000000000000 --- a/arch/arm/mach-s3c2410/cpu.h +++ /dev/null @@ -1,69 +0,0 @@ -/* arch/arm/mach-s3c2410/cpu.h - * - * Copyright (c) 2004-2005 Simtec Electronics - * Ben Dooks - * - * Header file for S3C24XX CPU support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* todo - fix when rmk changes iodescs to use `void __iomem *` */ - -#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } - -#ifndef MHZ -#define MHZ (1000*1000) -#endif - -#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000) - -/* forward declaration */ -struct s3c24xx_uart_resources; -struct platform_device; -struct s3c2410_uartcfg; -struct map_desc; - -/* core initialisation functions */ - -extern void s3c24xx_init_irq(void); - -extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); - -extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); - -extern void s3c24xx_init_clocks(int xtal); - -extern void s3c24xx_init_uartdevs(char *name, - struct s3c24xx_uart_resources *res, - struct s3c2410_uartcfg *cfg, int no); - -/* the board structure is used at first initialsation time - * to get info such as the devices to register for this - * board. This is done because platfrom_add_devices() cannot - * be called from the map_io entry. -*/ - -struct s3c24xx_board { - struct platform_device **devices; - unsigned int devices_count; - - struct clk **clocks; - unsigned int clocks_count; -}; - -extern void s3c24xx_set_board(struct s3c24xx_board *board); - -/* timer for 2410/2440 */ - -struct sys_timer; -extern struct sys_timer s3c24xx_timer; - -/* system device classes */ - -extern struct sysdev_class s3c2410_sysclass; -extern struct sysdev_class s3c2412_sysclass; -extern struct sysdev_class s3c2440_sysclass; -extern struct sysdev_class s3c2442_sysclass; diff --git a/arch/arm/mach-s3c2410/devs.c b/arch/arm/mach-s3c2410/devs.c deleted file mode 100644 index faccde2092d2..000000000000 --- a/arch/arm/mach-s3c2410/devs.c +++ /dev/null @@ -1,585 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/devs.c - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks - * - * Base S3C24XX platform device definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "devs.h" -#include "cpu.h" - -/* Serial port registrations */ - -static struct resource s3c2410_uart0_resource[] = { - [0] = { - .start = S3C2410_PA_UART0, - .end = S3C2410_PA_UART0 + 0x3fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3CUART_RX0, - .end = IRQ_S3CUART_ERR0, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource s3c2410_uart1_resource[] = { - [0] = { - .start = S3C2410_PA_UART1, - .end = S3C2410_PA_UART1 + 0x3fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3CUART_RX1, - .end = IRQ_S3CUART_ERR1, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource s3c2410_uart2_resource[] = { - [0] = { - .start = S3C2410_PA_UART2, - .end = S3C2410_PA_UART2 + 0x3fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3CUART_RX2, - .end = IRQ_S3CUART_ERR2, - .flags = IORESOURCE_IRQ, - } -}; - -struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { - [0] = { - .resources = s3c2410_uart0_resource, - .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource), - }, - [1] = { - .resources = s3c2410_uart1_resource, - .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource), - }, - [2] = { - .resources = s3c2410_uart2_resource, - .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), - }, -}; - -/* yart devices */ - -static struct platform_device s3c24xx_uart_device0 = { - .id = 0, -}; - -static struct platform_device s3c24xx_uart_device1 = { - .id = 1, -}; - -static struct platform_device s3c24xx_uart_device2 = { - .id = 2, -}; - -struct platform_device *s3c24xx_uart_src[3] = { - &s3c24xx_uart_device0, - &s3c24xx_uart_device1, - &s3c24xx_uart_device2, -}; - -struct platform_device *s3c24xx_uart_devs[3] = { -}; - -/* USB Host Controller */ - -static struct resource s3c_usb_resource[] = { - [0] = { - .start = S3C24XX_PA_USBHOST, - .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USBH, - .end = IRQ_USBH, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 s3c_device_usb_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_usb = { - .name = "s3c2410-ohci", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_usb_resource), - .resource = s3c_usb_resource, - .dev = { - .dma_mask = &s3c_device_usb_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_usb); - -/* LCD Controller */ - -static struct resource s3c_lcd_resource[] = { - [0] = { - .start = S3C24XX_PA_LCD, - .end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_LCD, - .end = IRQ_LCD, - .flags = IORESOURCE_IRQ, - } - -}; - -static u64 s3c_device_lcd_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_lcd = { - .name = "s3c2410-lcd", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_lcd_resource), - .resource = s3c_lcd_resource, - .dev = { - .dma_mask = &s3c_device_lcd_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_lcd); - -void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) -{ - struct s3c2410fb_mach_info *npd; - - npd = kmalloc(sizeof(*npd), GFP_KERNEL); - if (npd) { - memcpy(npd, pd, sizeof(*npd)); - s3c_device_lcd.dev.platform_data = npd; - } else { - printk(KERN_ERR "no memory for LCD platform data\n"); - } -} - -/* NAND Controller */ - -static struct resource s3c_nand_resource[] = { - [0] = { - .start = S3C2410_PA_NAND, - .end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1, - .flags = IORESOURCE_MEM, - } -}; - -struct platform_device s3c_device_nand = { - .name = "s3c2410-nand", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_nand_resource), - .resource = s3c_nand_resource, -}; - -EXPORT_SYMBOL(s3c_device_nand); - -/* USB Device (Gadget)*/ - -static struct resource s3c_usbgadget_resource[] = { - [0] = { - .start = S3C24XX_PA_USBDEV, - .end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USBD, - .end = IRQ_USBD, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_usbgadget = { - .name = "s3c2410-usbgadget", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_usbgadget_resource), - .resource = s3c_usbgadget_resource, -}; - -EXPORT_SYMBOL(s3c_device_usbgadget); - -/* Watchdog */ - -static struct resource s3c_wdt_resource[] = { - [0] = { - .start = S3C24XX_PA_WATCHDOG, - .end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_WDT, - .end = IRQ_WDT, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_wdt = { - .name = "s3c2410-wdt", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_wdt_resource), - .resource = s3c_wdt_resource, -}; - -EXPORT_SYMBOL(s3c_device_wdt); - -/* I2C */ - -static struct resource s3c_i2c_resource[] = { - [0] = { - .start = S3C24XX_PA_IIC, - .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IIC, - .end = IRQ_IIC, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_i2c = { - .name = "s3c2410-i2c", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_i2c_resource), - .resource = s3c_i2c_resource, -}; - -EXPORT_SYMBOL(s3c_device_i2c); - -/* IIS */ - -static struct resource s3c_iis_resource[] = { - [0] = { - .start = S3C24XX_PA_IIS, - .end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1, - .flags = IORESOURCE_MEM, - } -}; - -static u64 s3c_device_iis_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_iis = { - .name = "s3c2410-iis", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_iis_resource), - .resource = s3c_iis_resource, - .dev = { - .dma_mask = &s3c_device_iis_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_iis); - -/* RTC */ - -static struct resource s3c_rtc_resource[] = { - [0] = { - .start = S3C24XX_PA_RTC, - .end = S3C24XX_PA_RTC + 0xff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_RTC, - .end = IRQ_RTC, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_TICK, - .end = IRQ_TICK, - .flags = IORESOURCE_IRQ - } -}; - -struct platform_device s3c_device_rtc = { - .name = "s3c2410-rtc", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_rtc_resource), - .resource = s3c_rtc_resource, -}; - -EXPORT_SYMBOL(s3c_device_rtc); - -/* ADC */ - -static struct resource s3c_adc_resource[] = { - [0] = { - .start = S3C24XX_PA_ADC, - .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TC, - .end = IRQ_TC, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_ADC, - .end = IRQ_ADC, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_adc = { - .name = "s3c2410-adc", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_adc_resource), - .resource = s3c_adc_resource, -}; - -/* SDI */ - -static struct resource s3c_sdi_resource[] = { - [0] = { - .start = S3C2410_PA_SDI, - .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SDI, - .end = IRQ_SDI, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_sdi = { - .name = "s3c2410-sdi", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_sdi_resource), - .resource = s3c_sdi_resource, -}; - -EXPORT_SYMBOL(s3c_device_sdi); - -/* SPI (0) */ - -static struct resource s3c_spi0_resource[] = { - [0] = { - .start = S3C24XX_PA_SPI, - .end = S3C24XX_PA_SPI + 0x1f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SPI0, - .end = IRQ_SPI0, - .flags = IORESOURCE_IRQ, - } - -}; - -static u64 s3c_device_spi0_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_spi0 = { - .name = "s3c2410-spi", - .id = 0, - .num_resources = ARRAY_SIZE(s3c_spi0_resource), - .resource = s3c_spi0_resource, - .dev = { - .dma_mask = &s3c_device_spi0_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_spi0); - -/* SPI (1) */ - -static struct resource s3c_spi1_resource[] = { - [0] = { - .start = S3C24XX_PA_SPI + 0x20, - .end = S3C24XX_PA_SPI + 0x20 + 0x1f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SPI1, - .end = IRQ_SPI1, - .flags = IORESOURCE_IRQ, - } - -}; - -static u64 s3c_device_spi1_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_spi1 = { - .name = "s3c2410-spi", - .id = 1, - .num_resources = ARRAY_SIZE(s3c_spi1_resource), - .resource = s3c_spi1_resource, - .dev = { - .dma_mask = &s3c_device_spi1_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_spi1); - -/* pwm timer blocks */ - -static struct resource s3c_timer0_resource[] = { - [0] = { - .start = S3C24XX_PA_TIMER + 0x0C, - .end = S3C24XX_PA_TIMER + 0x0C + 0xB, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TIMER0, - .end = IRQ_TIMER0, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_timer0 = { - .name = "s3c2410-timer", - .id = 0, - .num_resources = ARRAY_SIZE(s3c_timer0_resource), - .resource = s3c_timer0_resource, -}; - -EXPORT_SYMBOL(s3c_device_timer0); - -/* timer 1 */ - -static struct resource s3c_timer1_resource[] = { - [0] = { - .start = S3C24XX_PA_TIMER + 0x18, - .end = S3C24XX_PA_TIMER + 0x23, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TIMER1, - .end = IRQ_TIMER1, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_timer1 = { - .name = "s3c2410-timer", - .id = 1, - .num_resources = ARRAY_SIZE(s3c_timer1_resource), - .resource = s3c_timer1_resource, -}; - -EXPORT_SYMBOL(s3c_device_timer1); - -/* timer 2 */ - -static struct resource s3c_timer2_resource[] = { - [0] = { - .start = S3C24XX_PA_TIMER + 0x24, - .end = S3C24XX_PA_TIMER + 0x2F, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TIMER2, - .end = IRQ_TIMER2, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_timer2 = { - .name = "s3c2410-timer", - .id = 2, - .num_resources = ARRAY_SIZE(s3c_timer2_resource), - .resource = s3c_timer2_resource, -}; - -EXPORT_SYMBOL(s3c_device_timer2); - -/* timer 3 */ - -static struct resource s3c_timer3_resource[] = { - [0] = { - .start = S3C24XX_PA_TIMER + 0x30, - .end = S3C24XX_PA_TIMER + 0x3B, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TIMER3, - .end = IRQ_TIMER3, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_timer3 = { - .name = "s3c2410-timer", - .id = 3, - .num_resources = ARRAY_SIZE(s3c_timer3_resource), - .resource = s3c_timer3_resource, -}; - -EXPORT_SYMBOL(s3c_device_timer3); - -#ifdef CONFIG_CPU_S3C2440 - -/* Camif Controller */ - -static struct resource s3c_camif_resource[] = { - [0] = { - .start = S3C2440_PA_CAMIF, - .end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CAM, - .end = IRQ_CAM, - .flags = IORESOURCE_IRQ, - } - -}; - -static u64 s3c_device_camif_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_camif = { - .name = "s3c2440-camif", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_camif_resource), - .resource = s3c_camif_resource, - .dev = { - .dma_mask = &s3c_device_camif_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_camif); - -#endif // CONFIG_CPU_S32440 diff --git a/arch/arm/mach-s3c2410/devs.h b/arch/arm/mach-s3c2410/devs.h deleted file mode 100644 index 14fb0bade716..000000000000 --- a/arch/arm/mach-s3c2410/devs.h +++ /dev/null @@ -1,51 +0,0 @@ -/* arch/arm/mach-s3c2410/devs.h - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks - * - * Header file for s3c2410 standard platform devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ -#include - -struct s3c24xx_uart_resources { - struct resource *resources; - unsigned long nr_resources; -}; - -extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; - -extern struct platform_device *s3c24xx_uart_devs[]; -extern struct platform_device *s3c24xx_uart_src[]; - -extern struct platform_device s3c_device_usb; -extern struct platform_device s3c_device_lcd; -extern struct platform_device s3c_device_wdt; -extern struct platform_device s3c_device_i2c; -extern struct platform_device s3c_device_iis; -extern struct platform_device s3c_device_rtc; -extern struct platform_device s3c_device_adc; -extern struct platform_device s3c_device_sdi; - -extern struct platform_device s3c_device_spi0; -extern struct platform_device s3c_device_spi1; - -extern struct platform_device s3c_device_nand; - -extern struct platform_device s3c_device_timer0; -extern struct platform_device s3c_device_timer1; -extern struct platform_device s3c_device_timer2; -extern struct platform_device s3c_device_timer3; - -extern struct platform_device s3c_device_usbgadget; - -/* s3c2440 specific devices */ - -#ifdef CONFIG_CPU_S3C2440 - -extern struct platform_device s3c_device_camif; - -#endif diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index fa860e716b4f..22c613600caa 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c @@ -1,9 +1,9 @@ /* linux/arch/arm/mach-s3c2410/dma.c * - * Copyright (c) 2003-2005,2006 Simtec Electronics + * Copyright (c) 2006 Simtec Electronics * Ben Dooks * - * S3C2410 DMA core + * S3C2410 DMA selection * * http://armlinux.simtec.co.uk/ * @@ -12,1430 +12,150 @@ * published by the Free Software Foundation. */ - -#ifdef CONFIG_S3C2410_DMA_DEBUG -#define DEBUG -#endif - -#include +#include #include -#include -#include -#include #include -#include -#include -#include +#include -#include -#include -#include -#include #include - -#include -#include - -#include "dma.h" - -/* io map for dma */ -static void __iomem *dma_base; -static struct kmem_cache *dma_kmem; - -struct s3c24xx_dma_selection dma_sel; - -/* dma channel state information */ -struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; - -/* debugging functions */ - -#define BUF_MAGIC (0xcafebabe) - -#define dmawarn(fmt...) printk(KERN_DEBUG fmt) - -#define dma_regaddr(chan, reg) ((chan)->regs + (reg)) - -#if 1 -#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg)) -#else -static inline void -dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val) -{ - pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg); - writel(val, dma_regaddr(chan, reg)); -} -#endif - -#define dma_rdreg(chan, reg) readl((chan)->regs + (reg)) - -/* captured register state for debug */ - -struct s3c2410_dma_regstate { - unsigned long dcsrc; - unsigned long disrc; - unsigned long dstat; - unsigned long dcon; - unsigned long dmsktrig; +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { + [DMACH_XD0] = { + .name = "xdreq0", + .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID, + }, + [DMACH_XD1] = { + .name = "xdreq1", + .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID, + }, + [DMACH_SDI] = { + .name = "sdi", + .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID, + .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, + .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, + .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, + }, + [DMACH_SPI0] = { + .name = "spi0", + .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, + .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, + }, + [DMACH_SPI1] = { + .name = "spi1", + .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, + .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, + }, + [DMACH_UART0] = { + .name = "uart0", + .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, + }, + [DMACH_UART1] = { + .name = "uart1", + .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, + }, + [DMACH_UART2] = { + .name = "uart2", + .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, + }, + [DMACH_TIMER] = { + .name = "timer", + .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID, + .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID, + .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID, + }, + [DMACH_I2S_IN] = { + .name = "i2s-sdi", + .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, + .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, + .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, + }, + [DMACH_I2S_OUT] = { + .name = "i2s-sdo", + .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, + }, + [DMACH_USB_EP1] = { + .name = "usb-ep1", + .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID, + }, + [DMACH_USB_EP2] = { + .name = "usb-ep2", + .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID, + }, + [DMACH_USB_EP3] = { + .name = "usb-ep3", + .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID, + }, + [DMACH_USB_EP4] = { + .name = "usb-ep4", + .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID, + }, }; -#ifdef CONFIG_S3C2410_DMA_DEBUG - -/* dmadbg_showregs - * - * simple debug routine to print the current state of the dma registers -*/ - -static void -dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs) -{ - regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC); - regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC); - regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT); - regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON); - regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); -} - -static void -dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan, - struct s3c2410_dma_regstate *regs) -{ - printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n", - chan->number, fname, line, - regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig, - regs->dcon); -} - -static void -dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan) -{ - struct s3c2410_dma_regstate state; - - dmadbg_capture(chan, &state); - - printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n", - chan->number, fname, line, chan->load_state, - chan->curr, chan->next, chan->end); - - dmadbg_dumpregs(fname, line, chan, &state); -} - -static void -dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan) -{ - struct s3c2410_dma_regstate state; - - dmadbg_capture(chan, &state); - dmadbg_dumpregs(fname, line, chan, &state); -} - -#define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan)) -#define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan)) -#else -#define dbg_showregs(chan) do { } while(0) -#define dbg_showchan(chan) do { } while(0) -#endif /* CONFIG_S3C2410_DMA_DEBUG */ - -static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX]; - -/* lookup_dma_channel - * - * change the dma channel number given into a real dma channel id -*/ - -static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel) -{ - if (channel & DMACH_LOW_LEVEL) - return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL]; - else - return dma_chan_map[channel]; -} - -/* s3c2410_dma_stats_timeout - * - * Update DMA stats from timeout info -*/ - -static void -s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val) +static void s3c2410_dma_select(struct s3c2410_dma_chan *chan, + struct s3c24xx_dma_map *map) { - if (stats == NULL) - return; - - if (val > stats->timeout_longest) - stats->timeout_longest = val; - if (val < stats->timeout_shortest) - stats->timeout_shortest = val; - - stats->timeout_avg += val; + chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID; } -/* s3c2410_dma_waitforload - * - * wait for the DMA engine to load a buffer, and update the state accordingly -*/ - -static int -s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line) -{ - int timeout = chan->load_timeout; - int took; - - if (chan->load_state != S3C2410_DMALOAD_1LOADED) { - printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line); - return 0; - } - - if (chan->stats != NULL) - chan->stats->loads++; - - while (--timeout > 0) { - if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) { - took = chan->load_timeout - timeout; - - s3c2410_dma_stats_timeout(chan->stats, took); - - switch (chan->load_state) { - case S3C2410_DMALOAD_1LOADED: - chan->load_state = S3C2410_DMALOAD_1RUNNING; - break; - - default: - printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state); - } - - return 1; - } - } - - if (chan->stats != NULL) { - chan->stats->timeout_failed++; - } - - return 0; -} - - - -/* s3c2410_dma_loadbuffer - * - * load a buffer, and update the channel state -*/ - -static inline int -s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan, - struct s3c2410_dma_buf *buf) -{ - unsigned long reload; - - pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n", - buf, (unsigned long)buf->data, buf->size); - - if (buf == NULL) { - dmawarn("buffer is NULL\n"); - return -EINVAL; - } - - /* check the state of the channel before we do anything */ - - if (chan->load_state == S3C2410_DMALOAD_1LOADED) { - dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n"); - } - - if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) { - dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n"); - } - - /* it would seem sensible if we are the last buffer to not bother - * with the auto-reload bit, so that the DMA engine will not try - * and load another transfer after this one has finished... - */ - if (chan->load_state == S3C2410_DMALOAD_NONE) { - pr_debug("load_state is none, checking for noreload (next=%p)\n", - buf->next); - reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0; - } else { - //pr_debug("load_state is %d => autoreload\n", chan->load_state); - reload = S3C2410_DCON_AUTORELOAD; - } - - if ((buf->data & 0xf0000000) != 0x30000000) { - dmawarn("dmaload: buffer is %p\n", (void *)buf->data); - } - - writel(buf->data, chan->addr_reg); - - dma_wrreg(chan, S3C2410_DMA_DCON, - chan->dcon | reload | (buf->size/chan->xfer_unit)); - - chan->next = buf->next; - - /* update the state of the channel */ - - switch (chan->load_state) { - case S3C2410_DMALOAD_NONE: - chan->load_state = S3C2410_DMALOAD_1LOADED; - break; - - case S3C2410_DMALOAD_1RUNNING: - chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING; - break; - - default: - dmawarn("dmaload: unknown state %d in loadbuffer\n", - chan->load_state); - break; - } - - return 0; -} - -/* s3c2410_dma_call_op - * - * small routine to call the op routine with the given op if it has been - * registered -*/ - -static void -s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op) -{ - if (chan->op_fn != NULL) { - (chan->op_fn)(chan, op); - } -} - -/* s3c2410_dma_buffdone - * - * small wrapper to check if callback routine needs to be called, and - * if so, call it -*/ - -static inline void -s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf, - enum s3c2410_dma_buffresult result) -{ -#if 0 - pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n", - chan->callback_fn, buf, buf->id, buf->size, result); -#endif - - if (chan->callback_fn != NULL) { - (chan->callback_fn)(chan, buf->id, buf->size, result); - } -} - -/* s3c2410_dma_start - * - * start a dma channel going -*/ - -static int s3c2410_dma_start(struct s3c2410_dma_chan *chan) -{ - unsigned long tmp; - unsigned long flags; - - pr_debug("s3c2410_start_dma: channel=%d\n", chan->number); - - local_irq_save(flags); - - if (chan->state == S3C2410_DMA_RUNNING) { - pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state); - local_irq_restore(flags); - return 0; - } - - chan->state = S3C2410_DMA_RUNNING; - - /* check wether there is anything to load, and if not, see - * if we can find anything to load - */ - - if (chan->load_state == S3C2410_DMALOAD_NONE) { - if (chan->next == NULL) { - printk(KERN_ERR "dma%d: channel has nothing loaded\n", - chan->number); - chan->state = S3C2410_DMA_IDLE; - local_irq_restore(flags); - return -EINVAL; - } - - s3c2410_dma_loadbuffer(chan, chan->next); - } - - dbg_showchan(chan); - - /* enable the channel */ - - if (!chan->irq_enabled) { - enable_irq(chan->irq); - chan->irq_enabled = 1; - } - - /* start the channel going */ - - tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); - tmp &= ~S3C2410_DMASKTRIG_STOP; - tmp |= S3C2410_DMASKTRIG_ON; - dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); - - pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp); - -#if 0 - /* the dma buffer loads should take care of clearing the AUTO - * reloading feature */ - tmp = dma_rdreg(chan, S3C2410_DMA_DCON); - tmp &= ~S3C2410_DCON_NORELOAD; - dma_wrreg(chan, S3C2410_DMA_DCON, tmp); -#endif - - s3c2410_dma_call_op(chan, S3C2410_DMAOP_START); - - dbg_showchan(chan); - - /* if we've only loaded one buffer onto the channel, then chec - * to see if we have another, and if so, try and load it so when - * the first buffer is finished, the new one will be loaded onto - * the channel */ - - if (chan->next != NULL) { - if (chan->load_state == S3C2410_DMALOAD_1LOADED) { - - if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { - pr_debug("%s: buff not yet loaded, no more todo\n", - __FUNCTION__); - } else { - chan->load_state = S3C2410_DMALOAD_1RUNNING; - s3c2410_dma_loadbuffer(chan, chan->next); - } - - } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { - s3c2410_dma_loadbuffer(chan, chan->next); - } - } - - - local_irq_restore(flags); - - return 0; -} - -/* s3c2410_dma_canload - * - * work out if we can queue another buffer into the DMA engine -*/ - -static int -s3c2410_dma_canload(struct s3c2410_dma_chan *chan) -{ - if (chan->load_state == S3C2410_DMALOAD_NONE || - chan->load_state == S3C2410_DMALOAD_1RUNNING) - return 1; - - return 0; -} - -/* s3c2410_dma_enqueue - * - * queue an given buffer for dma transfer. - * - * id the device driver's id information for this buffer - * data the physical address of the buffer data - * size the size of the buffer in bytes - * - * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART - * is checked, and if set, the channel is started. If this flag isn't set, - * then an error will be returned. - * - * It is possible to queue more than one DMA buffer onto a channel at - * once, and the code will deal with the re-loading of the next buffer - * when necessary. -*/ - -int s3c2410_dma_enqueue(unsigned int channel, void *id, - dma_addr_t data, int size) -{ - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - struct s3c2410_dma_buf *buf; - unsigned long flags; - - if (chan == NULL) - return -EINVAL; - - pr_debug("%s: id=%p, data=%08x, size=%d\n", - __FUNCTION__, id, (unsigned int)data, size); - - buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); - if (buf == NULL) { - pr_debug("%s: out of memory (%ld alloc)\n", - __FUNCTION__, (long)sizeof(*buf)); - return -ENOMEM; - } - - //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); - //dbg_showchan(chan); - - buf->next = NULL; - buf->data = buf->ptr = data; - buf->size = size; - buf->id = id; - buf->magic = BUF_MAGIC; - - local_irq_save(flags); - - if (chan->curr == NULL) { - /* we've got nothing loaded... */ - pr_debug("%s: buffer %p queued onto empty channel\n", - __FUNCTION__, buf); - - chan->curr = buf; - chan->end = buf; - chan->next = NULL; - } else { - pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n", - chan->number, __FUNCTION__, buf); - - if (chan->end == NULL) - pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n", - chan->number, __FUNCTION__, chan); - - chan->end->next = buf; - chan->end = buf; - } - - /* if necessary, update the next buffer field */ - if (chan->next == NULL) - chan->next = buf; - - /* check to see if we can load a buffer */ - if (chan->state == S3C2410_DMA_RUNNING) { - if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) { - if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { - printk(KERN_ERR "dma%d: loadbuffer:" - "timeout loading buffer\n", - chan->number); - dbg_showchan(chan); - local_irq_restore(flags); - return -EINVAL; - } - } - - while (s3c2410_dma_canload(chan) && chan->next != NULL) { - s3c2410_dma_loadbuffer(chan, chan->next); - } - } else if (chan->state == S3C2410_DMA_IDLE) { - if (chan->flags & S3C2410_DMAF_AUTOSTART) { - s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START); - } - } - - local_irq_restore(flags); - return 0; -} - -EXPORT_SYMBOL(s3c2410_dma_enqueue); - -static inline void -s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf) -{ - int magicok = (buf->magic == BUF_MAGIC); - - buf->magic = -1; - - if (magicok) { - kmem_cache_free(dma_kmem, buf); - } else { - printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf); - } -} - -/* s3c2410_dma_lastxfer - * - * called when the system is out of buffers, to ensure that the channel - * is prepared for shutdown. -*/ - -static inline void -s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan) -{ -#if 0 - pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n", - chan->number, chan->load_state); -#endif - - switch (chan->load_state) { - case S3C2410_DMALOAD_NONE: - break; - - case S3C2410_DMALOAD_1LOADED: - if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { - /* flag error? */ - printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", - chan->number, __FUNCTION__); - return; - } - break; - - case S3C2410_DMALOAD_1LOADED_1RUNNING: - /* I belive in this case we do not have anything to do - * until the next buffer comes along, and we turn off the - * reload */ - return; - - default: - pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n", - chan->number, chan->load_state); - return; - - } - - /* hopefully this'll shut the damned thing up after the transfer... */ - dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD); -} - - -#define dmadbg2(x...) - -static irqreturn_t -s3c2410_dma_irq(int irq, void *devpw) -{ - struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw; - struct s3c2410_dma_buf *buf; - - buf = chan->curr; - - dbg_showchan(chan); - - /* modify the channel state */ - - switch (chan->load_state) { - case S3C2410_DMALOAD_1RUNNING: - /* TODO - if we are running only one buffer, we probably - * want to reload here, and then worry about the buffer - * callback */ - - chan->load_state = S3C2410_DMALOAD_NONE; - break; - - case S3C2410_DMALOAD_1LOADED: - /* iirc, we should go back to NONE loaded here, we - * had a buffer, and it was never verified as being - * loaded. - */ - - chan->load_state = S3C2410_DMALOAD_NONE; - break; - - case S3C2410_DMALOAD_1LOADED_1RUNNING: - /* we'll worry about checking to see if another buffer is - * ready after we've called back the owner. This should - * ensure we do not wait around too long for the DMA - * engine to start the next transfer - */ - - chan->load_state = S3C2410_DMALOAD_1LOADED; - break; - - case S3C2410_DMALOAD_NONE: - printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n", - chan->number); - break; - - default: - printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n", - chan->number, chan->load_state); - break; - } - - if (buf != NULL) { - /* update the chain to make sure that if we load any more - * buffers when we call the callback function, things should - * work properly */ - - chan->curr = buf->next; - buf->next = NULL; - - if (buf->magic != BUF_MAGIC) { - printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n", - chan->number, __FUNCTION__, buf); - return IRQ_HANDLED; - } - - s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK); - - /* free resouces */ - s3c2410_dma_freebuf(buf); - } else { - } - - /* only reload if the channel is still running... our buffer done - * routine may have altered the state by requesting the dma channel - * to stop or shutdown... */ - - /* todo: check that when the channel is shut-down from inside this - * function, we cope with unsetting reload, etc */ - - if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) { - unsigned long flags; - - switch (chan->load_state) { - case S3C2410_DMALOAD_1RUNNING: - /* don't need to do anything for this state */ - break; - - case S3C2410_DMALOAD_NONE: - /* can load buffer immediately */ - break; - - case S3C2410_DMALOAD_1LOADED: - if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { - /* flag error? */ - printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", - chan->number, __FUNCTION__); - return IRQ_HANDLED; - } - - break; - - case S3C2410_DMALOAD_1LOADED_1RUNNING: - goto no_load; - - default: - printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n", - chan->number, chan->load_state); - return IRQ_HANDLED; - } - - local_irq_save(flags); - s3c2410_dma_loadbuffer(chan, chan->next); - local_irq_restore(flags); - } else { - s3c2410_dma_lastxfer(chan); - - /* see if we can stop this channel.. */ - if (chan->load_state == S3C2410_DMALOAD_NONE) { - pr_debug("dma%d: end of transfer, stopping channel (%ld)\n", - chan->number, jiffies); - s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL, - S3C2410_DMAOP_STOP); - } - } - - no_load: - return IRQ_HANDLED; -} - -static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel); - -/* s3c2410_request_dma - * - * get control of an dma channel -*/ - -int s3c2410_dma_request(unsigned int channel, - struct s3c2410_dma_client *client, - void *dev) -{ - struct s3c2410_dma_chan *chan; - unsigned long flags; - int err; - - pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n", - channel, client->name, dev); - - local_irq_save(flags); - - chan = s3c2410_dma_map_channel(channel); - if (chan == NULL) { - local_irq_restore(flags); - return -EBUSY; - } - - dbg_showchan(chan); - - chan->client = client; - chan->in_use = 1; - - if (!chan->irq_claimed) { - pr_debug("dma%d: %s : requesting irq %d\n", - channel, __FUNCTION__, chan->irq); - - chan->irq_claimed = 1; - local_irq_restore(flags); - - err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED, - client->name, (void *)chan); - - local_irq_save(flags); - - if (err) { - chan->in_use = 0; - chan->irq_claimed = 0; - local_irq_restore(flags); - - printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n", - client->name, chan->irq, chan->number); - return err; - } - - chan->irq_enabled = 1; - } - - local_irq_restore(flags); - - /* need to setup */ - - pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan); - - return 0; -} - -EXPORT_SYMBOL(s3c2410_dma_request); - -/* s3c2410_dma_free - * - * release the given channel back to the system, will stop and flush - * any outstanding transfers, and ensure the channel is ready for the - * next claimant. - * - * Note, although a warning is currently printed if the freeing client - * info is not the same as the registrant's client info, the free is still - * allowed to go through. -*/ +static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = { + .select = s3c2410_dma_select, + .dcon_mask = 7 << 24, + .map = s3c2410_dma_mappings, + .map_size = ARRAY_SIZE(s3c2410_dma_mappings), +}; -int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) +static int s3c2410_dma_add(struct sys_device *sysdev) { - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - unsigned long flags; - - if (chan == NULL) - return -EINVAL; - - local_irq_save(flags); - - if (chan->client != client) { - printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n", - channel, chan->client, client); - } - - /* sort out stopping and freeing the channel */ - - if (chan->state != S3C2410_DMA_IDLE) { - pr_debug("%s: need to stop dma channel %p\n", - __FUNCTION__, chan); - - /* possibly flush the channel */ - s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP); - } - - chan->client = NULL; - chan->in_use = 0; - - if (chan->irq_claimed) - free_irq(chan->irq, (void *)chan); - - chan->irq_claimed = 0; - - if (!(channel & DMACH_LOW_LEVEL)) - dma_chan_map[channel] = NULL; - - local_irq_restore(flags); - - return 0; + return s3c24xx_dma_init_map(&s3c2410_dma_sel); } -EXPORT_SYMBOL(s3c2410_dma_free); - -static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan) -{ - unsigned long flags; - unsigned long tmp; - - pr_debug("%s:\n", __FUNCTION__); - - dbg_showchan(chan); - - local_irq_save(flags); - - s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP); - - tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); - tmp |= S3C2410_DMASKTRIG_STOP; - //tmp &= ~S3C2410_DMASKTRIG_ON; - dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); - -#if 0 - /* should also clear interrupts, according to WinCE BSP */ - tmp = dma_rdreg(chan, S3C2410_DMA_DCON); - tmp |= S3C2410_DCON_NORELOAD; - dma_wrreg(chan, S3C2410_DMA_DCON, tmp); -#endif - - /* should stop do this, or should we wait for flush? */ - chan->state = S3C2410_DMA_IDLE; - chan->load_state = S3C2410_DMALOAD_NONE; - - local_irq_restore(flags); - - return 0; -} +#if defined(CONFIG_CPU_S3C2410) +static struct sysdev_driver s3c2410_dma_driver = { + .add = s3c2410_dma_add, +}; -void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan) +static int __init s3c2410_dma_init(void) { - unsigned long tmp; - unsigned int timeout = 0x10000; - - while (timeout-- > 0) { - tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); - - if (!(tmp & S3C2410_DMASKTRIG_ON)) - return; - } - - pr_debug("dma%d: failed to stop?\n", chan->number); + return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver); } - -/* s3c2410_dma_flush - * - * stop the channel, and remove all current and pending transfers -*/ - -static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan) -{ - struct s3c2410_dma_buf *buf, *next; - unsigned long flags; - - pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number); - - dbg_showchan(chan); - - local_irq_save(flags); - - if (chan->state != S3C2410_DMA_IDLE) { - pr_debug("%s: stopping channel...\n", __FUNCTION__ ); - s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP); - } - - buf = chan->curr; - if (buf == NULL) - buf = chan->next; - - chan->curr = chan->next = chan->end = NULL; - - if (buf != NULL) { - for ( ; buf != NULL; buf = next) { - next = buf->next; - - pr_debug("%s: free buffer %p, next %p\n", - __FUNCTION__, buf, buf->next); - - s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT); - s3c2410_dma_freebuf(buf); - } - } - - dbg_showregs(chan); - - s3c2410_dma_waitforstop(chan); - -#if 0 - /* should also clear interrupts, according to WinCE BSP */ - { - unsigned long tmp; - - tmp = dma_rdreg(chan, S3C2410_DMA_DCON); - tmp |= S3C2410_DCON_NORELOAD; - dma_wrreg(chan, S3C2410_DMA_DCON, tmp); - } +arch_initcall(s3c2410_dma_init); #endif - dbg_showregs(chan); - - local_irq_restore(flags); - - return 0; -} - -int -s3c2410_dma_started(struct s3c2410_dma_chan *chan) -{ - unsigned long flags; - - local_irq_save(flags); - - dbg_showchan(chan); - - /* if we've only loaded one buffer onto the channel, then chec - * to see if we have another, and if so, try and load it so when - * the first buffer is finished, the new one will be loaded onto - * the channel */ - - if (chan->next != NULL) { - if (chan->load_state == S3C2410_DMALOAD_1LOADED) { - - if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { - pr_debug("%s: buff not yet loaded, no more todo\n", - __FUNCTION__); - } else { - chan->load_state = S3C2410_DMALOAD_1RUNNING; - s3c2410_dma_loadbuffer(chan, chan->next); - } - - } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { - s3c2410_dma_loadbuffer(chan, chan->next); - } - } - - - local_irq_restore(flags); - - return 0; - -} - -int -s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op) -{ - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - - if (chan == NULL) - return -EINVAL; - - switch (op) { - case S3C2410_DMAOP_START: - return s3c2410_dma_start(chan); - - case S3C2410_DMAOP_STOP: - return s3c2410_dma_dostop(chan); - - case S3C2410_DMAOP_PAUSE: - case S3C2410_DMAOP_RESUME: - return -ENOENT; - - case S3C2410_DMAOP_FLUSH: - return s3c2410_dma_flush(chan); - - case S3C2410_DMAOP_STARTED: - return s3c2410_dma_started(chan); - - case S3C2410_DMAOP_TIMEOUT: - return 0; - - } - - return -ENOENT; /* unknown, don't bother */ -} - -EXPORT_SYMBOL(s3c2410_dma_ctrl); - -/* DMA configuration for each channel - * - * DISRCC -> source of the DMA (AHB,APB) - * DISRC -> source address of the DMA - * DIDSTC -> destination of the DMA (AHB,APD) - * DIDST -> destination address of the DMA -*/ - -/* s3c2410_dma_config - * - * xfersize: size of unit in bytes (1,2,4) - * dcon: base value of the DCONx register -*/ - -int s3c2410_dma_config(dmach_t channel, - int xferunit, - int dcon) -{ - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - - pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", - __FUNCTION__, channel, xferunit, dcon); - - if (chan == NULL) - return -EINVAL; - - pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon); - - dcon |= chan->dcon & dma_sel.dcon_mask; - - pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon); - - switch (xferunit) { - case 1: - dcon |= S3C2410_DCON_BYTE; - break; - - case 2: - dcon |= S3C2410_DCON_HALFWORD; - break; - - case 4: - dcon |= S3C2410_DCON_WORD; - break; - - default: - pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit); - return -EINVAL; - } - - dcon |= S3C2410_DCON_HWTRIG; - dcon |= S3C2410_DCON_INTREQ; - - pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon); - - chan->dcon = dcon; - chan->xfer_unit = xferunit; - - return 0; -} - -EXPORT_SYMBOL(s3c2410_dma_config); - -int s3c2410_dma_setflags(dmach_t channel, unsigned int flags) -{ - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - - if (chan == NULL) - return -EINVAL; - - pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags); - - chan->flags = flags; - - return 0; -} - -EXPORT_SYMBOL(s3c2410_dma_setflags); - - -/* do we need to protect the settings of the fields from - * irq? -*/ - -int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) -{ - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - - if (chan == NULL) - return -EINVAL; - - pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn); - - chan->op_fn = rtn; - - return 0; -} - -EXPORT_SYMBOL(s3c2410_dma_set_opfn); - -int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn) -{ - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - - if (chan == NULL) - return -EINVAL; - - pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn); - - chan->callback_fn = rtn; - - return 0; -} - -EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn); - -/* s3c2410_dma_devconfig - * - * configure the dma source/destination hardware type and address - * - * source: S3C2410_DMASRC_HW: source is hardware - * S3C2410_DMASRC_MEM: source is memory - * - * hwcfg: the value for xxxSTCn register, - * bit 0: 0=increment pointer, 1=leave pointer - * bit 1: 0=soucre is AHB, 1=soucre is APB - * - * devaddr: physical address of the source -*/ - -int s3c2410_dma_devconfig(int channel, - enum s3c2410_dmasrc source, - int hwcfg, - unsigned long devaddr) -{ - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - - if (chan == NULL) - return -EINVAL; - - pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n", - __FUNCTION__, (int)source, hwcfg, devaddr); - - chan->source = source; - chan->dev_addr = devaddr; - - switch (source) { - case S3C2410_DMASRC_HW: - /* source is hardware */ - pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n", - __FUNCTION__, devaddr, hwcfg); - dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3); - dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr); - dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0)); - - chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST); - return 0; - - case S3C2410_DMASRC_MEM: - /* source is memory */ - pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n", - __FUNCTION__, devaddr, hwcfg); - dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0)); - dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr); - dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3); - - chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC); - return 0; - } - - printk(KERN_ERR "dma%d: invalid source type (%d)\n", channel, source); - return -EINVAL; -} - -EXPORT_SYMBOL(s3c2410_dma_devconfig); - -/* s3c2410_dma_getposition - * - * returns the current transfer points for the dma source and destination -*/ - -int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst) -{ - struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); - - if (chan == NULL) - return -EINVAL; - - if (src != NULL) - *src = dma_rdreg(chan, S3C2410_DMA_DCSRC); - - if (dst != NULL) - *dst = dma_rdreg(chan, S3C2410_DMA_DCDST); - - return 0; -} - -EXPORT_SYMBOL(s3c2410_dma_getposition); - - -/* system device class */ - -#ifdef CONFIG_PM - -static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state) -{ - struct s3c2410_dma_chan *cp = container_of(dev, struct s3c2410_dma_chan, dev); - - printk(KERN_DEBUG "suspending dma channel %d\n", cp->number); - - if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) { - /* the dma channel is still working, which is probably - * a bad thing to do over suspend/resume. We stop the - * channel and assume that the client is either going to - * retry after resume, or that it is broken. - */ - - printk(KERN_INFO "dma: stopping channel %d due to suspend\n", - cp->number); - - s3c2410_dma_dostop(cp); - } - - return 0; -} - -static int s3c2410_dma_resume(struct sys_device *dev) -{ - return 0; -} - -#else -#define s3c2410_dma_suspend NULL -#define s3c2410_dma_resume NULL -#endif /* CONFIG_PM */ - -struct sysdev_class dma_sysclass = { - set_kset_name("s3c24xx-dma"), - .suspend = s3c2410_dma_suspend, - .resume = s3c2410_dma_resume, +#if defined(CONFIG_CPU_S3C2442) +/* S3C2442 DMA contains the same selection table as the S3C2410 */ +static struct sysdev_driver s3c2442_dma_driver = { + .add = s3c2410_dma_add, }; -/* kmem cache implementation */ - -static void s3c2410_dma_cache_ctor(void *p, struct kmem_cache *c, unsigned long f) -{ - memset(p, 0, sizeof(struct s3c2410_dma_buf)); -} - -/* initialisation code */ - -static int __init s3c2410_init_dma(void) -{ - struct s3c2410_dma_chan *cp; - int channel; - int ret; - - printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n"); - - dma_base = ioremap(S3C24XX_PA_DMA, 0x200); - if (dma_base == NULL) { - printk(KERN_ERR "dma failed to remap register block\n"); - return -ENOMEM; - } - - printk("Registering sysclass\n"); - - ret = sysdev_class_register(&dma_sysclass); - if (ret != 0) { - printk(KERN_ERR "dma sysclass registration failed\n"); - goto err; - } - - dma_kmem = kmem_cache_create("dma_desc", sizeof(struct s3c2410_dma_buf), 0, - SLAB_HWCACHE_ALIGN, - s3c2410_dma_cache_ctor, NULL); - - if (dma_kmem == NULL) { - printk(KERN_ERR "dma failed to make kmem cache\n"); - ret = -ENOMEM; - goto err; - } - - for (channel = 0; channel < S3C2410_DMA_CHANNELS; channel++) { - cp = &s3c2410_chans[channel]; - - memset(cp, 0, sizeof(struct s3c2410_dma_chan)); - - /* dma channel irqs are in order.. */ - cp->number = channel; - cp->irq = channel + IRQ_DMA0; - cp->regs = dma_base + (channel*0x40); - - /* point current stats somewhere */ - cp->stats = &cp->stats_store; - cp->stats_store.timeout_shortest = LONG_MAX; - - /* basic channel configuration */ - - cp->load_timeout = 1<<18; - - /* register system device */ - - cp->dev.cls = &dma_sysclass; - cp->dev.id = channel; - ret = sysdev_register(&cp->dev); - - printk("DMA channel %d at %p, irq %d\n", - cp->number, cp->regs, cp->irq); - } - - return 0; - - err: - kmem_cache_destroy(dma_kmem); - iounmap(dma_base); - dma_base = NULL; - return ret; -} - -core_initcall(s3c2410_init_dma); - -static inline int is_channel_valid(unsigned int channel) +static int __init s3c2442_dma_init(void) { - return (channel & DMA_CH_VALID); + return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver); } -/* s3c2410_dma_map_channel() - * - * turn the virtual channel number into a real, and un-used hardware - * channel. - * - * currently this code uses first-free channel from the specified harware - * map, not taking into account anything that the board setup code may - * have to say about the likely peripheral set to be in use. -*/ - -struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel) -{ - struct s3c24xx_dma_map *ch_map; - struct s3c2410_dma_chan *dmach; - int ch; - - if (dma_sel.map == NULL || channel > dma_sel.map_size) - return NULL; - - ch_map = dma_sel.map + channel; - - for (ch = 0; ch < S3C2410_DMA_CHANNELS; ch++) { - if (!is_channel_valid(ch_map->channels[ch])) - continue; - - if (s3c2410_chans[ch].in_use == 0) { - printk("mapped channel %d to %d\n", channel, ch); - break; - } - } - - if (ch >= S3C2410_DMA_CHANNELS) - return NULL; - - /* update our channel mapping */ - - dmach = &s3c2410_chans[ch]; - dma_chan_map[channel] = dmach; - - /* select the channel */ - - (dma_sel.select)(dmach, ch_map); - - return dmach; -} - -static void s3c24xx_dma_show_ch(struct s3c24xx_dma_map *map, int ch) -{ - /* show the channel configuration */ - - printk("%2d: %20s, channels %c%c%c%c\n", ch, map->name, - (is_channel_valid(map->channels[0]) ? '0' : '-'), - (is_channel_valid(map->channels[1]) ? '1' : '-'), - (is_channel_valid(map->channels[2]) ? '2' : '-'), - (is_channel_valid(map->channels[3]) ? '3' : '-')); -} - -static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch) -{ - if (1) - s3c24xx_dma_show_ch(map, ch); - - return 0; -} - -int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel) -{ - struct s3c24xx_dma_map *nmap; - size_t map_sz = sizeof(*nmap) * sel->map_size; - int ptr; - - nmap = kmalloc(map_sz, GFP_KERNEL); - if (nmap == NULL) - return -ENOMEM; - - memcpy(nmap, sel->map, map_sz); - memcpy(&dma_sel, sel, sizeof(*sel)); - - dma_sel.map = nmap; - - for (ptr = 0; ptr < sel->map_size; ptr++) - s3c24xx_dma_check_entry(nmap+ptr, ptr); +arch_initcall(s3c2442_dma_init); +#endif - return 0; -} diff --git a/arch/arm/mach-s3c2410/dma.h b/arch/arm/mach-s3c2410/dma.h deleted file mode 100644 index 0ebfe0aab80b..000000000000 --- a/arch/arm/mach-s3c2410/dma.h +++ /dev/null @@ -1,45 +0,0 @@ -/* arch/arm/mach-s3c2410/dma.h - * - * Copyright (C) 2006 Simtec Electronics - * Ben Dooks - * - * Samsung S3C24XX DMA support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -extern struct sysdev_class dma_sysclass; -extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; - -#define DMA_CH_VALID (1<<31) - -struct s3c24xx_dma_addr { - unsigned long from; - unsigned long to; -}; - -/* struct s3c24xx_dma_map - * - * this holds the mapping information for the channel selected - * to be connected to the specified device -*/ - -struct s3c24xx_dma_map { - const char *name; - struct s3c24xx_dma_addr hw_addr; - - unsigned long channels[S3C2410_DMA_CHANNELS]; -}; - -struct s3c24xx_dma_selection { - struct s3c24xx_dma_map *map; - unsigned long map_size; - unsigned long dcon_mask; - - void (*select)(struct s3c2410_dma_chan *chan, - struct s3c24xx_dma_map *map); -}; - -extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel); diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c index f6fb215bb48c..01e795d1146e 100644 --- a/arch/arm/mach-s3c2410/gpio.c +++ b/arch/arm/mach-s3c2410/gpio.c @@ -1,9 +1,9 @@ /* linux/arch/arm/mach-s3c2410/gpio.c * - * Copyright (c) 2004-2005 Simtec Electronics + * Copyright (c) 2004-2006 Simtec Electronics * Ben Dooks * - * S3C24XX GPIO support + * S3C2410 GPIO support * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,8 +18,7 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - + */ #include #include @@ -33,156 +32,40 @@ #include -void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function) -{ - void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long mask; - unsigned long con; - unsigned long flags; - - if (pin < S3C2410_GPIO_BANKB) { - mask = 1 << S3C2410_GPIO_OFFSET(pin); - } else { - mask = 3 << S3C2410_GPIO_OFFSET(pin)*2; - } - - switch (function) { - case S3C2410_GPIO_LEAVE: - mask = 0; - function = 0; - break; - - case S3C2410_GPIO_INPUT: - case S3C2410_GPIO_OUTPUT: - case S3C2410_GPIO_SFN2: - case S3C2410_GPIO_SFN3: - if (pin < S3C2410_GPIO_BANKB) { - function -= 1; - function &= 1; - function <<= S3C2410_GPIO_OFFSET(pin); - } else { - function &= 3; - function <<= S3C2410_GPIO_OFFSET(pin)*2; - } - } - - /* modify the specified register wwith IRQs off */ - - local_irq_save(flags); - - con = __raw_readl(base + 0x00); - con &= ~mask; - con |= function; - - __raw_writel(con, base + 0x00); - - local_irq_restore(flags); -} - -EXPORT_SYMBOL(s3c2410_gpio_cfgpin); - -unsigned int s3c2410_gpio_getcfg(unsigned int pin) -{ - void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long val = __raw_readl(base); - - if (pin < S3C2410_GPIO_BANKB) { - val >>= S3C2410_GPIO_OFFSET(pin); - val &= 1; - val += 1; - } else { - val >>= S3C2410_GPIO_OFFSET(pin)*2; - val &= 3; - } - - return val | S3C2410_GPIO_INPUT; -} - -EXPORT_SYMBOL(s3c2410_gpio_getcfg); - -void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) +int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, + unsigned int config) { - void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long offs = S3C2410_GPIO_OFFSET(pin); + void __iomem *reg = S3C24XX_EINFLT0; unsigned long flags; - unsigned long up; - - if (pin < S3C2410_GPIO_BANKB) - return; - - local_irq_save(flags); - - up = __raw_readl(base + 0x08); - up &= ~(1L << offs); - up |= to << offs; - __raw_writel(up, base + 0x08); + unsigned long val; - local_irq_restore(flags); -} + if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15) + return -1; -EXPORT_SYMBOL(s3c2410_gpio_pullup); + config &= 0xff; -void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) -{ - void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long offs = S3C2410_GPIO_OFFSET(pin); - unsigned long flags; - unsigned long dat; + pin -= S3C2410_GPG8; + reg += pin & ~3; local_irq_save(flags); - dat = __raw_readl(base + 0x04); - dat &= ~(1 << offs); - dat |= to << offs; - __raw_writel(dat, base + 0x04); - - local_irq_restore(flags); -} - -EXPORT_SYMBOL(s3c2410_gpio_setpin); - -unsigned int s3c2410_gpio_getpin(unsigned int pin) -{ - void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long offs = S3C2410_GPIO_OFFSET(pin); + /* update filter width and clock source */ - return __raw_readl(base + 0x04) & (1<< offs); -} + val = __raw_readl(reg); + val &= ~(0xff << ((pin & 3) * 8)); + val |= config << ((pin & 3) * 8); + __raw_writel(val, reg); -EXPORT_SYMBOL(s3c2410_gpio_getpin); + /* update filter enable */ -unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change) -{ - unsigned long flags; - unsigned long misccr; + val = __raw_readl(S3C24XX_EXTINT2); + val &= ~(1 << ((pin * 4) + 3)); + val |= on << ((pin * 4) + 3); + __raw_writel(val, S3C24XX_EXTINT2); - local_irq_save(flags); - misccr = __raw_readl(S3C24XX_MISCCR); - misccr &= ~clear; - misccr ^= change; - __raw_writel(misccr, S3C24XX_MISCCR); local_irq_restore(flags); - return misccr; -} - -EXPORT_SYMBOL(s3c2410_modify_misccr); - -int s3c2410_gpio_getirq(unsigned int pin) -{ - if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15) - return -1; /* not valid interrupts */ - - if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7) - return -1; /* not valid pin */ - - if (pin < S3C2410_GPF4) - return (pin - S3C2410_GPF0) + IRQ_EINT0; - - if (pin < S3C2410_GPG0) - return (pin - S3C2410_GPF4) + IRQ_EINT4; - - return (pin - S3C2410_GPG0) + IRQ_EINT8; + return 0; } -EXPORT_SYMBOL(s3c2410_gpio_getirq); +EXPORT_SYMBOL(s3c2410_gpio_irqfilter); diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c index 3c0ed7871c55..53cbdaa43ac6 100644 --- a/arch/arm/mach-s3c2410/irq.c +++ b/arch/arm/mach-s3c2410/irq.c @@ -1,6 +1,6 @@ /* linux/arch/arm/mach-s3c2410/irq.c * - * Copyright (c) 2003,2004 Simtec Electronics + * Copyright (c) 2006 Simtec Electronics * Ben Dooks * * This program is free software; you can redistribute it and/or modify @@ -17,37 +17,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * - * Changelog: - * - * 22-Jul-2004 Ben Dooks - * Fixed compile warnings - * - * 22-Jul-2004 Roc Wu - * Fixed s3c_extirq_type - * - * 21-Jul-2004 Arnaud Patard (Rtp) - * Addition of ADC/TC demux - * - * 04-Oct-2004 Klaus Fetscher - * Fix for set_irq_type() on low EINT numbers - * - * 05-Oct-2004 Ben Dooks - * Tidy up KF's patch and sort out new release - * - * 05-Oct-2004 Ben Dooks - * Add support for power management controls - * - * 04-Nov-2004 Ben Dooks - * Fix standard IRQ wake for EINT0..4 and RTC - * - * 22-Feb-2005 Ben Dooks - * Fixed edge-triggering on ADC IRQ - * - * 28-Jun-2005 Ben Dooks - * Mark IRQ_LCD valid - * - * 25-Jul-2005 Ben Dooks - * Split the S3C2440 IRQ code to seperate file */ #include @@ -57,745 +26,23 @@ #include #include -#include -#include -#include - -#include - -#include -#include - -#include "cpu.h" -#include "pm.h" -#include "irq.h" - -/* wakeup irq control */ - -#ifdef CONFIG_PM - -/* state for IRQs over sleep */ - -/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources - * - * set bit to 1 in allow bitfield to enable the wakeup settings on it -*/ - -unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; -unsigned long s3c_irqwake_intmask = 0xffffffffL; -unsigned long s3c_irqwake_eintallow = 0x0000fff0L; -unsigned long s3c_irqwake_eintmask = 0xffffffffL; - -int -s3c_irq_wake(unsigned int irqno, unsigned int state) -{ - unsigned long irqbit = 1 << (irqno - IRQ_EINT0); - - if (!(s3c_irqwake_intallow & irqbit)) - return -ENOENT; - - printk(KERN_INFO "wake %s for irq %d\n", - state ? "enabled" : "disabled", irqno); - - if (!state) - s3c_irqwake_intmask |= irqbit; - else - s3c_irqwake_intmask &= ~irqbit; - - return 0; -} - -static int -s3c_irqext_wake(unsigned int irqno, unsigned int state) -{ - unsigned long bit = 1L << (irqno - EXTINT_OFF); - - if (!(s3c_irqwake_eintallow & bit)) - return -ENOENT; - - printk(KERN_INFO "wake %s for irq %d\n", - state ? "enabled" : "disabled", irqno); - - if (!state) - s3c_irqwake_eintmask |= bit; - else - s3c_irqwake_eintmask &= ~bit; - - return 0; -} - -#else -#define s3c_irqext_wake NULL -#define s3c_irq_wake NULL -#endif - - -static void -s3c_irq_mask(unsigned int irqno) -{ - unsigned long mask; - - irqno -= IRQ_EINT0; - - mask = __raw_readl(S3C2410_INTMSK); - mask |= 1UL << irqno; - __raw_writel(mask, S3C2410_INTMSK); -} - -static inline void -s3c_irq_ack(unsigned int irqno) -{ - unsigned long bitval = 1UL << (irqno - IRQ_EINT0); - - __raw_writel(bitval, S3C2410_SRCPND); - __raw_writel(bitval, S3C2410_INTPND); -} - -static inline void -s3c_irq_maskack(unsigned int irqno) -{ - unsigned long bitval = 1UL << (irqno - IRQ_EINT0); - unsigned long mask; - - mask = __raw_readl(S3C2410_INTMSK); - __raw_writel(mask|bitval, S3C2410_INTMSK); - - __raw_writel(bitval, S3C2410_SRCPND); - __raw_writel(bitval, S3C2410_INTPND); -} - - -static void -s3c_irq_unmask(unsigned int irqno) -{ - unsigned long mask; - - if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23) - irqdbf2("s3c_irq_unmask %d\n", irqno); - - irqno -= IRQ_EINT0; - - mask = __raw_readl(S3C2410_INTMSK); - mask &= ~(1UL << irqno); - __raw_writel(mask, S3C2410_INTMSK); -} - -struct irq_chip s3c_irq_level_chip = { - .name = "s3c-level", - .ack = s3c_irq_maskack, - .mask = s3c_irq_mask, - .unmask = s3c_irq_unmask, - .set_wake = s3c_irq_wake -}; - -static struct irq_chip s3c_irq_chip = { - .name = "s3c", - .ack = s3c_irq_ack, - .mask = s3c_irq_mask, - .unmask = s3c_irq_unmask, - .set_wake = s3c_irq_wake -}; - -static void -s3c_irqext_mask(unsigned int irqno) -{ - unsigned long mask; - - irqno -= EXTINT_OFF; - - mask = __raw_readl(S3C24XX_EINTMASK); - mask |= ( 1UL << irqno); - __raw_writel(mask, S3C24XX_EINTMASK); -} - -static void -s3c_irqext_ack(unsigned int irqno) -{ - unsigned long req; - unsigned long bit; - unsigned long mask; +#include +#include - bit = 1UL << (irqno - EXTINT_OFF); - - mask = __raw_readl(S3C24XX_EINTMASK); - - __raw_writel(bit, S3C24XX_EINTPEND); - - req = __raw_readl(S3C24XX_EINTPEND); - req &= ~mask; - - /* not sure if we should be acking the parent irq... */ - - if (irqno <= IRQ_EINT7 ) { - if ((req & 0xf0) == 0) - s3c_irq_ack(IRQ_EINT4t7); - } else { - if ((req >> 8) == 0) - s3c_irq_ack(IRQ_EINT8t23); - } -} - -static void -s3c_irqext_unmask(unsigned int irqno) +static int s3c2410_irq_add(struct sys_device *sysdev) { - unsigned long mask; - - irqno -= EXTINT_OFF; - - mask = __raw_readl(S3C24XX_EINTMASK); - mask &= ~( 1UL << irqno); - __raw_writel(mask, S3C24XX_EINTMASK); -} - -int -s3c_irqext_type(unsigned int irq, unsigned int type) -{ - void __iomem *extint_reg; - void __iomem *gpcon_reg; - unsigned long gpcon_offset, extint_offset; - unsigned long newvalue = 0, value; - - if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3)) - { - gpcon_reg = S3C2410_GPFCON; - extint_reg = S3C24XX_EXTINT0; - gpcon_offset = (irq - IRQ_EINT0) * 2; - extint_offset = (irq - IRQ_EINT0) * 4; - } - else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7)) - { - gpcon_reg = S3C2410_GPFCON; - extint_reg = S3C24XX_EXTINT0; - gpcon_offset = (irq - (EXTINT_OFF)) * 2; - extint_offset = (irq - (EXTINT_OFF)) * 4; - } - else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15)) - { - gpcon_reg = S3C2410_GPGCON; - extint_reg = S3C24XX_EXTINT1; - gpcon_offset = (irq - IRQ_EINT8) * 2; - extint_offset = (irq - IRQ_EINT8) * 4; - } - else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23)) - { - gpcon_reg = S3C2410_GPGCON; - extint_reg = S3C24XX_EXTINT2; - gpcon_offset = (irq - IRQ_EINT8) * 2; - extint_offset = (irq - IRQ_EINT16) * 4; - } else - return -1; - - /* Set the GPIO to external interrupt mode */ - value = __raw_readl(gpcon_reg); - value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); - __raw_writel(value, gpcon_reg); - - /* Set the external interrupt to pointed trigger type */ - switch (type) - { - case IRQT_NOEDGE: - printk(KERN_WARNING "No edge setting!\n"); - break; - - case IRQT_RISING: - newvalue = S3C2410_EXTINT_RISEEDGE; - break; - - case IRQT_FALLING: - newvalue = S3C2410_EXTINT_FALLEDGE; - break; - - case IRQT_BOTHEDGE: - newvalue = S3C2410_EXTINT_BOTHEDGE; - break; - - case IRQT_LOW: - newvalue = S3C2410_EXTINT_LOWLEV; - break; - - case IRQT_HIGH: - newvalue = S3C2410_EXTINT_HILEV; - break; - - default: - printk(KERN_ERR "No such irq type %d", type); - return -1; - } - - value = __raw_readl(extint_reg); - value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); - __raw_writel(value, extint_reg); - return 0; } -static struct irq_chip s3c_irqext_chip = { - .name = "s3c-ext", - .mask = s3c_irqext_mask, - .unmask = s3c_irqext_unmask, - .ack = s3c_irqext_ack, - .set_type = s3c_irqext_type, - .set_wake = s3c_irqext_wake -}; - -static struct irq_chip s3c_irq_eint0t4 = { - .name = "s3c-ext0", - .ack = s3c_irq_ack, - .mask = s3c_irq_mask, - .unmask = s3c_irq_unmask, - .set_wake = s3c_irq_wake, - .set_type = s3c_irqext_type, -}; - -/* mask values for the parent registers for each of the interrupt types */ - -#define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0)) -#define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0)) -#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0)) -#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0)) - - -/* UART0 */ - -static void -s3c_irq_uart0_mask(unsigned int irqno) -{ - s3c_irqsub_mask(irqno, INTMSK_UART0, 7); -} - -static void -s3c_irq_uart0_unmask(unsigned int irqno) -{ - s3c_irqsub_unmask(irqno, INTMSK_UART0); -} - -static void -s3c_irq_uart0_ack(unsigned int irqno) -{ - s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); -} - -static struct irq_chip s3c_irq_uart0 = { - .name = "s3c-uart0", - .mask = s3c_irq_uart0_mask, - .unmask = s3c_irq_uart0_unmask, - .ack = s3c_irq_uart0_ack, -}; - -/* UART1 */ - -static void -s3c_irq_uart1_mask(unsigned int irqno) -{ - s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3); -} - -static void -s3c_irq_uart1_unmask(unsigned int irqno) -{ - s3c_irqsub_unmask(irqno, INTMSK_UART1); -} - -static void -s3c_irq_uart1_ack(unsigned int irqno) -{ - s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); -} - -static struct irq_chip s3c_irq_uart1 = { - .name = "s3c-uart1", - .mask = s3c_irq_uart1_mask, - .unmask = s3c_irq_uart1_unmask, - .ack = s3c_irq_uart1_ack, -}; - -/* UART2 */ - -static void -s3c_irq_uart2_mask(unsigned int irqno) -{ - s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6); -} - -static void -s3c_irq_uart2_unmask(unsigned int irqno) -{ - s3c_irqsub_unmask(irqno, INTMSK_UART2); -} - -static void -s3c_irq_uart2_ack(unsigned int irqno) -{ - s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); -} - -static struct irq_chip s3c_irq_uart2 = { - .name = "s3c-uart2", - .mask = s3c_irq_uart2_mask, - .unmask = s3c_irq_uart2_unmask, - .ack = s3c_irq_uart2_ack, -}; - -/* ADC and Touchscreen */ - -static void -s3c_irq_adc_mask(unsigned int irqno) -{ - s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9); -} - -static void -s3c_irq_adc_unmask(unsigned int irqno) -{ - s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT); -} - -static void -s3c_irq_adc_ack(unsigned int irqno) -{ - s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); -} - -static struct irq_chip s3c_irq_adc = { - .name = "s3c-adc", - .mask = s3c_irq_adc_mask, - .unmask = s3c_irq_adc_unmask, - .ack = s3c_irq_adc_ack, -}; - -/* irq demux for adc */ -static void s3c_irq_demux_adc(unsigned int irq, - struct irq_desc *desc) -{ - unsigned int subsrc, submsk; - unsigned int offset = 9; - struct irq_desc *mydesc; - - /* read the current pending interrupts, and the mask - * for what it is available */ - - subsrc = __raw_readl(S3C2410_SUBSRCPND); - submsk = __raw_readl(S3C2410_INTSUBMSK); - - subsrc &= ~submsk; - subsrc >>= offset; - subsrc &= 3; - - if (subsrc != 0) { - if (subsrc & 1) { - mydesc = irq_desc + IRQ_TC; - desc_handle_irq(IRQ_TC, mydesc); - } - if (subsrc & 2) { - mydesc = irq_desc + IRQ_ADC; - desc_handle_irq(IRQ_ADC, mydesc); - } - } -} - -static void s3c_irq_demux_uart(unsigned int start) -{ - unsigned int subsrc, submsk; - unsigned int offset = start - IRQ_S3CUART_RX0; - struct irq_desc *desc; - - /* read the current pending interrupts, and the mask - * for what it is available */ - - subsrc = __raw_readl(S3C2410_SUBSRCPND); - submsk = __raw_readl(S3C2410_INTSUBMSK); - - irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n", - start, offset, subsrc, submsk); - - subsrc &= ~submsk; - subsrc >>= offset; - subsrc &= 7; - - if (subsrc != 0) { - desc = irq_desc + start; - - if (subsrc & 1) - desc_handle_irq(start, desc); - - desc++; - - if (subsrc & 2) - desc_handle_irq(start+1, desc); - - desc++; - - if (subsrc & 4) - desc_handle_irq(start+2, desc); - } -} - -/* uart demux entry points */ - -static void -s3c_irq_demux_uart0(unsigned int irq, - struct irq_desc *desc) -{ - irq = irq; - s3c_irq_demux_uart(IRQ_S3CUART_RX0); -} - -static void -s3c_irq_demux_uart1(unsigned int irq, - struct irq_desc *desc) -{ - irq = irq; - s3c_irq_demux_uart(IRQ_S3CUART_RX1); -} - -static void -s3c_irq_demux_uart2(unsigned int irq, - struct irq_desc *desc) -{ - irq = irq; - s3c_irq_demux_uart(IRQ_S3CUART_RX2); -} - -static void -s3c_irq_demux_extint8(unsigned int irq, - struct irq_desc *desc) -{ - unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); - unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); - - eintpnd &= ~eintmsk; - eintpnd &= ~0xff; /* ignore lower irqs */ - - /* we may as well handle all the pending IRQs here */ - - while (eintpnd) { - irq = __ffs(eintpnd); - eintpnd &= ~(1< - * - * Header file for S3C24XX CPU IRQ support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#define irqdbf(x...) -#define irqdbf2(x...) - -#define EXTINT_OFF (IRQ_EINT4 - 4) - -extern struct irq_chip s3c_irq_level_chip; - -static inline void -s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, - int subcheck) -{ - unsigned long mask; - unsigned long submask; - - submask = __raw_readl(S3C2410_INTSUBMSK); - mask = __raw_readl(S3C2410_INTMSK); - - submask |= (1UL << (irqno - IRQ_S3CUART_RX0)); - - /* check to see if we need to mask the parent IRQ */ - - if ((submask & subcheck) == subcheck) { - __raw_writel(mask | parentbit, S3C2410_INTMSK); - } - - /* write back masks */ - __raw_writel(submask, S3C2410_INTSUBMSK); - -} - -static inline void -s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit) -{ - unsigned long mask; - unsigned long submask; - - submask = __raw_readl(S3C2410_INTSUBMSK); - mask = __raw_readl(S3C2410_INTMSK); - - submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0)); - mask &= ~parentbit; - - /* write back masks */ - __raw_writel(submask, S3C2410_INTSUBMSK); - __raw_writel(mask, S3C2410_INTMSK); -} - - -static inline void -s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group) -{ - unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); - - s3c_irqsub_mask(irqno, parentmask, group); - - __raw_writel(bit, S3C2410_SUBSRCPND); - - /* only ack parent if we've got all the irqs (seems we must - * ack, all and hope that the irq system retriggers ok when - * the interrupt goes off again) - */ - - if (1) { - __raw_writel(parentmask, S3C2410_SRCPND); - __raw_writel(parentmask, S3C2410_INTPND); - } -} - -static inline void -s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group) -{ - unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); - - __raw_writel(bit, S3C2410_SUBSRCPND); - - /* only ack parent if we've got all the irqs (seems we must - * ack, all and hope that the irq system retriggers ok when - * the interrupt goes off again) - */ - - if (1) { - __raw_writel(parentmask, S3C2410_SRCPND); - __raw_writel(parentmask, S3C2410_INTPND); - } -} - -/* exported for use in arch/arm/mach-s3c2410 */ - -#ifdef CONFIG_PM -extern int s3c_irq_wake(unsigned int irqno, unsigned int state); -#else -#define s3c_irq_wake NULL -#endif - -extern int s3c_irqext_type(unsigned int irq, unsigned int type); diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c index 817e2c684410..d54cda1b3006 100644 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c +++ b/arch/arm/mach-s3c2410/mach-amlm5900.c @@ -1,4 +1,4 @@ -/*********************************************************************** +/* linux/arch/arm/mach-s3c2410/mach-amlm5900.c * * linux/arch/arm/mach-s3c2410/mach-amlm5900.c * @@ -52,8 +52,8 @@ #include #include -#include "devs.h" -#include "cpu.h" +#include +#include #ifdef CONFIG_MTD_PARTITIONS diff --git a/arch/arm/mach-s3c2410/mach-anubis.c b/arch/arm/mach-s3c2410/mach-anubis.c deleted file mode 100644 index 0fad0c2fe07b..000000000000 --- a/arch/arm/mach-s3c2410/mach-anubis.c +++ /dev/null @@ -1,325 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-anubis.c - * - * Copyright (c) 2003-2005 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "clock.h" -#include "devs.h" -#include "cpu.h" - -#define COPYRIGHT ", (c) 2005 Simtec Electronics" - -static struct map_desc anubis_iodesc[] __initdata = { - /* ISA IO areas */ - - { - .virtual = (u32)S3C24XX_VA_ISA_BYTE, - .pfn = __phys_to_pfn(0x0), - .length = SZ_4M, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(0x0), - .length = SZ_4M, - .type = MT_DEVICE, - }, - - /* we could possibly compress the next set down into a set of smaller tables - * pagetables, but that would mean using an L2 section, and it still means - * we cannot actually feed the same register to an LDR due to 16K spacing - */ - - /* CPLD control registers */ - - { - .virtual = (u32)ANUBIS_VA_CTRL1, - .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (u32)ANUBIS_VA_CTRL2, - .pfn = __phys_to_pfn(ANUBIS_PA_CTRL2), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = { - [0] = { - .name = "uclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, - [1] = { - .name = "pclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - } -}; - - -static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - .clocks = anubis_serial_clocks, - .clocks_size = ARRAY_SIZE(anubis_serial_clocks), - }, - [1] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - .clocks = anubis_serial_clocks, - .clocks_size = ARRAY_SIZE(anubis_serial_clocks), - }, -}; - -/* NAND Flash on Anubis board */ - -static int external_map[] = { 2 }; -static int chip0_map[] = { 0 }; -static int chip1_map[] = { 1 }; - -static struct mtd_partition anubis_default_nand_part[] = { - [0] = { - .name = "Boot Agent", - .size = SZ_16K, - .offset = 0, - }, - [1] = { - .name = "/boot", - .size = SZ_4M - SZ_16K, - .offset = SZ_16K, - }, - [2] = { - .name = "user1", - .offset = SZ_4M, - .size = SZ_32M - SZ_4M, - }, - [3] = { - .name = "user2", - .offset = SZ_32M, - .size = MTDPART_SIZ_FULL, - } -}; - -/* the Anubis has 3 selectable slots for nand-flash, the two - * on-board chip areas, as well as the external slot. - * - * Note, there is no current hot-plug support for the External - * socket. -*/ - -static struct s3c2410_nand_set anubis_nand_sets[] = { - [1] = { - .name = "External", - .nr_chips = 1, - .nr_map = external_map, - .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), - .partitions = anubis_default_nand_part, - }, - [0] = { - .name = "chip0", - .nr_chips = 1, - .nr_map = chip0_map, - .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), - .partitions = anubis_default_nand_part, - }, - [2] = { - .name = "chip1", - .nr_chips = 1, - .nr_map = chip1_map, - .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), - .partitions = anubis_default_nand_part, - }, -}; - -static void anubis_nand_select(struct s3c2410_nand_set *set, int slot) -{ - unsigned int tmp; - - slot = set->nr_map[slot] & 3; - - pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n", - slot, set, set->nr_map); - - tmp = __raw_readb(ANUBIS_VA_CTRL1); - tmp &= ~ANUBIS_CTRL1_NANDSEL; - tmp |= slot; - - pr_debug("anubis_nand: ctrl1 now %02x\n", tmp); - - __raw_writeb(tmp, ANUBIS_VA_CTRL1); -} - -static struct s3c2410_platform_nand anubis_nand_info = { - .tacls = 25, - .twrph0 = 55, - .twrph1 = 40, - .nr_sets = ARRAY_SIZE(anubis_nand_sets), - .sets = anubis_nand_sets, - .select_chip = anubis_nand_select, -}; - -/* IDE channels */ - -static struct resource anubis_ide0_resource[] = { - { - .start = S3C2410_CS3, - .end = S3C2410_CS3 + (8*32) - 1, - .flags = IORESOURCE_MEM, - }, { - .start = S3C2410_CS3 + (1<<26), - .end = S3C2410_CS3 + (1<<26) + (8*32) - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_IDE0, - .end = IRQ_IDE0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device anubis_device_ide0 = { - .name = "simtec-ide", - .id = 0, - .num_resources = ARRAY_SIZE(anubis_ide0_resource), - .resource = anubis_ide0_resource, -}; - -static struct resource anubis_ide1_resource[] = { - { - .start = S3C2410_CS4, - .end = S3C2410_CS4 + (8*32) - 1, - .flags = IORESOURCE_MEM, - }, { - .start = S3C2410_CS4 + (1<<26), - .end = S3C2410_CS4 + (1<<26) + (8*32) - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_IDE0, - .end = IRQ_IDE0, - .flags = IORESOURCE_IRQ, - }, -}; - - -static struct platform_device anubis_device_ide1 = { - .name = "simtec-ide", - .id = 1, - .num_resources = ARRAY_SIZE(anubis_ide1_resource), - .resource = anubis_ide1_resource, -}; - -/* Standard Anubis devices */ - -static struct platform_device *anubis_devices[] __initdata = { - &s3c_device_usb, - &s3c_device_wdt, - &s3c_device_adc, - &s3c_device_i2c, - &s3c_device_rtc, - &s3c_device_nand, - &anubis_device_ide0, - &anubis_device_ide1, -}; - -static struct clk *anubis_clocks[] = { - &s3c24xx_dclk0, - &s3c24xx_dclk1, - &s3c24xx_clkout0, - &s3c24xx_clkout1, - &s3c24xx_uclk, -}; - -static struct s3c24xx_board anubis_board __initdata = { - .devices = anubis_devices, - .devices_count = ARRAY_SIZE(anubis_devices), - .clocks = anubis_clocks, - .clocks_count = ARRAY_SIZE(anubis_clocks), -}; - -static void __init anubis_map_io(void) -{ - /* initialise the clocks */ - - s3c24xx_dclk0.parent = NULL; - s3c24xx_dclk0.rate = 12*1000*1000; - - s3c24xx_dclk1.parent = NULL; - s3c24xx_dclk1.rate = 24*1000*1000; - - s3c24xx_clkout0.parent = &s3c24xx_dclk0; - s3c24xx_clkout1.parent = &s3c24xx_dclk1; - - s3c24xx_uclk.parent = &s3c24xx_clkout1; - - s3c_device_nand.dev.platform_data = &anubis_nand_info; - - s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); - s3c24xx_init_clocks(0); - s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); - s3c24xx_set_board(&anubis_board); - - /* ensure that the GPIO is setup */ - s3c2410_gpio_setpin(S3C2410_GPA0, 1); -} - -MACHINE_START(ANUBIS, "Simtec-Anubis") - /* Maintainer: Ben Dooks */ - .phys_io = S3C2410_PA_UART, - .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, - .boot_params = S3C2410_SDRAM_PA + 0x100, - .map_io = anubis_map_io, - .init_irq = s3c24xx_init_irq, - .timer = &s3c24xx_timer, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index b8b76757ec54..7b81296427eb 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -50,9 +50,9 @@ #include -#include "clock.h" -#include "devs.h" -#include "cpu.h" +#include +#include +#include #include "usb-simtec.h" #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics" diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 15b625eae499..5af26e177966 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -38,10 +38,10 @@ #include #include -#include "clock.h" -#include "devs.h" -#include "cpu.h" -#include "pm.h" +#include +#include +#include +#include static struct map_desc h1940_iodesc[] __initdata = { [0] = { diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 0411e9adb54d..dbac7311f98f 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c @@ -38,10 +38,10 @@ #include #include -#include "s3c2410.h" -#include "clock.h" -#include "devs.h" -#include "cpu.h" +#include +#include +#include +#include static struct map_desc n30_iodesc[] __initdata = { /* nothing here yet */ diff --git a/arch/arm/mach-s3c2410/mach-nexcoder.c b/arch/arm/mach-s3c2410/mach-nexcoder.c deleted file mode 100644 index d6dfdad8c90b..000000000000 --- a/arch/arm/mach-s3c2410/mach-nexcoder.c +++ /dev/null @@ -1,158 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-nexcoder.c - * - * Copyright (c) 2004 Nex Vision - * Guillaume GOURAT - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 15-10-2004 GG Created initial version - * 12-03-2005 BJD Updated for release - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -//#include -#include -#include - -#include "s3c2410.h" -#include "s3c2440.h" -#include "clock.h" -#include "devs.h" -#include "cpu.h" - -static struct map_desc nexcoder_iodesc[] __initdata = { - /* nothing here yet */ -}; - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg nexcoder_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - } -}; - -/* NOR Flash on NexVision NexCoder 2440 board */ - -static struct resource nexcoder_nor_resource[] = { - [0] = { - .start = S3C2410_CS0, - .end = S3C2410_CS0 + (8*1024*1024) - 1, - .flags = IORESOURCE_MEM, - } -}; - -static struct map_info nexcoder_nor_map = { - .bankwidth = 2, -}; - -static struct platform_device nexcoder_device_nor = { - .name = "mtd-flash", - .id = -1, - .num_resources = ARRAY_SIZE(nexcoder_nor_resource), - .resource = nexcoder_nor_resource, - .dev = - { - .platform_data = &nexcoder_nor_map, - } -}; - -/* Standard Nexcoder devices */ - -static struct platform_device *nexcoder_devices[] __initdata = { - &s3c_device_usb, - &s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c, - &s3c_device_iis, - &s3c_device_rtc, - &s3c_device_camif, - &s3c_device_spi0, - &s3c_device_spi1, - &nexcoder_device_nor, -}; - -static struct s3c24xx_board nexcoder_board __initdata = { - .devices = nexcoder_devices, - .devices_count = ARRAY_SIZE(nexcoder_devices), -}; - - -static void __init nexcoder_sensorboard_init(void) -{ - // Initialize SCCB bus - s3c2410_gpio_setpin(S3C2410_GPE14, 1); // IICSCL - s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_OUTP); - s3c2410_gpio_setpin(S3C2410_GPE15, 1); // IICSDA - s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_OUTP); - - // Power up the sensor board - s3c2410_gpio_setpin(S3C2410_GPF1, 1); - s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_OUTP); // CAM_GPIO7 => nLDO_PWRDN - s3c2410_gpio_setpin(S3C2410_GPF2, 0); - s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); // CAM_GPIO6 => CAM_PWRDN -} - -static void __init nexcoder_map_io(void) -{ - s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc)); - s3c24xx_init_clocks(0); - s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs)); - s3c24xx_set_board(&nexcoder_board); - nexcoder_sensorboard_init(); -} - - -MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440") - /* Maintainer: Guillaume GOURAT */ - .phys_io = S3C2410_PA_UART, - .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, - .boot_params = S3C2410_SDRAM_PA + 0x100, - .map_io = nexcoder_map_io, - .init_irq = s3c24xx_init_irq, - .timer = &s3c24xx_timer, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-osiris.c b/arch/arm/mach-s3c2410/mach-osiris.c deleted file mode 100644 index 37b40850c9b9..000000000000 --- a/arch/arm/mach-s3c2410/mach-osiris.c +++ /dev/null @@ -1,303 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-osiris.c - * - * Copyright (c) 2005 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "clock.h" -#include "devs.h" -#include "cpu.h" - -/* onboard perihpheral map */ - -static struct map_desc osiris_iodesc[] __initdata = { - /* ISA IO areas (may be over-written later) */ - - { - .virtual = (u32)S3C24XX_VA_ISA_BYTE, - .pfn = __phys_to_pfn(S3C2410_CS5), - .length = SZ_16M, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS5), - .length = SZ_16M, - .type = MT_DEVICE, - }, - - /* CPLD control registers */ - - { - .virtual = (u32)OSIRIS_VA_CTRL1, - .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = (u32)OSIRIS_VA_CTRL2, - .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2), - .length = SZ_16K, - .type = MT_DEVICE, - }, -}; - -#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = { - [0] = { - .name = "uclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, - [1] = { - .name = "pclk", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - } -}; - -static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - .clocks = osiris_serial_clocks, - .clocks_size = ARRAY_SIZE(osiris_serial_clocks), - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - .clocks = osiris_serial_clocks, - .clocks_size = ARRAY_SIZE(osiris_serial_clocks), - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - .clocks = osiris_serial_clocks, - .clocks_size = ARRAY_SIZE(osiris_serial_clocks), - } -}; - -/* NAND Flash on Osiris board */ - -static int external_map[] = { 2 }; -static int chip0_map[] = { 0 }; -static int chip1_map[] = { 1 }; - -static struct mtd_partition osiris_default_nand_part[] = { - [0] = { - .name = "Boot Agent", - .size = SZ_16K, - .offset = 0, - }, - [1] = { - .name = "/boot", - .size = SZ_4M - SZ_16K, - .offset = SZ_16K, - }, - [2] = { - .name = "user1", - .offset = SZ_4M, - .size = SZ_32M - SZ_4M, - }, - [3] = { - .name = "user2", - .offset = SZ_32M, - .size = MTDPART_SIZ_FULL, - } -}; - -/* the Osiris has 3 selectable slots for nand-flash, the two - * on-board chip areas, as well as the external slot. - * - * Note, there is no current hot-plug support for the External - * socket. -*/ - -static struct s3c2410_nand_set osiris_nand_sets[] = { - [1] = { - .name = "External", - .nr_chips = 1, - .nr_map = external_map, - .nr_partitions = ARRAY_SIZE(osiris_default_nand_part), - .partitions = osiris_default_nand_part, - }, - [0] = { - .name = "chip0", - .nr_chips = 1, - .nr_map = chip0_map, - .nr_partitions = ARRAY_SIZE(osiris_default_nand_part), - .partitions = osiris_default_nand_part, - }, - [2] = { - .name = "chip1", - .nr_chips = 1, - .nr_map = chip1_map, - .nr_partitions = ARRAY_SIZE(osiris_default_nand_part), - .partitions = osiris_default_nand_part, - }, -}; - -static void osiris_nand_select(struct s3c2410_nand_set *set, int slot) -{ - unsigned int tmp; - - slot = set->nr_map[slot] & 3; - - pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n", - slot, set, set->nr_map); - - tmp = __raw_readb(OSIRIS_VA_CTRL1); - tmp &= ~OSIRIS_CTRL1_NANDSEL; - tmp |= slot; - - pr_debug("osiris_nand: ctrl1 now %02x\n", tmp); - - __raw_writeb(tmp, OSIRIS_VA_CTRL1); -} - -static struct s3c2410_platform_nand osiris_nand_info = { - .tacls = 25, - .twrph0 = 60, - .twrph1 = 60, - .nr_sets = ARRAY_SIZE(osiris_nand_sets), - .sets = osiris_nand_sets, - .select_chip = osiris_nand_select, -}; - -/* PCMCIA control and configuration */ - -static struct resource osiris_pcmcia_resource[] = { - [0] = { - .start = 0x0f000000, - .end = 0x0f100000, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0x0c000000, - .end = 0x0c100000, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device osiris_pcmcia = { - .name = "osiris-pcmcia", - .id = -1, - .num_resources = ARRAY_SIZE(osiris_pcmcia_resource), - .resource = osiris_pcmcia_resource, -}; - -/* Standard Osiris devices */ - -static struct platform_device *osiris_devices[] __initdata = { - &s3c_device_i2c, - &s3c_device_nand, - &osiris_pcmcia, -}; - -static struct clk *osiris_clocks[] = { - &s3c24xx_dclk0, - &s3c24xx_dclk1, - &s3c24xx_clkout0, - &s3c24xx_clkout1, - &s3c24xx_uclk, -}; - -static struct s3c24xx_board osiris_board __initdata = { - .devices = osiris_devices, - .devices_count = ARRAY_SIZE(osiris_devices), - .clocks = osiris_clocks, - .clocks_count = ARRAY_SIZE(osiris_clocks), -}; - -static void __init osiris_map_io(void) -{ - unsigned long flags; - - /* initialise the clocks */ - - s3c24xx_dclk0.parent = NULL; - s3c24xx_dclk0.rate = 12*1000*1000; - - s3c24xx_dclk1.parent = NULL; - s3c24xx_dclk1.rate = 24*1000*1000; - - s3c24xx_clkout0.parent = &s3c24xx_dclk0; - s3c24xx_clkout1.parent = &s3c24xx_dclk1; - - s3c24xx_uclk.parent = &s3c24xx_clkout1; - - s3c_device_nand.dev.platform_data = &osiris_nand_info; - - s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc)); - s3c24xx_init_clocks(0); - s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); - s3c24xx_set_board(&osiris_board); - - /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */ - - local_irq_save(flags); - __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON); - local_irq_restore(flags); - - /* write-protect line to the NAND */ - s3c2410_gpio_setpin(S3C2410_GPA0, 1); -} - -MACHINE_START(OSIRIS, "Simtec-OSIRIS") - /* Maintainer: Ben Dooks */ - .phys_io = S3C2410_PA_UART, - .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, - .boot_params = S3C2410_SDRAM_PA + 0x100, - .map_io = osiris_map_io, - .init_irq = s3c24xx_init_irq, - .timer = &s3c24xx_timer, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c index 2c738b375e4d..c78ab75b44f3 100644 --- a/arch/arm/mach-s3c2410/mach-otom.c +++ b/arch/arm/mach-s3c2410/mach-otom.c @@ -32,10 +32,10 @@ #include #include -#include "s3c2410.h" -#include "clock.h" -#include "devs.h" -#include "cpu.h" +#include +#include +#include +#include static struct map_desc otom11_iodesc[] __initdata = { /* Device area */ diff --git a/arch/arm/mach-s3c2410/mach-rx3715.c b/arch/arm/mach-s3c2410/mach-rx3715.c deleted file mode 100644 index ecbcdf79d739..000000000000 --- a/arch/arm/mach-s3c2410/mach-rx3715.c +++ /dev/null @@ -1,244 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-rx3715.c - * - * Copyright (c) 2003,2004 Simtec Electronics - * Ben Dooks - * - * http://www.handhelds.org/projects/rx3715.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "clock.h" -#include "devs.h" -#include "cpu.h" -#include "pm.h" - -static struct map_desc rx3715_iodesc[] __initdata = { - /* dump ISA space somewhere unused */ - - { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS3), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_BYTE, - .pfn = __phys_to_pfn(S3C2410_CS3), - .length = SZ_1M, - .type = MT_DEVICE, - }, -}; - - -static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = { - [0] = { - .name = "fclk", - .divisor = 0, - .min_baud = 0, - .max_baud = 0, - } -}; - -static struct s3c2410_uartcfg rx3715_uartcfgs[] = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - .clocks = rx3715_serial_clocks, - .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x00, - .clocks = rx3715_serial_clocks, - .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), - }, - /* IR port */ - [2] = { - .hwport = 2, - .uart_flags = UPF_CONS_FLOW, - .ucon = 0x3c5, - .ulcon = 0x43, - .ufcon = 0x51, - .clocks = rx3715_serial_clocks, - .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), - } -}; - -/* framebuffer lcd controller information */ - -static struct s3c2410fb_mach_info rx3715_lcdcfg __initdata = { - .regs = { - .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | \ - S3C2410_LCDCON1_TFT | \ - S3C2410_LCDCON1_CLKVAL(0x0C), - - .lcdcon2 = S3C2410_LCDCON2_VBPD(5) | \ - S3C2410_LCDCON2_LINEVAL(319) | \ - S3C2410_LCDCON2_VFPD(6) | \ - S3C2410_LCDCON2_VSPW(2), - - .lcdcon3 = S3C2410_LCDCON3_HBPD(35) | \ - S3C2410_LCDCON3_HOZVAL(239) | \ - S3C2410_LCDCON3_HFPD(35), - - .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | \ - S3C2410_LCDCON4_HSPW(7), - - .lcdcon5 = S3C2410_LCDCON5_INVVLINE | - S3C2410_LCDCON5_FRM565 | - S3C2410_LCDCON5_HWSWP, - }, - - .lpcsel = 0xf82, - - .gpccon = 0xaa955699, - .gpccon_mask = 0xffc003cc, - .gpcup = 0x0000ffff, - .gpcup_mask = 0xffffffff, - - .gpdcon = 0xaa95aaa1, - .gpdcon_mask = 0xffc0fff0, - .gpdup = 0x0000faff, - .gpdup_mask = 0xffffffff, - - .fixed_syncs = 1, - .width = 240, - .height = 320, - - .xres = { - .min = 240, - .max = 240, - .defval = 240, - }, - - .yres = { - .max = 320, - .min = 320, - .defval = 320, - }, - - .bpp = { - .min = 16, - .max = 16, - .defval = 16, - }, -}; - -static struct mtd_partition rx3715_nand_part[] = { - [0] = { - .name = "Whole Flash", - .offset = 0, - .size = MTDPART_SIZ_FULL, - .mask_flags = MTD_WRITEABLE, - } -}; - -static struct s3c2410_nand_set rx3715_nand_sets[] = { - [0] = { - .name = "Internal", - .nr_chips = 1, - .nr_partitions = ARRAY_SIZE(rx3715_nand_part), - .partitions = rx3715_nand_part, - }, -}; - -static struct s3c2410_platform_nand rx3715_nand_info = { - .tacls = 25, - .twrph0 = 50, - .twrph1 = 15, - .nr_sets = ARRAY_SIZE(rx3715_nand_sets), - .sets = rx3715_nand_sets, -}; - -static struct platform_device *rx3715_devices[] __initdata = { - &s3c_device_usb, - &s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c, - &s3c_device_iis, - &s3c_device_nand, -}; - -static struct s3c24xx_board rx3715_board __initdata = { - .devices = rx3715_devices, - .devices_count = ARRAY_SIZE(rx3715_devices) -}; - -static void __init rx3715_map_io(void) -{ - s3c_device_nand.dev.platform_data = &rx3715_nand_info; - - s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); - s3c24xx_init_clocks(16934000); - s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); - s3c24xx_set_board(&rx3715_board); -} - -static void __init rx3715_init_irq(void) -{ - s3c24xx_init_irq(); -} - -static void __init rx3715_init_machine(void) -{ - memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); - s3c2410_pm_init(); - - s3c24xx_fb_set_platdata(&rx3715_lcdcfg); -} - - -MACHINE_START(RX3715, "IPAQ-RX3715") - /* Maintainer: Ben Dooks */ - .phys_io = S3C2410_PA_UART, - .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, - .boot_params = S3C2410_SDRAM_PA + 0x100, - .map_io = rx3715_map_io, - .init_irq = rx3715_init_irq, - .init_machine = rx3715_init_machine, - .timer = &s3c24xx_timer, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c index 01c0c986d827..57b8a80f33d0 100644 --- a/arch/arm/mach-s3c2410/mach-smdk2410.c +++ b/arch/arm/mach-s3c2410/mach-smdk2410.c @@ -1,4 +1,4 @@ -/*********************************************************************** +/* linux/arch/arm/mach-s3c2410/mach-smdk2410.c * * linux/arch/arm/mach-s3c2410/mach-smdk2410.c * @@ -49,10 +49,10 @@ #include -#include "devs.h" -#include "cpu.h" +#include +#include -#include "common-smdk.h" +#include static struct map_desc smdk2410_iodesc[] __initdata = { /* nothing here yet */ diff --git a/arch/arm/mach-s3c2410/mach-smdk2413.c b/arch/arm/mach-s3c2410/mach-smdk2413.c deleted file mode 100644 index 4f89abd7a6df..000000000000 --- a/arch/arm/mach-s3c2410/mach-smdk2413.c +++ /dev/null @@ -1,140 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-smdk2413.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * Thanks to Dimity Andric (TomTom) and Steven Ryu (Samsung) for the - * loans of SMDK2413 to work with. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -//#include -#include -#include -#include - -#include -#include - -#include "s3c2410.h" -#include "s3c2412.h" -#include "clock.h" -#include "devs.h" -#include "cpu.h" - -#include "common-smdk.h" - -static struct map_desc smdk2413_iodesc[] __initdata = { -}; - -static struct s3c2410_uartcfg smdk2413_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, - /* IR port */ - [2] = { - .hwport = 2, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x43, - .ufcon = 0x51, - } -}; - -static struct platform_device *smdk2413_devices[] __initdata = { - &s3c_device_usb, - //&s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c, - &s3c_device_iis, -}; - -static struct s3c24xx_board smdk2413_board __initdata = { - .devices = smdk2413_devices, - .devices_count = ARRAY_SIZE(smdk2413_devices) -}; - -static void __init smdk2413_fixup(struct machine_desc *desc, - struct tag *tags, char **cmdline, - struct meminfo *mi) -{ - if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) { - mi->nr_banks=1; - mi->bank[0].start = 0x30000000; - mi->bank[0].size = SZ_64M; - mi->bank[0].node = 0; - } -} - -static void __init smdk2413_map_io(void) -{ - s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc)); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs)); - s3c24xx_set_board(&smdk2413_board); -} - -static void __init smdk2413_machine_init(void) -{ - smdk_machine_init(); -} - -MACHINE_START(S3C2413, "S3C2413") - /* Maintainer: Ben Dooks */ - .phys_io = S3C2410_PA_UART, - .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, - .boot_params = S3C2410_SDRAM_PA + 0x100, - - .fixup = smdk2413_fixup, - .init_irq = s3c24xx_init_irq, - .map_io = smdk2413_map_io, - .init_machine = smdk2413_machine_init, - .timer = &s3c24xx_timer, -MACHINE_END - -MACHINE_START(SMDK2413, "SMDK2413") - /* Maintainer: Ben Dooks */ - .phys_io = S3C2410_PA_UART, - .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, - .boot_params = S3C2410_SDRAM_PA + 0x100, - - .fixup = smdk2413_fixup, - .init_irq = s3c24xx_init_irq, - .map_io = smdk2413_map_io, - .init_machine = smdk2413_machine_init, - .timer = &s3c24xx_timer, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-smdk2440.c b/arch/arm/mach-s3c2410/mach-smdk2440.c deleted file mode 100644 index 2b61f4ed1da4..000000000000 --- a/arch/arm/mach-s3c2410/mach-smdk2440.c +++ /dev/null @@ -1,208 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-smdk2440.c - * - * Copyright (c) 2004,2005 Simtec Electronics - * Ben Dooks - * - * http://www.fluff.org/ben/smdk2440/ - * - * Thanks to Dimity Andric and TomTom for the loan of an SMDK2440. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -//#include -#include -#include -#include - -#include -#include - -#include "s3c2410.h" -#include "s3c2440.h" -#include "clock.h" -#include "devs.h" -#include "cpu.h" - -#include "common-smdk.h" - -static struct map_desc smdk2440_iodesc[] __initdata = { - /* ISA IO Space map (memory space selected by A24) */ - - { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS2), - .length = 0x10000, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, - .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), - .length = SZ_4M, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_BYTE, - .pfn = __phys_to_pfn(S3C2410_CS2), - .length = 0x10000, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000, - .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), - .length = SZ_4M, - .type = MT_DEVICE, - } -}; - -#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg smdk2440_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, - /* IR port */ - [2] = { - .hwport = 2, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x43, - .ufcon = 0x51, - } -}; - -/* LCD driver info */ - -static struct s3c2410fb_mach_info smdk2440_lcd_cfg __initdata = { - .regs = { - - .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | - S3C2410_LCDCON1_TFT | - S3C2410_LCDCON1_CLKVAL(0x04), - - .lcdcon2 = S3C2410_LCDCON2_VBPD(7) | - S3C2410_LCDCON2_LINEVAL(319) | - S3C2410_LCDCON2_VFPD(6) | - S3C2410_LCDCON2_VSPW(3), - - .lcdcon3 = S3C2410_LCDCON3_HBPD(19) | - S3C2410_LCDCON3_HOZVAL(239) | - S3C2410_LCDCON3_HFPD(7), - - .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | - S3C2410_LCDCON4_HSPW(3), - - .lcdcon5 = S3C2410_LCDCON5_FRM565 | - S3C2410_LCDCON5_INVVLINE | - S3C2410_LCDCON5_INVVFRAME | - S3C2410_LCDCON5_PWREN | - S3C2410_LCDCON5_HWSWP, - }, - -#if 0 - /* currently setup by downloader */ - .gpccon = 0xaa940659, - .gpccon_mask = 0xffffffff, - .gpcup = 0x0000ffff, - .gpcup_mask = 0xffffffff, - .gpdcon = 0xaa84aaa0, - .gpdcon_mask = 0xffffffff, - .gpdup = 0x0000faff, - .gpdup_mask = 0xffffffff, -#endif - - .lpcsel = ((0xCE6) & ~7) | 1<<4, - - .width = 240, - .height = 320, - - .xres = { - .min = 240, - .max = 240, - .defval = 240, - }, - - .yres = { - .min = 320, - .max = 320, - .defval = 320, - }, - - .bpp = { - .min = 16, - .max = 16, - .defval = 16, - }, -}; - -static struct platform_device *smdk2440_devices[] __initdata = { - &s3c_device_usb, - &s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c, - &s3c_device_iis, -}; - -static struct s3c24xx_board smdk2440_board __initdata = { - .devices = smdk2440_devices, - .devices_count = ARRAY_SIZE(smdk2440_devices) -}; - -static void __init smdk2440_map_io(void) -{ - s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc)); - s3c24xx_init_clocks(16934400); - s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs)); - s3c24xx_set_board(&smdk2440_board); -} - -static void __init smdk2440_machine_init(void) -{ - s3c24xx_fb_set_platdata(&smdk2440_lcd_cfg); - - smdk_machine_init(); -} - -MACHINE_START(S3C2440, "SMDK2440") - /* Maintainer: Ben Dooks */ - .phys_io = S3C2410_PA_UART, - .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, - .boot_params = S3C2410_SDRAM_PA + 0x100, - - .init_irq = s3c24xx_init_irq, - .map_io = smdk2440_map_io, - .init_machine = smdk2440_machine_init, - .timer = &s3c24xx_timer, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index a382fc095110..c947c75bcbf0 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c @@ -43,9 +43,9 @@ #include #include -#include "clock.h" -#include "devs.h" -#include "cpu.h" +#include +#include +#include #include "usb-simtec.h" /* macros for virtual address mods for the io space entries */ diff --git a/arch/arm/mach-s3c2410/mach-vstms.c b/arch/arm/mach-s3c2410/mach-vstms.c deleted file mode 100644 index 0360e1055bcd..000000000000 --- a/arch/arm/mach-s3c2410/mach-vstms.c +++ /dev/null @@ -1,169 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-vstms.c - * - * (C) 2006 Thomas Gleixner - * - * Derived from mach-smdk2413.c - (C) 2006 Simtec Electronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include - -#include "s3c2410.h" -#include "s3c2412.h" -#include "clock.h" -#include "devs.h" -#include "cpu.h" - - -static struct map_desc vstms_iodesc[] __initdata = { -}; - -static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - } -}; - -static struct mtd_partition vstms_nand_part[] = { - [0] = { - .name = "Boot Agent", - .size = 0x7C000, - .offset = 0, - }, - [1] = { - .name = "UBoot Config", - .offset = 0x7C000, - .size = 0x4000, - }, - [2] = { - .name = "Kernel", - .offset = 0x80000, - .size = 0x200000, - }, - [3] = { - .name = "RFS", - .offset = 0x280000, - .size = 0x3d80000, - }, -}; - -static struct s3c2410_nand_set vstms_nand_sets[] = { - [0] = { - .name = "NAND", - .nr_chips = 1, - .nr_partitions = ARRAY_SIZE(vstms_nand_part), - .partitions = vstms_nand_part, - }, -}; - -/* choose a set of timings which should suit most 512Mbit - * chips and beyond. -*/ - -static struct s3c2410_platform_nand vstms_nand_info = { - .tacls = 20, - .twrph0 = 60, - .twrph1 = 20, - .nr_sets = ARRAY_SIZE(vstms_nand_sets), - .sets = vstms_nand_sets, -}; - -static struct platform_device *vstms_devices[] __initdata = { - &s3c_device_usb, - &s3c_device_wdt, - &s3c_device_i2c, - &s3c_device_iis, - &s3c_device_rtc, - &s3c_device_nand, -}; - -static struct s3c24xx_board vstms_board __initdata = { - .devices = vstms_devices, - .devices_count = ARRAY_SIZE(vstms_devices) -}; - -static void __init vstms_fixup(struct machine_desc *desc, - struct tag *tags, char **cmdline, - struct meminfo *mi) -{ - if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) { - mi->nr_banks=1; - mi->bank[0].start = 0x30000000; - mi->bank[0].size = SZ_64M; - mi->bank[0].node = 0; - } -} - -static void __init vstms_map_io(void) -{ - s3c_device_nand.dev.platform_data = &vstms_nand_info; - - s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc)); - s3c24xx_init_clocks(12000000); - s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs)); - s3c24xx_set_board(&vstms_board); -} - -MACHINE_START(VSTMS, "VSTMS") - .phys_io = S3C2410_PA_UART, - .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, - .boot_params = S3C2410_SDRAM_PA + 0x100, - - .fixup = vstms_fixup, - .init_irq = s3c24xx_init_irq, - .map_io = vstms_map_io, - .timer = &s3c24xx_timer, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/pm-simtec.c b/arch/arm/mach-s3c2410/pm-simtec.c deleted file mode 100644 index 619133eb7168..000000000000 --- a/arch/arm/mach-s3c2410/pm-simtec.c +++ /dev/null @@ -1,66 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/pm-simtec.c - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks - * - * http://armlinux.simtec.co.uk/ - * - * Power Management helpers for Simtec S3C24XX implementations - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include -#include -#include - -#include - -#include "pm.h" - -#define COPYRIGHT ", (c) 2005 Simtec Electronics" - -/* pm_simtec_init - * - * enable the power management functions -*/ - -static __init int pm_simtec_init(void) -{ - unsigned long gstatus4; - - /* check which machine we are running on */ - - if (!machine_is_bast() && !machine_is_vr1000() && - !machine_is_anubis() && !machine_is_osiris() && - !machine_is_aml_m5900()) - return 0; - - printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n"); - - gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30; - gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28; - gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK); - - __raw_writel(gstatus4, S3C2410_GSTATUS4); - - return s3c2410_pm_init(); -} - -arch_initcall(pm_simtec_init); diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index ebf294dd31da..3b3a7db4e0dd 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c @@ -1,11 +1,9 @@ /* linux/arch/arm/mach-s3c2410/pm.c * - * Copyright (c) 2004,2006 Simtec Electronics + * Copyright (c) 2006 Simtec Electronics * Ben Dooks * - * S3C24XX Power Manager (Suspend-To-RAM) support - * - * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information + * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,640 +18,139 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Parts based on arch/arm/mach-pxa/pm.c - * - * Thanks to Dimitry Andric for debugging */ #include #include #include #include -#include -#include -#include -#include -#include +#include -#include #include #include -#include -#include -#include -#include -#include - -#include - -#include "pm.h" - -/* for external use */ - -unsigned long s3c_pm_flags; - -#define PFX "s3c24xx-pm: " - -static struct sleep_save core_save[] = { - SAVE_ITEM(S3C2410_LOCKTIME), - SAVE_ITEM(S3C2410_CLKCON), - - /* we restore the timings here, with the proviso that the board - * brings the system up in an slower, or equal frequency setting - * to the original system. - * - * if we cannot guarantee this, then things are going to go very - * wrong here, as we modify the refresh and both pll settings. - */ - - SAVE_ITEM(S3C2410_BWSCON), - SAVE_ITEM(S3C2410_BANKCON0), - SAVE_ITEM(S3C2410_BANKCON1), - SAVE_ITEM(S3C2410_BANKCON2), - SAVE_ITEM(S3C2410_BANKCON3), - SAVE_ITEM(S3C2410_BANKCON4), - SAVE_ITEM(S3C2410_BANKCON5), - - SAVE_ITEM(S3C2410_CLKDIVN), - SAVE_ITEM(S3C2410_MPLLCON), - SAVE_ITEM(S3C2410_UPLLCON), - SAVE_ITEM(S3C2410_CLKSLOW), - SAVE_ITEM(S3C2410_REFRESH), -}; - -static struct sleep_save gpio_save[] = { - SAVE_ITEM(S3C2410_GPACON), - SAVE_ITEM(S3C2410_GPADAT), - - SAVE_ITEM(S3C2410_GPBCON), - SAVE_ITEM(S3C2410_GPBDAT), - SAVE_ITEM(S3C2410_GPBUP), - - SAVE_ITEM(S3C2410_GPCCON), - SAVE_ITEM(S3C2410_GPCDAT), - SAVE_ITEM(S3C2410_GPCUP), - - SAVE_ITEM(S3C2410_GPDCON), - SAVE_ITEM(S3C2410_GPDDAT), - SAVE_ITEM(S3C2410_GPDUP), - - SAVE_ITEM(S3C2410_GPECON), - SAVE_ITEM(S3C2410_GPEDAT), - SAVE_ITEM(S3C2410_GPEUP), - - SAVE_ITEM(S3C2410_GPFCON), - SAVE_ITEM(S3C2410_GPFDAT), - SAVE_ITEM(S3C2410_GPFUP), +#include - SAVE_ITEM(S3C2410_GPGCON), - SAVE_ITEM(S3C2410_GPGDAT), - SAVE_ITEM(S3C2410_GPGUP), - - SAVE_ITEM(S3C2410_GPHCON), - SAVE_ITEM(S3C2410_GPHDAT), - SAVE_ITEM(S3C2410_GPHUP), +#include +#include - SAVE_ITEM(S3C2410_DCLKCON), -}; +#include +#include #ifdef CONFIG_S3C2410_PM_DEBUG - -#define SAVE_UART(va) \ - SAVE_ITEM((va) + S3C2410_ULCON), \ - SAVE_ITEM((va) + S3C2410_UCON), \ - SAVE_ITEM((va) + S3C2410_UFCON), \ - SAVE_ITEM((va) + S3C2410_UMCON), \ - SAVE_ITEM((va) + S3C2410_UBRDIV) - -static struct sleep_save uart_save[] = { - SAVE_UART(S3C24XX_VA_UART0), - SAVE_UART(S3C24XX_VA_UART1), -#ifndef CONFIG_CPU_S3C2400 - SAVE_UART(S3C24XX_VA_UART2), -#endif -}; - -/* debug - * - * we send the debug to printascii() to allow it to be seen if the - * system never wakes up from the sleep -*/ - -extern void printascii(const char *); - -void pm_dbg(const char *fmt, ...) -{ - va_list va; - char buff[256]; - - va_start(va, fmt); - vsprintf(buff, fmt, va); - va_end(va); - - printascii(buff); -} - -static void s3c2410_pm_debug_init(void) -{ - unsigned long tmp = __raw_readl(S3C2410_CLKCON); - - /* re-start uart clocks */ - tmp |= S3C2410_CLKCON_UART0; - tmp |= S3C2410_CLKCON_UART1; - tmp |= S3C2410_CLKCON_UART2; - - __raw_writel(tmp, S3C2410_CLKCON); - udelay(10); -} - +extern void pm_dbg(const char *fmt, ...); #define DBG(fmt...) pm_dbg(fmt) #else #define DBG(fmt...) printk(KERN_DEBUG fmt) - -#define s3c2410_pm_debug_init() do { } while(0) - -static struct sleep_save uart_save[] = {}; #endif -#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0 - -/* suspend checking code... - * - * this next area does a set of crc checks over all the installed - * memory, so the system can verify if the resume was ok. - * - * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, - * increasing it will mean that the area corrupted will be less easy to spot, - * and reducing the size will cause the CRC save area to grow -*/ - -#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) - -static u32 crc_size; /* size needed for the crc block */ -static u32 *crcs; /* allocated over suspend/resume */ - -typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); - -/* s3c2410_pm_run_res - * - * go thorugh the given resource list, and look for system ram -*/ - -static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) -{ - while (ptr != NULL) { - if (ptr->child != NULL) - s3c2410_pm_run_res(ptr->child, fn, arg); - - if ((ptr->flags & IORESOURCE_MEM) && - strcmp(ptr->name, "System RAM") == 0) { - DBG("Found system RAM at %08lx..%08lx\n", - ptr->start, ptr->end); - arg = (fn)(ptr, arg); - } - - ptr = ptr->sibling; - } -} - -static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg) -{ - s3c2410_pm_run_res(&iomem_resource, fn, arg); -} - -static u32 *s3c2410_pm_countram(struct resource *res, u32 *val) -{ - u32 size = (u32)(res->end - res->start)+1; - - size += CHECK_CHUNKSIZE-1; - size /= CHECK_CHUNKSIZE; - - DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size); - - *val += size * sizeof(u32); - return val; -} - -/* s3c2410_pm_prepare_check - * - * prepare the necessary information for creating the CRCs. This - * must be done before the final save, as it will require memory - * allocating, and thus touching bits of the kernel we do not - * know about. -*/ - -static void s3c2410_pm_check_prepare(void) +static void s3c2410_pm_prepare(void) { - crc_size = 0; + /* ensure at least GSTATUS3 has the resume address */ - s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size); + __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3); - DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size); + DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); + DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); - crcs = kmalloc(crc_size+4, GFP_KERNEL); - if (crcs == NULL) - printk(KERN_ERR "Cannot allocated CRC save area\n"); -} + if (machine_is_h1940()) { + void *base = phys_to_virt(H1940_SUSPEND_CHECK); + unsigned long ptr; + unsigned long calc = 0; -static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val) -{ - unsigned long addr, left; + /* generate check for the bootloader to check on resume */ - for (addr = res->start; addr < res->end; - addr += CHECK_CHUNKSIZE) { - left = res->end - addr; + for (ptr = 0; ptr < 0x40000; ptr += 0x400) + calc += __raw_readl(base+ptr); - if (left > CHECK_CHUNKSIZE) - left = CHECK_CHUNKSIZE; - - *val = crc32_le(~0, phys_to_virt(addr), left); - val++; + __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); } - return val; -} - -/* s3c2410_pm_check_store - * - * compute the CRC values for the memory blocks before the final - * sleep. -*/ - -static void s3c2410_pm_check_store(void) -{ - if (crcs != NULL) - s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs); -} - -/* in_region - * - * return TRUE if the area defined by ptr..ptr+size contatins the - * what..what+whatsz -*/ - -static inline int in_region(void *ptr, int size, void *what, size_t whatsz) -{ - if ((what+whatsz) < ptr) - return 0; - - if (what > (ptr+size)) - return 0; - - return 1; -} - -static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val) -{ - void *save_at = phys_to_virt(s3c2410_sleep_save_phys); - unsigned long addr; - unsigned long left; - void *ptr; - u32 calc; - - for (addr = res->start; addr < res->end; - addr += CHECK_CHUNKSIZE) { - left = res->end - addr; + /* the RX3715 uses similar code and the same H1940 and the + * same offsets for resume and checksum pointers */ - if (left > CHECK_CHUNKSIZE) - left = CHECK_CHUNKSIZE; + if (machine_is_rx3715()) { + void *base = phys_to_virt(H1940_SUSPEND_CHECK); + unsigned long ptr; + unsigned long calc = 0; - ptr = phys_to_virt(addr); + /* generate check for the bootloader to check on resume */ - if (in_region(ptr, left, crcs, crc_size)) { - DBG("skipping %08lx, has crc block in\n", addr); - goto skip_check; - } + for (ptr = 0; ptr < 0x40000; ptr += 0x4) + calc += __raw_readl(base+ptr); - if (in_region(ptr, left, save_at, 32*4 )) { - DBG("skipping %08lx, has save block in\n", addr); - goto skip_check; - } - - /* calculate and check the checksum */ - - calc = crc32_le(~0, ptr, left); - if (calc != *val) { - printk(KERN_ERR PFX "Restore CRC error at " - "%08lx (%08x vs %08x)\n", addr, calc, *val); - - DBG("Restore CRC error at %08lx (%08x vs %08x)\n", - addr, calc, *val); - } - - skip_check: - val++; + __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); } - return val; -} + if ( machine_is_aml_m5900() ) + s3c2410_gpio_setpin(S3C2410_GPF2, 1); -/* s3c2410_pm_check_restore - * - * check the CRCs after the restore event and free the memory used - * to hold them -*/ - -static void s3c2410_pm_check_restore(void) -{ - if (crcs != NULL) { - s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs); - kfree(crcs); - crcs = NULL; - } } -#else - -#define s3c2410_pm_check_prepare() do { } while(0) -#define s3c2410_pm_check_restore() do { } while(0) -#define s3c2410_pm_check_store() do { } while(0) -#endif - -/* helper functions to save and restore register state */ - -void s3c2410_pm_do_save(struct sleep_save *ptr, int count) +static int s3c2410_pm_resume(struct sys_device *dev) { - for (; count > 0; count--, ptr++) { - ptr->val = __raw_readl(ptr->reg); - DBG("saved %p value %08lx\n", ptr->reg, ptr->val); - } -} + unsigned long tmp; -/* s3c2410_pm_do_restore - * - * restore the system from the given list of saved registers - * - * Note, we do not use DBG() in here, as the system may not have - * restore the UARTs state yet -*/ + /* unset the return-from-sleep flag, to ensure reset */ -void s3c2410_pm_do_restore(struct sleep_save *ptr, int count) -{ - for (; count > 0; count--, ptr++) { - printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", - ptr->reg, ptr->val, __raw_readl(ptr->reg)); - - __raw_writel(ptr->val, ptr->reg); - } -} + tmp = __raw_readl(S3C2410_GSTATUS2); + tmp &= S3C2410_GSTATUS2_OFFRESET; + __raw_writel(tmp, S3C2410_GSTATUS2); -/* s3c2410_pm_do_restore_core - * - * similar to s3c2410_pm_do_restore_core - * - * WARNING: Do not put any debug in here that may effect memory or use - * peripherals, as things may be changing! -*/ + if ( machine_is_aml_m5900() ) + s3c2410_gpio_setpin(S3C2410_GPF2, 0); -static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count) -{ - for (; count > 0; count--, ptr++) { - __raw_writel(ptr->val, ptr->reg); - } + return 0; } -/* s3c2410_pm_show_resume_irqs - * - * print any IRQs asserted at resume time (ie, we woke from) -*/ - -static void s3c2410_pm_show_resume_irqs(int start, unsigned long which, - unsigned long mask) +static int s3c2410_pm_add(struct sys_device *dev) { - int i; + pm_cpu_prep = s3c2410_pm_prepare; + pm_cpu_sleep = s3c2410_cpu_suspend; - which &= ~mask; - - for (i = 0; i <= 31; i++) { - if ((which) & (1L< - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* s3c2410_pm_init - * - * called from board at initialisation time to setup the power - * management -*/ - -#ifdef CONFIG_PM - -extern __init int s3c2410_pm_init(void); - -#else - -static inline int s3c2410_pm_init(void) -{ - return 0; -} -#endif - -/* configuration for the IRQ mask over sleep */ -extern unsigned long s3c_irqwake_intmask; -extern unsigned long s3c_irqwake_eintmask; - -/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */ -extern unsigned long s3c_irqwake_intallow; -extern unsigned long s3c_irqwake_eintallow; - -/* per-cpu sleep functions */ - -extern void (*pm_cpu_prep)(void); -extern void (*pm_cpu_sleep)(void); - -/* Flags for PM Control */ - -extern unsigned long s3c_pm_flags; - -/* from sleep.S */ - -extern int s3c2410_cpu_save(unsigned long *saveblk); -extern void s3c2410_cpu_suspend(void); -extern void s3c2410_cpu_resume(void); - -extern unsigned long s3c2410_sleep_save_phys; - -/* sleep save info */ - -struct sleep_save { - void __iomem *reg; - unsigned long val; -}; - -#define SAVE_ITEM(x) \ - { .reg = (x) } - -extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count); -extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count); - -#ifdef CONFIG_PM -extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state); -extern int s3c24xx_irq_resume(struct sys_device *dev); -#else -#define s3c24xx_irq_suspend NULL -#define s3c24xx_irq_resume NULL -#endif diff --git a/arch/arm/mach-s3c2410/s3c2400-gpio.c b/arch/arm/mach-s3c2410/s3c2400-gpio.c deleted file mode 100644 index 1576d01d5f82..000000000000 --- a/arch/arm/mach-s3c2410/s3c2400-gpio.c +++ /dev/null @@ -1,42 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2400-gpio.c - * - * Copyright (c) 2006 Lucas Correia Villa Real - * - * S3C2400 GPIO support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -int s3c2400_gpio_getirq(unsigned int pin) -{ - if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7) - return -1; /* not valid interrupts */ - - return (pin - S3C2410_GPE0) + IRQ_EINT0; -} - -EXPORT_SYMBOL(s3c2400_gpio_getirq); diff --git a/arch/arm/mach-s3c2410/s3c2400.h b/arch/arm/mach-s3c2410/s3c2400.h deleted file mode 100644 index 8b2394e1ed40..000000000000 --- a/arch/arm/mach-s3c2410/s3c2400.h +++ /dev/null @@ -1,31 +0,0 @@ -/* arch/arm/mach-s3c2410/s3c2400.h - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks - * - * Header file for S3C2400 cpu support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 09-Fev-2006 LCVR First version, based on s3c2410.h -*/ - -#ifdef CONFIG_CPU_S3C2400 - -extern int s3c2400_init(void); - -extern void s3c2400_map_io(struct map_desc *mach_desc, int size); - -extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no); - -extern void s3c2400_init_clocks(int xtal); - -#else -#define s3c2400_init_clocks NULL -#define s3c2400_init_uarts NULL -#define s3c2400_map_io NULL -#define s3c2400_init NULL -#endif diff --git a/arch/arm/mach-s3c2410/s3c2410-clock.c b/arch/arm/mach-s3c2410/s3c2410-clock.c deleted file mode 100644 index 992cc6af230e..000000000000 --- a/arch/arm/mach-s3c2410/s3c2410-clock.c +++ /dev/null @@ -1,276 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2410-clock.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * S3C2410,S3C2440,S3C2442 Clock control support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include -#include -#include - -#include "s3c2410.h" -#include "clock.h" -#include "cpu.h" - -int s3c2410_clkcon_enable(struct clk *clk, int enable) -{ - unsigned int clocks = clk->ctrlbit; - unsigned long clkcon; - - clkcon = __raw_readl(S3C2410_CLKCON); - - if (enable) - clkcon |= clocks; - else - clkcon &= ~clocks; - - /* ensure none of the special function bits set */ - clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER); - - __raw_writel(clkcon, S3C2410_CLKCON); - - return 0; -} - -static int s3c2410_upll_enable(struct clk *clk, int enable) -{ - unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); - unsigned long orig = clkslow; - - if (enable) - clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF; - else - clkslow |= S3C2410_CLKSLOW_UCLK_OFF; - - __raw_writel(clkslow, S3C2410_CLKSLOW); - - /* if we started the UPLL, then allow to settle */ - - if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF)) - udelay(200); - - return 0; -} - -/* standard clock definitions */ - -static struct clk init_clocks_disable[] = { - { - .name = "nand", - .id = -1, - .parent = &clk_h, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_NAND, - }, { - .name = "sdi", - .id = -1, - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_SDI, - }, { - .name = "adc", - .id = -1, - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_ADC, - }, { - .name = "i2c", - .id = -1, - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_IIC, - }, { - .name = "iis", - .id = -1, - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_IIS, - }, { - .name = "spi", - .id = -1, - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_SPI, - } -}; - -static struct clk init_clocks[] = { - { - .name = "lcd", - .id = -1, - .parent = &clk_h, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_LCDC, - }, { - .name = "gpio", - .id = -1, - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_GPIO, - }, { - .name = "usb-host", - .id = -1, - .parent = &clk_h, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_USBH, - }, { - .name = "usb-device", - .id = -1, - .parent = &clk_h, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_USBD, - }, { - .name = "timers", - .id = -1, - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_PWMT, - }, { - .name = "uart", - .id = 0, - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_UART0, - }, { - .name = "uart", - .id = 1, - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_UART1, - }, { - .name = "uart", - .id = 2, - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_UART2, - }, { - .name = "rtc", - .id = -1, - .parent = &clk_p, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2410_CLKCON_RTC, - }, { - .name = "watchdog", - .id = -1, - .parent = &clk_p, - .ctrlbit = 0, - }, { - .name = "usb-bus-host", - .id = -1, - .parent = &clk_usb_bus, - }, { - .name = "usb-bus-gadget", - .id = -1, - .parent = &clk_usb_bus, - }, -}; - -/* s3c2410_baseclk_add() - * - * Add all the clocks used by the s3c2410 or compatible CPUs - * such as the S3C2440 and S3C2442. - * - * We cannot use a system device as we are needed before any - * of the init-calls that initialise the devices are actually - * done. -*/ - -int __init s3c2410_baseclk_add(void) -{ - unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); - unsigned long clkcon = __raw_readl(S3C2410_CLKCON); - struct clk *clkp; - struct clk *xtal; - int ret; - int ptr; - - clk_upll.enable = s3c2410_upll_enable; - - if (s3c24xx_register_clock(&clk_usb_bus) < 0) - printk(KERN_ERR "failed to register usb bus clock\n"); - - /* register clocks from clock array */ - - clkp = init_clocks; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { - /* ensure that we note the clock state */ - - clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0; - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } - - /* We must be careful disabling the clocks we are not intending to - * be using at boot time, as subsytems such as the LCD which do - * their own DMA requests to the bus can cause the system to lockup - * if they where in the middle of requesting bus access. - * - * Disabling the LCD clock if the LCD is active is very dangerous, - * and therefore the bootloader should be careful to not enable - * the LCD clock if it is not needed. - */ - - /* install (and disable) the clocks we do not need immediately */ - - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - - s3c2410_clkcon_enable(clkp, 0); - } - - /* show the clock-slow value */ - - xtal = clk_get(NULL, "xtal"); - - printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n", - print_mhz(clk_get_rate(xtal) / - ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))), - (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast", - (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", - (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); - - return 0; -} diff --git a/arch/arm/mach-s3c2410/s3c2410-dma.c b/arch/arm/mach-s3c2410/s3c2410-dma.c deleted file mode 100644 index e67ba3911f11..000000000000 --- a/arch/arm/mach-s3c2410/s3c2410-dma.c +++ /dev/null @@ -1,161 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2410-dma.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * S3C2410 DMA selection - * - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include - -#include -#include -#include "dma.h" - -#include "cpu.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { - [DMACH_XD0] = { - .name = "xdreq0", - .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID, - }, - [DMACH_XD1] = { - .name = "xdreq1", - .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID, - }, - [DMACH_SDI] = { - .name = "sdi", - .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID, - .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, - .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, - .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, - }, - [DMACH_SPI0] = { - .name = "spi0", - .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, - }, - [DMACH_SPI1] = { - .name = "spi1", - .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, - }, - [DMACH_UART0] = { - .name = "uart0", - .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, - }, - [DMACH_UART1] = { - .name = "uart1", - .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, - }, - [DMACH_UART2] = { - .name = "uart2", - .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, - }, - [DMACH_TIMER] = { - .name = "timer", - .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID, - .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID, - .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID, - }, - [DMACH_I2S_IN] = { - .name = "i2s-sdi", - .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, - .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, - .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, - }, - [DMACH_I2S_OUT] = { - .name = "i2s-sdo", - .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, - }, - [DMACH_USB_EP1] = { - .name = "usb-ep1", - .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID, - }, - [DMACH_USB_EP2] = { - .name = "usb-ep2", - .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID, - }, - [DMACH_USB_EP3] = { - .name = "usb-ep3", - .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID, - }, - [DMACH_USB_EP4] = { - .name = "usb-ep4", - .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID, - }, -}; - -static void s3c2410_dma_select(struct s3c2410_dma_chan *chan, - struct s3c24xx_dma_map *map) -{ - chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID; -} - -static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = { - .select = s3c2410_dma_select, - .dcon_mask = 7 << 24, - .map = s3c2410_dma_mappings, - .map_size = ARRAY_SIZE(s3c2410_dma_mappings), -}; - -static int s3c2410_dma_add(struct sys_device *sysdev) -{ - return s3c24xx_dma_init_map(&s3c2410_dma_sel); -} - -#if defined(CONFIG_CPU_S3C2410) -static struct sysdev_driver s3c2410_dma_driver = { - .add = s3c2410_dma_add, -}; - -static int __init s3c2410_dma_init(void) -{ - return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver); -} - -arch_initcall(s3c2410_dma_init); -#endif - -#if defined(CONFIG_CPU_S3C2442) -/* S3C2442 DMA contains the same selection table as the S3C2410 */ -static struct sysdev_driver s3c2442_dma_driver = { - .add = s3c2410_dma_add, -}; - -static int __init s3c2442_dma_init(void) -{ - return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver); -} - -arch_initcall(s3c2442_dma_init); -#endif - diff --git a/arch/arm/mach-s3c2410/s3c2410-gpio.c b/arch/arm/mach-s3c2410/s3c2410-gpio.c deleted file mode 100644 index ec3a276cc3cf..000000000000 --- a/arch/arm/mach-s3c2410/s3c2410-gpio.c +++ /dev/null @@ -1,71 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2410-gpio.c - * - * Copyright (c) 2004-2006 Simtec Electronics - * Ben Dooks - * - * S3C2410 GPIO support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, - unsigned int config) -{ - void __iomem *reg = S3C24XX_EINFLT0; - unsigned long flags; - unsigned long val; - - if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15) - return -1; - - config &= 0xff; - - pin -= S3C2410_GPG8; - reg += pin & ~3; - - local_irq_save(flags); - - /* update filter width and clock source */ - - val = __raw_readl(reg); - val &= ~(0xff << ((pin & 3) * 8)); - val |= config << ((pin & 3) * 8); - __raw_writel(val, reg); - - /* update filter enable */ - - val = __raw_readl(S3C24XX_EXTINT2); - val &= ~(1 << ((pin * 4) + 3)); - val |= on << ((pin * 4) + 3); - __raw_writel(val, S3C24XX_EXTINT2); - - local_irq_restore(flags); - - return 0; -} - -EXPORT_SYMBOL(s3c2410_gpio_irqfilter); diff --git a/arch/arm/mach-s3c2410/s3c2410-irq.c b/arch/arm/mach-s3c2410/s3c2410-irq.c deleted file mode 100644 index c796c9c76e78..000000000000 --- a/arch/arm/mach-s3c2410/s3c2410-irq.c +++ /dev/null @@ -1,48 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2410-irq.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * -*/ - -#include -#include -#include -#include -#include -#include - -#include "cpu.h" -#include "pm.h" - -static int s3c2410_irq_add(struct sys_device *sysdev) -{ - return 0; -} - -static struct sysdev_driver s3c2410_irq_driver = { - .add = s3c2410_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, -}; - -static int s3c2410_irq_init(void) -{ - return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver); -} - -arch_initcall(s3c2410_irq_init); diff --git a/arch/arm/mach-s3c2410/s3c2410-pm.c b/arch/arm/mach-s3c2410/s3c2410-pm.c deleted file mode 100644 index 8bb6e5e21f59..000000000000 --- a/arch/arm/mach-s3c2410/s3c2410-pm.c +++ /dev/null @@ -1,156 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2410-pm.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include - -#include "cpu.h" -#include "pm.h" - -#ifdef CONFIG_S3C2410_PM_DEBUG -extern void pm_dbg(const char *fmt, ...); -#define DBG(fmt...) pm_dbg(fmt) -#else -#define DBG(fmt...) printk(KERN_DEBUG fmt) -#endif - -static void s3c2410_pm_prepare(void) -{ - /* ensure at least GSTATUS3 has the resume address */ - - __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3); - - DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); - DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); - - if (machine_is_h1940()) { - void *base = phys_to_virt(H1940_SUSPEND_CHECK); - unsigned long ptr; - unsigned long calc = 0; - - /* generate check for the bootloader to check on resume */ - - for (ptr = 0; ptr < 0x40000; ptr += 0x400) - calc += __raw_readl(base+ptr); - - __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); - } - - /* the RX3715 uses similar code and the same H1940 and the - * same offsets for resume and checksum pointers */ - - if (machine_is_rx3715()) { - void *base = phys_to_virt(H1940_SUSPEND_CHECK); - unsigned long ptr; - unsigned long calc = 0; - - /* generate check for the bootloader to check on resume */ - - for (ptr = 0; ptr < 0x40000; ptr += 0x4) - calc += __raw_readl(base+ptr); - - __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); - } - - if ( machine_is_aml_m5900() ) - s3c2410_gpio_setpin(S3C2410_GPF2, 1); - -} - -static int s3c2410_pm_resume(struct sys_device *dev) -{ - unsigned long tmp; - - /* unset the return-from-sleep flag, to ensure reset */ - - tmp = __raw_readl(S3C2410_GSTATUS2); - tmp &= S3C2410_GSTATUS2_OFFRESET; - __raw_writel(tmp, S3C2410_GSTATUS2); - - if ( machine_is_aml_m5900() ) - s3c2410_gpio_setpin(S3C2410_GPF2, 0); - - return 0; -} - -static int s3c2410_pm_add(struct sys_device *dev) -{ - pm_cpu_prep = s3c2410_pm_prepare; - pm_cpu_sleep = s3c2410_cpu_suspend; - - return 0; -} - -#if defined(CONFIG_CPU_S3C2410) -static struct sysdev_driver s3c2410_pm_driver = { - .add = s3c2410_pm_add, - .resume = s3c2410_pm_resume, -}; - -/* register ourselves */ - -static int __init s3c2410_pm_drvinit(void) -{ - return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_pm_driver); -} - -arch_initcall(s3c2410_pm_drvinit); -#endif - -#if defined(CONFIG_CPU_S3C2440) -static struct sysdev_driver s3c2440_pm_driver = { - .add = s3c2410_pm_add, - .resume = s3c2410_pm_resume, -}; - -static int __init s3c2440_pm_drvinit(void) -{ - return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_pm_driver); -} - -arch_initcall(s3c2440_pm_drvinit); -#endif - -#if defined(CONFIG_CPU_S3C2442) -static struct sysdev_driver s3c2442_pm_driver = { - .add = s3c2410_pm_add, - .resume = s3c2410_pm_resume, -}; - -static int __init s3c2442_pm_drvinit(void) -{ - return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_pm_driver); -} - -arch_initcall(s3c2442_pm_drvinit); -#endif diff --git a/arch/arm/mach-s3c2410/s3c2410-sleep.S b/arch/arm/mach-s3c2410/s3c2410-sleep.S deleted file mode 100644 index 9179a1024588..000000000000 --- a/arch/arm/mach-s3c2410/s3c2410-sleep.S +++ /dev/null @@ -1,68 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2410-sleep.S - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks - * - * S3C2410 Power Manager (Suspend-To-RAM) support - * - * Based on PXA/SA1100 sleep code by: - * Nicolas Pitre, (c) 2002 Monta Vista Software Inc - * Cliff Brake, (c) 2001 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include - -#include -#include -#include -#include - - /* s3c2410_cpu_suspend - * - * put the cpu into sleep mode - */ - -ENTRY(s3c2410_cpu_suspend) - @@ prepare cpu to sleep - - ldr r4, =S3C2410_REFRESH - ldr r5, =S3C24XX_MISCCR - ldr r6, =S3C2410_CLKCON - ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB) - ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB) - ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB) - - orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command - orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals - orr r9, r9, #S3C2410_CLKCON_POWER @ power down command - - teq pc, #0 @ first as a trial-run to load cache - bl s3c2410_do_sleep - teq r0, r0 @ now do it for real - b s3c2410_do_sleep @ - - @@ align next bit of code to cache line - .align 8 -s3c2410_do_sleep: - streq r7, [ r4 ] @ SDRAM sleep command - streq r8, [ r5 ] @ SDRAM power-down config - streq r9, [ r6 ] @ CPU sleep -1: beq 1b - mov pc, r14 diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index 4cdc0d70c19f..d96fdcf2d2e3 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c @@ -31,10 +31,10 @@ #include #include -#include "s3c2410.h" -#include "cpu.h" -#include "devs.h" -#include "clock.h" +#include +#include +#include +#include /* Initial IO mappings */ diff --git a/arch/arm/mach-s3c2410/s3c2410.h b/arch/arm/mach-s3c2410/s3c2410.h deleted file mode 100644 index fbed084f26d0..000000000000 --- a/arch/arm/mach-s3c2410/s3c2410.h +++ /dev/null @@ -1,31 +0,0 @@ -/* arch/arm/mach-s3c2410/s3c2410.h - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks - * - * Header file for s3c2410 machine directory - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#ifdef CONFIG_CPU_S3C2410 - -extern int s3c2410_init(void); - -extern void s3c2410_map_io(struct map_desc *mach_desc, int size); - -extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); - -extern void s3c2410_init_clocks(int xtal); - -extern int s3c2410_baseclk_add(void); - -#else -#define s3c2410_init_clocks NULL -#define s3c2410_init_uarts NULL -#define s3c2410_map_io NULL -#define s3c2410_init NULL -#endif diff --git a/arch/arm/mach-s3c2410/s3c2412-clock.c b/arch/arm/mach-s3c2410/s3c2412-clock.c deleted file mode 100644 index 8f94ad83901d..000000000000 --- a/arch/arm/mach-s3c2410/s3c2412-clock.c +++ /dev/null @@ -1,716 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2412-clock.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * S3C2412,S3C2413 Clock control support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include -#include -#include - -#include "s3c2412.h" -#include "clock.h" -#include "cpu.h" - -/* We currently have to assume that the system is running - * from the XTPll input, and that all ***REFCLKs are being - * fed from it, as we cannot read the state of OM[4] from - * software. - * - * It would be possible for each board initialisation to - * set the correct muxing at initialisation -*/ - -static int s3c2412_clkcon_enable(struct clk *clk, int enable) -{ - unsigned int clocks = clk->ctrlbit; - unsigned long clkcon; - - clkcon = __raw_readl(S3C2410_CLKCON); - - if (enable) - clkcon |= clocks; - else - clkcon &= ~clocks; - - __raw_writel(clkcon, S3C2410_CLKCON); - - return 0; -} - -static int s3c2412_upll_enable(struct clk *clk, int enable) -{ - unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); - unsigned long orig = upllcon; - - if (!enable) - upllcon |= S3C2412_PLLCON_OFF; - else - upllcon &= ~S3C2412_PLLCON_OFF; - - __raw_writel(upllcon, S3C2410_UPLLCON); - - /* allow ~150uS for the PLL to settle and lock */ - - if (enable && (orig & S3C2412_PLLCON_OFF)) - udelay(150); - - return 0; -} - -/* clock selections */ - -/* CPU EXTCLK input */ -static struct clk clk_ext = { - .name = "extclk", - .id = -1, -}; - -static struct clk clk_erefclk = { - .name = "erefclk", - .id = -1, -}; - -static struct clk clk_urefclk = { - .name = "urefclk", - .id = -1, -}; - -static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_urefclk) - clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL; - else if (parent == &clk_upll) - clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static struct clk clk_usysclk = { - .name = "usysclk", - .id = -1, - .parent = &clk_xtal, - .set_parent = s3c2412_setparent_usysclk, -}; - -static struct clk clk_mrefclk = { - .name = "mrefclk", - .parent = &clk_xtal, - .id = -1, -}; - -static struct clk clk_mdivclk = { - .name = "mdivclk", - .parent = &clk_xtal, - .id = -1, -}; - -static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_usysclk) - clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK; - else if (parent == &clk_h) - clksrc |= S3C2412_CLKSRC_USBCLK_HCLK; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - return parent_rate; - - div = parent_rate / rate; - if (div > 2) - div = 2; - - return parent_rate / div; -} - -static unsigned long s3c2412_getrate_usbsrc(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2410_CLKDIVN); - - return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1); -} - -static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); - - rate = s3c2412_roundrate_usbsrc(clk, rate); - - if ((parent_rate / rate) == 2) - clkdivn |= S3C2412_CLKDIVN_USB48DIV; - else - clkdivn &= ~S3C2412_CLKDIVN_USB48DIV; - - __raw_writel(clkdivn, S3C2410_CLKDIVN); - return 0; -} - -static struct clk clk_usbsrc = { - .name = "usbsrc", - .id = -1, - .get_rate = s3c2412_getrate_usbsrc, - .set_rate = s3c2412_setrate_usbsrc, - .round_rate = s3c2412_roundrate_usbsrc, - .set_parent = s3c2412_setparent_usbsrc, -}; - -static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_mdivclk) - clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL; - else if (parent == &clk_upll) - clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static struct clk clk_msysclk = { - .name = "msysclk", - .id = -1, - .set_parent = s3c2412_setparent_msysclk, -}; - -/* these next clocks have an divider immediately after them, - * so we can register them with their divider and leave out the - * intermediate clock stage -*/ -static unsigned long s3c2412_roundrate_clksrc(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - return parent_rate; - - /* note, we remove the +/- 1 calculations as they cancel out */ - - div = (rate / parent_rate); - - if (div < 1) - div = 1; - else if (div > 16) - div = 16; - - return parent_rate / div; -} - -static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_erefclk) - clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL; - else if (parent == &clk_mpll) - clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static unsigned long s3c2412_getrate_uart(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2410_CLKDIVN); - - div &= S3C2412_CLKDIVN_UARTDIV_MASK; - div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); - - rate = s3c2412_roundrate_clksrc(clk, rate); - - clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK; - clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT; - - __raw_writel(clkdivn, S3C2410_CLKDIVN); - return 0; -} - -static struct clk clk_uart = { - .name = "uartclk", - .id = -1, - .get_rate = s3c2412_getrate_uart, - .set_rate = s3c2412_setrate_uart, - .set_parent = s3c2412_setparent_uart, - .round_rate = s3c2412_roundrate_clksrc, -}; - -static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_erefclk) - clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL; - else if (parent == &clk_mpll) - clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static unsigned long s3c2412_getrate_i2s(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2410_CLKDIVN); - - div &= S3C2412_CLKDIVN_I2SDIV_MASK; - div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); - - rate = s3c2412_roundrate_clksrc(clk, rate); - - clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK; - clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT; - - __raw_writel(clkdivn, S3C2410_CLKDIVN); - return 0; -} - -static struct clk clk_i2s = { - .name = "i2sclk", - .id = -1, - .get_rate = s3c2412_getrate_i2s, - .set_rate = s3c2412_setrate_i2s, - .set_parent = s3c2412_setparent_i2s, - .round_rate = s3c2412_roundrate_clksrc, -}; - -static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_usysclk) - clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK; - else if (parent == &clk_h) - clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} -static unsigned long s3c2412_getrate_cam(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2410_CLKDIVN); - - div &= S3C2412_CLKDIVN_CAMDIV_MASK; - div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); - - rate = s3c2412_roundrate_clksrc(clk, rate); - - clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK; - clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT; - - __raw_writel(clkdivn, S3C2410_CLKDIVN); - return 0; -} - -static struct clk clk_cam = { - .name = "camif-upll", /* same as 2440 name */ - .id = -1, - .get_rate = s3c2412_getrate_cam, - .set_rate = s3c2412_setrate_cam, - .set_parent = s3c2412_setparent_cam, - .round_rate = s3c2412_roundrate_clksrc, -}; - -/* standard clock definitions */ - -static struct clk init_clocks_disable[] = { - { - .name = "nand", - .id = -1, - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_NAND, - }, { - .name = "sdi", - .id = -1, - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_SDI, - }, { - .name = "adc", - .id = -1, - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_ADC, - }, { - .name = "i2c", - .id = -1, - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_IIC, - }, { - .name = "iis", - .id = -1, - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_IIS, - }, { - .name = "spi", - .id = -1, - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_SPI, - } -}; - -static struct clk init_clocks[] = { - { - .name = "dma", - .id = 0, - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_DMA0, - }, { - .name = "dma", - .id = 1, - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_DMA1, - }, { - .name = "dma", - .id = 2, - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_DMA2, - }, { - .name = "dma", - .id = 3, - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_DMA3, - }, { - .name = "lcd", - .id = -1, - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_LCDC, - }, { - .name = "gpio", - .id = -1, - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_GPIO, - }, { - .name = "usb-host", - .id = -1, - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_USBH, - }, { - .name = "usb-device", - .id = -1, - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_USBD, - }, { - .name = "timers", - .id = -1, - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_PWMT, - }, { - .name = "uart", - .id = 0, - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_UART0, - }, { - .name = "uart", - .id = 1, - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_UART1, - }, { - .name = "uart", - .id = 2, - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_UART2, - }, { - .name = "rtc", - .id = -1, - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_RTC, - }, { - .name = "watchdog", - .id = -1, - .parent = &clk_p, - .ctrlbit = 0, - }, { - .name = "usb-bus-gadget", - .id = -1, - .parent = &clk_usb_bus, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_USB_DEV48, - }, { - .name = "usb-bus-host", - .id = -1, - .parent = &clk_usb_bus, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_USB_HOST48, - } -}; - -/* clocks to add where we need to check their parentage */ - -struct clk_init { - struct clk *clk; - unsigned int bit; - struct clk *src_0; - struct clk *src_1; -}; - -static struct clk_init clks_src[] __initdata = { - { - .clk = &clk_usysclk, - .bit = S3C2412_CLKSRC_USBCLK_HCLK, - .src_0 = &clk_urefclk, - .src_1 = &clk_upll, - }, { - .clk = &clk_i2s, - .bit = S3C2412_CLKSRC_I2SCLK_MPLL, - .src_0 = &clk_erefclk, - .src_1 = &clk_mpll, - }, { - .clk = &clk_cam, - .bit = S3C2412_CLKSRC_CAMCLK_HCLK, - .src_0 = &clk_usysclk, - .src_1 = &clk_h, - }, { - .clk = &clk_msysclk, - .bit = S3C2412_CLKSRC_MSYSCLK_MPLL, - .src_0 = &clk_mdivclk, - .src_1 = &clk_mpll, - }, { - .clk = &clk_uart, - .bit = S3C2412_CLKSRC_UARTCLK_MPLL, - .src_0 = &clk_erefclk, - .src_1 = &clk_mpll, - }, { - .clk = &clk_usbsrc, - .bit = S3C2412_CLKSRC_USBCLK_HCLK, - .src_0 = &clk_usysclk, - .src_1 = &clk_h, - }, -}; - -/* s3c2412_clk_initparents - * - * Initialise the parents for the clocks that we get at start-time -*/ - -static void __init s3c2412_clk_initparents(void) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - struct clk_init *cip = clks_src; - struct clk *src; - int ptr; - int ret; - - for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) { - ret = s3c24xx_register_clock(cip->clk); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - cip->clk->name, ret); - } - - src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0; - - printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name); - clk_set_parent(cip->clk, src); - } -} - -/* clocks to add straight away */ - -static struct clk *clks[] __initdata = { - &clk_ext, - &clk_usb_bus, - &clk_erefclk, - &clk_urefclk, - &clk_mrefclk, -}; - -int __init s3c2412_baseclk_add(void) -{ - unsigned long clkcon = __raw_readl(S3C2410_CLKCON); - struct clk *clkp; - int ret; - int ptr; - - clk_upll.enable = s3c2412_upll_enable; - clk_usb_bus.parent = &clk_usbsrc; - clk_usb_bus.rate = 0x0; - - s3c2412_clk_initparents(); - - for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { - clkp = clks[ptr]; - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } - - /* ensure usb bus clock is within correct rate of 48MHz */ - - if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) { - printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n"); - - /* for the moment, let's use the UPLL, and see if we can - * get 48MHz */ - - clk_set_parent(&clk_usysclk, &clk_upll); - clk_set_parent(&clk_usbsrc, &clk_usysclk); - clk_set_rate(&clk_usbsrc, 48*1000*1000); - } - - printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", - (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on", - print_mhz(clk_get_rate(&clk_upll)), - print_mhz(clk_get_rate(&clk_usb_bus))); - - /* register clocks from clock array */ - - clkp = init_clocks; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { - /* ensure that we note the clock state */ - - clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0; - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } - - /* We must be careful disabling the clocks we are not intending to - * be using at boot time, as subsytems such as the LCD which do - * their own DMA requests to the bus can cause the system to lockup - * if they where in the middle of requesting bus access. - * - * Disabling the LCD clock if the LCD is active is very dangerous, - * and therefore the bootloader should be careful to not enable - * the LCD clock if it is not needed. - */ - - /* install (and disable) the clocks we do not need immediately */ - - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - - s3c2412_clkcon_enable(clkp, 0); - } - - return 0; -} diff --git a/arch/arm/mach-s3c2410/s3c2412-dma.c b/arch/arm/mach-s3c2410/s3c2412-dma.c deleted file mode 100644 index 138f726ac6bf..000000000000 --- a/arch/arm/mach-s3c2410/s3c2412-dma.c +++ /dev/null @@ -1,161 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2412-dma.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * S3C2412 DMA selection - * - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include - -#include -#include -#include - -#include "dma.h" -#include "cpu.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID } - -static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = { - [DMACH_XD0] = { - .name = "xdreq0", - .channels = MAP(S3C2412_DMAREQSEL_XDREQ0), - }, - [DMACH_XD1] = { - .name = "xdreq1", - .channels = MAP(S3C2412_DMAREQSEL_XDREQ1), - }, - [DMACH_SDI] = { - .name = "sdi", - .channels = MAP(S3C2412_DMAREQSEL_SDI), - .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, - .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, - }, - [DMACH_SPI0] = { - .name = "spi0", - .channels = MAP(S3C2412_DMAREQSEL_SPI0TX), - .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, - }, - [DMACH_SPI1] = { - .name = "spi1", - .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), - .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, - }, - [DMACH_UART0] = { - .name = "uart0", - .channels = MAP(S3C2412_DMAREQSEL_UART0_0), - .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, - }, - [DMACH_UART1] = { - .name = "uart1", - .channels = MAP(S3C2412_DMAREQSEL_UART1_0), - .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, - }, - [DMACH_UART2] = { - .name = "uart2", - .channels = MAP(S3C2412_DMAREQSEL_UART2_0), - .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, - }, - [DMACH_UART0_SRC2] = { - .name = "uart0", - .channels = MAP(S3C2412_DMAREQSEL_UART0_1), - .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, - }, - [DMACH_UART1_SRC2] = { - .name = "uart1", - .channels = MAP(S3C2412_DMAREQSEL_UART1_1), - .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, - }, - [DMACH_UART2_SRC2] = { - .name = "uart2", - .channels = MAP(S3C2412_DMAREQSEL_UART2_1), - .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, - }, - [DMACH_TIMER] = { - .name = "timer", - .channels = MAP(S3C2412_DMAREQSEL_TIMER), - }, - [DMACH_I2S_IN] = { - .name = "i2s-sdi", - .channels = MAP(S3C2412_DMAREQSEL_I2SRX), - .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, - }, - [DMACH_I2S_OUT] = { - .name = "i2s-sdo", - .channels = MAP(S3C2412_DMAREQSEL_I2STX), - .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, - }, - [DMACH_USB_EP1] = { - .name = "usb-ep1", - .channels = MAP(S3C2412_DMAREQSEL_USBEP1), - }, - [DMACH_USB_EP2] = { - .name = "usb-ep2", - .channels = MAP(S3C2412_DMAREQSEL_USBEP2), - }, - [DMACH_USB_EP3] = { - .name = "usb-ep3", - .channels = MAP(S3C2412_DMAREQSEL_USBEP3), - }, - [DMACH_USB_EP4] = { - .name = "usb-ep4", - .channels = MAP(S3C2412_DMAREQSEL_USBEP4), - }, -}; - -static void s3c2412_dma_select(struct s3c2410_dma_chan *chan, - struct s3c24xx_dma_map *map) -{ - writel(map->channels[0] | S3C2412_DMAREQSEL_HW, - chan->regs + S3C2412_DMA_DMAREQSEL); -} - -static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { - .select = s3c2412_dma_select, - .dcon_mask = 0, - .map = s3c2412_dma_mappings, - .map_size = ARRAY_SIZE(s3c2412_dma_mappings), -}; - -static int s3c2412_dma_add(struct sys_device *sysdev) -{ - return s3c24xx_dma_init_map(&s3c2412_dma_sel); -} - -static struct sysdev_driver s3c2412_dma_driver = { - .add = s3c2412_dma_add, -}; - -static int __init s3c2412_dma_init(void) -{ - return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver); -} - -arch_initcall(s3c2412_dma_init); diff --git a/arch/arm/mach-s3c2410/s3c2412-irq.c b/arch/arm/mach-s3c2410/s3c2412-irq.c deleted file mode 100644 index ffcc30b23a80..000000000000 --- a/arch/arm/mach-s3c2410/s3c2412-irq.c +++ /dev/null @@ -1,133 +0,0 @@ -/* linux/arch/arm/mach-s3c2412/s3c2412-irq.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * -*/ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include -#include - -#include "cpu.h" -#include "irq.h" -#include "pm.h" - -/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by - * having them turn up in both the INT* and the EINT* registers. Whilst - * both show the status, they both now need to be acked when the IRQs - * go off. -*/ - -static void -s3c2412_irq_mask(unsigned int irqno) -{ - unsigned long bitval = 1UL << (irqno - IRQ_EINT0); - unsigned long mask; - - mask = __raw_readl(S3C2410_INTMSK); - __raw_writel(mask | bitval, S3C2410_INTMSK); - - mask = __raw_readl(S3C2412_EINTMASK); - __raw_writel(mask | bitval, S3C2412_EINTMASK); -} - -static inline void -s3c2412_irq_ack(unsigned int irqno) -{ - unsigned long bitval = 1UL << (irqno - IRQ_EINT0); - - __raw_writel(bitval, S3C2412_EINTPEND); - __raw_writel(bitval, S3C2410_SRCPND); - __raw_writel(bitval, S3C2410_INTPND); -} - -static inline void -s3c2412_irq_maskack(unsigned int irqno) -{ - unsigned long bitval = 1UL << (irqno - IRQ_EINT0); - unsigned long mask; - - mask = __raw_readl(S3C2410_INTMSK); - __raw_writel(mask|bitval, S3C2410_INTMSK); - - mask = __raw_readl(S3C2412_EINTMASK); - __raw_writel(mask | bitval, S3C2412_EINTMASK); - - __raw_writel(bitval, S3C2412_EINTPEND); - __raw_writel(bitval, S3C2410_SRCPND); - __raw_writel(bitval, S3C2410_INTPND); -} - -static void -s3c2412_irq_unmask(unsigned int irqno) -{ - unsigned long bitval = 1UL << (irqno - IRQ_EINT0); - unsigned long mask; - - mask = __raw_readl(S3C2412_EINTMASK); - __raw_writel(mask & ~bitval, S3C2412_EINTMASK); - - mask = __raw_readl(S3C2410_INTMSK); - __raw_writel(mask & ~bitval, S3C2410_INTMSK); -} - -static struct irq_chip s3c2412_irq_eint0t4 = { - .ack = s3c2412_irq_ack, - .mask = s3c2412_irq_mask, - .unmask = s3c2412_irq_unmask, - .set_wake = s3c_irq_wake, - .set_type = s3c_irqext_type, -}; - -static int s3c2412_irq_add(struct sys_device *sysdev) -{ - unsigned int irqno; - - for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { - set_irq_chip(irqno, &s3c2412_irq_eint0t4); - set_irq_handler(irqno, handle_edge_irq); - set_irq_flags(irqno, IRQF_VALID); - } - - return 0; -} - -static struct sysdev_driver s3c2412_irq_driver = { - .add = s3c2412_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, -}; - -static int s3c2412_irq_init(void) -{ - return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_irq_driver); -} - -arch_initcall(s3c2412_irq_init); diff --git a/arch/arm/mach-s3c2410/s3c2412-pm.c b/arch/arm/mach-s3c2410/s3c2412-pm.c deleted file mode 100644 index 19b63322d259..000000000000 --- a/arch/arm/mach-s3c2410/s3c2412-pm.c +++ /dev/null @@ -1,128 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2412-pm.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * http://armlinux.simtec.co.uk/. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "cpu.h" -#include "pm.h" - -#include "s3c2412.h" - -static void s3c2412_cpu_suspend(void) -{ - unsigned long tmp; - - /* set our standby method to sleep */ - - tmp = __raw_readl(S3C2412_PWRCFG); - tmp |= S3C2412_PWRCFG_STANDBYWFI_SLEEP; - __raw_writel(tmp, S3C2412_PWRCFG); - - /* issue the standby signal into the pm unit. Note, we - * issue a write-buffer drain just in case */ - - tmp = 0; - - asm("b 1f\n\t" - ".align 5\n\t" - "1:\n\t" - "mcr p15, 0, %0, c7, c10, 4\n\t" - "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); - - /* we should never get past here */ - - panic("sleep resumed to originator?"); -} - -static void s3c2412_pm_prepare(void) -{ -} - -static int s3c2412_pm_add(struct sys_device *sysdev) -{ - pm_cpu_prep = s3c2412_pm_prepare; - pm_cpu_sleep = s3c2412_cpu_suspend; - - return 0; -} - -static struct sleep_save s3c2412_sleep[] = { - SAVE_ITEM(S3C2412_DSC0), - SAVE_ITEM(S3C2412_DSC1), - SAVE_ITEM(S3C2413_GPJDAT), - SAVE_ITEM(S3C2413_GPJCON), - SAVE_ITEM(S3C2413_GPJUP), - - /* save the PWRCFG to get back to original sleep method */ - - SAVE_ITEM(S3C2412_PWRCFG), - - /* save the sleep configuration anyway, just in case these - * get damaged during wakeup */ - - SAVE_ITEM(S3C2412_GPBSLPCON), - SAVE_ITEM(S3C2412_GPCSLPCON), - SAVE_ITEM(S3C2412_GPDSLPCON), - SAVE_ITEM(S3C2412_GPESLPCON), - SAVE_ITEM(S3C2412_GPFSLPCON), - SAVE_ITEM(S3C2412_GPGSLPCON), - SAVE_ITEM(S3C2412_GPHSLPCON), - SAVE_ITEM(S3C2413_GPJSLPCON), -}; - -static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state) -{ - s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); - return 0; -} - -static int s3c2412_pm_resume(struct sys_device *dev) -{ - unsigned long tmp; - - tmp = __raw_readl(S3C2412_PWRCFG); - tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK; - tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE; - __raw_writel(tmp, S3C2412_PWRCFG); - - s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); - return 0; -} - -static struct sysdev_driver s3c2412_pm_driver = { - .add = s3c2412_pm_add, - .suspend = s3c2412_pm_suspend, - .resume = s3c2412_pm_resume, -}; - -static __init int s3c2412_pm_init(void) -{ - return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver); -} - -arch_initcall(s3c2412_pm_init); diff --git a/arch/arm/mach-s3c2410/s3c2412.c b/arch/arm/mach-s3c2410/s3c2412.c deleted file mode 100644 index 2f651a811ecd..000000000000 --- a/arch/arm/mach-s3c2410/s3c2412.c +++ /dev/null @@ -1,181 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2412.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * http://armlinux.simtec.co.uk/. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -#include "s3c2412.h" -#include "cpu.h" -#include "devs.h" -#include "clock.h" -#include "pm.h" - -#ifndef CONFIG_CPU_S3C2412_ONLY -void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; - -static inline void s3c2412_init_gpio2(void) -{ - s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10; -} -#else -#define s3c2412_init_gpio2() do { } while(0) -#endif - -/* Initial IO mappings */ - -static struct map_desc s3c2412_iodesc[] __initdata = { - IODESC_ENT(CLKPWR), - IODESC_ENT(LCD), - IODESC_ENT(TIMER), - IODESC_ENT(WATCHDOG), -}; - -/* uart registration process */ - -void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no) -{ - s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no); - - /* rename devices that are s3c2412/s3c2413 specific */ - s3c_device_sdi.name = "s3c2412-sdi"; - s3c_device_lcd.name = "s3c2412-lcd"; - s3c_device_nand.name = "s3c2412-nand"; -} - -/* s3c2412_idle - * - * use the standard idle call by ensuring the idle mode - * in power config, then issuing the idle co-processor - * instruction -*/ - -static void s3c2412_idle(void) -{ - unsigned long tmp; - - /* ensure our idle mode is to go to idle */ - - tmp = __raw_readl(S3C2412_PWRCFG); - tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK; - tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE; - __raw_writel(tmp, S3C2412_PWRCFG); - - cpu_do_idle(); -} - -/* s3c2412_map_io - * - * register the standard cpu IO areas, and any passed in from the - * machine specific initialisation. -*/ - -void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size) -{ - /* move base of IO */ - - s3c2412_init_gpio2(); - - /* set our idle function */ - - s3c24xx_idle = s3c2412_idle; - - /* register our io-tables */ - - iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); - iotable_init(mach_desc, mach_size); -} - -void __init s3c2412_init_clocks(int xtal) -{ - unsigned long tmp; - unsigned long fclk; - unsigned long hclk; - unsigned long pclk; - - /* now we've got our machine bits initialised, work out what - * clocks we've got */ - - fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2); - - tmp = __raw_readl(S3C2410_CLKDIVN); - - /* work out clock scalings */ - - hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); - hclk /= ((tmp & S3C2421_CLKDIVN_ARMDIVN) ? 2 : 1); - pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); - - /* print brieft summary of clocks, etc */ - - printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", - print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); - - /* initialise the clocks here, to allow other things like the - * console to use them - */ - - s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); - s3c2412_baseclk_add(); -} - -/* need to register class before we actually register the device, and - * we also need to ensure that it has been initialised before any of the - * drivers even try to use it (even if not on an s3c2412 based system) - * as a driver which may support both 2410 and 2440 may try and use it. -*/ - -struct sysdev_class s3c2412_sysclass = { - set_kset_name("s3c2412-core"), -}; - -static int __init s3c2412_core_init(void) -{ - return sysdev_class_register(&s3c2412_sysclass); -} - -core_initcall(s3c2412_core_init); - -static struct sys_device s3c2412_sysdev = { - .cls = &s3c2412_sysclass, -}; - -int __init s3c2412_init(void) -{ - printk("S3C2412: Initialising architecture\n"); - - return sysdev_register(&s3c2412_sysdev); -} diff --git a/arch/arm/mach-s3c2410/s3c2412.h b/arch/arm/mach-s3c2410/s3c2412.h deleted file mode 100644 index c6e56032a6e7..000000000000 --- a/arch/arm/mach-s3c2410/s3c2412.h +++ /dev/null @@ -1,29 +0,0 @@ -/* arch/arm/mach-s3c2410/s3c2412.h - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * Header file for s3c2412 cpu support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifdef CONFIG_CPU_S3C2412 - -extern int s3c2412_init(void); - -extern void s3c2412_map_io(struct map_desc *mach_desc, int size); - -extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); - -extern void s3c2412_init_clocks(int xtal); - -extern int s3c2412_baseclk_add(void); -#else -#define s3c2412_init_clocks NULL -#define s3c2412_init_uarts NULL -#define s3c2412_map_io NULL -#define s3c2412_init NULL -#endif diff --git a/arch/arm/mach-s3c2410/s3c2440-clock.c b/arch/arm/mach-s3c2410/s3c2440-clock.c deleted file mode 100644 index ba13c1d079d1..000000000000 --- a/arch/arm/mach-s3c2410/s3c2440-clock.c +++ /dev/null @@ -1,170 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2440-clock.c - * - * Copyright (c) 2004-2005 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C2440 Clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "clock.h" -#include "cpu.h" - -/* S3C2440 extended clock support */ - -static unsigned long s3c2440_camif_upll_round(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - return parent_rate; - - /* note, we remove the +/- 1 calculations for the divisor */ - - div = (parent_rate / rate) / 2; - - if (div < 1) - div = 1; - else if (div > 16) - div = 16; - - return parent_rate / (div * 2); -} - -static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); - - rate = s3c2440_camif_upll_round(clk, rate); - - camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK); - - if (rate != parent_rate) { - camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; - camdivn |= (((parent_rate / rate) / 2) - 1); - } - - __raw_writel(camdivn, S3C2440_CAMDIVN); - - return 0; -} - -/* Extra S3C2440 clocks */ - -static struct clk s3c2440_clk_cam = { - .name = "camif", - .id = -1, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2440_CLKCON_CAMERA, -}; - -static struct clk s3c2440_clk_cam_upll = { - .name = "camif-upll", - .id = -1, - .set_rate = s3c2440_camif_upll_setrate, - .round_rate = s3c2440_camif_upll_round, -}; - -static struct clk s3c2440_clk_ac97 = { - .name = "ac97", - .id = -1, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2440_CLKCON_CAMERA, -}; - -static int s3c2440_clk_add(struct sys_device *sysdev) -{ - unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); - unsigned long clkdivn; - struct clk *clock_h; - struct clk *clock_p; - struct clk *clock_upll; - - printk("S3C2440: Clock Support, DVS %s\n", - (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off"); - - clock_p = clk_get(NULL, "pclk"); - clock_h = clk_get(NULL, "hclk"); - clock_upll = clk_get(NULL, "upll"); - - if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) { - printk(KERN_ERR "S3C2440: Failed to get parent clocks\n"); - return -EINVAL; - } - - /* check rate of UPLL, and if it is near 96MHz, then change - * to using half the UPLL rate for the system */ - - if (clk_get_rate(clock_upll) > (94 * MHZ)) { - clk_usb_bus.rate = clk_get_rate(clock_upll) / 2; - - mutex_lock(&clocks_mutex); - - clkdivn = __raw_readl(S3C2410_CLKDIVN); - clkdivn |= S3C2440_CLKDIVN_UCLK; - __raw_writel(clkdivn, S3C2410_CLKDIVN); - - mutex_unlock(&clocks_mutex); - } - - s3c2440_clk_cam.parent = clock_h; - s3c2440_clk_ac97.parent = clock_p; - s3c2440_clk_cam_upll.parent = clock_upll; - - s3c24xx_register_clock(&s3c2440_clk_ac97); - s3c24xx_register_clock(&s3c2440_clk_cam); - s3c24xx_register_clock(&s3c2440_clk_cam_upll); - - clk_disable(&s3c2440_clk_ac97); - clk_disable(&s3c2440_clk_cam); - - return 0; -} - -static struct sysdev_driver s3c2440_clk_driver = { - .add = s3c2440_clk_add, -}; - -static __init int s3c24xx_clk_driver(void) -{ - return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver); -} - -arch_initcall(s3c24xx_clk_driver); diff --git a/arch/arm/mach-s3c2410/s3c2440-dma.c b/arch/arm/mach-s3c2410/s3c2440-dma.c deleted file mode 100644 index 47b861b9443d..000000000000 --- a/arch/arm/mach-s3c2410/s3c2440-dma.c +++ /dev/null @@ -1,165 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2440-dma.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * S3C2440 DMA selection - * - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include - -#include -#include -#include "dma.h" - -#include "cpu.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = { - [DMACH_XD0] = { - .name = "xdreq0", - .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID, - }, - [DMACH_XD1] = { - .name = "xdreq1", - .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID, - }, - [DMACH_SDI] = { - .name = "sdi", - .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID, - .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID, - .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, - .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, - .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, - }, - [DMACH_SPI0] = { - .name = "spi0", - .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, - }, - [DMACH_SPI1] = { - .name = "spi1", - .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, - .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, - }, - [DMACH_UART0] = { - .name = "uart0", - .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, - }, - [DMACH_UART1] = { - .name = "uart1", - .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, - }, - [DMACH_UART2] = { - .name = "uart2", - .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, - .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, - }, - [DMACH_TIMER] = { - .name = "timer", - .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID, - .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID, - .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID, - }, - [DMACH_I2S_IN] = { - .name = "i2s-sdi", - .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, - .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, - .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, - }, - [DMACH_I2S_OUT] = { - .name = "i2s-sdo", - .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID, - .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, - .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, - }, - [DMACH_PCM_IN] = { - .name = "pcm-in", - .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID, - .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID, - .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA, - }, - [DMACH_PCM_OUT] = { - .name = "pcm-out", - .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID, - .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID, - .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA, - }, - [DMACH_MIC_IN] = { - .name = "mic-in", - .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID, - .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID, - .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA, - }, - [DMACH_USB_EP1] = { - .name = "usb-ep1", - .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID, - }, - [DMACH_USB_EP2] = { - .name = "usb-ep2", - .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID, - }, - [DMACH_USB_EP3] = { - .name = "usb-ep3", - .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID, - }, - [DMACH_USB_EP4] = { - .name = "usb-ep4", - .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID, - }, -}; - -static void s3c2440_dma_select(struct s3c2410_dma_chan *chan, - struct s3c24xx_dma_map *map) -{ - chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID; -} - -static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = { - .select = s3c2440_dma_select, - .dcon_mask = 7 << 24, - .map = s3c2440_dma_mappings, - .map_size = ARRAY_SIZE(s3c2440_dma_mappings), -}; - -static int s3c2440_dma_add(struct sys_device *sysdev) -{ - return s3c24xx_dma_init_map(&s3c2440_dma_sel); -} - -static struct sysdev_driver s3c2440_dma_driver = { - .add = s3c2440_dma_add, -}; - -static int __init s3c2440_dma_init(void) -{ - return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_dma_driver); -} - -arch_initcall(s3c2440_dma_init); - diff --git a/arch/arm/mach-s3c2410/s3c2440-dsc.c b/arch/arm/mach-s3c2410/s3c2440-dsc.c deleted file mode 100644 index c92ea66ba45e..000000000000 --- a/arch/arm/mach-s3c2410/s3c2440-dsc.c +++ /dev/null @@ -1,54 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2440-dsc.c - * - * Copyright (c) 2004-2005 Simtec Electronics - * Ben Dooks - * - * Samsung S3C2440 Drive Strength Control support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "cpu.h" -#include "s3c2440.h" - -int s3c2440_set_dsc(unsigned int pin, unsigned int value) -{ - void __iomem *base; - unsigned long val; - unsigned long flags; - unsigned long mask; - - base = (pin & S3C2440_SELECT_DSC1) ? S3C2440_DSC1 : S3C2440_DSC0; - mask = 3 << S3C2440_DSC_GETSHIFT(pin); - - local_irq_save(flags); - - val = __raw_readl(base); - val &= ~mask; - val |= value & mask; - __raw_writel(val, base); - - local_irq_restore(flags); - return 0; -} - -EXPORT_SYMBOL(s3c2440_set_dsc); diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c deleted file mode 100644 index 1ba19b27ab05..000000000000 --- a/arch/arm/mach-s3c2410/s3c2440-irq.c +++ /dev/null @@ -1,130 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2440-irq.c - * - * Copyright (c) 2003,2004 Simtec Electronics - * Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * -*/ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include -#include - -#include "cpu.h" -#include "pm.h" -#include "irq.h" - -/* WDT/AC97 */ - -static void s3c_irq_demux_wdtac97(unsigned int irq, - struct irq_desc *desc) -{ - unsigned int subsrc, submsk; - struct irq_desc *mydesc; - - /* read the current pending interrupts, and the mask - * for what it is available */ - - subsrc = __raw_readl(S3C2410_SUBSRCPND); - submsk = __raw_readl(S3C2410_INTSUBMSK); - - subsrc &= ~submsk; - subsrc >>= 13; - subsrc &= 3; - - if (subsrc != 0) { - if (subsrc & 1) { - mydesc = irq_desc + IRQ_S3C2440_WDT; - desc_handle_irq(IRQ_S3C2440_WDT, mydesc); - } - if (subsrc & 2) { - mydesc = irq_desc + IRQ_S3C2440_AC97; - desc_handle_irq(IRQ_S3C2440_AC97, mydesc); - } - } -} - - -#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0)) - -static void -s3c_irq_wdtac97_mask(unsigned int irqno) -{ - s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13); -} - -static void -s3c_irq_wdtac97_unmask(unsigned int irqno) -{ - s3c_irqsub_unmask(irqno, INTMSK_WDT); -} - -static void -s3c_irq_wdtac97_ack(unsigned int irqno) -{ - s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13); -} - -static struct irq_chip s3c_irq_wdtac97 = { - .mask = s3c_irq_wdtac97_mask, - .unmask = s3c_irq_wdtac97_unmask, - .ack = s3c_irq_wdtac97_ack, -}; - -static int s3c2440_irq_add(struct sys_device *sysdev) -{ - unsigned int irqno; - - printk("S3C2440: IRQ Support\n"); - - /* add new chained handler for wdt, ac7 */ - - set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); - set_irq_handler(IRQ_WDT, handle_level_irq); - set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); - - for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { - set_irq_chip(irqno, &s3c_irq_wdtac97); - set_irq_handler(irqno, handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); - } - - return 0; -} - -static struct sysdev_driver s3c2440_irq_driver = { - .add = s3c2440_irq_add, -}; - -static int s3c2440_irq_init(void) -{ - return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver); -} - -arch_initcall(s3c2440_irq_init); - diff --git a/arch/arm/mach-s3c2410/s3c2440.c b/arch/arm/mach-s3c2410/s3c2440.c deleted file mode 100644 index 344eb27cca48..000000000000 --- a/arch/arm/mach-s3c2410/s3c2440.c +++ /dev/null @@ -1,52 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2440.c - * - * Copyright (c) 2004-2006 Simtec Electronics - * Ben Dooks - * - * Samsung S3C2440 Mobile CPU support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "s3c2440.h" -#include "devs.h" -#include "cpu.h" - -static struct sys_device s3c2440_sysdev = { - .cls = &s3c2440_sysclass, -}; - -int __init s3c2440_init(void) -{ - printk("S3C2440: Initialising architecture\n"); - - /* change irq for watchdog */ - - s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT; - s3c_device_wdt.resource[1].end = IRQ_S3C2440_WDT; - - /* register our system device for everything else */ - - return sysdev_register(&s3c2440_sysdev); -} diff --git a/arch/arm/mach-s3c2410/s3c2440.h b/arch/arm/mach-s3c2410/s3c2440.h deleted file mode 100644 index dcd316076c59..000000000000 --- a/arch/arm/mach-s3c2410/s3c2440.h +++ /dev/null @@ -1,17 +0,0 @@ -/* arch/arm/mach-s3c2410/s3c2440.h - * - * Copyright (c) 2004-2005 Simtec Electronics - * Ben Dooks - * - * Header file for s3c2440 cpu support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifdef CONFIG_CPU_S3C2440 -extern int s3c2440_init(void); -#else -#define s3c2440_init NULL -#endif diff --git a/arch/arm/mach-s3c2410/s3c2442-clock.c b/arch/arm/mach-s3c2410/s3c2442-clock.c deleted file mode 100644 index 4e292ca7c9be..000000000000 --- a/arch/arm/mach-s3c2410/s3c2442-clock.c +++ /dev/null @@ -1,171 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2442-clock.c - * - * Copyright (c) 2004-2005 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C2442 Clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "clock.h" -#include "cpu.h" - -/* S3C2442 extended clock support */ - -static unsigned long s3c2442_camif_upll_round(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - return parent_rate; - - div = parent_rate / rate; - - if (div == 3) - return parent_rate / 3; - - /* note, we remove the +/- 1 calculations for the divisor */ - - div /= 2; - - if (div < 1) - div = 1; - else if (div > 16) - div = 16; - - return parent_rate / (div * 2); -} - -static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); - - rate = s3c2442_camif_upll_round(clk, rate); - - camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3; - - if (rate == parent_rate) { - camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL; - } else if ((parent_rate / rate) == 3) { - camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; - camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3; - } else { - camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK; - camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; - camdivn |= (((parent_rate / rate) / 2) - 1); - } - - __raw_writel(camdivn, S3C2440_CAMDIVN); - - return 0; -} - -/* Extra S3C2442 clocks */ - -static struct clk s3c2442_clk_cam = { - .name = "camif", - .id = -1, - .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2440_CLKCON_CAMERA, -}; - -static struct clk s3c2442_clk_cam_upll = { - .name = "camif-upll", - .id = -1, - .set_rate = s3c2442_camif_upll_setrate, - .round_rate = s3c2442_camif_upll_round, -}; - -static int s3c2442_clk_add(struct sys_device *sysdev) -{ - unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); - unsigned long clkdivn; - struct clk *clock_h; - struct clk *clock_p; - struct clk *clock_upll; - - printk("S3C2442: Clock Support, DVS %s\n", - (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off"); - - clock_p = clk_get(NULL, "pclk"); - clock_h = clk_get(NULL, "hclk"); - clock_upll = clk_get(NULL, "upll"); - - if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) { - printk(KERN_ERR "S3C2442: Failed to get parent clocks\n"); - return -EINVAL; - } - - /* check rate of UPLL, and if it is near 96MHz, then change - * to using half the UPLL rate for the system */ - - if (clk_get_rate(clock_upll) > (94 * MHZ)) { - clk_usb_bus.rate = clk_get_rate(clock_upll) / 2; - - mutex_lock(&clocks_mutex); - - clkdivn = __raw_readl(S3C2410_CLKDIVN); - clkdivn |= S3C2440_CLKDIVN_UCLK; - __raw_writel(clkdivn, S3C2410_CLKDIVN); - - mutex_unlock(&clocks_mutex); - } - - s3c2442_clk_cam.parent = clock_h; - s3c2442_clk_cam_upll.parent = clock_upll; - - s3c24xx_register_clock(&s3c2442_clk_cam); - s3c24xx_register_clock(&s3c2442_clk_cam_upll); - - clk_disable(&s3c2442_clk_cam); - - return 0; -} - -static struct sysdev_driver s3c2442_clk_driver = { - .add = s3c2442_clk_add, -}; - -static __init int s3c2442_clk_init(void) -{ - return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver); -} - -arch_initcall(s3c2442_clk_init); diff --git a/arch/arm/mach-s3c2410/s3c2442.c b/arch/arm/mach-s3c2410/s3c2442.c deleted file mode 100644 index 428732ee68c4..000000000000 --- a/arch/arm/mach-s3c2410/s3c2442.c +++ /dev/null @@ -1,34 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2442.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * Samsung S3C2442 Mobile CPU support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "s3c2442.h" -#include "cpu.h" - -static struct sys_device s3c2442_sysdev = { - .cls = &s3c2442_sysclass, -}; - -int __init s3c2442_init(void) -{ - printk("S3C2442: Initialising architecture\n"); - - return sysdev_register(&s3c2442_sysdev); -} diff --git a/arch/arm/mach-s3c2410/s3c2442.h b/arch/arm/mach-s3c2410/s3c2442.h deleted file mode 100644 index 0ae37d24866c..000000000000 --- a/arch/arm/mach-s3c2410/s3c2442.h +++ /dev/null @@ -1,17 +0,0 @@ -/* arch/arm/mach-s3c2410/s3c2442.h - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * Header file for s3c2442 cpu support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifdef CONFIG_CPU_S3C2442 -extern int s3c2442_init(void); -#else -#define s3c2442_init NULL -#endif diff --git a/arch/arm/mach-s3c2410/s3c244x-irq.c b/arch/arm/mach-s3c2410/s3c244x-irq.c deleted file mode 100644 index ede94636a72a..000000000000 --- a/arch/arm/mach-s3c2410/s3c244x-irq.c +++ /dev/null @@ -1,146 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c244x-irq.c - * - * Copyright (c) 2003,2004 Simtec Electronics - * Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * -*/ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include -#include - -#include "cpu.h" -#include "pm.h" -#include "irq.h" - -/* camera irq */ - -static void s3c_irq_demux_cam(unsigned int irq, - struct irq_desc *desc) -{ - unsigned int subsrc, submsk; - struct irq_desc *mydesc; - - /* read the current pending interrupts, and the mask - * for what it is available */ - - subsrc = __raw_readl(S3C2410_SUBSRCPND); - submsk = __raw_readl(S3C2410_INTSUBMSK); - - subsrc &= ~submsk; - subsrc >>= 11; - subsrc &= 3; - - if (subsrc != 0) { - if (subsrc & 1) { - mydesc = irq_desc + IRQ_S3C2440_CAM_C; - desc_handle_irq(IRQ_S3C2440_CAM_C, mydesc); - } - if (subsrc & 2) { - mydesc = irq_desc + IRQ_S3C2440_CAM_P; - desc_handle_irq(IRQ_S3C2440_CAM_P, mydesc); - } - } -} - -#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0)) - -static void -s3c_irq_cam_mask(unsigned int irqno) -{ - s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11); -} - -static void -s3c_irq_cam_unmask(unsigned int irqno) -{ - s3c_irqsub_unmask(irqno, INTMSK_CAM); -} - -static void -s3c_irq_cam_ack(unsigned int irqno) -{ - s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11); -} - -static struct irq_chip s3c_irq_cam = { - .mask = s3c_irq_cam_mask, - .unmask = s3c_irq_cam_unmask, - .ack = s3c_irq_cam_ack, -}; - -static int s3c244x_irq_add(struct sys_device *sysdev) -{ - unsigned int irqno; - - set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); - set_irq_handler(IRQ_NFCON, handle_level_irq); - set_irq_flags(IRQ_NFCON, IRQF_VALID); - - /* add chained handler for camera */ - - set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); - set_irq_handler(IRQ_CAM, handle_level_irq); - set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); - - for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { - set_irq_chip(irqno, &s3c_irq_cam); - set_irq_handler(irqno, handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); - } - - return 0; -} - -static struct sysdev_driver s3c2440_irq_driver = { - .add = s3c244x_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, -}; - -static int s3c2440_irq_init(void) -{ - return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver); -} - -arch_initcall(s3c2440_irq_init); - -static struct sysdev_driver s3c2442_irq_driver = { - .add = s3c244x_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, -}; - - -static int s3c2442_irq_init(void) -{ - return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_irq_driver); -} - -arch_initcall(s3c2442_irq_init); diff --git a/arch/arm/mach-s3c2410/s3c244x.c b/arch/arm/mach-s3c2410/s3c244x.c deleted file mode 100644 index 23c7494ad10d..000000000000 --- a/arch/arm/mach-s3c2410/s3c244x.c +++ /dev/null @@ -1,184 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c244x.c - * - * Copyright (c) 2004-2006 Simtec Electronics - * Ben Dooks - * - * Samsung S3C2440 and S3C2442 Mobile CPU support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "s3c2410.h" -#include "s3c2440.h" -#include "s3c244x.h" -#include "clock.h" -#include "devs.h" -#include "cpu.h" -#include "pm.h" - -static struct map_desc s3c244x_iodesc[] __initdata = { - IODESC_ENT(CLKPWR), - IODESC_ENT(TIMER), - IODESC_ENT(WATCHDOG), - IODESC_ENT(LCD), -}; - -/* uart initialisation */ - -void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no) -{ - s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no); -} - -void __init s3c244x_map_io(struct map_desc *mach_desc, int size) -{ - /* register our io-tables */ - - iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc)); - iotable_init(mach_desc, size); - - /* rename any peripherals used differing from the s3c2410 */ - - s3c_device_i2c.name = "s3c2440-i2c"; - s3c_device_nand.name = "s3c2440-nand"; - s3c_device_usbgadget.name = "s3c2440-usbgadget"; -} - -void __init s3c244x_init_clocks(int xtal) -{ - unsigned long clkdiv; - unsigned long camdiv; - unsigned long hclk, fclk, pclk; - int hdiv = 1; - - /* now we've got our machine bits initialised, work out what - * clocks we've got */ - - fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; - - clkdiv = __raw_readl(S3C2410_CLKDIVN); - camdiv = __raw_readl(S3C2440_CAMDIVN); - - /* work out clock scalings */ - - switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) { - case S3C2440_CLKDIVN_HDIVN_1: - hdiv = 1; - break; - - case S3C2440_CLKDIVN_HDIVN_2: - hdiv = 2; - break; - - case S3C2440_CLKDIVN_HDIVN_4_8: - hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4; - break; - - case S3C2440_CLKDIVN_HDIVN_3_6: - hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3; - break; - } - - hclk = fclk / hdiv; - pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1); - - /* print brief summary of clocks, etc */ - - printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", - print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); - - /* initialise the clocks here, to allow other things like the - * console to use them, and to add new ones after the initialisation - */ - - s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); - s3c2410_baseclk_add(); -} - -#ifdef CONFIG_PM - -static struct sleep_save s3c244x_sleep[] = { - SAVE_ITEM(S3C2440_DSC0), - SAVE_ITEM(S3C2440_DSC1), - SAVE_ITEM(S3C2440_GPJDAT), - SAVE_ITEM(S3C2440_GPJCON), - SAVE_ITEM(S3C2440_GPJUP) -}; - -static int s3c244x_suspend(struct sys_device *dev, pm_message_t state) -{ - s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); - return 0; -} - -static int s3c244x_resume(struct sys_device *dev) -{ - s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); - return 0; -} - -#else -#define s3c244x_suspend NULL -#define s3c244x_resume NULL -#endif - -/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */ - -struct sysdev_class s3c2440_sysclass = { - set_kset_name("s3c2440-core"), - .suspend = s3c244x_suspend, - .resume = s3c244x_resume -}; - -struct sysdev_class s3c2442_sysclass = { - set_kset_name("s3c2442-core"), - .suspend = s3c244x_suspend, - .resume = s3c244x_resume -}; - -/* need to register class before we actually register the device, and - * we also need to ensure that it has been initialised before any of the - * drivers even try to use it (even if not on an s3c2440 based system) - * as a driver which may support both 2410 and 2440 may try and use it. -*/ - -static int __init s3c2440_core_init(void) -{ - return sysdev_class_register(&s3c2440_sysclass); -} - -core_initcall(s3c2440_core_init); - -static int __init s3c2442_core_init(void) -{ - return sysdev_class_register(&s3c2442_sysclass); -} - -core_initcall(s3c2442_core_init); diff --git a/arch/arm/mach-s3c2410/s3c244x.h b/arch/arm/mach-s3c2410/s3c244x.h deleted file mode 100644 index 1488c1eb37e6..000000000000 --- a/arch/arm/mach-s3c2410/s3c244x.h +++ /dev/null @@ -1,25 +0,0 @@ -/* arch/arm/mach-s3c2410/s3c244x.h - * - * Copyright (c) 2004-2005 Simtec Electronics - * Ben Dooks - * - * Header file for S3C2440 and S3C2442 cpu support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) - -extern void s3c244x_map_io(struct map_desc *mach_desc, int size); - -extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); - -extern void s3c244x_init_clocks(int xtal); - -#else -#define s3c244x_init_clocks NULL -#define s3c244x_init_uarts NULL -#define s3c244x_map_io NULL -#endif diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S index 2018c2e1dcc5..9179a1024588 100644 --- a/arch/arm/mach-s3c2410/sleep.S +++ b/arch/arm/mach-s3c2410/sleep.S @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c2410/sleep.S +/* linux/arch/arm/mach-s3c2410/s3c2410-sleep.S * * Copyright (c) 2004 Simtec Electronics * Ben Dooks @@ -34,126 +34,35 @@ #include #include -/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not - * reset the UART configuration, only enable if you really need this! -*/ -//#define CONFIG_DEBUG_RESUME - - .text - - /* s3c2410_cpu_save - * - * save enough of the CPU state to allow us to re-start - * pm.c code. as we store items like the sp/lr, we will - * end up returning from this function when the cpu resumes - * so the return value is set to mark this. - * - * This arangement means we avoid having to flush the cache - * from this code. - * - * entry: - * r0 = pointer to save block - * - * exit: - * r0 = 0 => we stored everything - * 1 => resumed from sleep - */ - -ENTRY(s3c2410_cpu_save) - stmfd sp!, { r4 - r12, lr } - - @@ store co-processor registers - - mrc p15, 0, r4, c15, c1, 0 @ CP access register - mrc p15, 0, r5, c13, c0, 0 @ PID - mrc p15, 0, r6, c3, c0, 0 @ Domain ID - mrc p15, 0, r7, c2, c0, 0 @ translation table base address - mrc p15, 0, r8, c1, c0, 0 @ control register - - stmia r0, { r4 - r13 } - - mov r0, #0 - ldmfd sp, { r4 - r12, pc } - - @@ return to the caller, after having the MMU - @@ turned on, this restores the last bits from the - @@ stack -resume_with_mmu: - mov r0, #1 - ldmfd sp!, { r4 - r12, pc } - - .ltorg - - @@ the next bits sit in the .data segment, even though they - @@ happen to be code... the s3c2410_sleep_save_phys needs to be - @@ accessed by the resume code before it can restore the MMU. - @@ This means that the variable has to be close enough for the - @@ code to read it... since the .text segment needs to be RO, - @@ the data segment can be the only place to put this code. - - .data - - .global s3c2410_sleep_save_phys -s3c2410_sleep_save_phys: - .word 0 - - /* s3c2410_cpu_resume + /* s3c2410_cpu_suspend * - * resume code entry for bootloader to call - * - * we must put this code here in the data segment as we have no - * other way of restoring the stack pointer after sleep, and we - * must not write to the code segment (code is read-only) + * put the cpu into sleep mode */ -ENTRY(s3c2410_cpu_resume) - mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE - msr cpsr_c, r0 - - @@ load UART to allow us to print the two characters for - @@ resume debug - - mov r2, #S3C24XX_PA_UART & 0xff000000 - orr r2, r2, #S3C24XX_PA_UART & 0xff000 - -#if 0 - /* SMDK2440 LED set */ - mov r14, #S3C24XX_PA_GPIO - ldr r12, [ r14, #0x54 ] - bic r12, r12, #3<<4 - orr r12, r12, #1<<7 - str r12, [ r14, #0x54 ] -#endif - -#ifdef CONFIG_DEBUG_RESUME - mov r3, #'L' - strb r3, [ r2, #S3C2410_UTXH ] -1001: - ldrb r14, [ r3, #S3C2410_UTRSTAT ] - tst r14, #S3C2410_UTRSTAT_TXE - beq 1001b -#endif /* CONFIG_DEBUG_RESUME */ - - mov r1, #0 - mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs - mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches - - ldr r0, s3c2410_sleep_save_phys @ address of restore block - ldmia r0, { r4 - r13 } - - mcr p15, 0, r4, c15, c1, 0 @ CP access register - mcr p15, 0, r5, c13, c0, 0 @ PID - mcr p15, 0, r6, c3, c0, 0 @ Domain ID - mcr p15, 0, r7, c2, c0, 0 @ translation table base - -#ifdef CONFIG_DEBUG_RESUME - mov r3, #'R' - strb r3, [ r2, #S3C2410_UTXH ] -#endif - - ldr r2, =resume_with_mmu - mcr p15, 0, r8, c1, c0, 0 @ turn on MMU, etc - nop @ second-to-last before mmu - mov pc, r2 @ go back to virtual address - - .ltorg +ENTRY(s3c2410_cpu_suspend) + @@ prepare cpu to sleep + + ldr r4, =S3C2410_REFRESH + ldr r5, =S3C24XX_MISCCR + ldr r6, =S3C2410_CLKCON + ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB) + ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB) + ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB) + + orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command + orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals + orr r9, r9, #S3C2410_CLKCON_POWER @ power down command + + teq pc, #0 @ first as a trial-run to load cache + bl s3c2410_do_sleep + teq r0, r0 @ now do it for real + b s3c2410_do_sleep @ + + @@ align next bit of code to cache line + .align 8 +s3c2410_do_sleep: + streq r7, [ r4 ] @ SDRAM sleep command + streq r8, [ r5 ] @ SDRAM power-down config + streq r9, [ r6 ] @ CPU sleep +1: beq 1b + mov pc, r14 diff --git a/arch/arm/mach-s3c2410/time.c b/arch/arm/mach-s3c2410/time.c deleted file mode 100644 index 9910bf0f2cea..000000000000 --- a/arch/arm/mach-s3c2410/time.c +++ /dev/null @@ -1,262 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/time.c - * - * Copyright (C) 2003-2005 Simtec Electronics - * Ben Dooks, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "clock.h" -#include "cpu.h" - -static unsigned long timer_startval; -static unsigned long timer_usec_ticks; - -#define TIMER_USEC_SHIFT 16 - -/* we use the shifted arithmetic to work out the ratio of timer ticks - * to usecs, as often the peripheral clock is not a nice even multiple - * of 1MHz. - * - * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok - * for the current HZ value of 200 without producing overflows. - * - * Original patch by Dimitry Andric, updated by Ben Dooks -*/ - - -/* timer_mask_usec_ticks - * - * given a clock and divisor, make the value to pass into timer_ticks_to_usec - * to scale the ticks into usecs -*/ - -static inline unsigned long -timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk) -{ - unsigned long den = pclk / 1000; - - return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den; -} - -/* timer_ticks_to_usec - * - * convert timer ticks to usec. -*/ - -static inline unsigned long timer_ticks_to_usec(unsigned long ticks) -{ - unsigned long res; - - res = ticks * timer_usec_ticks; - res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */ - - return res >> TIMER_USEC_SHIFT; -} - -/*** - * Returns microsecond since last clock interrupt. Note that interrupts - * will have been disabled by do_gettimeoffset() - * IRQs are disabled before entering here from do_gettimeofday() - */ - -#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) - -static unsigned long s3c2410_gettimeoffset (void) -{ - unsigned long tdone; - unsigned long irqpend; - unsigned long tval; - - /* work out how many ticks have gone since last timer interrupt */ - - tval = __raw_readl(S3C2410_TCNTO(4)); - tdone = timer_startval - tval; - - /* check to see if there is an interrupt pending */ - - irqpend = __raw_readl(S3C2410_SRCPND); - if (irqpend & SRCPND_TIMER4) { - /* re-read the timer, and try and fix up for the missed - * interrupt. Note, the interrupt may go off before the - * timer has re-loaded from wrapping. - */ - - tval = __raw_readl(S3C2410_TCNTO(4)); - tdone = timer_startval - tval; - - if (tval != 0) - tdone += timer_startval; - } - - return timer_ticks_to_usec(tdone); -} - - -/* - * IRQ handler for the timer - */ -static irqreturn_t -s3c2410_timer_interrupt(int irq, void *dev_id) -{ - write_seqlock(&xtime_lock); - timer_tick(); - write_sequnlock(&xtime_lock); - return IRQ_HANDLED; -} - -static struct irqaction s3c2410_timer_irq = { - .name = "S3C2410 Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = s3c2410_timer_interrupt, -}; - -#define use_tclk1_12() ( \ - machine_is_bast() || \ - machine_is_vr1000() || \ - machine_is_anubis() || \ - machine_is_osiris() ) - -/* - * Set up timer interrupt, and return the current time in seconds. - * - * Currently we only use timer4, as it is the only timer which has no - * other function that can be exploited externally - */ -static void s3c2410_timer_setup (void) -{ - unsigned long tcon; - unsigned long tcnt; - unsigned long tcfg1; - unsigned long tcfg0; - - tcnt = 0xffff; /* default value for tcnt */ - - /* read the current timer configuration bits */ - - tcon = __raw_readl(S3C2410_TCON); - tcfg1 = __raw_readl(S3C2410_TCFG1); - tcfg0 = __raw_readl(S3C2410_TCFG0); - - /* configure the system for whichever machine is in use */ - - if (use_tclk1_12()) { - /* timer is at 12MHz, scaler is 1 */ - timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); - tcnt = 12000000 / HZ; - - tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; - tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1; - } else { - unsigned long pclk; - struct clk *clk; - - /* for the h1940 (and others), we use the pclk from the core - * to generate the timer values. since values around 50 to - * 70MHz are not values we can directly generate the timer - * value from, we need to pre-scale and divide before using it. - * - * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz - * (8.45 ticks per usec) - */ - - /* this is used as default if no other timer can be found */ - - clk = clk_get(NULL, "timers"); - if (IS_ERR(clk)) - panic("failed to get clock for system timer"); - - clk_enable(clk); - - pclk = clk_get_rate(clk); - - /* configure clock tick */ - - timer_usec_ticks = timer_mask_usec_ticks(6, pclk); - - tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; - tcfg1 |= S3C2410_TCFG1_MUX4_DIV2; - - tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; - tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT; - - tcnt = (pclk / 6) / HZ; - } - - /* timers reload after counting zero, so reduce the count by 1 */ - - tcnt--; - - printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n", - tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks); - - /* check to see if timer is within 16bit range... */ - if (tcnt > 0xffff) { - panic("setup_timer: HZ is too small, cannot configure timer!"); - return; - } - - __raw_writel(tcfg1, S3C2410_TCFG1); - __raw_writel(tcfg0, S3C2410_TCFG0); - - timer_startval = tcnt; - __raw_writel(tcnt, S3C2410_TCNTB(4)); - - /* ensure timer is stopped... */ - - tcon &= ~(7<<20); - tcon |= S3C2410_TCON_T4RELOAD; - tcon |= S3C2410_TCON_T4MANUALUPD; - - __raw_writel(tcon, S3C2410_TCON); - __raw_writel(tcnt, S3C2410_TCNTB(4)); - __raw_writel(tcnt, S3C2410_TCMPB(4)); - - /* start the timer running */ - tcon |= S3C2410_TCON_T4START; - tcon &= ~S3C2410_TCON_T4MANUALUPD; - __raw_writel(tcon, S3C2410_TCON); -} - -static void __init s3c2410_timer_init (void) -{ - s3c2410_timer_setup(); - setup_irq(IRQ_TIMER4, &s3c2410_timer_irq); -} - -struct sys_timer s3c24xx_timer = { - .init = s3c2410_timer_init, - .offset = s3c2410_gettimeoffset, - .resume = s3c2410_timer_setup -}; diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c index 22b0e1cdd4bf..bcd562ac1d3d 100644 --- a/arch/arm/mach-s3c2410/usb-simtec.c +++ b/arch/arm/mach-s3c2410/usb-simtec.c @@ -35,7 +35,7 @@ #include #include -#include "devs.h" +#include #include "usb-simtec.h" /* control power and monitor over-current events on various Simtec diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig new file mode 100644 index 000000000000..6d629de84cdb --- /dev/null +++ b/arch/arm/mach-s3c2412/Kconfig @@ -0,0 +1,58 @@ +# arch/arm/mach-s3c2412/Kconfig +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + +config CPU_S3C2412 + bool + depends on ARCH_S3C2410 + select S3C2412_PM if PM + select S3C2412_DMA if S3C2410_DMA + help + Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line + +config CPU_S3C2412_ONLY + bool + depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \ + !CPU_S3C2440 && !CPU_S3C2442 && CPU_S3C2412 + default y if CPU_S3C2412 + +config S3C2412_DMA + bool + depends on CPU_S3C2412 + help + Internal config node for S3C2412 DMA support + +config S3C2412_PM + bool + help + Internal config node to apply S3C2412 power management + + +menu "S3C2412 Machines" + +config MACH_SMDK2413 + bool "SMDK2413" + select CPU_S3C2412 + select MACH_S3C2413 + select MACH_SMDK + help + Say Y here if you are using an SMDK2413 + +config MACH_S3C2413 + bool + help + Internal node for S3C2413 version of SMDK2413, so that + machine_is_s3c2413() will work when MACH_SMDK2413 is + selected + +config MACH_VSTMS + bool "VMSTMS" + select CPU_S3C2412 + help + Say Y here if you are using an VSTMS board + + +endmenu + diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile new file mode 100644 index 000000000000..f8e011691b31 --- /dev/null +++ b/arch/arm/mach-s3c2412/Makefile @@ -0,0 +1,21 @@ +# arch/arm/mach-s3c2412/Makefile +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +obj-$(CONFIG_CPU_S3C2412) += s3c2412.o +obj-$(CONFIG_CPU_S3C2412) += irq.o +obj-$(CONFIG_CPU_S3C2412) += clock.o +obj-$(CONFIG_S3C2412_DMA) += dma.o +obj-$(CONFIG_S3C2412_PM) += pm.o + +# Machine support + +obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o +obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c new file mode 100644 index 000000000000..6a8e4448770b --- /dev/null +++ b/arch/arm/mach-s3c2412/clock.c @@ -0,0 +1,716 @@ +/* linux/arch/arm/mach-s3c2412/clock.c + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * S3C2412,S3C2413 Clock control support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +/* We currently have to assume that the system is running + * from the XTPll input, and that all ***REFCLKs are being + * fed from it, as we cannot read the state of OM[4] from + * software. + * + * It would be possible for each board initialisation to + * set the correct muxing at initialisation +*/ + +static int s3c2412_clkcon_enable(struct clk *clk, int enable) +{ + unsigned int clocks = clk->ctrlbit; + unsigned long clkcon; + + clkcon = __raw_readl(S3C2410_CLKCON); + + if (enable) + clkcon |= clocks; + else + clkcon &= ~clocks; + + __raw_writel(clkcon, S3C2410_CLKCON); + + return 0; +} + +static int s3c2412_upll_enable(struct clk *clk, int enable) +{ + unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); + unsigned long orig = upllcon; + + if (!enable) + upllcon |= S3C2412_PLLCON_OFF; + else + upllcon &= ~S3C2412_PLLCON_OFF; + + __raw_writel(upllcon, S3C2410_UPLLCON); + + /* allow ~150uS for the PLL to settle and lock */ + + if (enable && (orig & S3C2412_PLLCON_OFF)) + udelay(150); + + return 0; +} + +/* clock selections */ + +/* CPU EXTCLK input */ +static struct clk clk_ext = { + .name = "extclk", + .id = -1, +}; + +static struct clk clk_erefclk = { + .name = "erefclk", + .id = -1, +}; + +static struct clk clk_urefclk = { + .name = "urefclk", + .id = -1, +}; + +static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) +{ + unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); + + if (parent == &clk_urefclk) + clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL; + else if (parent == &clk_upll) + clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL; + else + return -EINVAL; + + clk->parent = parent; + + __raw_writel(clksrc, S3C2412_CLKSRC); + return 0; +} + +static struct clk clk_usysclk = { + .name = "usysclk", + .id = -1, + .parent = &clk_xtal, + .set_parent = s3c2412_setparent_usysclk, +}; + +static struct clk clk_mrefclk = { + .name = "mrefclk", + .parent = &clk_xtal, + .id = -1, +}; + +static struct clk clk_mdivclk = { + .name = "mdivclk", + .parent = &clk_xtal, + .id = -1, +}; + +static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) +{ + unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); + + if (parent == &clk_usysclk) + clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK; + else if (parent == &clk_h) + clksrc |= S3C2412_CLKSRC_USBCLK_HCLK; + else + return -EINVAL; + + clk->parent = parent; + + __raw_writel(clksrc, S3C2412_CLKSRC); + return 0; +} + +static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk, + unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + int div; + + if (rate > parent_rate) + return parent_rate; + + div = parent_rate / rate; + if (div > 2) + div = 2; + + return parent_rate / div; +} + +static unsigned long s3c2412_getrate_usbsrc(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2410_CLKDIVN); + + return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1); +} + +static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); + + rate = s3c2412_roundrate_usbsrc(clk, rate); + + if ((parent_rate / rate) == 2) + clkdivn |= S3C2412_CLKDIVN_USB48DIV; + else + clkdivn &= ~S3C2412_CLKDIVN_USB48DIV; + + __raw_writel(clkdivn, S3C2410_CLKDIVN); + return 0; +} + +static struct clk clk_usbsrc = { + .name = "usbsrc", + .id = -1, + .get_rate = s3c2412_getrate_usbsrc, + .set_rate = s3c2412_setrate_usbsrc, + .round_rate = s3c2412_roundrate_usbsrc, + .set_parent = s3c2412_setparent_usbsrc, +}; + +static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) +{ + unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); + + if (parent == &clk_mdivclk) + clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL; + else if (parent == &clk_upll) + clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL; + else + return -EINVAL; + + clk->parent = parent; + + __raw_writel(clksrc, S3C2412_CLKSRC); + return 0; +} + +static struct clk clk_msysclk = { + .name = "msysclk", + .id = -1, + .set_parent = s3c2412_setparent_msysclk, +}; + +/* these next clocks have an divider immediately after them, + * so we can register them with their divider and leave out the + * intermediate clock stage +*/ +static unsigned long s3c2412_roundrate_clksrc(struct clk *clk, + unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + int div; + + if (rate > parent_rate) + return parent_rate; + + /* note, we remove the +/- 1 calculations as they cancel out */ + + div = (rate / parent_rate); + + if (div < 1) + div = 1; + else if (div > 16) + div = 16; + + return parent_rate / div; +} + +static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent) +{ + unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); + + if (parent == &clk_erefclk) + clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL; + else if (parent == &clk_mpll) + clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL; + else + return -EINVAL; + + clk->parent = parent; + + __raw_writel(clksrc, S3C2412_CLKSRC); + return 0; +} + +static unsigned long s3c2412_getrate_uart(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2410_CLKDIVN); + + div &= S3C2412_CLKDIVN_UARTDIV_MASK; + div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT; + + return parent_rate / (div + 1); +} + +static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); + + rate = s3c2412_roundrate_clksrc(clk, rate); + + clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK; + clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT; + + __raw_writel(clkdivn, S3C2410_CLKDIVN); + return 0; +} + +static struct clk clk_uart = { + .name = "uartclk", + .id = -1, + .get_rate = s3c2412_getrate_uart, + .set_rate = s3c2412_setrate_uart, + .set_parent = s3c2412_setparent_uart, + .round_rate = s3c2412_roundrate_clksrc, +}; + +static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent) +{ + unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); + + if (parent == &clk_erefclk) + clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL; + else if (parent == &clk_mpll) + clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL; + else + return -EINVAL; + + clk->parent = parent; + + __raw_writel(clksrc, S3C2412_CLKSRC); + return 0; +} + +static unsigned long s3c2412_getrate_i2s(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2410_CLKDIVN); + + div &= S3C2412_CLKDIVN_I2SDIV_MASK; + div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT; + + return parent_rate / (div + 1); +} + +static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); + + rate = s3c2412_roundrate_clksrc(clk, rate); + + clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK; + clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT; + + __raw_writel(clkdivn, S3C2410_CLKDIVN); + return 0; +} + +static struct clk clk_i2s = { + .name = "i2sclk", + .id = -1, + .get_rate = s3c2412_getrate_i2s, + .set_rate = s3c2412_setrate_i2s, + .set_parent = s3c2412_setparent_i2s, + .round_rate = s3c2412_roundrate_clksrc, +}; + +static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent) +{ + unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); + + if (parent == &clk_usysclk) + clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK; + else if (parent == &clk_h) + clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK; + else + return -EINVAL; + + clk->parent = parent; + + __raw_writel(clksrc, S3C2412_CLKSRC); + return 0; +} +static unsigned long s3c2412_getrate_cam(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2410_CLKDIVN); + + div &= S3C2412_CLKDIVN_CAMDIV_MASK; + div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT; + + return parent_rate / (div + 1); +} + +static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); + + rate = s3c2412_roundrate_clksrc(clk, rate); + + clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK; + clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT; + + __raw_writel(clkdivn, S3C2410_CLKDIVN); + return 0; +} + +static struct clk clk_cam = { + .name = "camif-upll", /* same as 2440 name */ + .id = -1, + .get_rate = s3c2412_getrate_cam, + .set_rate = s3c2412_setrate_cam, + .set_parent = s3c2412_setparent_cam, + .round_rate = s3c2412_roundrate_clksrc, +}; + +/* standard clock definitions */ + +static struct clk init_clocks_disable[] = { + { + .name = "nand", + .id = -1, + .parent = &clk_h, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_NAND, + }, { + .name = "sdi", + .id = -1, + .parent = &clk_p, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_SDI, + }, { + .name = "adc", + .id = -1, + .parent = &clk_p, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_ADC, + }, { + .name = "i2c", + .id = -1, + .parent = &clk_p, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_IIC, + }, { + .name = "iis", + .id = -1, + .parent = &clk_p, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_IIS, + }, { + .name = "spi", + .id = -1, + .parent = &clk_p, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_SPI, + } +}; + +static struct clk init_clocks[] = { + { + .name = "dma", + .id = 0, + .parent = &clk_h, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_DMA0, + }, { + .name = "dma", + .id = 1, + .parent = &clk_h, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_DMA1, + }, { + .name = "dma", + .id = 2, + .parent = &clk_h, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_DMA2, + }, { + .name = "dma", + .id = 3, + .parent = &clk_h, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_DMA3, + }, { + .name = "lcd", + .id = -1, + .parent = &clk_h, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_LCDC, + }, { + .name = "gpio", + .id = -1, + .parent = &clk_p, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_GPIO, + }, { + .name = "usb-host", + .id = -1, + .parent = &clk_h, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_USBH, + }, { + .name = "usb-device", + .id = -1, + .parent = &clk_h, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_USBD, + }, { + .name = "timers", + .id = -1, + .parent = &clk_p, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_PWMT, + }, { + .name = "uart", + .id = 0, + .parent = &clk_p, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_UART0, + }, { + .name = "uart", + .id = 1, + .parent = &clk_p, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_UART1, + }, { + .name = "uart", + .id = 2, + .parent = &clk_p, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_UART2, + }, { + .name = "rtc", + .id = -1, + .parent = &clk_p, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_RTC, + }, { + .name = "watchdog", + .id = -1, + .parent = &clk_p, + .ctrlbit = 0, + }, { + .name = "usb-bus-gadget", + .id = -1, + .parent = &clk_usb_bus, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_USB_DEV48, + }, { + .name = "usb-bus-host", + .id = -1, + .parent = &clk_usb_bus, + .enable = s3c2412_clkcon_enable, + .ctrlbit = S3C2412_CLKCON_USB_HOST48, + } +}; + +/* clocks to add where we need to check their parentage */ + +struct clk_init { + struct clk *clk; + unsigned int bit; + struct clk *src_0; + struct clk *src_1; +}; + +static struct clk_init clks_src[] __initdata = { + { + .clk = &clk_usysclk, + .bit = S3C2412_CLKSRC_USBCLK_HCLK, + .src_0 = &clk_urefclk, + .src_1 = &clk_upll, + }, { + .clk = &clk_i2s, + .bit = S3C2412_CLKSRC_I2SCLK_MPLL, + .src_0 = &clk_erefclk, + .src_1 = &clk_mpll, + }, { + .clk = &clk_cam, + .bit = S3C2412_CLKSRC_CAMCLK_HCLK, + .src_0 = &clk_usysclk, + .src_1 = &clk_h, + }, { + .clk = &clk_msysclk, + .bit = S3C2412_CLKSRC_MSYSCLK_MPLL, + .src_0 = &clk_mdivclk, + .src_1 = &clk_mpll, + }, { + .clk = &clk_uart, + .bit = S3C2412_CLKSRC_UARTCLK_MPLL, + .src_0 = &clk_erefclk, + .src_1 = &clk_mpll, + }, { + .clk = &clk_usbsrc, + .bit = S3C2412_CLKSRC_USBCLK_HCLK, + .src_0 = &clk_usysclk, + .src_1 = &clk_h, + }, +}; + +/* s3c2412_clk_initparents + * + * Initialise the parents for the clocks that we get at start-time +*/ + +static void __init s3c2412_clk_initparents(void) +{ + unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); + struct clk_init *cip = clks_src; + struct clk *src; + int ptr; + int ret; + + for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) { + ret = s3c24xx_register_clock(cip->clk); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + cip->clk->name, ret); + } + + src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0; + + printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name); + clk_set_parent(cip->clk, src); + } +} + +/* clocks to add straight away */ + +static struct clk *clks[] __initdata = { + &clk_ext, + &clk_usb_bus, + &clk_erefclk, + &clk_urefclk, + &clk_mrefclk, +}; + +int __init s3c2412_baseclk_add(void) +{ + unsigned long clkcon = __raw_readl(S3C2410_CLKCON); + struct clk *clkp; + int ret; + int ptr; + + clk_upll.enable = s3c2412_upll_enable; + clk_usb_bus.parent = &clk_usbsrc; + clk_usb_bus.rate = 0x0; + + s3c2412_clk_initparents(); + + for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { + clkp = clks[ptr]; + + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + } + + /* ensure usb bus clock is within correct rate of 48MHz */ + + if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) { + printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n"); + + /* for the moment, let's use the UPLL, and see if we can + * get 48MHz */ + + clk_set_parent(&clk_usysclk, &clk_upll); + clk_set_parent(&clk_usbsrc, &clk_usysclk); + clk_set_rate(&clk_usbsrc, 48*1000*1000); + } + + printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", + (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on", + print_mhz(clk_get_rate(&clk_upll)), + print_mhz(clk_get_rate(&clk_usb_bus))); + + /* register clocks from clock array */ + + clkp = init_clocks; + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { + /* ensure that we note the clock state */ + + clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0; + + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + } + + /* We must be careful disabling the clocks we are not intending to + * be using at boot time, as subsytems such as the LCD which do + * their own DMA requests to the bus can cause the system to lockup + * if they where in the middle of requesting bus access. + * + * Disabling the LCD clock if the LCD is active is very dangerous, + * and therefore the bootloader should be careful to not enable + * the LCD clock if it is not needed. + */ + + /* install (and disable) the clocks we do not need immediately */ + + clkp = init_clocks_disable; + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { + + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + + s3c2412_clkcon_enable(clkp, 0); + } + + return 0; +} diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c new file mode 100644 index 000000000000..28b598287fae --- /dev/null +++ b/arch/arm/mach-s3c2412/dma.c @@ -0,0 +1,161 @@ +/* linux/arch/arm/mach-s3c2412/dma.c + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * S3C2412 DMA selection + * + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID } + +static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = { + [DMACH_XD0] = { + .name = "xdreq0", + .channels = MAP(S3C2412_DMAREQSEL_XDREQ0), + }, + [DMACH_XD1] = { + .name = "xdreq1", + .channels = MAP(S3C2412_DMAREQSEL_XDREQ1), + }, + [DMACH_SDI] = { + .name = "sdi", + .channels = MAP(S3C2412_DMAREQSEL_SDI), + .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, + .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, + }, + [DMACH_SPI0] = { + .name = "spi0", + .channels = MAP(S3C2412_DMAREQSEL_SPI0TX), + .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, + .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, + }, + [DMACH_SPI1] = { + .name = "spi1", + .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), + .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, + .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, + }, + [DMACH_UART0] = { + .name = "uart0", + .channels = MAP(S3C2412_DMAREQSEL_UART0_0), + .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, + }, + [DMACH_UART1] = { + .name = "uart1", + .channels = MAP(S3C2412_DMAREQSEL_UART1_0), + .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, + }, + [DMACH_UART2] = { + .name = "uart2", + .channels = MAP(S3C2412_DMAREQSEL_UART2_0), + .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, + }, + [DMACH_UART0_SRC2] = { + .name = "uart0", + .channels = MAP(S3C2412_DMAREQSEL_UART0_1), + .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, + }, + [DMACH_UART1_SRC2] = { + .name = "uart1", + .channels = MAP(S3C2412_DMAREQSEL_UART1_1), + .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, + }, + [DMACH_UART2_SRC2] = { + .name = "uart2", + .channels = MAP(S3C2412_DMAREQSEL_UART2_1), + .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, + }, + [DMACH_TIMER] = { + .name = "timer", + .channels = MAP(S3C2412_DMAREQSEL_TIMER), + }, + [DMACH_I2S_IN] = { + .name = "i2s-sdi", + .channels = MAP(S3C2412_DMAREQSEL_I2SRX), + .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, + }, + [DMACH_I2S_OUT] = { + .name = "i2s-sdo", + .channels = MAP(S3C2412_DMAREQSEL_I2STX), + .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, + }, + [DMACH_USB_EP1] = { + .name = "usb-ep1", + .channels = MAP(S3C2412_DMAREQSEL_USBEP1), + }, + [DMACH_USB_EP2] = { + .name = "usb-ep2", + .channels = MAP(S3C2412_DMAREQSEL_USBEP2), + }, + [DMACH_USB_EP3] = { + .name = "usb-ep3", + .channels = MAP(S3C2412_DMAREQSEL_USBEP3), + }, + [DMACH_USB_EP4] = { + .name = "usb-ep4", + .channels = MAP(S3C2412_DMAREQSEL_USBEP4), + }, +}; + +static void s3c2412_dma_select(struct s3c2410_dma_chan *chan, + struct s3c24xx_dma_map *map) +{ + writel(map->channels[0] | S3C2412_DMAREQSEL_HW, + chan->regs + S3C2412_DMA_DMAREQSEL); +} + +static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { + .select = s3c2412_dma_select, + .dcon_mask = 0, + .map = s3c2412_dma_mappings, + .map_size = ARRAY_SIZE(s3c2412_dma_mappings), +}; + +static int s3c2412_dma_add(struct sys_device *sysdev) +{ + return s3c24xx_dma_init_map(&s3c2412_dma_sel); +} + +static struct sysdev_driver s3c2412_dma_driver = { + .add = s3c2412_dma_add, +}; + +static int __init s3c2412_dma_init(void) +{ + return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver); +} + +arch_initcall(s3c2412_dma_init); diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c new file mode 100644 index 000000000000..e89dbdcb1b7b --- /dev/null +++ b/arch/arm/mach-s3c2412/irq.c @@ -0,0 +1,133 @@ +/* linux/arch/arm/mach-s3c2412/irq.c + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * +*/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by + * having them turn up in both the INT* and the EINT* registers. Whilst + * both show the status, they both now need to be acked when the IRQs + * go off. +*/ + +static void +s3c2412_irq_mask(unsigned int irqno) +{ + unsigned long bitval = 1UL << (irqno - IRQ_EINT0); + unsigned long mask; + + mask = __raw_readl(S3C2410_INTMSK); + __raw_writel(mask | bitval, S3C2410_INTMSK); + + mask = __raw_readl(S3C2412_EINTMASK); + __raw_writel(mask | bitval, S3C2412_EINTMASK); +} + +static inline void +s3c2412_irq_ack(unsigned int irqno) +{ + unsigned long bitval = 1UL << (irqno - IRQ_EINT0); + + __raw_writel(bitval, S3C2412_EINTPEND); + __raw_writel(bitval, S3C2410_SRCPND); + __raw_writel(bitval, S3C2410_INTPND); +} + +static inline void +s3c2412_irq_maskack(unsigned int irqno) +{ + unsigned long bitval = 1UL << (irqno - IRQ_EINT0); + unsigned long mask; + + mask = __raw_readl(S3C2410_INTMSK); + __raw_writel(mask|bitval, S3C2410_INTMSK); + + mask = __raw_readl(S3C2412_EINTMASK); + __raw_writel(mask | bitval, S3C2412_EINTMASK); + + __raw_writel(bitval, S3C2412_EINTPEND); + __raw_writel(bitval, S3C2410_SRCPND); + __raw_writel(bitval, S3C2410_INTPND); +} + +static void +s3c2412_irq_unmask(unsigned int irqno) +{ + unsigned long bitval = 1UL << (irqno - IRQ_EINT0); + unsigned long mask; + + mask = __raw_readl(S3C2412_EINTMASK); + __raw_writel(mask & ~bitval, S3C2412_EINTMASK); + + mask = __raw_readl(S3C2410_INTMSK); + __raw_writel(mask & ~bitval, S3C2410_INTMSK); +} + +static struct irq_chip s3c2412_irq_eint0t4 = { + .ack = s3c2412_irq_ack, + .mask = s3c2412_irq_mask, + .unmask = s3c2412_irq_unmask, + .set_wake = s3c_irq_wake, + .set_type = s3c_irqext_type, +}; + +static int s3c2412_irq_add(struct sys_device *sysdev) +{ + unsigned int irqno; + + for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { + set_irq_chip(irqno, &s3c2412_irq_eint0t4); + set_irq_handler(irqno, handle_edge_irq); + set_irq_flags(irqno, IRQF_VALID); + } + + return 0; +} + +static struct sysdev_driver s3c2412_irq_driver = { + .add = s3c2412_irq_add, + .suspend = s3c24xx_irq_suspend, + .resume = s3c24xx_irq_resume, +}; + +static int s3c2412_irq_init(void) +{ + return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_irq_driver); +} + +arch_initcall(s3c2412_irq_init); diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c new file mode 100644 index 000000000000..32b15617ef2a --- /dev/null +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c @@ -0,0 +1,140 @@ +/* linux/arch/arm/mach-s3c2412/mach-smdk2413.c + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * Thanks to Dimity Andric (TomTom) and Steven Ryu (Samsung) for the + * loans of SMDK2413 to work with. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +//#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include + +static struct map_desc smdk2413_iodesc[] __initdata = { +}; + +static struct s3c2410_uartcfg smdk2413_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + }, + /* IR port */ + [2] = { + .hwport = 2, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x43, + .ufcon = 0x51, + } +}; + +static struct platform_device *smdk2413_devices[] __initdata = { + &s3c_device_usb, + //&s3c_device_lcd, + &s3c_device_wdt, + &s3c_device_i2c, + &s3c_device_iis, +}; + +static struct s3c24xx_board smdk2413_board __initdata = { + .devices = smdk2413_devices, + .devices_count = ARRAY_SIZE(smdk2413_devices) +}; + +static void __init smdk2413_fixup(struct machine_desc *desc, + struct tag *tags, char **cmdline, + struct meminfo *mi) +{ + if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) { + mi->nr_banks=1; + mi->bank[0].start = 0x30000000; + mi->bank[0].size = SZ_64M; + mi->bank[0].node = 0; + } +} + +static void __init smdk2413_map_io(void) +{ + s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc)); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs)); + s3c24xx_set_board(&smdk2413_board); +} + +static void __init smdk2413_machine_init(void) +{ + smdk_machine_init(); +} + +MACHINE_START(S3C2413, "S3C2413") + /* Maintainer: Ben Dooks */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + + .fixup = smdk2413_fixup, + .init_irq = s3c24xx_init_irq, + .map_io = smdk2413_map_io, + .init_machine = smdk2413_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END + +MACHINE_START(SMDK2413, "SMDK2413") + /* Maintainer: Ben Dooks */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + + .fixup = smdk2413_fixup, + .init_irq = s3c24xx_init_irq, + .map_io = smdk2413_map_io, + .init_machine = smdk2413_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c new file mode 100644 index 000000000000..f1afb707ff16 --- /dev/null +++ b/arch/arm/mach-s3c2412/mach-vstms.c @@ -0,0 +1,169 @@ +/* linux/arch/arm/mach-s3c2412/mach-vstms.c + * + * (C) 2006 Thomas Gleixner + * + * Derived from mach-smdk2413.c - (C) 2006 Simtec Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include + + +static struct map_desc vstms_iodesc[] __initdata = { +}; + +static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + } +}; + +static struct mtd_partition vstms_nand_part[] = { + [0] = { + .name = "Boot Agent", + .size = 0x7C000, + .offset = 0, + }, + [1] = { + .name = "UBoot Config", + .offset = 0x7C000, + .size = 0x4000, + }, + [2] = { + .name = "Kernel", + .offset = 0x80000, + .size = 0x200000, + }, + [3] = { + .name = "RFS", + .offset = 0x280000, + .size = 0x3d80000, + }, +}; + +static struct s3c2410_nand_set vstms_nand_sets[] = { + [0] = { + .name = "NAND", + .nr_chips = 1, + .nr_partitions = ARRAY_SIZE(vstms_nand_part), + .partitions = vstms_nand_part, + }, +}; + +/* choose a set of timings which should suit most 512Mbit + * chips and beyond. +*/ + +static struct s3c2410_platform_nand vstms_nand_info = { + .tacls = 20, + .twrph0 = 60, + .twrph1 = 20, + .nr_sets = ARRAY_SIZE(vstms_nand_sets), + .sets = vstms_nand_sets, +}; + +static struct platform_device *vstms_devices[] __initdata = { + &s3c_device_usb, + &s3c_device_wdt, + &s3c_device_i2c, + &s3c_device_iis, + &s3c_device_rtc, + &s3c_device_nand, +}; + +static struct s3c24xx_board vstms_board __initdata = { + .devices = vstms_devices, + .devices_count = ARRAY_SIZE(vstms_devices) +}; + +static void __init vstms_fixup(struct machine_desc *desc, + struct tag *tags, char **cmdline, + struct meminfo *mi) +{ + if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) { + mi->nr_banks=1; + mi->bank[0].start = 0x30000000; + mi->bank[0].size = SZ_64M; + mi->bank[0].node = 0; + } +} + +static void __init vstms_map_io(void) +{ + s3c_device_nand.dev.platform_data = &vstms_nand_info; + + s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc)); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs)); + s3c24xx_set_board(&vstms_board); +} + +MACHINE_START(VSTMS, "VSTMS") + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + + .fixup = vstms_fixup, + .init_irq = s3c24xx_init_irq, + .map_io = vstms_map_io, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c new file mode 100644 index 000000000000..8988dac388a9 --- /dev/null +++ b/arch/arm/mach-s3c2412/pm.c @@ -0,0 +1,128 @@ +/* linux/arch/arm/mach-s3c2412/pm.c + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * http://armlinux.simtec.co.uk/. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +static void s3c2412_cpu_suspend(void) +{ + unsigned long tmp; + + /* set our standby method to sleep */ + + tmp = __raw_readl(S3C2412_PWRCFG); + tmp |= S3C2412_PWRCFG_STANDBYWFI_SLEEP; + __raw_writel(tmp, S3C2412_PWRCFG); + + /* issue the standby signal into the pm unit. Note, we + * issue a write-buffer drain just in case */ + + tmp = 0; + + asm("b 1f\n\t" + ".align 5\n\t" + "1:\n\t" + "mcr p15, 0, %0, c7, c10, 4\n\t" + "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); + + /* we should never get past here */ + + panic("sleep resumed to originator?"); +} + +static void s3c2412_pm_prepare(void) +{ +} + +static int s3c2412_pm_add(struct sys_device *sysdev) +{ + pm_cpu_prep = s3c2412_pm_prepare; + pm_cpu_sleep = s3c2412_cpu_suspend; + + return 0; +} + +static struct sleep_save s3c2412_sleep[] = { + SAVE_ITEM(S3C2412_DSC0), + SAVE_ITEM(S3C2412_DSC1), + SAVE_ITEM(S3C2413_GPJDAT), + SAVE_ITEM(S3C2413_GPJCON), + SAVE_ITEM(S3C2413_GPJUP), + + /* save the PWRCFG to get back to original sleep method */ + + SAVE_ITEM(S3C2412_PWRCFG), + + /* save the sleep configuration anyway, just in case these + * get damaged during wakeup */ + + SAVE_ITEM(S3C2412_GPBSLPCON), + SAVE_ITEM(S3C2412_GPCSLPCON), + SAVE_ITEM(S3C2412_GPDSLPCON), + SAVE_ITEM(S3C2412_GPESLPCON), + SAVE_ITEM(S3C2412_GPFSLPCON), + SAVE_ITEM(S3C2412_GPGSLPCON), + SAVE_ITEM(S3C2412_GPHSLPCON), + SAVE_ITEM(S3C2413_GPJSLPCON), +}; + +static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state) +{ + s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); + return 0; +} + +static int s3c2412_pm_resume(struct sys_device *dev) +{ + unsigned long tmp; + + tmp = __raw_readl(S3C2412_PWRCFG); + tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK; + tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE; + __raw_writel(tmp, S3C2412_PWRCFG); + + s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); + return 0; +} + +static struct sysdev_driver s3c2412_pm_driver = { + .add = s3c2412_pm_add, + .suspend = s3c2412_pm_suspend, + .resume = s3c2412_pm_resume, +}; + +static __init int s3c2412_pm_init(void) +{ + return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver); +} + +arch_initcall(s3c2412_pm_init); diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c new file mode 100644 index 000000000000..aafe0bc593f1 --- /dev/null +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -0,0 +1,181 @@ +/* linux/arch/arm/mach-s3c2412/s3c2412.c + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * http://armlinux.simtec.co.uk/. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#ifndef CONFIG_CPU_S3C2412_ONLY +void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; + +static inline void s3c2412_init_gpio2(void) +{ + s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10; +} +#else +#define s3c2412_init_gpio2() do { } while(0) +#endif + +/* Initial IO mappings */ + +static struct map_desc s3c2412_iodesc[] __initdata = { + IODESC_ENT(CLKPWR), + IODESC_ENT(LCD), + IODESC_ENT(TIMER), + IODESC_ENT(WATCHDOG), +}; + +/* uart registration process */ + +void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no); + + /* rename devices that are s3c2412/s3c2413 specific */ + s3c_device_sdi.name = "s3c2412-sdi"; + s3c_device_lcd.name = "s3c2412-lcd"; + s3c_device_nand.name = "s3c2412-nand"; +} + +/* s3c2412_idle + * + * use the standard idle call by ensuring the idle mode + * in power config, then issuing the idle co-processor + * instruction +*/ + +static void s3c2412_idle(void) +{ + unsigned long tmp; + + /* ensure our idle mode is to go to idle */ + + tmp = __raw_readl(S3C2412_PWRCFG); + tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK; + tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE; + __raw_writel(tmp, S3C2412_PWRCFG); + + cpu_do_idle(); +} + +/* s3c2412_map_io + * + * register the standard cpu IO areas, and any passed in from the + * machine specific initialisation. +*/ + +void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size) +{ + /* move base of IO */ + + s3c2412_init_gpio2(); + + /* set our idle function */ + + s3c24xx_idle = s3c2412_idle; + + /* register our io-tables */ + + iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); + iotable_init(mach_desc, mach_size); +} + +void __init s3c2412_init_clocks(int xtal) +{ + unsigned long tmp; + unsigned long fclk; + unsigned long hclk; + unsigned long pclk; + + /* now we've got our machine bits initialised, work out what + * clocks we've got */ + + fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2); + + tmp = __raw_readl(S3C2410_CLKDIVN); + + /* work out clock scalings */ + + hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); + hclk /= ((tmp & S3C2421_CLKDIVN_ARMDIVN) ? 2 : 1); + pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); + + /* print brieft summary of clocks, etc */ + + printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", + print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); + + /* initialise the clocks here, to allow other things like the + * console to use them + */ + + s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); + s3c2412_baseclk_add(); +} + +/* need to register class before we actually register the device, and + * we also need to ensure that it has been initialised before any of the + * drivers even try to use it (even if not on an s3c2412 based system) + * as a driver which may support both 2410 and 2440 may try and use it. +*/ + +struct sysdev_class s3c2412_sysclass = { + set_kset_name("s3c2412-core"), +}; + +static int __init s3c2412_core_init(void) +{ + return sysdev_class_register(&s3c2412_sysclass); +} + +core_initcall(s3c2412_core_init); + +static struct sys_device s3c2412_sysdev = { + .cls = &s3c2412_sysclass, +}; + +int __init s3c2412_init(void) +{ + printk("S3C2412: Initialising architecture\n"); + + return sysdev_register(&s3c2412_sysdev); +} diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig new file mode 100644 index 000000000000..e3bfda098c0f --- /dev/null +++ b/arch/arm/mach-s3c2440/Kconfig @@ -0,0 +1,71 @@ +# arch/arm/mach-s3c2440/Kconfig +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + +config CPU_S3C2440 + bool + depends on ARCH_S3C2410 + select S3C2410_CLOCK + select S3C2410_PM if PM + select S3C2410_GPIO + select S3C2440_DMA if S3C2410_DMA + select CPU_S3C244X + help + Support for S3C2440 Samsung Mobile CPU based systems. + +config S3C2440_DMA + bool + depends on ARCH_S3C2410 && CPU_S3C24405B + help + Support for S3C2440 specific DMA code5A + + +menu "S3C2440 Machines" + +config MACH_ANUBIS + bool "Simtec Electronics ANUBIS" + select CPU_S3C2440 + select PM_SIMTEC if PM + help + Say Y here if you are using the Simtec Electronics ANUBIS + development system + +config MACH_OSIRIS + bool "Simtec IM2440D20 (OSIRIS) module" + select CPU_S3C2440 + select PM_SIMTEC if PM + help + Say Y here if you are using the Simtec IM2440D20 module, also + known as the Osiris. + +config MACH_RX3715 + bool "HP iPAQ rx3715" + select CPU_S3C2440 + select PM_H1940 if PM + help + Say Y here if you are using the HP iPAQ rx3715. + +config ARCH_S3C2440 + bool "SMDK2440" + select CPU_S3C2440 + select MACH_SMDK + help + Say Y here if you are using the SMDK2440. + +config MACH_NEXCODER_2440 + bool "NexVision NEXCODER 2440 Light Board" + select CPU_S3C2440 + help + Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board + +config SMDK2440_CPU2440 + bool "SMDK2440 with S3C2440 CPU module" + depends on ARCH_S3C2440 + default y if ARCH_S3C2440 + select CPU_S3C2440 + + +endmenu + diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile new file mode 100644 index 000000000000..c81ed6248dcb --- /dev/null +++ b/arch/arm/mach-s3c2440/Makefile @@ -0,0 +1,23 @@ +# arch/arm/mach-s3c2440/Makefile +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +obj-$(CONFIG_CPU_S3C2440) += s3c2440.o dsc.o +obj-$(CONFIG_CPU_S3C2440) += irq.o +obj-$(CONFIG_CPU_S3C2440) += clock.o +obj-$(CONFIG_S3C2440_DMA) += dma.o + +# Machine support + +obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o +obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o +obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o +obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o +obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c new file mode 100644 index 000000000000..79e2ea4adaf3 --- /dev/null +++ b/arch/arm/mach-s3c2440/clock.c @@ -0,0 +1,170 @@ +/* linux/arch/arm/mach-s3c2440/clock.c + * + * Copyright (c) 2004-2005 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C2440 Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include + +/* S3C2440 extended clock support */ + +static unsigned long s3c2440_camif_upll_round(struct clk *clk, + unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + int div; + + if (rate > parent_rate) + return parent_rate; + + /* note, we remove the +/- 1 calculations for the divisor */ + + div = (parent_rate / rate) / 2; + + if (div < 1) + div = 1; + else if (div > 16) + div = 16; + + return parent_rate / (div * 2); +} + +static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); + + rate = s3c2440_camif_upll_round(clk, rate); + + camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK); + + if (rate != parent_rate) { + camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; + camdivn |= (((parent_rate / rate) / 2) - 1); + } + + __raw_writel(camdivn, S3C2440_CAMDIVN); + + return 0; +} + +/* Extra S3C2440 clocks */ + +static struct clk s3c2440_clk_cam = { + .name = "camif", + .id = -1, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2440_CLKCON_CAMERA, +}; + +static struct clk s3c2440_clk_cam_upll = { + .name = "camif-upll", + .id = -1, + .set_rate = s3c2440_camif_upll_setrate, + .round_rate = s3c2440_camif_upll_round, +}; + +static struct clk s3c2440_clk_ac97 = { + .name = "ac97", + .id = -1, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2440_CLKCON_CAMERA, +}; + +static int s3c2440_clk_add(struct sys_device *sysdev) +{ + unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); + unsigned long clkdivn; + struct clk *clock_h; + struct clk *clock_p; + struct clk *clock_upll; + + printk("S3C2440: Clock Support, DVS %s\n", + (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off"); + + clock_p = clk_get(NULL, "pclk"); + clock_h = clk_get(NULL, "hclk"); + clock_upll = clk_get(NULL, "upll"); + + if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) { + printk(KERN_ERR "S3C2440: Failed to get parent clocks\n"); + return -EINVAL; + } + + /* check rate of UPLL, and if it is near 96MHz, then change + * to using half the UPLL rate for the system */ + + if (clk_get_rate(clock_upll) > (94 * MHZ)) { + clk_usb_bus.rate = clk_get_rate(clock_upll) / 2; + + mutex_lock(&clocks_mutex); + + clkdivn = __raw_readl(S3C2410_CLKDIVN); + clkdivn |= S3C2440_CLKDIVN_UCLK; + __raw_writel(clkdivn, S3C2410_CLKDIVN); + + mutex_unlock(&clocks_mutex); + } + + s3c2440_clk_cam.parent = clock_h; + s3c2440_clk_ac97.parent = clock_p; + s3c2440_clk_cam_upll.parent = clock_upll; + + s3c24xx_register_clock(&s3c2440_clk_ac97); + s3c24xx_register_clock(&s3c2440_clk_cam); + s3c24xx_register_clock(&s3c2440_clk_cam_upll); + + clk_disable(&s3c2440_clk_ac97); + clk_disable(&s3c2440_clk_cam); + + return 0; +} + +static struct sysdev_driver s3c2440_clk_driver = { + .add = s3c2440_clk_add, +}; + +static __init int s3c24xx_clk_driver(void) +{ + return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver); +} + +arch_initcall(s3c24xx_clk_driver); diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c new file mode 100644 index 000000000000..8e51137620f2 --- /dev/null +++ b/arch/arm/mach-s3c2440/dma.c @@ -0,0 +1,165 @@ +/* linux/arch/arm/mach-s3c2440/dma.c + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * S3C2440 DMA selection + * + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = { + [DMACH_XD0] = { + .name = "xdreq0", + .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID, + }, + [DMACH_XD1] = { + .name = "xdreq1", + .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID, + }, + [DMACH_SDI] = { + .name = "sdi", + .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID, + .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID, + .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, + .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, + .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, + }, + [DMACH_SPI0] = { + .name = "spi0", + .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT, + .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT, + }, + [DMACH_SPI1] = { + .name = "spi1", + .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT, + .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT, + }, + [DMACH_UART0] = { + .name = "uart0", + .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH, + }, + [DMACH_UART1] = { + .name = "uart1", + .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH, + }, + [DMACH_UART2] = { + .name = "uart2", + .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH, + .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH, + }, + [DMACH_TIMER] = { + .name = "timer", + .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID, + .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID, + .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID, + }, + [DMACH_I2S_IN] = { + .name = "i2s-sdi", + .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, + .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, + .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO, + }, + [DMACH_I2S_OUT] = { + .name = "i2s-sdo", + .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID, + .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, + .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO, + }, + [DMACH_PCM_IN] = { + .name = "pcm-in", + .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID, + .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID, + .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA, + }, + [DMACH_PCM_OUT] = { + .name = "pcm-out", + .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID, + .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID, + .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA, + }, + [DMACH_MIC_IN] = { + .name = "mic-in", + .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID, + .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID, + .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA, + }, + [DMACH_USB_EP1] = { + .name = "usb-ep1", + .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID, + }, + [DMACH_USB_EP2] = { + .name = "usb-ep2", + .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID, + }, + [DMACH_USB_EP3] = { + .name = "usb-ep3", + .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID, + }, + [DMACH_USB_EP4] = { + .name = "usb-ep4", + .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID, + }, +}; + +static void s3c2440_dma_select(struct s3c2410_dma_chan *chan, + struct s3c24xx_dma_map *map) +{ + chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID; +} + +static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = { + .select = s3c2440_dma_select, + .dcon_mask = 7 << 24, + .map = s3c2440_dma_mappings, + .map_size = ARRAY_SIZE(s3c2440_dma_mappings), +}; + +static int s3c2440_dma_add(struct sys_device *sysdev) +{ + return s3c24xx_dma_init_map(&s3c2440_dma_sel); +} + +static struct sysdev_driver s3c2440_dma_driver = { + .add = s3c2440_dma_add, +}; + +static int __init s3c2440_dma_init(void) +{ + return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_dma_driver); +} + +arch_initcall(s3c2440_dma_init); + diff --git a/arch/arm/mach-s3c2440/dsc.c b/arch/arm/mach-s3c2440/dsc.c new file mode 100644 index 000000000000..2995ff5681bb --- /dev/null +++ b/arch/arm/mach-s3c2440/dsc.c @@ -0,0 +1,54 @@ +/* linux/arch/arm/mach-s3c2440/dsc.c + * + * Copyright (c) 2004-2005 Simtec Electronics + * Ben Dooks + * + * Samsung S3C2440 Drive Strength Control support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include + +int s3c2440_set_dsc(unsigned int pin, unsigned int value) +{ + void __iomem *base; + unsigned long val; + unsigned long flags; + unsigned long mask; + + base = (pin & S3C2440_SELECT_DSC1) ? S3C2440_DSC1 : S3C2440_DSC0; + mask = 3 << S3C2440_DSC_GETSHIFT(pin); + + local_irq_save(flags); + + val = __raw_readl(base); + val &= ~mask; + val |= value & mask; + __raw_writel(val, base); + + local_irq_restore(flags); + return 0; +} + +EXPORT_SYMBOL(s3c2440_set_dsc); diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c new file mode 100644 index 000000000000..1069d13d8c57 --- /dev/null +++ b/arch/arm/mach-s3c2440/irq.c @@ -0,0 +1,130 @@ +/* linux/arch/arm/mach-s3c2440/irq.c + * + * Copyright (c) 2003,2004 Simtec Electronics + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * +*/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +/* WDT/AC97 */ + +static void s3c_irq_demux_wdtac97(unsigned int irq, + struct irq_desc *desc) +{ + unsigned int subsrc, submsk; + struct irq_desc *mydesc; + + /* read the current pending interrupts, and the mask + * for what it is available */ + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + subsrc &= ~submsk; + subsrc >>= 13; + subsrc &= 3; + + if (subsrc != 0) { + if (subsrc & 1) { + mydesc = irq_desc + IRQ_S3C2440_WDT; + desc_handle_irq(IRQ_S3C2440_WDT, mydesc); + } + if (subsrc & 2) { + mydesc = irq_desc + IRQ_S3C2440_AC97; + desc_handle_irq(IRQ_S3C2440_AC97, mydesc); + } + } +} + + +#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0)) + +static void +s3c_irq_wdtac97_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13); +} + +static void +s3c_irq_wdtac97_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_WDT); +} + +static void +s3c_irq_wdtac97_ack(unsigned int irqno) +{ + s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13); +} + +static struct irq_chip s3c_irq_wdtac97 = { + .mask = s3c_irq_wdtac97_mask, + .unmask = s3c_irq_wdtac97_unmask, + .ack = s3c_irq_wdtac97_ack, +}; + +static int s3c2440_irq_add(struct sys_device *sysdev) +{ + unsigned int irqno; + + printk("S3C2440: IRQ Support\n"); + + /* add new chained handler for wdt, ac7 */ + + set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); + set_irq_handler(IRQ_WDT, handle_level_irq); + set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); + + for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { + set_irq_chip(irqno, &s3c_irq_wdtac97); + set_irq_handler(irqno, handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } + + return 0; +} + +static struct sysdev_driver s3c2440_irq_driver = { + .add = s3c2440_irq_add, +}; + +static int s3c2440_irq_init(void) +{ + return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver); +} + +arch_initcall(s3c2440_irq_init); + diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c new file mode 100644 index 000000000000..3f0288eb1ed5 --- /dev/null +++ b/arch/arm/mach-s3c2440/mach-anubis.c @@ -0,0 +1,325 @@ +/* linux/arch/arm/mach-s3c2440/mach-anubis.c + * + * Copyright (c) 2003-2005 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#define COPYRIGHT ", (c) 2005 Simtec Electronics" + +static struct map_desc anubis_iodesc[] __initdata = { + /* ISA IO areas */ + + { + .virtual = (u32)S3C24XX_VA_ISA_BYTE, + .pfn = __phys_to_pfn(0x0), + .length = SZ_4M, + .type = MT_DEVICE, + }, { + .virtual = (u32)S3C24XX_VA_ISA_WORD, + .pfn = __phys_to_pfn(0x0), + .length = SZ_4M, + .type = MT_DEVICE, + }, + + /* we could possibly compress the next set down into a set of smaller tables + * pagetables, but that would mean using an L2 section, and it still means + * we cannot actually feed the same register to an LDR due to 16K spacing + */ + + /* CPLD control registers */ + + { + .virtual = (u32)ANUBIS_VA_CTRL1, + .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (u32)ANUBIS_VA_CTRL2, + .pfn = __phys_to_pfn(ANUBIS_PA_CTRL2), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE + +static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = { + [0] = { + .name = "uclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, + [1] = { + .name = "pclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + } +}; + + +static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + .clocks = anubis_serial_clocks, + .clocks_size = ARRAY_SIZE(anubis_serial_clocks), + }, + [1] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + .clocks = anubis_serial_clocks, + .clocks_size = ARRAY_SIZE(anubis_serial_clocks), + }, +}; + +/* NAND Flash on Anubis board */ + +static int external_map[] = { 2 }; +static int chip0_map[] = { 0 }; +static int chip1_map[] = { 1 }; + +static struct mtd_partition anubis_default_nand_part[] = { + [0] = { + .name = "Boot Agent", + .size = SZ_16K, + .offset = 0, + }, + [1] = { + .name = "/boot", + .size = SZ_4M - SZ_16K, + .offset = SZ_16K, + }, + [2] = { + .name = "user1", + .offset = SZ_4M, + .size = SZ_32M - SZ_4M, + }, + [3] = { + .name = "user2", + .offset = SZ_32M, + .size = MTDPART_SIZ_FULL, + } +}; + +/* the Anubis has 3 selectable slots for nand-flash, the two + * on-board chip areas, as well as the external slot. + * + * Note, there is no current hot-plug support for the External + * socket. +*/ + +static struct s3c2410_nand_set anubis_nand_sets[] = { + [1] = { + .name = "External", + .nr_chips = 1, + .nr_map = external_map, + .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), + .partitions = anubis_default_nand_part, + }, + [0] = { + .name = "chip0", + .nr_chips = 1, + .nr_map = chip0_map, + .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), + .partitions = anubis_default_nand_part, + }, + [2] = { + .name = "chip1", + .nr_chips = 1, + .nr_map = chip1_map, + .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), + .partitions = anubis_default_nand_part, + }, +}; + +static void anubis_nand_select(struct s3c2410_nand_set *set, int slot) +{ + unsigned int tmp; + + slot = set->nr_map[slot] & 3; + + pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n", + slot, set, set->nr_map); + + tmp = __raw_readb(ANUBIS_VA_CTRL1); + tmp &= ~ANUBIS_CTRL1_NANDSEL; + tmp |= slot; + + pr_debug("anubis_nand: ctrl1 now %02x\n", tmp); + + __raw_writeb(tmp, ANUBIS_VA_CTRL1); +} + +static struct s3c2410_platform_nand anubis_nand_info = { + .tacls = 25, + .twrph0 = 55, + .twrph1 = 40, + .nr_sets = ARRAY_SIZE(anubis_nand_sets), + .sets = anubis_nand_sets, + .select_chip = anubis_nand_select, +}; + +/* IDE channels */ + +static struct resource anubis_ide0_resource[] = { + { + .start = S3C2410_CS3, + .end = S3C2410_CS3 + (8*32) - 1, + .flags = IORESOURCE_MEM, + }, { + .start = S3C2410_CS3 + (1<<26), + .end = S3C2410_CS3 + (1<<26) + (8*32) - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_IDE0, + .end = IRQ_IDE0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device anubis_device_ide0 = { + .name = "simtec-ide", + .id = 0, + .num_resources = ARRAY_SIZE(anubis_ide0_resource), + .resource = anubis_ide0_resource, +}; + +static struct resource anubis_ide1_resource[] = { + { + .start = S3C2410_CS4, + .end = S3C2410_CS4 + (8*32) - 1, + .flags = IORESOURCE_MEM, + }, { + .start = S3C2410_CS4 + (1<<26), + .end = S3C2410_CS4 + (1<<26) + (8*32) - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_IDE0, + .end = IRQ_IDE0, + .flags = IORESOURCE_IRQ, + }, +}; + + +static struct platform_device anubis_device_ide1 = { + .name = "simtec-ide", + .id = 1, + .num_resources = ARRAY_SIZE(anubis_ide1_resource), + .resource = anubis_ide1_resource, +}; + +/* Standard Anubis devices */ + +static struct platform_device *anubis_devices[] __initdata = { + &s3c_device_usb, + &s3c_device_wdt, + &s3c_device_adc, + &s3c_device_i2c, + &s3c_device_rtc, + &s3c_device_nand, + &anubis_device_ide0, + &anubis_device_ide1, +}; + +static struct clk *anubis_clocks[] = { + &s3c24xx_dclk0, + &s3c24xx_dclk1, + &s3c24xx_clkout0, + &s3c24xx_clkout1, + &s3c24xx_uclk, +}; + +static struct s3c24xx_board anubis_board __initdata = { + .devices = anubis_devices, + .devices_count = ARRAY_SIZE(anubis_devices), + .clocks = anubis_clocks, + .clocks_count = ARRAY_SIZE(anubis_clocks), +}; + +static void __init anubis_map_io(void) +{ + /* initialise the clocks */ + + s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.rate = 12*1000*1000; + + s3c24xx_dclk1.parent = NULL; + s3c24xx_dclk1.rate = 24*1000*1000; + + s3c24xx_clkout0.parent = &s3c24xx_dclk0; + s3c24xx_clkout1.parent = &s3c24xx_dclk1; + + s3c24xx_uclk.parent = &s3c24xx_clkout1; + + s3c_device_nand.dev.platform_data = &anubis_nand_info; + + s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); + s3c24xx_init_clocks(0); + s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); + s3c24xx_set_board(&anubis_board); + + /* ensure that the GPIO is setup */ + s3c2410_gpio_setpin(S3C2410_GPA0, 1); +} + +MACHINE_START(ANUBIS, "Simtec-Anubis") + /* Maintainer: Ben Dooks */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = anubis_map_io, + .init_irq = s3c24xx_init_irq, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c new file mode 100644 index 000000000000..6d551d88330b --- /dev/null +++ b/arch/arm/mach-s3c2440/mach-nexcoder.c @@ -0,0 +1,158 @@ +/* linux/arch/arm/mach-s3c2440/mach-nexcoder.c + * + * Copyright (c) 2004 Nex Vision + * Guillaume GOURAT + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Modifications: + * 15-10-2004 GG Created initial version + * 12-03-2005 BJD Updated for release + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +//#include +#include +#include + +#include +#include +#include +#include +#include + +static struct map_desc nexcoder_iodesc[] __initdata = { + /* nothing here yet */ +}; + +#define UCON S3C2410_UCON_DEFAULT +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE + +static struct s3c2410_uartcfg nexcoder_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + } +}; + +/* NOR Flash on NexVision NexCoder 2440 board */ + +static struct resource nexcoder_nor_resource[] = { + [0] = { + .start = S3C2410_CS0, + .end = S3C2410_CS0 + (8*1024*1024) - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct map_info nexcoder_nor_map = { + .bankwidth = 2, +}; + +static struct platform_device nexcoder_device_nor = { + .name = "mtd-flash", + .id = -1, + .num_resources = ARRAY_SIZE(nexcoder_nor_resource), + .resource = nexcoder_nor_resource, + .dev = + { + .platform_data = &nexcoder_nor_map, + } +}; + +/* Standard Nexcoder devices */ + +static struct platform_device *nexcoder_devices[] __initdata = { + &s3c_device_usb, + &s3c_device_lcd, + &s3c_device_wdt, + &s3c_device_i2c, + &s3c_device_iis, + &s3c_device_rtc, + &s3c_device_camif, + &s3c_device_spi0, + &s3c_device_spi1, + &nexcoder_device_nor, +}; + +static struct s3c24xx_board nexcoder_board __initdata = { + .devices = nexcoder_devices, + .devices_count = ARRAY_SIZE(nexcoder_devices), +}; + + +static void __init nexcoder_sensorboard_init(void) +{ + // Initialize SCCB bus + s3c2410_gpio_setpin(S3C2410_GPE14, 1); // IICSCL + s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_OUTP); + s3c2410_gpio_setpin(S3C2410_GPE15, 1); // IICSDA + s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_OUTP); + + // Power up the sensor board + s3c2410_gpio_setpin(S3C2410_GPF1, 1); + s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_OUTP); // CAM_GPIO7 => nLDO_PWRDN + s3c2410_gpio_setpin(S3C2410_GPF2, 0); + s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); // CAM_GPIO6 => CAM_PWRDN +} + +static void __init nexcoder_map_io(void) +{ + s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc)); + s3c24xx_init_clocks(0); + s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs)); + s3c24xx_set_board(&nexcoder_board); + nexcoder_sensorboard_init(); +} + + +MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440") + /* Maintainer: Guillaume GOURAT */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = nexcoder_map_io, + .init_irq = s3c24xx_init_irq, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c new file mode 100644 index 000000000000..2ed8e51f20c8 --- /dev/null +++ b/arch/arm/mach-s3c2440/mach-osiris.c @@ -0,0 +1,303 @@ +/* linux/arch/arm/mach-s3c2440/mach-osiris.c + * + * Copyright (c) 2005 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +/* onboard perihpheral map */ + +static struct map_desc osiris_iodesc[] __initdata = { + /* ISA IO areas (may be over-written later) */ + + { + .virtual = (u32)S3C24XX_VA_ISA_BYTE, + .pfn = __phys_to_pfn(S3C2410_CS5), + .length = SZ_16M, + .type = MT_DEVICE, + }, { + .virtual = (u32)S3C24XX_VA_ISA_WORD, + .pfn = __phys_to_pfn(S3C2410_CS5), + .length = SZ_16M, + .type = MT_DEVICE, + }, + + /* CPLD control registers */ + + { + .virtual = (u32)OSIRIS_VA_CTRL1, + .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (u32)OSIRIS_VA_CTRL2, + .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2), + .length = SZ_16K, + .type = MT_DEVICE, + }, +}; + +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE + +static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = { + [0] = { + .name = "uclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, + [1] = { + .name = "pclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + } +}; + +static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + .clocks = osiris_serial_clocks, + .clocks_size = ARRAY_SIZE(osiris_serial_clocks), + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + .clocks = osiris_serial_clocks, + .clocks_size = ARRAY_SIZE(osiris_serial_clocks), + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + .clocks = osiris_serial_clocks, + .clocks_size = ARRAY_SIZE(osiris_serial_clocks), + } +}; + +/* NAND Flash on Osiris board */ + +static int external_map[] = { 2 }; +static int chip0_map[] = { 0 }; +static int chip1_map[] = { 1 }; + +static struct mtd_partition osiris_default_nand_part[] = { + [0] = { + .name = "Boot Agent", + .size = SZ_16K, + .offset = 0, + }, + [1] = { + .name = "/boot", + .size = SZ_4M - SZ_16K, + .offset = SZ_16K, + }, + [2] = { + .name = "user1", + .offset = SZ_4M, + .size = SZ_32M - SZ_4M, + }, + [3] = { + .name = "user2", + .offset = SZ_32M, + .size = MTDPART_SIZ_FULL, + } +}; + +/* the Osiris has 3 selectable slots for nand-flash, the two + * on-board chip areas, as well as the external slot. + * + * Note, there is no current hot-plug support for the External + * socket. +*/ + +static struct s3c2410_nand_set osiris_nand_sets[] = { + [1] = { + .name = "External", + .nr_chips = 1, + .nr_map = external_map, + .nr_partitions = ARRAY_SIZE(osiris_default_nand_part), + .partitions = osiris_default_nand_part, + }, + [0] = { + .name = "chip0", + .nr_chips = 1, + .nr_map = chip0_map, + .nr_partitions = ARRAY_SIZE(osiris_default_nand_part), + .partitions = osiris_default_nand_part, + }, + [2] = { + .name = "chip1", + .nr_chips = 1, + .nr_map = chip1_map, + .nr_partitions = ARRAY_SIZE(osiris_default_nand_part), + .partitions = osiris_default_nand_part, + }, +}; + +static void osiris_nand_select(struct s3c2410_nand_set *set, int slot) +{ + unsigned int tmp; + + slot = set->nr_map[slot] & 3; + + pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n", + slot, set, set->nr_map); + + tmp = __raw_readb(OSIRIS_VA_CTRL1); + tmp &= ~OSIRIS_CTRL1_NANDSEL; + tmp |= slot; + + pr_debug("osiris_nand: ctrl1 now %02x\n", tmp); + + __raw_writeb(tmp, OSIRIS_VA_CTRL1); +} + +static struct s3c2410_platform_nand osiris_nand_info = { + .tacls = 25, + .twrph0 = 60, + .twrph1 = 60, + .nr_sets = ARRAY_SIZE(osiris_nand_sets), + .sets = osiris_nand_sets, + .select_chip = osiris_nand_select, +}; + +/* PCMCIA control and configuration */ + +static struct resource osiris_pcmcia_resource[] = { + [0] = { + .start = 0x0f000000, + .end = 0x0f100000, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0x0c000000, + .end = 0x0c100000, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device osiris_pcmcia = { + .name = "osiris-pcmcia", + .id = -1, + .num_resources = ARRAY_SIZE(osiris_pcmcia_resource), + .resource = osiris_pcmcia_resource, +}; + +/* Standard Osiris devices */ + +static struct platform_device *osiris_devices[] __initdata = { + &s3c_device_i2c, + &s3c_device_nand, + &osiris_pcmcia, +}; + +static struct clk *osiris_clocks[] = { + &s3c24xx_dclk0, + &s3c24xx_dclk1, + &s3c24xx_clkout0, + &s3c24xx_clkout1, + &s3c24xx_uclk, +}; + +static struct s3c24xx_board osiris_board __initdata = { + .devices = osiris_devices, + .devices_count = ARRAY_SIZE(osiris_devices), + .clocks = osiris_clocks, + .clocks_count = ARRAY_SIZE(osiris_clocks), +}; + +static void __init osiris_map_io(void) +{ + unsigned long flags; + + /* initialise the clocks */ + + s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.rate = 12*1000*1000; + + s3c24xx_dclk1.parent = NULL; + s3c24xx_dclk1.rate = 24*1000*1000; + + s3c24xx_clkout0.parent = &s3c24xx_dclk0; + s3c24xx_clkout1.parent = &s3c24xx_dclk1; + + s3c24xx_uclk.parent = &s3c24xx_clkout1; + + s3c_device_nand.dev.platform_data = &osiris_nand_info; + + s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc)); + s3c24xx_init_clocks(0); + s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); + s3c24xx_set_board(&osiris_board); + + /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */ + + local_irq_save(flags); + __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON); + local_irq_restore(flags); + + /* write-protect line to the NAND */ + s3c2410_gpio_setpin(S3C2410_GPA0, 1); +} + +MACHINE_START(OSIRIS, "Simtec-OSIRIS") + /* Maintainer: Ben Dooks */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = osiris_map_io, + .init_irq = s3c24xx_init_irq, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c new file mode 100644 index 000000000000..1d4e19bd9206 --- /dev/null +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -0,0 +1,244 @@ +/* linux/arch/arm/mach-s3c2440/mach-rx3715.c + * + * Copyright (c) 2003,2004 Simtec Electronics + * Ben Dooks + * + * http://www.handhelds.org/projects/rx3715.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +static struct map_desc rx3715_iodesc[] __initdata = { + /* dump ISA space somewhere unused */ + + { + .virtual = (u32)S3C24XX_VA_ISA_WORD, + .pfn = __phys_to_pfn(S3C2410_CS3), + .length = SZ_1M, + .type = MT_DEVICE, + }, { + .virtual = (u32)S3C24XX_VA_ISA_BYTE, + .pfn = __phys_to_pfn(S3C2410_CS3), + .length = SZ_1M, + .type = MT_DEVICE, + }, +}; + + +static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = { + [0] = { + .name = "fclk", + .divisor = 0, + .min_baud = 0, + .max_baud = 0, + } +}; + +static struct s3c2410_uartcfg rx3715_uartcfgs[] = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + .clocks = rx3715_serial_clocks, + .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x00, + .clocks = rx3715_serial_clocks, + .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), + }, + /* IR port */ + [2] = { + .hwport = 2, + .uart_flags = UPF_CONS_FLOW, + .ucon = 0x3c5, + .ulcon = 0x43, + .ufcon = 0x51, + .clocks = rx3715_serial_clocks, + .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), + } +}; + +/* framebuffer lcd controller information */ + +static struct s3c2410fb_mach_info rx3715_lcdcfg __initdata = { + .regs = { + .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | \ + S3C2410_LCDCON1_TFT | \ + S3C2410_LCDCON1_CLKVAL(0x0C), + + .lcdcon2 = S3C2410_LCDCON2_VBPD(5) | \ + S3C2410_LCDCON2_LINEVAL(319) | \ + S3C2410_LCDCON2_VFPD(6) | \ + S3C2410_LCDCON2_VSPW(2), + + .lcdcon3 = S3C2410_LCDCON3_HBPD(35) | \ + S3C2410_LCDCON3_HOZVAL(239) | \ + S3C2410_LCDCON3_HFPD(35), + + .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | \ + S3C2410_LCDCON4_HSPW(7), + + .lcdcon5 = S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_HWSWP, + }, + + .lpcsel = 0xf82, + + .gpccon = 0xaa955699, + .gpccon_mask = 0xffc003cc, + .gpcup = 0x0000ffff, + .gpcup_mask = 0xffffffff, + + .gpdcon = 0xaa95aaa1, + .gpdcon_mask = 0xffc0fff0, + .gpdup = 0x0000faff, + .gpdup_mask = 0xffffffff, + + .fixed_syncs = 1, + .width = 240, + .height = 320, + + .xres = { + .min = 240, + .max = 240, + .defval = 240, + }, + + .yres = { + .max = 320, + .min = 320, + .defval = 320, + }, + + .bpp = { + .min = 16, + .max = 16, + .defval = 16, + }, +}; + +static struct mtd_partition rx3715_nand_part[] = { + [0] = { + .name = "Whole Flash", + .offset = 0, + .size = MTDPART_SIZ_FULL, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct s3c2410_nand_set rx3715_nand_sets[] = { + [0] = { + .name = "Internal", + .nr_chips = 1, + .nr_partitions = ARRAY_SIZE(rx3715_nand_part), + .partitions = rx3715_nand_part, + }, +}; + +static struct s3c2410_platform_nand rx3715_nand_info = { + .tacls = 25, + .twrph0 = 50, + .twrph1 = 15, + .nr_sets = ARRAY_SIZE(rx3715_nand_sets), + .sets = rx3715_nand_sets, +}; + +static struct platform_device *rx3715_devices[] __initdata = { + &s3c_device_usb, + &s3c_device_lcd, + &s3c_device_wdt, + &s3c_device_i2c, + &s3c_device_iis, + &s3c_device_nand, +}; + +static struct s3c24xx_board rx3715_board __initdata = { + .devices = rx3715_devices, + .devices_count = ARRAY_SIZE(rx3715_devices) +}; + +static void __init rx3715_map_io(void) +{ + s3c_device_nand.dev.platform_data = &rx3715_nand_info; + + s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); + s3c24xx_init_clocks(16934000); + s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); + s3c24xx_set_board(&rx3715_board); +} + +static void __init rx3715_init_irq(void) +{ + s3c24xx_init_irq(); +} + +static void __init rx3715_init_machine(void) +{ + memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); + s3c2410_pm_init(); + + s3c24xx_fb_set_platdata(&rx3715_lcdcfg); +} + + +MACHINE_START(RX3715, "IPAQ-RX3715") + /* Maintainer: Ben Dooks */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = rx3715_map_io, + .init_irq = rx3715_init_irq, + .init_machine = rx3715_init_machine, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c new file mode 100644 index 000000000000..270e42b9b5c1 --- /dev/null +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c @@ -0,0 +1,208 @@ +/* linux/arch/arm/mach-s3c2440/mach-smdk2440.c + * + * Copyright (c) 2004,2005 Simtec Electronics + * Ben Dooks + * + * http://www.fluff.org/ben/smdk2440/ + * + * Thanks to Dimity Andric and TomTom for the loan of an SMDK2440. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +//#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include + +static struct map_desc smdk2440_iodesc[] __initdata = { + /* ISA IO Space map (memory space selected by A24) */ + + { + .virtual = (u32)S3C24XX_VA_ISA_WORD, + .pfn = __phys_to_pfn(S3C2410_CS2), + .length = 0x10000, + .type = MT_DEVICE, + }, { + .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, + .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), + .length = SZ_4M, + .type = MT_DEVICE, + }, { + .virtual = (u32)S3C24XX_VA_ISA_BYTE, + .pfn = __phys_to_pfn(S3C2410_CS2), + .length = 0x10000, + .type = MT_DEVICE, + }, { + .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000, + .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), + .length = SZ_4M, + .type = MT_DEVICE, + } +}; + +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE + +static struct s3c2410_uartcfg smdk2440_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + }, + /* IR port */ + [2] = { + .hwport = 2, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x43, + .ufcon = 0x51, + } +}; + +/* LCD driver info */ + +static struct s3c2410fb_mach_info smdk2440_lcd_cfg __initdata = { + .regs = { + + .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | + S3C2410_LCDCON1_TFT | + S3C2410_LCDCON1_CLKVAL(0x04), + + .lcdcon2 = S3C2410_LCDCON2_VBPD(7) | + S3C2410_LCDCON2_LINEVAL(319) | + S3C2410_LCDCON2_VFPD(6) | + S3C2410_LCDCON2_VSPW(3), + + .lcdcon3 = S3C2410_LCDCON3_HBPD(19) | + S3C2410_LCDCON3_HOZVAL(239) | + S3C2410_LCDCON3_HFPD(7), + + .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | + S3C2410_LCDCON4_HSPW(3), + + .lcdcon5 = S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_INVVFRAME | + S3C2410_LCDCON5_PWREN | + S3C2410_LCDCON5_HWSWP, + }, + +#if 0 + /* currently setup by downloader */ + .gpccon = 0xaa940659, + .gpccon_mask = 0xffffffff, + .gpcup = 0x0000ffff, + .gpcup_mask = 0xffffffff, + .gpdcon = 0xaa84aaa0, + .gpdcon_mask = 0xffffffff, + .gpdup = 0x0000faff, + .gpdup_mask = 0xffffffff, +#endif + + .lpcsel = ((0xCE6) & ~7) | 1<<4, + + .width = 240, + .height = 320, + + .xres = { + .min = 240, + .max = 240, + .defval = 240, + }, + + .yres = { + .min = 320, + .max = 320, + .defval = 320, + }, + + .bpp = { + .min = 16, + .max = 16, + .defval = 16, + }, +}; + +static struct platform_device *smdk2440_devices[] __initdata = { + &s3c_device_usb, + &s3c_device_lcd, + &s3c_device_wdt, + &s3c_device_i2c, + &s3c_device_iis, +}; + +static struct s3c24xx_board smdk2440_board __initdata = { + .devices = smdk2440_devices, + .devices_count = ARRAY_SIZE(smdk2440_devices) +}; + +static void __init smdk2440_map_io(void) +{ + s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc)); + s3c24xx_init_clocks(16934400); + s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs)); + s3c24xx_set_board(&smdk2440_board); +} + +static void __init smdk2440_machine_init(void) +{ + s3c24xx_fb_set_platdata(&smdk2440_lcd_cfg); + + smdk_machine_init(); +} + +MACHINE_START(S3C2440, "SMDK2440") + /* Maintainer: Ben Dooks */ + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + + .init_irq = s3c24xx_init_irq, + .map_io = smdk2440_map_io, + .init_machine = smdk2440_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c new file mode 100644 index 000000000000..90e1da61fbc3 --- /dev/null +++ b/arch/arm/mach-s3c2440/s3c2440.c @@ -0,0 +1,52 @@ +/* linux/arch/arm/mach-s3c2440/s3c2440.c + * + * Copyright (c) 2004-2006 Simtec Electronics + * Ben Dooks + * + * Samsung S3C2440 Mobile CPU support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +static struct sys_device s3c2440_sysdev = { + .cls = &s3c2440_sysclass, +}; + +int __init s3c2440_init(void) +{ + printk("S3C2440: Initialising architecture\n"); + + /* change irq for watchdog */ + + s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT; + s3c_device_wdt.resource[1].end = IRQ_S3C2440_WDT; + + /* register our system device for everything else */ + + return sysdev_register(&s3c2440_sysdev); +} diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig new file mode 100644 index 000000000000..bf8d87abfab3 --- /dev/null +++ b/arch/arm/mach-s3c2442/Kconfig @@ -0,0 +1,27 @@ +# arch/arm/mach-s3c2442/Kconfig +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + +config CPU_S3C2442 + bool + depends on ARCH_S3C2420 + select S3C2410_CLOCK + select S3C2410_GPIO + select S3C2410_PM if PM + select CPU_S3C244X + help + Support for S3C2442 Samsung Mobile CPU based systems. + + +menu "S3C2442 Machines" + +config SMDK2440_CPU2442 + bool "SMDM2440 with S3C2442 CPU module" + depends on ARCH_S3C2440 + select CPU_S3C2442 + + +endmenu + diff --git a/arch/arm/mach-s3c2442/Makefile b/arch/arm/mach-s3c2442/Makefile new file mode 100644 index 000000000000..2a909c6c5798 --- /dev/null +++ b/arch/arm/mach-s3c2442/Makefile @@ -0,0 +1,16 @@ +# arch/arm/mach-s3c2442/Makefile +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +obj-$(CONFIG_CPU_S3C2442) += s3c2442.o +obj-$(CONFIG_CPU_S3C2442) += clock.o + +# Machine support + diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c new file mode 100644 index 000000000000..5b9e830ac4d3 --- /dev/null +++ b/arch/arm/mach-s3c2442/clock.c @@ -0,0 +1,171 @@ +/* linux/arch/arm/mach-s3c2442/clock.c + * + * Copyright (c) 2004-2005 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C2442 Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include + +/* S3C2442 extended clock support */ + +static unsigned long s3c2442_camif_upll_round(struct clk *clk, + unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + int div; + + if (rate > parent_rate) + return parent_rate; + + div = parent_rate / rate; + + if (div == 3) + return parent_rate / 3; + + /* note, we remove the +/- 1 calculations for the divisor */ + + div /= 2; + + if (div < 1) + div = 1; + else if (div > 16) + div = 16; + + return parent_rate / (div * 2); +} + +static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); + + rate = s3c2442_camif_upll_round(clk, rate); + + camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3; + + if (rate == parent_rate) { + camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL; + } else if ((parent_rate / rate) == 3) { + camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; + camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3; + } else { + camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK; + camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; + camdivn |= (((parent_rate / rate) / 2) - 1); + } + + __raw_writel(camdivn, S3C2440_CAMDIVN); + + return 0; +} + +/* Extra S3C2442 clocks */ + +static struct clk s3c2442_clk_cam = { + .name = "camif", + .id = -1, + .enable = s3c2410_clkcon_enable, + .ctrlbit = S3C2440_CLKCON_CAMERA, +}; + +static struct clk s3c2442_clk_cam_upll = { + .name = "camif-upll", + .id = -1, + .set_rate = s3c2442_camif_upll_setrate, + .round_rate = s3c2442_camif_upll_round, +}; + +static int s3c2442_clk_add(struct sys_device *sysdev) +{ + unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); + unsigned long clkdivn; + struct clk *clock_h; + struct clk *clock_p; + struct clk *clock_upll; + + printk("S3C2442: Clock Support, DVS %s\n", + (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off"); + + clock_p = clk_get(NULL, "pclk"); + clock_h = clk_get(NULL, "hclk"); + clock_upll = clk_get(NULL, "upll"); + + if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) { + printk(KERN_ERR "S3C2442: Failed to get parent clocks\n"); + return -EINVAL; + } + + /* check rate of UPLL, and if it is near 96MHz, then change + * to using half the UPLL rate for the system */ + + if (clk_get_rate(clock_upll) > (94 * MHZ)) { + clk_usb_bus.rate = clk_get_rate(clock_upll) / 2; + + mutex_lock(&clocks_mutex); + + clkdivn = __raw_readl(S3C2410_CLKDIVN); + clkdivn |= S3C2440_CLKDIVN_UCLK; + __raw_writel(clkdivn, S3C2410_CLKDIVN); + + mutex_unlock(&clocks_mutex); + } + + s3c2442_clk_cam.parent = clock_h; + s3c2442_clk_cam_upll.parent = clock_upll; + + s3c24xx_register_clock(&s3c2442_clk_cam); + s3c24xx_register_clock(&s3c2442_clk_cam_upll); + + clk_disable(&s3c2442_clk_cam); + + return 0; +} + +static struct sysdev_driver s3c2442_clk_driver = { + .add = s3c2442_clk_add, +}; + +static __init int s3c2442_clk_init(void) +{ + return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver); +} + +arch_initcall(s3c2442_clk_init); diff --git a/arch/arm/mach-s3c2442/s3c2442.c b/arch/arm/mach-s3c2442/s3c2442.c new file mode 100644 index 000000000000..fbf8264249da --- /dev/null +++ b/arch/arm/mach-s3c2442/s3c2442.c @@ -0,0 +1,34 @@ +/* linux/arch/arm/mach-s3c2442/s3c2442.c + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * Samsung S3C2442 Mobile CPU support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static struct sys_device s3c2442_sysdev = { + .cls = &s3c2442_sysclass, +}; + +int __init s3c2442_init(void) +{ + printk("S3C2442: Initialising architecture\n"); + + return sysdev_register(&s3c2442_sysdev); +} diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig new file mode 100644 index 000000000000..97813645b5ee --- /dev/null +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -0,0 +1,96 @@ +# arch/arm/plat-s3c24xx/Kconfig +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + +config PLAT_S3C24XX + bool + depends on ARCH_S3C2410 + default y + help + Base platform code for any Samsung S3C device + +config CPU_S3C244X + bool + depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442) + help + Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems. + +config PM_SIMTEC + bool + help + Common power management code for systems that are + compatible with the Simtec style of power management + +config S3C2410_BOOT_WATCHDOG + bool "S3C2410 Initialisation watchdog" + depends on ARCH_S3C2410 && S3C2410_WATCHDOG + help + Say y to enable the watchdog during the kernel decompression + stage. If the kernel fails to uncompress, then the watchdog + will trigger a reset and the system should restart. + +config S3C2410_BOOT_ERROR_RESET + bool "S3C2410 Reboot on decompression error" + depends on ARCH_S3C2410 + help + Say y here to use the watchdog to reset the system if the + kernel decompressor detects an error during decompression. + +config S3C2410_PM_DEBUG + bool "S3C2410 PM Suspend debug" + depends on ARCH_S3C2410 && PM + help + Say Y here if you want verbose debugging from the PM Suspend and + Resume code. See + for more information. + +config S3C2410_PM_CHECK + bool "S3C2410 PM Suspend Memory CRC" + depends on ARCH_S3C2410 && PM && CRC32 + help + Enable the PM code's memory area checksum over sleep. This option + will generate CRCs of all blocks of memory, and store them before + going to sleep. The blocks are then checked on resume for any + errors. + +config S3C2410_PM_CHECK_CHUNKSIZE + int "S3C2410 PM Suspend CRC Chunksize (KiB)" + depends on ARCH_S3C2410 && PM && S3C2410_PM_CHECK + default 64 + help + Set the chunksize in Kilobytes of the CRC for checking memory + corruption over suspend and resume. A smaller value will mean that + the CRC data block will take more memory, but wil identify any + faults with better precision. + +config S3C2410_LOWLEVEL_UART_PORT + int "S3C2410 UART to use for low-level messages" + default 0 + help + Choice of which UART port to use for the low-level messages, + such as the `Uncompressing...` at start time. The value of + this configuration should be between zero and two. The port + must have been initialised by the boot-loader before use. + +config S3C2410_DMA + bool "S3C2410 DMA support" + depends on ARCH_S3C2410 + help + S3C2410 DMA support. This is needed for drivers like sound which + use the S3C2410's DMA system to move data to and from the + peripheral blocks. + +config S3C2410_DMA_DEBUG + bool "S3C2410 DMA support debug" + depends on ARCH_S3C2410 && S3C2410_DMA + help + Enable debugging output for the DMA code. This option sends info + to the kernel log, at priority KERN_DEBUG. + +config MACH_SMDK + bool + help + Common machine code for SMDK2410 and SMDK2440 + diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile new file mode 100644 index 000000000000..8e5ccaa1f03c --- /dev/null +++ b/arch/arm/plat-s3c24xx/Makefile @@ -0,0 +1,30 @@ +# arch/arm/plat-s3c24xx/Makefile +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + + +# Core files + +obj-y += cpu.o +obj-y += irq.o +obj-y += devs.o +obj-y += gpio.o +obj-y += time.o +obj-y += clock.o + +# Architecture dependant builds + +obj-$(CONFIG_CPU_S3C244X) += s3c244x.o +obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o +obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o +obj-$(CONFIG_PM) += pm.o +obj-$(CONFIG_PM) += sleep.o +obj-$(CONFIG_S3C2410_DMA) += dma.o +obj-$(CONFIG_MACH_SMDK) += common-smdk.o diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c new file mode 100644 index 000000000000..d3dc03a7383a --- /dev/null +++ b/arch/arm/plat-s3c24xx/clock.c @@ -0,0 +1,449 @@ +/* linux/arch/arm/plat-s3c24xx/clock.c + * + * Copyright (c) 2004-2005 Simtec Electronics + * Ben Dooks + * + * S3C24XX Core clock control support + * + * Based on, and code from linux/arch/arm/mach-versatile/clock.c + ** + ** Copyright (C) 2004 ARM Limited. + ** Written by Deep Blue Solutions Limited. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include + +/* clock information */ + +static LIST_HEAD(clocks); + +DEFINE_MUTEX(clocks_mutex); + +/* enable and disable calls for use with the clk struct */ + +static int clk_null_enable(struct clk *clk, int enable) +{ + return 0; +} + +/* Clock API calls */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + struct clk *p; + struct clk *clk = ERR_PTR(-ENOENT); + int idno; + + if (dev == NULL || dev->bus != &platform_bus_type) + idno = -1; + else + idno = to_platform_device(dev)->id; + + mutex_lock(&clocks_mutex); + + list_for_each_entry(p, &clocks, list) { + if (p->id == idno && + strcmp(id, p->name) == 0 && + try_module_get(p->owner)) { + clk = p; + break; + } + } + + /* check for the case where a device was supplied, but the + * clock that was being searched for is not device specific */ + + if (IS_ERR(clk)) { + list_for_each_entry(p, &clocks, list) { + if (p->id == -1 && strcmp(id, p->name) == 0 && + try_module_get(p->owner)) { + clk = p; + break; + } + } + } + + mutex_unlock(&clocks_mutex); + return clk; +} + +void clk_put(struct clk *clk) +{ + module_put(clk->owner); +} + +int clk_enable(struct clk *clk) +{ + if (IS_ERR(clk) || clk == NULL) + return -EINVAL; + + clk_enable(clk->parent); + + mutex_lock(&clocks_mutex); + + if ((clk->usage++) == 0) + (clk->enable)(clk, 1); + + mutex_unlock(&clocks_mutex); + return 0; +} + +void clk_disable(struct clk *clk) +{ + if (IS_ERR(clk) || clk == NULL) + return; + + mutex_lock(&clocks_mutex); + + if ((--clk->usage) == 0) + (clk->enable)(clk, 0); + + mutex_unlock(&clocks_mutex); + clk_disable(clk->parent); +} + + +unsigned long clk_get_rate(struct clk *clk) +{ + if (IS_ERR(clk)) + return 0; + + if (clk->rate != 0) + return clk->rate; + + if (clk->get_rate != NULL) + return (clk->get_rate)(clk); + + if (clk->parent != NULL) + return clk_get_rate(clk->parent); + + return clk->rate; +} + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (!IS_ERR(clk) && clk->round_rate) + return (clk->round_rate)(clk, rate); + + return rate; +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret; + + if (IS_ERR(clk)) + return -EINVAL; + + mutex_lock(&clocks_mutex); + ret = (clk->set_rate)(clk, rate); + mutex_unlock(&clocks_mutex); + + return ret; +} + +struct clk *clk_get_parent(struct clk *clk) +{ + return clk->parent; +} + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = 0; + + if (IS_ERR(clk)) + return -EINVAL; + + mutex_lock(&clocks_mutex); + + if (clk->set_parent) + ret = (clk->set_parent)(clk, parent); + + mutex_unlock(&clocks_mutex); + + return ret; +} + +EXPORT_SYMBOL(clk_get); +EXPORT_SYMBOL(clk_put); +EXPORT_SYMBOL(clk_enable); +EXPORT_SYMBOL(clk_disable); +EXPORT_SYMBOL(clk_get_rate); +EXPORT_SYMBOL(clk_round_rate); +EXPORT_SYMBOL(clk_set_rate); +EXPORT_SYMBOL(clk_get_parent); +EXPORT_SYMBOL(clk_set_parent); + +/* base clocks */ + +struct clk clk_xtal = { + .name = "xtal", + .id = -1, + .rate = 0, + .parent = NULL, + .ctrlbit = 0, +}; + +struct clk clk_mpll = { + .name = "mpll", + .id = -1, +}; + +struct clk clk_upll = { + .name = "upll", + .id = -1, + .parent = NULL, + .ctrlbit = 0, +}; + +struct clk clk_f = { + .name = "fclk", + .id = -1, + .rate = 0, + .parent = &clk_mpll, + .ctrlbit = 0, +}; + +struct clk clk_h = { + .name = "hclk", + .id = -1, + .rate = 0, + .parent = NULL, + .ctrlbit = 0, +}; + +struct clk clk_p = { + .name = "pclk", + .id = -1, + .rate = 0, + .parent = NULL, + .ctrlbit = 0, +}; + +struct clk clk_usb_bus = { + .name = "usb-bus", + .id = -1, + .rate = 0, + .parent = &clk_upll, +}; + +/* clocks that could be registered by external code */ + +static int s3c24xx_dclk_enable(struct clk *clk, int enable) +{ + unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON); + + if (enable) + dclkcon |= clk->ctrlbit; + else + dclkcon &= ~clk->ctrlbit; + + __raw_writel(dclkcon, S3C24XX_DCLKCON); + + return 0; +} + +static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) +{ + unsigned long dclkcon; + unsigned int uclk; + + if (parent == &clk_upll) + uclk = 1; + else if (parent == &clk_p) + uclk = 0; + else + return -EINVAL; + + clk->parent = parent; + + dclkcon = __raw_readl(S3C24XX_DCLKCON); + + if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) { + if (uclk) + dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK; + else + dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK; + } else { + if (uclk) + dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK; + else + dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK; + } + + __raw_writel(dclkcon, S3C24XX_DCLKCON); + + return 0; +} + + +static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) +{ + unsigned long mask; + unsigned long source; + + /* calculate the MISCCR setting for the clock */ + + if (parent == &clk_xtal) + source = S3C2410_MISCCR_CLK0_MPLL; + else if (parent == &clk_upll) + source = S3C2410_MISCCR_CLK0_UPLL; + else if (parent == &clk_f) + source = S3C2410_MISCCR_CLK0_FCLK; + else if (parent == &clk_h) + source = S3C2410_MISCCR_CLK0_HCLK; + else if (parent == &clk_p) + source = S3C2410_MISCCR_CLK0_PCLK; + else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0) + source = S3C2410_MISCCR_CLK0_DCLK0; + else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1) + source = S3C2410_MISCCR_CLK0_DCLK0; + else + return -EINVAL; + + clk->parent = parent; + + if (clk == &s3c24xx_dclk0) + mask = S3C2410_MISCCR_CLK0_MASK; + else { + source <<= 4; + mask = S3C2410_MISCCR_CLK1_MASK; + } + + s3c2410_modify_misccr(mask, source); + return 0; +} + +/* external clock definitions */ + +struct clk s3c24xx_dclk0 = { + .name = "dclk0", + .id = -1, + .ctrlbit = S3C2410_DCLKCON_DCLK0EN, + .enable = s3c24xx_dclk_enable, + .set_parent = s3c24xx_dclk_setparent, +}; + +struct clk s3c24xx_dclk1 = { + .name = "dclk1", + .id = -1, + .ctrlbit = S3C2410_DCLKCON_DCLK0EN, + .enable = s3c24xx_dclk_enable, + .set_parent = s3c24xx_dclk_setparent, +}; + +struct clk s3c24xx_clkout0 = { + .name = "clkout0", + .id = -1, + .set_parent = s3c24xx_clkout_setparent, +}; + +struct clk s3c24xx_clkout1 = { + .name = "clkout1", + .id = -1, + .set_parent = s3c24xx_clkout_setparent, +}; + +struct clk s3c24xx_uclk = { + .name = "uclk", + .id = -1, +}; + +/* initialise the clock system */ + +int s3c24xx_register_clock(struct clk *clk) +{ + clk->owner = THIS_MODULE; + + if (clk->enable == NULL) + clk->enable = clk_null_enable; + + /* add to the list of available clocks */ + + mutex_lock(&clocks_mutex); + list_add(&clk->list, &clocks); + mutex_unlock(&clocks_mutex); + + return 0; +} + +/* initalise all the clocks */ + +int __init s3c24xx_setup_clocks(unsigned long xtal, + unsigned long fclk, + unsigned long hclk, + unsigned long pclk) +{ + printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); + + /* initialise the main system clocks */ + + clk_xtal.rate = xtal; + clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal); + + clk_mpll.rate = fclk; + clk_h.rate = hclk; + clk_p.rate = pclk; + clk_f.rate = fclk; + + /* assume uart clocks are correctly setup */ + + /* register our clocks */ + + if (s3c24xx_register_clock(&clk_xtal) < 0) + printk(KERN_ERR "failed to register master xtal\n"); + + if (s3c24xx_register_clock(&clk_mpll) < 0) + printk(KERN_ERR "failed to register mpll clock\n"); + + if (s3c24xx_register_clock(&clk_upll) < 0) + printk(KERN_ERR "failed to register upll clock\n"); + + if (s3c24xx_register_clock(&clk_f) < 0) + printk(KERN_ERR "failed to register cpu fclk\n"); + + if (s3c24xx_register_clock(&clk_h) < 0) + printk(KERN_ERR "failed to register cpu hclk\n"); + + if (s3c24xx_register_clock(&clk_p) < 0) + printk(KERN_ERR "failed to register cpu pclk\n"); + + return 0; +} diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c new file mode 100644 index 000000000000..908efa7d745f --- /dev/null +++ b/arch/arm/plat-s3c24xx/common-smdk.c @@ -0,0 +1,200 @@ +/* linux/arch/arm/plat-s3c24xx/common-smdk.c + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * Common code for SMDK2410 and SMDK2440 boards + * + * http://www.fluff.org/ben/smdk2440/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include + +/* LED devices */ + +static struct s3c24xx_led_platdata smdk_pdata_led4 = { + .gpio = S3C2410_GPF4, + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .name = "led4", + .def_trigger = "timer", +}; + +static struct s3c24xx_led_platdata smdk_pdata_led5 = { + .gpio = S3C2410_GPF5, + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .name = "led5", + .def_trigger = "nand-disk", +}; + +static struct s3c24xx_led_platdata smdk_pdata_led6 = { + .gpio = S3C2410_GPF6, + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .name = "led6", +}; + +static struct s3c24xx_led_platdata smdk_pdata_led7 = { + .gpio = S3C2410_GPF7, + .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, + .name = "led7", +}; + +static struct platform_device smdk_led4 = { + .name = "s3c24xx_led", + .id = 0, + .dev = { + .platform_data = &smdk_pdata_led4, + }, +}; + +static struct platform_device smdk_led5 = { + .name = "s3c24xx_led", + .id = 1, + .dev = { + .platform_data = &smdk_pdata_led5, + }, +}; + +static struct platform_device smdk_led6 = { + .name = "s3c24xx_led", + .id = 2, + .dev = { + .platform_data = &smdk_pdata_led6, + }, +}; + +static struct platform_device smdk_led7 = { + .name = "s3c24xx_led", + .id = 3, + .dev = { + .platform_data = &smdk_pdata_led7, + }, +}; + +/* NAND parititon from 2.4.18-swl5 */ + +static struct mtd_partition smdk_default_nand_part[] = { + [0] = { + .name = "Boot Agent", + .size = SZ_16K, + .offset = 0, + }, + [1] = { + .name = "S3C2410 flash partition 1", + .offset = 0, + .size = SZ_2M, + }, + [2] = { + .name = "S3C2410 flash partition 2", + .offset = SZ_4M, + .size = SZ_4M, + }, + [3] = { + .name = "S3C2410 flash partition 3", + .offset = SZ_8M, + .size = SZ_2M, + }, + [4] = { + .name = "S3C2410 flash partition 4", + .offset = SZ_1M * 10, + .size = SZ_4M, + }, + [5] = { + .name = "S3C2410 flash partition 5", + .offset = SZ_1M * 14, + .size = SZ_1M * 10, + }, + [6] = { + .name = "S3C2410 flash partition 6", + .offset = SZ_1M * 24, + .size = SZ_1M * 24, + }, + [7] = { + .name = "S3C2410 flash partition 7", + .offset = SZ_1M * 48, + .size = SZ_16M, + } +}; + +static struct s3c2410_nand_set smdk_nand_sets[] = { + [0] = { + .name = "NAND", + .nr_chips = 1, + .nr_partitions = ARRAY_SIZE(smdk_default_nand_part), + .partitions = smdk_default_nand_part, + }, +}; + +/* choose a set of timings which should suit most 512Mbit + * chips and beyond. +*/ + +static struct s3c2410_platform_nand smdk_nand_info = { + .tacls = 20, + .twrph0 = 60, + .twrph1 = 20, + .nr_sets = ARRAY_SIZE(smdk_nand_sets), + .sets = smdk_nand_sets, +}; + +/* devices we initialise */ + +static struct platform_device __initdata *smdk_devs[] = { + &s3c_device_nand, + &smdk_led4, + &smdk_led5, + &smdk_led6, + &smdk_led7, +}; + +void __init smdk_machine_init(void) +{ + /* Configure the LEDs (even if we have no LED support)*/ + + s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP); + s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP); + s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP); + s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP); + + s3c2410_gpio_setpin(S3C2410_GPF4, 1); + s3c2410_gpio_setpin(S3C2410_GPF5, 1); + s3c2410_gpio_setpin(S3C2410_GPF6, 1); + s3c2410_gpio_setpin(S3C2410_GPF7, 1); + + s3c_device_nand.dev.platform_data = &smdk_nand_info; + + platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); + + s3c2410_pm_init(); +} diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c new file mode 100644 index 000000000000..2fbb74969379 --- /dev/null +++ b/arch/arm/plat-s3c24xx/cpu.c @@ -0,0 +1,357 @@ +/* linux/arch/arm/plat-s3c24xx/cpu.c + * + * Copyright (c) 2004-2005 Simtec Electronics + * http://www.simtec.co.uk/products/SWLINUX/ + * Ben Dooks + * + * S3C24XX CPU Support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include "s3c244x.h" +#include +#include + +struct cpu_table { + unsigned long idcode; + unsigned long idmask; + void (*map_io)(struct map_desc *mach_desc, int size); + void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); + void (*init_clocks)(int xtal); + int (*init)(void); + const char *name; +}; + +/* table of supported CPUs */ + +static const char name_s3c2400[] = "S3C2400"; +static const char name_s3c2410[] = "S3C2410"; +static const char name_s3c2412[] = "S3C2412"; +static const char name_s3c2440[] = "S3C2440"; +static const char name_s3c2442[] = "S3C2442"; +static const char name_s3c2410a[] = "S3C2410A"; +static const char name_s3c2440a[] = "S3C2440A"; + +static struct cpu_table cpu_ids[] __initdata = { + { + .idcode = 0x32410000, + .idmask = 0xffffffff, + .map_io = s3c2410_map_io, + .init_clocks = s3c2410_init_clocks, + .init_uarts = s3c2410_init_uarts, + .init = s3c2410_init, + .name = name_s3c2410 + }, + { + .idcode = 0x32410002, + .idmask = 0xffffffff, + .map_io = s3c2410_map_io, + .init_clocks = s3c2410_init_clocks, + .init_uarts = s3c2410_init_uarts, + .init = s3c2410_init, + .name = name_s3c2410a + }, + { + .idcode = 0x32440000, + .idmask = 0xffffffff, + .map_io = s3c244x_map_io, + .init_clocks = s3c244x_init_clocks, + .init_uarts = s3c244x_init_uarts, + .init = s3c2440_init, + .name = name_s3c2440 + }, + { + .idcode = 0x32440001, + .idmask = 0xffffffff, + .map_io = s3c244x_map_io, + .init_clocks = s3c244x_init_clocks, + .init_uarts = s3c244x_init_uarts, + .init = s3c2440_init, + .name = name_s3c2440a + }, + { + .idcode = 0x32440aaa, + .idmask = 0xffffffff, + .map_io = s3c244x_map_io, + .init_clocks = s3c244x_init_clocks, + .init_uarts = s3c244x_init_uarts, + .init = s3c2442_init, + .name = name_s3c2442 + }, + { + .idcode = 0x32412001, + .idmask = 0xffffffff, + .map_io = s3c2412_map_io, + .init_clocks = s3c2412_init_clocks, + .init_uarts = s3c2412_init_uarts, + .init = s3c2412_init, + .name = name_s3c2412, + }, + { /* a newer version of the s3c2412 */ + .idcode = 0x32412003, + .idmask = 0xffffffff, + .map_io = s3c2412_map_io, + .init_clocks = s3c2412_init_clocks, + .init_uarts = s3c2412_init_uarts, + .init = s3c2412_init, + .name = name_s3c2412, + }, + { + .idcode = 0x0, /* S3C2400 doesn't have an idcode */ + .idmask = 0xffffffff, + .map_io = s3c2400_map_io, + .init_clocks = s3c2400_init_clocks, + .init_uarts = s3c2400_init_uarts, + .init = s3c2400_init, + .name = name_s3c2400 + }, +}; + +/* minimal IO mapping */ + +static struct map_desc s3c_iodesc[] __initdata = { + IODESC_ENT(GPIO), + IODESC_ENT(IRQ), + IODESC_ENT(MEMCTRL), + IODESC_ENT(UART) +}; + + +static struct cpu_table * +s3c_lookup_cpu(unsigned long idcode) +{ + struct cpu_table *tab; + int count; + + tab = cpu_ids; + for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) { + if ((idcode & tab->idmask) == tab->idcode) + return tab; + } + + return NULL; +} + +/* board information */ + +static struct s3c24xx_board *board; + +void s3c24xx_set_board(struct s3c24xx_board *b) +{ + int i; + + board = b; + + if (b->clocks_count != 0) { + struct clk **ptr = b->clocks; + + for (i = b->clocks_count; i > 0; i--, ptr++) + s3c24xx_register_clock(*ptr); + } +} + +/* cpu information */ + +static struct cpu_table *cpu; + +static unsigned long s3c24xx_read_idcode_v5(void) +{ +#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) + return __raw_readl(S3C2412_GSTATUS1); +#else + return 1UL; /* don't look like an 2400 */ +#endif +} + +static unsigned long s3c24xx_read_idcode_v4(void) +{ +#ifndef CONFIG_CPU_S3C2400 + return __raw_readl(S3C2410_GSTATUS1); +#else + return 0UL; +#endif +} + +void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) +{ + unsigned long idcode = 0x0; + + /* initialise the io descriptors we need for initialisation */ + iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); + + if (cpu_architecture() >= CPU_ARCH_ARMv5) { + idcode = s3c24xx_read_idcode_v5(); + } else { + idcode = s3c24xx_read_idcode_v4(); + } + + cpu = s3c_lookup_cpu(idcode); + + if (cpu == NULL) { + printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); + panic("Unknown S3C24XX CPU"); + } + + printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); + + if (cpu->map_io == NULL || cpu->init == NULL) { + printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); + panic("Unsupported S3C24XX CPU"); + } + + (cpu->map_io)(mach_desc, size); +} + +/* s3c24xx_init_clocks + * + * Initialise the clock subsystem and associated information from the + * given master crystal value. + * + * xtal = 0 -> use default PLL crystal value (normally 12MHz) + * != 0 -> PLL crystal value in Hz +*/ + +void __init s3c24xx_init_clocks(int xtal) +{ + if (xtal == 0) + xtal = 12*1000*1000; + + if (cpu == NULL) + panic("s3c24xx_init_clocks: no cpu setup?\n"); + + if (cpu->init_clocks == NULL) + panic("s3c24xx_init_clocks: cpu has no clock init\n"); + else + (cpu->init_clocks)(xtal); +} + +/* uart management */ + +static int nr_uarts __initdata = 0; + +static struct s3c2410_uartcfg uart_cfgs[3]; + +/* s3c24xx_init_uartdevs + * + * copy the specified platform data and configuration into our central + * set of devices, before the data is thrown away after the init process. + * + * This also fills in the array passed to the serial driver for the + * early initialisation of the console. +*/ + +void __init s3c24xx_init_uartdevs(char *name, + struct s3c24xx_uart_resources *res, + struct s3c2410_uartcfg *cfg, int no) +{ + struct platform_device *platdev; + struct s3c2410_uartcfg *cfgptr = uart_cfgs; + struct s3c24xx_uart_resources *resp; + int uart; + + memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no); + + for (uart = 0; uart < no; uart++, cfg++, cfgptr++) { + platdev = s3c24xx_uart_src[cfgptr->hwport]; + + resp = res + cfgptr->hwport; + + s3c24xx_uart_devs[uart] = platdev; + + platdev->name = name; + platdev->resource = resp->resources; + platdev->num_resources = resp->nr_resources; + + platdev->dev.platform_data = cfgptr; + } + + nr_uarts = no; +} + +void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + if (cpu == NULL) + return; + + if (cpu->init_uarts == NULL) { + printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); + } else + (cpu->init_uarts)(cfg, no); +} + +static int __init s3c_arch_init(void) +{ + int ret; + + // do the correct init for cpu + + if (cpu == NULL) + panic("s3c_arch_init: NULL cpu\n"); + + ret = (cpu->init)(); + if (ret != 0) + return ret; + + ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); + if (ret != 0) + return ret; + + if (board != NULL) { + struct platform_device **ptr = board->devices; + int i; + + for (i = 0; i < board->devices_count; i++, ptr++) { + ret = platform_device_register(*ptr); + + if (ret) { + printk(KERN_ERR "s3c24xx: failed to add board device %s (%d) @%p\n", (*ptr)->name, ret, *ptr); + } + } + + /* mask any error, we may not need all these board + * devices */ + ret = 0; + } + + return ret; +} + +arch_initcall(s3c_arch_init); diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c new file mode 100644 index 000000000000..6d46c4e2a4f7 --- /dev/null +++ b/arch/arm/plat-s3c24xx/devs.c @@ -0,0 +1,585 @@ +/* linux/arch/arm/plat-s3c24xx/devs.c + * + * Copyright (c) 2004 Simtec Electronics + * Ben Dooks + * + * Base S3C24XX platform device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +/* Serial port registrations */ + +static struct resource s3c2410_uart0_resource[] = { + [0] = { + .start = S3C2410_PA_UART0, + .end = S3C2410_PA_UART0 + 0x3fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3CUART_RX0, + .end = IRQ_S3CUART_ERR0, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource s3c2410_uart1_resource[] = { + [0] = { + .start = S3C2410_PA_UART1, + .end = S3C2410_PA_UART1 + 0x3fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3CUART_RX1, + .end = IRQ_S3CUART_ERR1, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource s3c2410_uart2_resource[] = { + [0] = { + .start = S3C2410_PA_UART2, + .end = S3C2410_PA_UART2 + 0x3fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3CUART_RX2, + .end = IRQ_S3CUART_ERR2, + .flags = IORESOURCE_IRQ, + } +}; + +struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { + [0] = { + .resources = s3c2410_uart0_resource, + .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource), + }, + [1] = { + .resources = s3c2410_uart1_resource, + .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource), + }, + [2] = { + .resources = s3c2410_uart2_resource, + .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), + }, +}; + +/* yart devices */ + +static struct platform_device s3c24xx_uart_device0 = { + .id = 0, +}; + +static struct platform_device s3c24xx_uart_device1 = { + .id = 1, +}; + +static struct platform_device s3c24xx_uart_device2 = { + .id = 2, +}; + +struct platform_device *s3c24xx_uart_src[3] = { + &s3c24xx_uart_device0, + &s3c24xx_uart_device1, + &s3c24xx_uart_device2, +}; + +struct platform_device *s3c24xx_uart_devs[3] = { +}; + +/* USB Host Controller */ + +static struct resource s3c_usb_resource[] = { + [0] = { + .start = S3C24XX_PA_USBHOST, + .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USBH, + .end = IRQ_USBH, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s3c_device_usb_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_usb = { + .name = "s3c2410-ohci", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_usb_resource), + .resource = s3c_usb_resource, + .dev = { + .dma_mask = &s3c_device_usb_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_usb); + +/* LCD Controller */ + +static struct resource s3c_lcd_resource[] = { + [0] = { + .start = S3C24XX_PA_LCD, + .end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_LCD, + .end = IRQ_LCD, + .flags = IORESOURCE_IRQ, + } + +}; + +static u64 s3c_device_lcd_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_lcd = { + .name = "s3c2410-lcd", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_lcd_resource), + .resource = s3c_lcd_resource, + .dev = { + .dma_mask = &s3c_device_lcd_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_lcd); + +void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) +{ + struct s3c2410fb_mach_info *npd; + + npd = kmalloc(sizeof(*npd), GFP_KERNEL); + if (npd) { + memcpy(npd, pd, sizeof(*npd)); + s3c_device_lcd.dev.platform_data = npd; + } else { + printk(KERN_ERR "no memory for LCD platform data\n"); + } +} + +/* NAND Controller */ + +static struct resource s3c_nand_resource[] = { + [0] = { + .start = S3C2410_PA_NAND, + .end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1, + .flags = IORESOURCE_MEM, + } +}; + +struct platform_device s3c_device_nand = { + .name = "s3c2410-nand", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_nand_resource), + .resource = s3c_nand_resource, +}; + +EXPORT_SYMBOL(s3c_device_nand); + +/* USB Device (Gadget)*/ + +static struct resource s3c_usbgadget_resource[] = { + [0] = { + .start = S3C24XX_PA_USBDEV, + .end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USBD, + .end = IRQ_USBD, + .flags = IORESOURCE_IRQ, + } + +}; + +struct platform_device s3c_device_usbgadget = { + .name = "s3c2410-usbgadget", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_usbgadget_resource), + .resource = s3c_usbgadget_resource, +}; + +EXPORT_SYMBOL(s3c_device_usbgadget); + +/* Watchdog */ + +static struct resource s3c_wdt_resource[] = { + [0] = { + .start = S3C24XX_PA_WATCHDOG, + .end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_WDT, + .end = IRQ_WDT, + .flags = IORESOURCE_IRQ, + } + +}; + +struct platform_device s3c_device_wdt = { + .name = "s3c2410-wdt", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_wdt_resource), + .resource = s3c_wdt_resource, +}; + +EXPORT_SYMBOL(s3c_device_wdt); + +/* I2C */ + +static struct resource s3c_i2c_resource[] = { + [0] = { + .start = S3C24XX_PA_IIC, + .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IIC, + .end = IRQ_IIC, + .flags = IORESOURCE_IRQ, + } + +}; + +struct platform_device s3c_device_i2c = { + .name = "s3c2410-i2c", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_i2c_resource), + .resource = s3c_i2c_resource, +}; + +EXPORT_SYMBOL(s3c_device_i2c); + +/* IIS */ + +static struct resource s3c_iis_resource[] = { + [0] = { + .start = S3C24XX_PA_IIS, + .end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1, + .flags = IORESOURCE_MEM, + } +}; + +static u64 s3c_device_iis_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_iis = { + .name = "s3c2410-iis", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_iis_resource), + .resource = s3c_iis_resource, + .dev = { + .dma_mask = &s3c_device_iis_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_iis); + +/* RTC */ + +static struct resource s3c_rtc_resource[] = { + [0] = { + .start = S3C24XX_PA_RTC, + .end = S3C24XX_PA_RTC + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_RTC, + .end = IRQ_RTC, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_TICK, + .end = IRQ_TICK, + .flags = IORESOURCE_IRQ + } +}; + +struct platform_device s3c_device_rtc = { + .name = "s3c2410-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_rtc_resource), + .resource = s3c_rtc_resource, +}; + +EXPORT_SYMBOL(s3c_device_rtc); + +/* ADC */ + +static struct resource s3c_adc_resource[] = { + [0] = { + .start = S3C24XX_PA_ADC, + .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TC, + .end = IRQ_TC, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_ADC, + .end = IRQ_ADC, + .flags = IORESOURCE_IRQ, + } + +}; + +struct platform_device s3c_device_adc = { + .name = "s3c2410-adc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_adc_resource), + .resource = s3c_adc_resource, +}; + +/* SDI */ + +static struct resource s3c_sdi_resource[] = { + [0] = { + .start = S3C2410_PA_SDI, + .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SDI, + .end = IRQ_SDI, + .flags = IORESOURCE_IRQ, + } + +}; + +struct platform_device s3c_device_sdi = { + .name = "s3c2410-sdi", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_sdi_resource), + .resource = s3c_sdi_resource, +}; + +EXPORT_SYMBOL(s3c_device_sdi); + +/* SPI (0) */ + +static struct resource s3c_spi0_resource[] = { + [0] = { + .start = S3C24XX_PA_SPI, + .end = S3C24XX_PA_SPI + 0x1f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SPI0, + .end = IRQ_SPI0, + .flags = IORESOURCE_IRQ, + } + +}; + +static u64 s3c_device_spi0_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_spi0 = { + .name = "s3c2410-spi", + .id = 0, + .num_resources = ARRAY_SIZE(s3c_spi0_resource), + .resource = s3c_spi0_resource, + .dev = { + .dma_mask = &s3c_device_spi0_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_spi0); + +/* SPI (1) */ + +static struct resource s3c_spi1_resource[] = { + [0] = { + .start = S3C24XX_PA_SPI + 0x20, + .end = S3C24XX_PA_SPI + 0x20 + 0x1f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_SPI1, + .end = IRQ_SPI1, + .flags = IORESOURCE_IRQ, + } + +}; + +static u64 s3c_device_spi1_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_spi1 = { + .name = "s3c2410-spi", + .id = 1, + .num_resources = ARRAY_SIZE(s3c_spi1_resource), + .resource = s3c_spi1_resource, + .dev = { + .dma_mask = &s3c_device_spi1_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_spi1); + +/* pwm timer blocks */ + +static struct resource s3c_timer0_resource[] = { + [0] = { + .start = S3C24XX_PA_TIMER + 0x0C, + .end = S3C24XX_PA_TIMER + 0x0C + 0xB, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TIMER0, + .end = IRQ_TIMER0, + .flags = IORESOURCE_IRQ, + } + +}; + +struct platform_device s3c_device_timer0 = { + .name = "s3c2410-timer", + .id = 0, + .num_resources = ARRAY_SIZE(s3c_timer0_resource), + .resource = s3c_timer0_resource, +}; + +EXPORT_SYMBOL(s3c_device_timer0); + +/* timer 1 */ + +static struct resource s3c_timer1_resource[] = { + [0] = { + .start = S3C24XX_PA_TIMER + 0x18, + .end = S3C24XX_PA_TIMER + 0x23, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TIMER1, + .end = IRQ_TIMER1, + .flags = IORESOURCE_IRQ, + } + +}; + +struct platform_device s3c_device_timer1 = { + .name = "s3c2410-timer", + .id = 1, + .num_resources = ARRAY_SIZE(s3c_timer1_resource), + .resource = s3c_timer1_resource, +}; + +EXPORT_SYMBOL(s3c_device_timer1); + +/* timer 2 */ + +static struct resource s3c_timer2_resource[] = { + [0] = { + .start = S3C24XX_PA_TIMER + 0x24, + .end = S3C24XX_PA_TIMER + 0x2F, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TIMER2, + .end = IRQ_TIMER2, + .flags = IORESOURCE_IRQ, + } + +}; + +struct platform_device s3c_device_timer2 = { + .name = "s3c2410-timer", + .id = 2, + .num_resources = ARRAY_SIZE(s3c_timer2_resource), + .resource = s3c_timer2_resource, +}; + +EXPORT_SYMBOL(s3c_device_timer2); + +/* timer 3 */ + +static struct resource s3c_timer3_resource[] = { + [0] = { + .start = S3C24XX_PA_TIMER + 0x30, + .end = S3C24XX_PA_TIMER + 0x3B, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TIMER3, + .end = IRQ_TIMER3, + .flags = IORESOURCE_IRQ, + } + +}; + +struct platform_device s3c_device_timer3 = { + .name = "s3c2410-timer", + .id = 3, + .num_resources = ARRAY_SIZE(s3c_timer3_resource), + .resource = s3c_timer3_resource, +}; + +EXPORT_SYMBOL(s3c_device_timer3); + +#ifdef CONFIG_CPU_S3C2440 + +/* Camif Controller */ + +static struct resource s3c_camif_resource[] = { + [0] = { + .start = S3C2440_PA_CAMIF, + .end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CAM, + .end = IRQ_CAM, + .flags = IORESOURCE_IRQ, + } + +}; + +static u64 s3c_device_camif_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_camif = { + .name = "s3c2440-camif", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_camif_resource), + .resource = s3c_camif_resource, + .dev = { + .dma_mask = &s3c_device_camif_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_camif); + +#endif // CONFIG_CPU_S32440 diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c new file mode 100644 index 000000000000..c784e1f816bb --- /dev/null +++ b/arch/arm/plat-s3c24xx/dma.c @@ -0,0 +1,1441 @@ +/* linux/arch/arm/plat-s3c24xx/dma.c + * + * Copyright (c) 2003-2005,2006 Simtec Electronics + * Ben Dooks + * + * S3C2410 DMA core + * + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + + +#ifdef CONFIG_S3C2410_DMA_DEBUG +#define DEBUG +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include + +/* io map for dma */ +static void __iomem *dma_base; +static struct kmem_cache *dma_kmem; + +struct s3c24xx_dma_selection dma_sel; + +/* dma channel state information */ +struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; + +/* debugging functions */ + +#define BUF_MAGIC (0xcafebabe) + +#define dmawarn(fmt...) printk(KERN_DEBUG fmt) + +#define dma_regaddr(chan, reg) ((chan)->regs + (reg)) + +#if 1 +#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg)) +#else +static inline void +dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val) +{ + pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg); + writel(val, dma_regaddr(chan, reg)); +} +#endif + +#define dma_rdreg(chan, reg) readl((chan)->regs + (reg)) + +/* captured register state for debug */ + +struct s3c2410_dma_regstate { + unsigned long dcsrc; + unsigned long disrc; + unsigned long dstat; + unsigned long dcon; + unsigned long dmsktrig; +}; + +#ifdef CONFIG_S3C2410_DMA_DEBUG + +/* dmadbg_showregs + * + * simple debug routine to print the current state of the dma registers +*/ + +static void +dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs) +{ + regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC); + regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC); + regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT); + regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON); + regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); +} + +static void +dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan, + struct s3c2410_dma_regstate *regs) +{ + printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n", + chan->number, fname, line, + regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig, + regs->dcon); +} + +static void +dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan) +{ + struct s3c2410_dma_regstate state; + + dmadbg_capture(chan, &state); + + printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n", + chan->number, fname, line, chan->load_state, + chan->curr, chan->next, chan->end); + + dmadbg_dumpregs(fname, line, chan, &state); +} + +static void +dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan) +{ + struct s3c2410_dma_regstate state; + + dmadbg_capture(chan, &state); + dmadbg_dumpregs(fname, line, chan, &state); +} + +#define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan)) +#define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan)) +#else +#define dbg_showregs(chan) do { } while(0) +#define dbg_showchan(chan) do { } while(0) +#endif /* CONFIG_S3C2410_DMA_DEBUG */ + +static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX]; + +/* lookup_dma_channel + * + * change the dma channel number given into a real dma channel id +*/ + +static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel) +{ + if (channel & DMACH_LOW_LEVEL) + return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL]; + else + return dma_chan_map[channel]; +} + +/* s3c2410_dma_stats_timeout + * + * Update DMA stats from timeout info +*/ + +static void +s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val) +{ + if (stats == NULL) + return; + + if (val > stats->timeout_longest) + stats->timeout_longest = val; + if (val < stats->timeout_shortest) + stats->timeout_shortest = val; + + stats->timeout_avg += val; +} + +/* s3c2410_dma_waitforload + * + * wait for the DMA engine to load a buffer, and update the state accordingly +*/ + +static int +s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line) +{ + int timeout = chan->load_timeout; + int took; + + if (chan->load_state != S3C2410_DMALOAD_1LOADED) { + printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line); + return 0; + } + + if (chan->stats != NULL) + chan->stats->loads++; + + while (--timeout > 0) { + if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) { + took = chan->load_timeout - timeout; + + s3c2410_dma_stats_timeout(chan->stats, took); + + switch (chan->load_state) { + case S3C2410_DMALOAD_1LOADED: + chan->load_state = S3C2410_DMALOAD_1RUNNING; + break; + + default: + printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state); + } + + return 1; + } + } + + if (chan->stats != NULL) { + chan->stats->timeout_failed++; + } + + return 0; +} + + + +/* s3c2410_dma_loadbuffer + * + * load a buffer, and update the channel state +*/ + +static inline int +s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan, + struct s3c2410_dma_buf *buf) +{ + unsigned long reload; + + pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n", + buf, (unsigned long)buf->data, buf->size); + + if (buf == NULL) { + dmawarn("buffer is NULL\n"); + return -EINVAL; + } + + /* check the state of the channel before we do anything */ + + if (chan->load_state == S3C2410_DMALOAD_1LOADED) { + dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n"); + } + + if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) { + dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n"); + } + + /* it would seem sensible if we are the last buffer to not bother + * with the auto-reload bit, so that the DMA engine will not try + * and load another transfer after this one has finished... + */ + if (chan->load_state == S3C2410_DMALOAD_NONE) { + pr_debug("load_state is none, checking for noreload (next=%p)\n", + buf->next); + reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0; + } else { + //pr_debug("load_state is %d => autoreload\n", chan->load_state); + reload = S3C2410_DCON_AUTORELOAD; + } + + if ((buf->data & 0xf0000000) != 0x30000000) { + dmawarn("dmaload: buffer is %p\n", (void *)buf->data); + } + + writel(buf->data, chan->addr_reg); + + dma_wrreg(chan, S3C2410_DMA_DCON, + chan->dcon | reload | (buf->size/chan->xfer_unit)); + + chan->next = buf->next; + + /* update the state of the channel */ + + switch (chan->load_state) { + case S3C2410_DMALOAD_NONE: + chan->load_state = S3C2410_DMALOAD_1LOADED; + break; + + case S3C2410_DMALOAD_1RUNNING: + chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING; + break; + + default: + dmawarn("dmaload: unknown state %d in loadbuffer\n", + chan->load_state); + break; + } + + return 0; +} + +/* s3c2410_dma_call_op + * + * small routine to call the op routine with the given op if it has been + * registered +*/ + +static void +s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op) +{ + if (chan->op_fn != NULL) { + (chan->op_fn)(chan, op); + } +} + +/* s3c2410_dma_buffdone + * + * small wrapper to check if callback routine needs to be called, and + * if so, call it +*/ + +static inline void +s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf, + enum s3c2410_dma_buffresult result) +{ +#if 0 + pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n", + chan->callback_fn, buf, buf->id, buf->size, result); +#endif + + if (chan->callback_fn != NULL) { + (chan->callback_fn)(chan, buf->id, buf->size, result); + } +} + +/* s3c2410_dma_start + * + * start a dma channel going +*/ + +static int s3c2410_dma_start(struct s3c2410_dma_chan *chan) +{ + unsigned long tmp; + unsigned long flags; + + pr_debug("s3c2410_start_dma: channel=%d\n", chan->number); + + local_irq_save(flags); + + if (chan->state == S3C2410_DMA_RUNNING) { + pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state); + local_irq_restore(flags); + return 0; + } + + chan->state = S3C2410_DMA_RUNNING; + + /* check wether there is anything to load, and if not, see + * if we can find anything to load + */ + + if (chan->load_state == S3C2410_DMALOAD_NONE) { + if (chan->next == NULL) { + printk(KERN_ERR "dma%d: channel has nothing loaded\n", + chan->number); + chan->state = S3C2410_DMA_IDLE; + local_irq_restore(flags); + return -EINVAL; + } + + s3c2410_dma_loadbuffer(chan, chan->next); + } + + dbg_showchan(chan); + + /* enable the channel */ + + if (!chan->irq_enabled) { + enable_irq(chan->irq); + chan->irq_enabled = 1; + } + + /* start the channel going */ + + tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); + tmp &= ~S3C2410_DMASKTRIG_STOP; + tmp |= S3C2410_DMASKTRIG_ON; + dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); + + pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp); + +#if 0 + /* the dma buffer loads should take care of clearing the AUTO + * reloading feature */ + tmp = dma_rdreg(chan, S3C2410_DMA_DCON); + tmp &= ~S3C2410_DCON_NORELOAD; + dma_wrreg(chan, S3C2410_DMA_DCON, tmp); +#endif + + s3c2410_dma_call_op(chan, S3C2410_DMAOP_START); + + dbg_showchan(chan); + + /* if we've only loaded one buffer onto the channel, then chec + * to see if we have another, and if so, try and load it so when + * the first buffer is finished, the new one will be loaded onto + * the channel */ + + if (chan->next != NULL) { + if (chan->load_state == S3C2410_DMALOAD_1LOADED) { + + if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { + pr_debug("%s: buff not yet loaded, no more todo\n", + __FUNCTION__); + } else { + chan->load_state = S3C2410_DMALOAD_1RUNNING; + s3c2410_dma_loadbuffer(chan, chan->next); + } + + } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { + s3c2410_dma_loadbuffer(chan, chan->next); + } + } + + + local_irq_restore(flags); + + return 0; +} + +/* s3c2410_dma_canload + * + * work out if we can queue another buffer into the DMA engine +*/ + +static int +s3c2410_dma_canload(struct s3c2410_dma_chan *chan) +{ + if (chan->load_state == S3C2410_DMALOAD_NONE || + chan->load_state == S3C2410_DMALOAD_1RUNNING) + return 1; + + return 0; +} + +/* s3c2410_dma_enqueue + * + * queue an given buffer for dma transfer. + * + * id the device driver's id information for this buffer + * data the physical address of the buffer data + * size the size of the buffer in bytes + * + * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART + * is checked, and if set, the channel is started. If this flag isn't set, + * then an error will be returned. + * + * It is possible to queue more than one DMA buffer onto a channel at + * once, and the code will deal with the re-loading of the next buffer + * when necessary. +*/ + +int s3c2410_dma_enqueue(unsigned int channel, void *id, + dma_addr_t data, int size) +{ + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); + struct s3c2410_dma_buf *buf; + unsigned long flags; + + if (chan == NULL) + return -EINVAL; + + pr_debug("%s: id=%p, data=%08x, size=%d\n", + __FUNCTION__, id, (unsigned int)data, size); + + buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); + if (buf == NULL) { + pr_debug("%s: out of memory (%ld alloc)\n", + __FUNCTION__, (long)sizeof(*buf)); + return -ENOMEM; + } + + //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); + //dbg_showchan(chan); + + buf->next = NULL; + buf->data = buf->ptr = data; + buf->size = size; + buf->id = id; + buf->magic = BUF_MAGIC; + + local_irq_save(flags); + + if (chan->curr == NULL) { + /* we've got nothing loaded... */ + pr_debug("%s: buffer %p queued onto empty channel\n", + __FUNCTION__, buf); + + chan->curr = buf; + chan->end = buf; + chan->next = NULL; + } else { + pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n", + chan->number, __FUNCTION__, buf); + + if (chan->end == NULL) + pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n", + chan->number, __FUNCTION__, chan); + + chan->end->next = buf; + chan->end = buf; + } + + /* if necessary, update the next buffer field */ + if (chan->next == NULL) + chan->next = buf; + + /* check to see if we can load a buffer */ + if (chan->state == S3C2410_DMA_RUNNING) { + if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) { + if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { + printk(KERN_ERR "dma%d: loadbuffer:" + "timeout loading buffer\n", + chan->number); + dbg_showchan(chan); + local_irq_restore(flags); + return -EINVAL; + } + } + + while (s3c2410_dma_canload(chan) && chan->next != NULL) { + s3c2410_dma_loadbuffer(chan, chan->next); + } + } else if (chan->state == S3C2410_DMA_IDLE) { + if (chan->flags & S3C2410_DMAF_AUTOSTART) { + s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START); + } + } + + local_irq_restore(flags); + return 0; +} + +EXPORT_SYMBOL(s3c2410_dma_enqueue); + +static inline void +s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf) +{ + int magicok = (buf->magic == BUF_MAGIC); + + buf->magic = -1; + + if (magicok) { + kmem_cache_free(dma_kmem, buf); + } else { + printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf); + } +} + +/* s3c2410_dma_lastxfer + * + * called when the system is out of buffers, to ensure that the channel + * is prepared for shutdown. +*/ + +static inline void +s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan) +{ +#if 0 + pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n", + chan->number, chan->load_state); +#endif + + switch (chan->load_state) { + case S3C2410_DMALOAD_NONE: + break; + + case S3C2410_DMALOAD_1LOADED: + if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { + /* flag error? */ + printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", + chan->number, __FUNCTION__); + return; + } + break; + + case S3C2410_DMALOAD_1LOADED_1RUNNING: + /* I belive in this case we do not have anything to do + * until the next buffer comes along, and we turn off the + * reload */ + return; + + default: + pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n", + chan->number, chan->load_state); + return; + + } + + /* hopefully this'll shut the damned thing up after the transfer... */ + dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD); +} + + +#define dmadbg2(x...) + +static irqreturn_t +s3c2410_dma_irq(int irq, void *devpw) +{ + struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw; + struct s3c2410_dma_buf *buf; + + buf = chan->curr; + + dbg_showchan(chan); + + /* modify the channel state */ + + switch (chan->load_state) { + case S3C2410_DMALOAD_1RUNNING: + /* TODO - if we are running only one buffer, we probably + * want to reload here, and then worry about the buffer + * callback */ + + chan->load_state = S3C2410_DMALOAD_NONE; + break; + + case S3C2410_DMALOAD_1LOADED: + /* iirc, we should go back to NONE loaded here, we + * had a buffer, and it was never verified as being + * loaded. + */ + + chan->load_state = S3C2410_DMALOAD_NONE; + break; + + case S3C2410_DMALOAD_1LOADED_1RUNNING: + /* we'll worry about checking to see if another buffer is + * ready after we've called back the owner. This should + * ensure we do not wait around too long for the DMA + * engine to start the next transfer + */ + + chan->load_state = S3C2410_DMALOAD_1LOADED; + break; + + case S3C2410_DMALOAD_NONE: + printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n", + chan->number); + break; + + default: + printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n", + chan->number, chan->load_state); + break; + } + + if (buf != NULL) { + /* update the chain to make sure that if we load any more + * buffers when we call the callback function, things should + * work properly */ + + chan->curr = buf->next; + buf->next = NULL; + + if (buf->magic != BUF_MAGIC) { + printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n", + chan->number, __FUNCTION__, buf); + return IRQ_HANDLED; + } + + s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK); + + /* free resouces */ + s3c2410_dma_freebuf(buf); + } else { + } + + /* only reload if the channel is still running... our buffer done + * routine may have altered the state by requesting the dma channel + * to stop or shutdown... */ + + /* todo: check that when the channel is shut-down from inside this + * function, we cope with unsetting reload, etc */ + + if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) { + unsigned long flags; + + switch (chan->load_state) { + case S3C2410_DMALOAD_1RUNNING: + /* don't need to do anything for this state */ + break; + + case S3C2410_DMALOAD_NONE: + /* can load buffer immediately */ + break; + + case S3C2410_DMALOAD_1LOADED: + if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { + /* flag error? */ + printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", + chan->number, __FUNCTION__); + return IRQ_HANDLED; + } + + break; + + case S3C2410_DMALOAD_1LOADED_1RUNNING: + goto no_load; + + default: + printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n", + chan->number, chan->load_state); + return IRQ_HANDLED; + } + + local_irq_save(flags); + s3c2410_dma_loadbuffer(chan, chan->next); + local_irq_restore(flags); + } else { + s3c2410_dma_lastxfer(chan); + + /* see if we can stop this channel.. */ + if (chan->load_state == S3C2410_DMALOAD_NONE) { + pr_debug("dma%d: end of transfer, stopping channel (%ld)\n", + chan->number, jiffies); + s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL, + S3C2410_DMAOP_STOP); + } + } + + no_load: + return IRQ_HANDLED; +} + +static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel); + +/* s3c2410_request_dma + * + * get control of an dma channel +*/ + +int s3c2410_dma_request(unsigned int channel, + struct s3c2410_dma_client *client, + void *dev) +{ + struct s3c2410_dma_chan *chan; + unsigned long flags; + int err; + + pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n", + channel, client->name, dev); + + local_irq_save(flags); + + chan = s3c2410_dma_map_channel(channel); + if (chan == NULL) { + local_irq_restore(flags); + return -EBUSY; + } + + dbg_showchan(chan); + + chan->client = client; + chan->in_use = 1; + + if (!chan->irq_claimed) { + pr_debug("dma%d: %s : requesting irq %d\n", + channel, __FUNCTION__, chan->irq); + + chan->irq_claimed = 1; + local_irq_restore(flags); + + err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED, + client->name, (void *)chan); + + local_irq_save(flags); + + if (err) { + chan->in_use = 0; + chan->irq_claimed = 0; + local_irq_restore(flags); + + printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n", + client->name, chan->irq, chan->number); + return err; + } + + chan->irq_enabled = 1; + } + + local_irq_restore(flags); + + /* need to setup */ + + pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan); + + return 0; +} + +EXPORT_SYMBOL(s3c2410_dma_request); + +/* s3c2410_dma_free + * + * release the given channel back to the system, will stop and flush + * any outstanding transfers, and ensure the channel is ready for the + * next claimant. + * + * Note, although a warning is currently printed if the freeing client + * info is not the same as the registrant's client info, the free is still + * allowed to go through. +*/ + +int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) +{ + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); + unsigned long flags; + + if (chan == NULL) + return -EINVAL; + + local_irq_save(flags); + + if (chan->client != client) { + printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n", + channel, chan->client, client); + } + + /* sort out stopping and freeing the channel */ + + if (chan->state != S3C2410_DMA_IDLE) { + pr_debug("%s: need to stop dma channel %p\n", + __FUNCTION__, chan); + + /* possibly flush the channel */ + s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP); + } + + chan->client = NULL; + chan->in_use = 0; + + if (chan->irq_claimed) + free_irq(chan->irq, (void *)chan); + + chan->irq_claimed = 0; + + if (!(channel & DMACH_LOW_LEVEL)) + dma_chan_map[channel] = NULL; + + local_irq_restore(flags); + + return 0; +} + +EXPORT_SYMBOL(s3c2410_dma_free); + +static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan) +{ + unsigned long flags; + unsigned long tmp; + + pr_debug("%s:\n", __FUNCTION__); + + dbg_showchan(chan); + + local_irq_save(flags); + + s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP); + + tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); + tmp |= S3C2410_DMASKTRIG_STOP; + //tmp &= ~S3C2410_DMASKTRIG_ON; + dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); + +#if 0 + /* should also clear interrupts, according to WinCE BSP */ + tmp = dma_rdreg(chan, S3C2410_DMA_DCON); + tmp |= S3C2410_DCON_NORELOAD; + dma_wrreg(chan, S3C2410_DMA_DCON, tmp); +#endif + + /* should stop do this, or should we wait for flush? */ + chan->state = S3C2410_DMA_IDLE; + chan->load_state = S3C2410_DMALOAD_NONE; + + local_irq_restore(flags); + + return 0; +} + +void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan) +{ + unsigned long tmp; + unsigned int timeout = 0x10000; + + while (timeout-- > 0) { + tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); + + if (!(tmp & S3C2410_DMASKTRIG_ON)) + return; + } + + pr_debug("dma%d: failed to stop?\n", chan->number); +} + + +/* s3c2410_dma_flush + * + * stop the channel, and remove all current and pending transfers +*/ + +static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan) +{ + struct s3c2410_dma_buf *buf, *next; + unsigned long flags; + + pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number); + + dbg_showchan(chan); + + local_irq_save(flags); + + if (chan->state != S3C2410_DMA_IDLE) { + pr_debug("%s: stopping channel...\n", __FUNCTION__ ); + s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP); + } + + buf = chan->curr; + if (buf == NULL) + buf = chan->next; + + chan->curr = chan->next = chan->end = NULL; + + if (buf != NULL) { + for ( ; buf != NULL; buf = next) { + next = buf->next; + + pr_debug("%s: free buffer %p, next %p\n", + __FUNCTION__, buf, buf->next); + + s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT); + s3c2410_dma_freebuf(buf); + } + } + + dbg_showregs(chan); + + s3c2410_dma_waitforstop(chan); + +#if 0 + /* should also clear interrupts, according to WinCE BSP */ + { + unsigned long tmp; + + tmp = dma_rdreg(chan, S3C2410_DMA_DCON); + tmp |= S3C2410_DCON_NORELOAD; + dma_wrreg(chan, S3C2410_DMA_DCON, tmp); + } +#endif + + dbg_showregs(chan); + + local_irq_restore(flags); + + return 0; +} + +int +s3c2410_dma_started(struct s3c2410_dma_chan *chan) +{ + unsigned long flags; + + local_irq_save(flags); + + dbg_showchan(chan); + + /* if we've only loaded one buffer onto the channel, then chec + * to see if we have another, and if so, try and load it so when + * the first buffer is finished, the new one will be loaded onto + * the channel */ + + if (chan->next != NULL) { + if (chan->load_state == S3C2410_DMALOAD_1LOADED) { + + if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { + pr_debug("%s: buff not yet loaded, no more todo\n", + __FUNCTION__); + } else { + chan->load_state = S3C2410_DMALOAD_1RUNNING; + s3c2410_dma_loadbuffer(chan, chan->next); + } + + } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { + s3c2410_dma_loadbuffer(chan, chan->next); + } + } + + + local_irq_restore(flags); + + return 0; + +} + +int +s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op) +{ + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); + + if (chan == NULL) + return -EINVAL; + + switch (op) { + case S3C2410_DMAOP_START: + return s3c2410_dma_start(chan); + + case S3C2410_DMAOP_STOP: + return s3c2410_dma_dostop(chan); + + case S3C2410_DMAOP_PAUSE: + case S3C2410_DMAOP_RESUME: + return -ENOENT; + + case S3C2410_DMAOP_FLUSH: + return s3c2410_dma_flush(chan); + + case S3C2410_DMAOP_STARTED: + return s3c2410_dma_started(chan); + + case S3C2410_DMAOP_TIMEOUT: + return 0; + + } + + return -ENOENT; /* unknown, don't bother */ +} + +EXPORT_SYMBOL(s3c2410_dma_ctrl); + +/* DMA configuration for each channel + * + * DISRCC -> source of the DMA (AHB,APB) + * DISRC -> source address of the DMA + * DIDSTC -> destination of the DMA (AHB,APD) + * DIDST -> destination address of the DMA +*/ + +/* s3c2410_dma_config + * + * xfersize: size of unit in bytes (1,2,4) + * dcon: base value of the DCONx register +*/ + +int s3c2410_dma_config(dmach_t channel, + int xferunit, + int dcon) +{ + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); + + pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", + __FUNCTION__, channel, xferunit, dcon); + + if (chan == NULL) + return -EINVAL; + + pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon); + + dcon |= chan->dcon & dma_sel.dcon_mask; + + pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon); + + switch (xferunit) { + case 1: + dcon |= S3C2410_DCON_BYTE; + break; + + case 2: + dcon |= S3C2410_DCON_HALFWORD; + break; + + case 4: + dcon |= S3C2410_DCON_WORD; + break; + + default: + pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit); + return -EINVAL; + } + + dcon |= S3C2410_DCON_HWTRIG; + dcon |= S3C2410_DCON_INTREQ; + + pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon); + + chan->dcon = dcon; + chan->xfer_unit = xferunit; + + return 0; +} + +EXPORT_SYMBOL(s3c2410_dma_config); + +int s3c2410_dma_setflags(dmach_t channel, unsigned int flags) +{ + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); + + if (chan == NULL) + return -EINVAL; + + pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags); + + chan->flags = flags; + + return 0; +} + +EXPORT_SYMBOL(s3c2410_dma_setflags); + + +/* do we need to protect the settings of the fields from + * irq? +*/ + +int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) +{ + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); + + if (chan == NULL) + return -EINVAL; + + pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn); + + chan->op_fn = rtn; + + return 0; +} + +EXPORT_SYMBOL(s3c2410_dma_set_opfn); + +int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn) +{ + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); + + if (chan == NULL) + return -EINVAL; + + pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn); + + chan->callback_fn = rtn; + + return 0; +} + +EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn); + +/* s3c2410_dma_devconfig + * + * configure the dma source/destination hardware type and address + * + * source: S3C2410_DMASRC_HW: source is hardware + * S3C2410_DMASRC_MEM: source is memory + * + * hwcfg: the value for xxxSTCn register, + * bit 0: 0=increment pointer, 1=leave pointer + * bit 1: 0=soucre is AHB, 1=soucre is APB + * + * devaddr: physical address of the source +*/ + +int s3c2410_dma_devconfig(int channel, + enum s3c2410_dmasrc source, + int hwcfg, + unsigned long devaddr) +{ + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); + + if (chan == NULL) + return -EINVAL; + + pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n", + __FUNCTION__, (int)source, hwcfg, devaddr); + + chan->source = source; + chan->dev_addr = devaddr; + + switch (source) { + case S3C2410_DMASRC_HW: + /* source is hardware */ + pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n", + __FUNCTION__, devaddr, hwcfg); + dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3); + dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr); + dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0)); + + chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST); + return 0; + + case S3C2410_DMASRC_MEM: + /* source is memory */ + pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n", + __FUNCTION__, devaddr, hwcfg); + dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0)); + dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr); + dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3); + + chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC); + return 0; + } + + printk(KERN_ERR "dma%d: invalid source type (%d)\n", channel, source); + return -EINVAL; +} + +EXPORT_SYMBOL(s3c2410_dma_devconfig); + +/* s3c2410_dma_getposition + * + * returns the current transfer points for the dma source and destination +*/ + +int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst) +{ + struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); + + if (chan == NULL) + return -EINVAL; + + if (src != NULL) + *src = dma_rdreg(chan, S3C2410_DMA_DCSRC); + + if (dst != NULL) + *dst = dma_rdreg(chan, S3C2410_DMA_DCDST); + + return 0; +} + +EXPORT_SYMBOL(s3c2410_dma_getposition); + + +/* system device class */ + +#ifdef CONFIG_PM + +static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state) +{ + struct s3c2410_dma_chan *cp = container_of(dev, struct s3c2410_dma_chan, dev); + + printk(KERN_DEBUG "suspending dma channel %d\n", cp->number); + + if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) { + /* the dma channel is still working, which is probably + * a bad thing to do over suspend/resume. We stop the + * channel and assume that the client is either going to + * retry after resume, or that it is broken. + */ + + printk(KERN_INFO "dma: stopping channel %d due to suspend\n", + cp->number); + + s3c2410_dma_dostop(cp); + } + + return 0; +} + +static int s3c2410_dma_resume(struct sys_device *dev) +{ + return 0; +} + +#else +#define s3c2410_dma_suspend NULL +#define s3c2410_dma_resume NULL +#endif /* CONFIG_PM */ + +struct sysdev_class dma_sysclass = { + set_kset_name("s3c24xx-dma"), + .suspend = s3c2410_dma_suspend, + .resume = s3c2410_dma_resume, +}; + +/* kmem cache implementation */ + +static void s3c2410_dma_cache_ctor(void *p, struct kmem_cache *c, unsigned long f) +{ + memset(p, 0, sizeof(struct s3c2410_dma_buf)); +} + +/* initialisation code */ + +static int __init s3c2410_init_dma(void) +{ + struct s3c2410_dma_chan *cp; + int channel; + int ret; + + printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n"); + + dma_base = ioremap(S3C24XX_PA_DMA, 0x200); + if (dma_base == NULL) { + printk(KERN_ERR "dma failed to remap register block\n"); + return -ENOMEM; + } + + printk("Registering sysclass\n"); + + ret = sysdev_class_register(&dma_sysclass); + if (ret != 0) { + printk(KERN_ERR "dma sysclass registration failed\n"); + goto err; + } + + dma_kmem = kmem_cache_create("dma_desc", sizeof(struct s3c2410_dma_buf), 0, + SLAB_HWCACHE_ALIGN, + s3c2410_dma_cache_ctor, NULL); + + if (dma_kmem == NULL) { + printk(KERN_ERR "dma failed to make kmem cache\n"); + ret = -ENOMEM; + goto err; + } + + for (channel = 0; channel < S3C2410_DMA_CHANNELS; channel++) { + cp = &s3c2410_chans[channel]; + + memset(cp, 0, sizeof(struct s3c2410_dma_chan)); + + /* dma channel irqs are in order.. */ + cp->number = channel; + cp->irq = channel + IRQ_DMA0; + cp->regs = dma_base + (channel*0x40); + + /* point current stats somewhere */ + cp->stats = &cp->stats_store; + cp->stats_store.timeout_shortest = LONG_MAX; + + /* basic channel configuration */ + + cp->load_timeout = 1<<18; + + /* register system device */ + + cp->dev.cls = &dma_sysclass; + cp->dev.id = channel; + ret = sysdev_register(&cp->dev); + + printk("DMA channel %d at %p, irq %d\n", + cp->number, cp->regs, cp->irq); + } + + return 0; + + err: + kmem_cache_destroy(dma_kmem); + iounmap(dma_base); + dma_base = NULL; + return ret; +} + +core_initcall(s3c2410_init_dma); + +static inline int is_channel_valid(unsigned int channel) +{ + return (channel & DMA_CH_VALID); +} + +/* s3c2410_dma_map_channel() + * + * turn the virtual channel number into a real, and un-used hardware + * channel. + * + * currently this code uses first-free channel from the specified harware + * map, not taking into account anything that the board setup code may + * have to say about the likely peripheral set to be in use. +*/ + +struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel) +{ + struct s3c24xx_dma_map *ch_map; + struct s3c2410_dma_chan *dmach; + int ch; + + if (dma_sel.map == NULL || channel > dma_sel.map_size) + return NULL; + + ch_map = dma_sel.map + channel; + + for (ch = 0; ch < S3C2410_DMA_CHANNELS; ch++) { + if (!is_channel_valid(ch_map->channels[ch])) + continue; + + if (s3c2410_chans[ch].in_use == 0) { + printk("mapped channel %d to %d\n", channel, ch); + break; + } + } + + if (ch >= S3C2410_DMA_CHANNELS) + return NULL; + + /* update our channel mapping */ + + dmach = &s3c2410_chans[ch]; + dma_chan_map[channel] = dmach; + + /* select the channel */ + + (dma_sel.select)(dmach, ch_map); + + return dmach; +} + +static void s3c24xx_dma_show_ch(struct s3c24xx_dma_map *map, int ch) +{ + /* show the channel configuration */ + + printk("%2d: %20s, channels %c%c%c%c\n", ch, map->name, + (is_channel_valid(map->channels[0]) ? '0' : '-'), + (is_channel_valid(map->channels[1]) ? '1' : '-'), + (is_channel_valid(map->channels[2]) ? '2' : '-'), + (is_channel_valid(map->channels[3]) ? '3' : '-')); +} + +static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch) +{ + if (1) + s3c24xx_dma_show_ch(map, ch); + + return 0; +} + +int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel) +{ + struct s3c24xx_dma_map *nmap; + size_t map_sz = sizeof(*nmap) * sel->map_size; + int ptr; + + nmap = kmalloc(map_sz, GFP_KERNEL); + if (nmap == NULL) + return -ENOMEM; + + memcpy(nmap, sel->map, map_sz); + memcpy(&dma_sel, sel, sizeof(*sel)); + + dma_sel.map = nmap; + + for (ptr = 0; ptr < sel->map_size; ptr++) + s3c24xx_dma_check_entry(nmap+ptr, ptr); + + return 0; +} diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c new file mode 100644 index 000000000000..ec3a09c4d181 --- /dev/null +++ b/arch/arm/plat-s3c24xx/gpio.c @@ -0,0 +1,188 @@ +/* linux/arch/arm/plat-s3c24xx/gpio.c + * + * Copyright (c) 2004-2005 Simtec Electronics + * Ben Dooks + * + * S3C24XX GPIO support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function) +{ + void __iomem *base = S3C24XX_GPIO_BASE(pin); + unsigned long mask; + unsigned long con; + unsigned long flags; + + if (pin < S3C2410_GPIO_BANKB) { + mask = 1 << S3C2410_GPIO_OFFSET(pin); + } else { + mask = 3 << S3C2410_GPIO_OFFSET(pin)*2; + } + + switch (function) { + case S3C2410_GPIO_LEAVE: + mask = 0; + function = 0; + break; + + case S3C2410_GPIO_INPUT: + case S3C2410_GPIO_OUTPUT: + case S3C2410_GPIO_SFN2: + case S3C2410_GPIO_SFN3: + if (pin < S3C2410_GPIO_BANKB) { + function -= 1; + function &= 1; + function <<= S3C2410_GPIO_OFFSET(pin); + } else { + function &= 3; + function <<= S3C2410_GPIO_OFFSET(pin)*2; + } + } + + /* modify the specified register wwith IRQs off */ + + local_irq_save(flags); + + con = __raw_readl(base + 0x00); + con &= ~mask; + con |= function; + + __raw_writel(con, base + 0x00); + + local_irq_restore(flags); +} + +EXPORT_SYMBOL(s3c2410_gpio_cfgpin); + +unsigned int s3c2410_gpio_getcfg(unsigned int pin) +{ + void __iomem *base = S3C24XX_GPIO_BASE(pin); + unsigned long val = __raw_readl(base); + + if (pin < S3C2410_GPIO_BANKB) { + val >>= S3C2410_GPIO_OFFSET(pin); + val &= 1; + val += 1; + } else { + val >>= S3C2410_GPIO_OFFSET(pin)*2; + val &= 3; + } + + return val | S3C2410_GPIO_INPUT; +} + +EXPORT_SYMBOL(s3c2410_gpio_getcfg); + +void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) +{ + void __iomem *base = S3C24XX_GPIO_BASE(pin); + unsigned long offs = S3C2410_GPIO_OFFSET(pin); + unsigned long flags; + unsigned long up; + + if (pin < S3C2410_GPIO_BANKB) + return; + + local_irq_save(flags); + + up = __raw_readl(base + 0x08); + up &= ~(1L << offs); + up |= to << offs; + __raw_writel(up, base + 0x08); + + local_irq_restore(flags); +} + +EXPORT_SYMBOL(s3c2410_gpio_pullup); + +void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) +{ + void __iomem *base = S3C24XX_GPIO_BASE(pin); + unsigned long offs = S3C2410_GPIO_OFFSET(pin); + unsigned long flags; + unsigned long dat; + + local_irq_save(flags); + + dat = __raw_readl(base + 0x04); + dat &= ~(1 << offs); + dat |= to << offs; + __raw_writel(dat, base + 0x04); + + local_irq_restore(flags); +} + +EXPORT_SYMBOL(s3c2410_gpio_setpin); + +unsigned int s3c2410_gpio_getpin(unsigned int pin) +{ + void __iomem *base = S3C24XX_GPIO_BASE(pin); + unsigned long offs = S3C2410_GPIO_OFFSET(pin); + + return __raw_readl(base + 0x04) & (1<< offs); +} + +EXPORT_SYMBOL(s3c2410_gpio_getpin); + +unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change) +{ + unsigned long flags; + unsigned long misccr; + + local_irq_save(flags); + misccr = __raw_readl(S3C24XX_MISCCR); + misccr &= ~clear; + misccr ^= change; + __raw_writel(misccr, S3C24XX_MISCCR); + local_irq_restore(flags); + + return misccr; +} + +EXPORT_SYMBOL(s3c2410_modify_misccr); + +int s3c2410_gpio_getirq(unsigned int pin) +{ + if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15) + return -1; /* not valid interrupts */ + + if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7) + return -1; /* not valid pin */ + + if (pin < S3C2410_GPF4) + return (pin - S3C2410_GPF0) + IRQ_EINT0; + + if (pin < S3C2410_GPG0) + return (pin - S3C2410_GPF4) + IRQ_EINT4; + + return (pin - S3C2410_GPG0) + IRQ_EINT8; +} + +EXPORT_SYMBOL(s3c2410_gpio_getirq); diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c new file mode 100644 index 000000000000..ce186398e3fd --- /dev/null +++ b/arch/arm/plat-s3c24xx/irq.c @@ -0,0 +1,801 @@ +/* linux/arch/arm/plat-s3c24xx/irq.c + * + * Copyright (c) 2003,2004 Simtec Electronics + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Changelog: + * + * 22-Jul-2004 Ben Dooks + * Fixed compile warnings + * + * 22-Jul-2004 Roc Wu + * Fixed s3c_extirq_type + * + * 21-Jul-2004 Arnaud Patard (Rtp) + * Addition of ADC/TC demux + * + * 04-Oct-2004 Klaus Fetscher + * Fix for set_irq_type() on low EINT numbers + * + * 05-Oct-2004 Ben Dooks + * Tidy up KF's patch and sort out new release + * + * 05-Oct-2004 Ben Dooks + * Add support for power management controls + * + * 04-Nov-2004 Ben Dooks + * Fix standard IRQ wake for EINT0..4 and RTC + * + * 22-Feb-2005 Ben Dooks + * Fixed edge-triggering on ADC IRQ + * + * 28-Jun-2005 Ben Dooks + * Mark IRQ_LCD valid + * + * 25-Jul-2005 Ben Dooks + * Split the S3C2440 IRQ code to seperate file +*/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +/* wakeup irq control */ + +#ifdef CONFIG_PM + +/* state for IRQs over sleep */ + +/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources + * + * set bit to 1 in allow bitfield to enable the wakeup settings on it +*/ + +unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; +unsigned long s3c_irqwake_intmask = 0xffffffffL; +unsigned long s3c_irqwake_eintallow = 0x0000fff0L; +unsigned long s3c_irqwake_eintmask = 0xffffffffL; + +int +s3c_irq_wake(unsigned int irqno, unsigned int state) +{ + unsigned long irqbit = 1 << (irqno - IRQ_EINT0); + + if (!(s3c_irqwake_intallow & irqbit)) + return -ENOENT; + + printk(KERN_INFO "wake %s for irq %d\n", + state ? "enabled" : "disabled", irqno); + + if (!state) + s3c_irqwake_intmask |= irqbit; + else + s3c_irqwake_intmask &= ~irqbit; + + return 0; +} + +static int +s3c_irqext_wake(unsigned int irqno, unsigned int state) +{ + unsigned long bit = 1L << (irqno - EXTINT_OFF); + + if (!(s3c_irqwake_eintallow & bit)) + return -ENOENT; + + printk(KERN_INFO "wake %s for irq %d\n", + state ? "enabled" : "disabled", irqno); + + if (!state) + s3c_irqwake_eintmask |= bit; + else + s3c_irqwake_eintmask &= ~bit; + + return 0; +} + +#else +#define s3c_irqext_wake NULL +#define s3c_irq_wake NULL +#endif + + +static void +s3c_irq_mask(unsigned int irqno) +{ + unsigned long mask; + + irqno -= IRQ_EINT0; + + mask = __raw_readl(S3C2410_INTMSK); + mask |= 1UL << irqno; + __raw_writel(mask, S3C2410_INTMSK); +} + +static inline void +s3c_irq_ack(unsigned int irqno) +{ + unsigned long bitval = 1UL << (irqno - IRQ_EINT0); + + __raw_writel(bitval, S3C2410_SRCPND); + __raw_writel(bitval, S3C2410_INTPND); +} + +static inline void +s3c_irq_maskack(unsigned int irqno) +{ + unsigned long bitval = 1UL << (irqno - IRQ_EINT0); + unsigned long mask; + + mask = __raw_readl(S3C2410_INTMSK); + __raw_writel(mask|bitval, S3C2410_INTMSK); + + __raw_writel(bitval, S3C2410_SRCPND); + __raw_writel(bitval, S3C2410_INTPND); +} + + +static void +s3c_irq_unmask(unsigned int irqno) +{ + unsigned long mask; + + if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23) + irqdbf2("s3c_irq_unmask %d\n", irqno); + + irqno -= IRQ_EINT0; + + mask = __raw_readl(S3C2410_INTMSK); + mask &= ~(1UL << irqno); + __raw_writel(mask, S3C2410_INTMSK); +} + +struct irq_chip s3c_irq_level_chip = { + .name = "s3c-level", + .ack = s3c_irq_maskack, + .mask = s3c_irq_mask, + .unmask = s3c_irq_unmask, + .set_wake = s3c_irq_wake +}; + +static struct irq_chip s3c_irq_chip = { + .name = "s3c", + .ack = s3c_irq_ack, + .mask = s3c_irq_mask, + .unmask = s3c_irq_unmask, + .set_wake = s3c_irq_wake +}; + +static void +s3c_irqext_mask(unsigned int irqno) +{ + unsigned long mask; + + irqno -= EXTINT_OFF; + + mask = __raw_readl(S3C24XX_EINTMASK); + mask |= ( 1UL << irqno); + __raw_writel(mask, S3C24XX_EINTMASK); +} + +static void +s3c_irqext_ack(unsigned int irqno) +{ + unsigned long req; + unsigned long bit; + unsigned long mask; + + bit = 1UL << (irqno - EXTINT_OFF); + + mask = __raw_readl(S3C24XX_EINTMASK); + + __raw_writel(bit, S3C24XX_EINTPEND); + + req = __raw_readl(S3C24XX_EINTPEND); + req &= ~mask; + + /* not sure if we should be acking the parent irq... */ + + if (irqno <= IRQ_EINT7 ) { + if ((req & 0xf0) == 0) + s3c_irq_ack(IRQ_EINT4t7); + } else { + if ((req >> 8) == 0) + s3c_irq_ack(IRQ_EINT8t23); + } +} + +static void +s3c_irqext_unmask(unsigned int irqno) +{ + unsigned long mask; + + irqno -= EXTINT_OFF; + + mask = __raw_readl(S3C24XX_EINTMASK); + mask &= ~( 1UL << irqno); + __raw_writel(mask, S3C24XX_EINTMASK); +} + +int +s3c_irqext_type(unsigned int irq, unsigned int type) +{ + void __iomem *extint_reg; + void __iomem *gpcon_reg; + unsigned long gpcon_offset, extint_offset; + unsigned long newvalue = 0, value; + + if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3)) + { + gpcon_reg = S3C2410_GPFCON; + extint_reg = S3C24XX_EXTINT0; + gpcon_offset = (irq - IRQ_EINT0) * 2; + extint_offset = (irq - IRQ_EINT0) * 4; + } + else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7)) + { + gpcon_reg = S3C2410_GPFCON; + extint_reg = S3C24XX_EXTINT0; + gpcon_offset = (irq - (EXTINT_OFF)) * 2; + extint_offset = (irq - (EXTINT_OFF)) * 4; + } + else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15)) + { + gpcon_reg = S3C2410_GPGCON; + extint_reg = S3C24XX_EXTINT1; + gpcon_offset = (irq - IRQ_EINT8) * 2; + extint_offset = (irq - IRQ_EINT8) * 4; + } + else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23)) + { + gpcon_reg = S3C2410_GPGCON; + extint_reg = S3C24XX_EXTINT2; + gpcon_offset = (irq - IRQ_EINT8) * 2; + extint_offset = (irq - IRQ_EINT16) * 4; + } else + return -1; + + /* Set the GPIO to external interrupt mode */ + value = __raw_readl(gpcon_reg); + value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); + __raw_writel(value, gpcon_reg); + + /* Set the external interrupt to pointed trigger type */ + switch (type) + { + case IRQT_NOEDGE: + printk(KERN_WARNING "No edge setting!\n"); + break; + + case IRQT_RISING: + newvalue = S3C2410_EXTINT_RISEEDGE; + break; + + case IRQT_FALLING: + newvalue = S3C2410_EXTINT_FALLEDGE; + break; + + case IRQT_BOTHEDGE: + newvalue = S3C2410_EXTINT_BOTHEDGE; + break; + + case IRQT_LOW: + newvalue = S3C2410_EXTINT_LOWLEV; + break; + + case IRQT_HIGH: + newvalue = S3C2410_EXTINT_HILEV; + break; + + default: + printk(KERN_ERR "No such irq type %d", type); + return -1; + } + + value = __raw_readl(extint_reg); + value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); + __raw_writel(value, extint_reg); + + return 0; +} + +static struct irq_chip s3c_irqext_chip = { + .name = "s3c-ext", + .mask = s3c_irqext_mask, + .unmask = s3c_irqext_unmask, + .ack = s3c_irqext_ack, + .set_type = s3c_irqext_type, + .set_wake = s3c_irqext_wake +}; + +static struct irq_chip s3c_irq_eint0t4 = { + .name = "s3c-ext0", + .ack = s3c_irq_ack, + .mask = s3c_irq_mask, + .unmask = s3c_irq_unmask, + .set_wake = s3c_irq_wake, + .set_type = s3c_irqext_type, +}; + +/* mask values for the parent registers for each of the interrupt types */ + +#define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0)) +#define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0)) +#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0)) +#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0)) + + +/* UART0 */ + +static void +s3c_irq_uart0_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_UART0, 7); +} + +static void +s3c_irq_uart0_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_UART0); +} + +static void +s3c_irq_uart0_ack(unsigned int irqno) +{ + s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); +} + +static struct irq_chip s3c_irq_uart0 = { + .name = "s3c-uart0", + .mask = s3c_irq_uart0_mask, + .unmask = s3c_irq_uart0_unmask, + .ack = s3c_irq_uart0_ack, +}; + +/* UART1 */ + +static void +s3c_irq_uart1_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3); +} + +static void +s3c_irq_uart1_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_UART1); +} + +static void +s3c_irq_uart1_ack(unsigned int irqno) +{ + s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); +} + +static struct irq_chip s3c_irq_uart1 = { + .name = "s3c-uart1", + .mask = s3c_irq_uart1_mask, + .unmask = s3c_irq_uart1_unmask, + .ack = s3c_irq_uart1_ack, +}; + +/* UART2 */ + +static void +s3c_irq_uart2_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6); +} + +static void +s3c_irq_uart2_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_UART2); +} + +static void +s3c_irq_uart2_ack(unsigned int irqno) +{ + s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); +} + +static struct irq_chip s3c_irq_uart2 = { + .name = "s3c-uart2", + .mask = s3c_irq_uart2_mask, + .unmask = s3c_irq_uart2_unmask, + .ack = s3c_irq_uart2_ack, +}; + +/* ADC and Touchscreen */ + +static void +s3c_irq_adc_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9); +} + +static void +s3c_irq_adc_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT); +} + +static void +s3c_irq_adc_ack(unsigned int irqno) +{ + s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); +} + +static struct irq_chip s3c_irq_adc = { + .name = "s3c-adc", + .mask = s3c_irq_adc_mask, + .unmask = s3c_irq_adc_unmask, + .ack = s3c_irq_adc_ack, +}; + +/* irq demux for adc */ +static void s3c_irq_demux_adc(unsigned int irq, + struct irq_desc *desc) +{ + unsigned int subsrc, submsk; + unsigned int offset = 9; + struct irq_desc *mydesc; + + /* read the current pending interrupts, and the mask + * for what it is available */ + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + subsrc &= ~submsk; + subsrc >>= offset; + subsrc &= 3; + + if (subsrc != 0) { + if (subsrc & 1) { + mydesc = irq_desc + IRQ_TC; + desc_handle_irq(IRQ_TC, mydesc); + } + if (subsrc & 2) { + mydesc = irq_desc + IRQ_ADC; + desc_handle_irq(IRQ_ADC, mydesc); + } + } +} + +static void s3c_irq_demux_uart(unsigned int start) +{ + unsigned int subsrc, submsk; + unsigned int offset = start - IRQ_S3CUART_RX0; + struct irq_desc *desc; + + /* read the current pending interrupts, and the mask + * for what it is available */ + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n", + start, offset, subsrc, submsk); + + subsrc &= ~submsk; + subsrc >>= offset; + subsrc &= 7; + + if (subsrc != 0) { + desc = irq_desc + start; + + if (subsrc & 1) + desc_handle_irq(start, desc); + + desc++; + + if (subsrc & 2) + desc_handle_irq(start+1, desc); + + desc++; + + if (subsrc & 4) + desc_handle_irq(start+2, desc); + } +} + +/* uart demux entry points */ + +static void +s3c_irq_demux_uart0(unsigned int irq, + struct irq_desc *desc) +{ + irq = irq; + s3c_irq_demux_uart(IRQ_S3CUART_RX0); +} + +static void +s3c_irq_demux_uart1(unsigned int irq, + struct irq_desc *desc) +{ + irq = irq; + s3c_irq_demux_uart(IRQ_S3CUART_RX1); +} + +static void +s3c_irq_demux_uart2(unsigned int irq, + struct irq_desc *desc) +{ + irq = irq; + s3c_irq_demux_uart(IRQ_S3CUART_RX2); +} + +static void +s3c_irq_demux_extint8(unsigned int irq, + struct irq_desc *desc) +{ + unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); + unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); + + eintpnd &= ~eintmsk; + eintpnd &= ~0xff; /* ignore lower irqs */ + + /* we may as well handle all the pending IRQs here */ + + while (eintpnd) { + irq = __ffs(eintpnd); + eintpnd &= ~(1< + * + * http://armlinux.simtec.co.uk/ + * + * Power Management helpers for Simtec S3C24XX implementations + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include +#include + +#include + +#include + +#define COPYRIGHT ", (c) 2005 Simtec Electronics" + +/* pm_simtec_init + * + * enable the power management functions +*/ + +static __init int pm_simtec_init(void) +{ + unsigned long gstatus4; + + /* check which machine we are running on */ + + if (!machine_is_bast() && !machine_is_vr1000() && + !machine_is_anubis() && !machine_is_osiris() && + !machine_is_aml_m5900()) + return 0; + + printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n"); + + gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30; + gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28; + gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK); + + __raw_writel(gstatus4, S3C2410_GSTATUS4); + + return s3c2410_pm_init(); +} + +arch_initcall(pm_simtec_init); diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c new file mode 100644 index 000000000000..ecf68d611904 --- /dev/null +++ b/arch/arm/plat-s3c24xx/pm.c @@ -0,0 +1,659 @@ +/* linux/arch/arm/plat-s3c24xx/pm.c + * + * Copyright (c) 2004,2006 Simtec Electronics + * Ben Dooks + * + * S3C24XX Power Manager (Suspend-To-RAM) support + * + * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Parts based on arch/arm/mach-pxa/pm.c + * + * Thanks to Dimitry Andric for debugging +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include + +/* for external use */ + +unsigned long s3c_pm_flags; + +#define PFX "s3c24xx-pm: " + +static struct sleep_save core_save[] = { + SAVE_ITEM(S3C2410_LOCKTIME), + SAVE_ITEM(S3C2410_CLKCON), + + /* we restore the timings here, with the proviso that the board + * brings the system up in an slower, or equal frequency setting + * to the original system. + * + * if we cannot guarantee this, then things are going to go very + * wrong here, as we modify the refresh and both pll settings. + */ + + SAVE_ITEM(S3C2410_BWSCON), + SAVE_ITEM(S3C2410_BANKCON0), + SAVE_ITEM(S3C2410_BANKCON1), + SAVE_ITEM(S3C2410_BANKCON2), + SAVE_ITEM(S3C2410_BANKCON3), + SAVE_ITEM(S3C2410_BANKCON4), + SAVE_ITEM(S3C2410_BANKCON5), + + SAVE_ITEM(S3C2410_CLKDIVN), + SAVE_ITEM(S3C2410_MPLLCON), + SAVE_ITEM(S3C2410_UPLLCON), + SAVE_ITEM(S3C2410_CLKSLOW), + SAVE_ITEM(S3C2410_REFRESH), +}; + +static struct sleep_save gpio_save[] = { + SAVE_ITEM(S3C2410_GPACON), + SAVE_ITEM(S3C2410_GPADAT), + + SAVE_ITEM(S3C2410_GPBCON), + SAVE_ITEM(S3C2410_GPBDAT), + SAVE_ITEM(S3C2410_GPBUP), + + SAVE_ITEM(S3C2410_GPCCON), + SAVE_ITEM(S3C2410_GPCDAT), + SAVE_ITEM(S3C2410_GPCUP), + + SAVE_ITEM(S3C2410_GPDCON), + SAVE_ITEM(S3C2410_GPDDAT), + SAVE_ITEM(S3C2410_GPDUP), + + SAVE_ITEM(S3C2410_GPECON), + SAVE_ITEM(S3C2410_GPEDAT), + SAVE_ITEM(S3C2410_GPEUP), + + SAVE_ITEM(S3C2410_GPFCON), + SAVE_ITEM(S3C2410_GPFDAT), + SAVE_ITEM(S3C2410_GPFUP), + + SAVE_ITEM(S3C2410_GPGCON), + SAVE_ITEM(S3C2410_GPGDAT), + SAVE_ITEM(S3C2410_GPGUP), + + SAVE_ITEM(S3C2410_GPHCON), + SAVE_ITEM(S3C2410_GPHDAT), + SAVE_ITEM(S3C2410_GPHUP), + + SAVE_ITEM(S3C2410_DCLKCON), +}; + +#ifdef CONFIG_S3C2410_PM_DEBUG + +#define SAVE_UART(va) \ + SAVE_ITEM((va) + S3C2410_ULCON), \ + SAVE_ITEM((va) + S3C2410_UCON), \ + SAVE_ITEM((va) + S3C2410_UFCON), \ + SAVE_ITEM((va) + S3C2410_UMCON), \ + SAVE_ITEM((va) + S3C2410_UBRDIV) + +static struct sleep_save uart_save[] = { + SAVE_UART(S3C24XX_VA_UART0), + SAVE_UART(S3C24XX_VA_UART1), +#ifndef CONFIG_CPU_S3C2400 + SAVE_UART(S3C24XX_VA_UART2), +#endif +}; + +/* debug + * + * we send the debug to printascii() to allow it to be seen if the + * system never wakes up from the sleep +*/ + +extern void printascii(const char *); + +void pm_dbg(const char *fmt, ...) +{ + va_list va; + char buff[256]; + + va_start(va, fmt); + vsprintf(buff, fmt, va); + va_end(va); + + printascii(buff); +} + +static void s3c2410_pm_debug_init(void) +{ + unsigned long tmp = __raw_readl(S3C2410_CLKCON); + + /* re-start uart clocks */ + tmp |= S3C2410_CLKCON_UART0; + tmp |= S3C2410_CLKCON_UART1; + tmp |= S3C2410_CLKCON_UART2; + + __raw_writel(tmp, S3C2410_CLKCON); + udelay(10); +} + +#define DBG(fmt...) pm_dbg(fmt) +#else +#define DBG(fmt...) printk(KERN_DEBUG fmt) + +#define s3c2410_pm_debug_init() do { } while(0) + +static struct sleep_save uart_save[] = {}; +#endif + +#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0 + +/* suspend checking code... + * + * this next area does a set of crc checks over all the installed + * memory, so the system can verify if the resume was ok. + * + * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, + * increasing it will mean that the area corrupted will be less easy to spot, + * and reducing the size will cause the CRC save area to grow +*/ + +#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) + +static u32 crc_size; /* size needed for the crc block */ +static u32 *crcs; /* allocated over suspend/resume */ + +typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); + +/* s3c2410_pm_run_res + * + * go thorugh the given resource list, and look for system ram +*/ + +static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) +{ + while (ptr != NULL) { + if (ptr->child != NULL) + s3c2410_pm_run_res(ptr->child, fn, arg); + + if ((ptr->flags & IORESOURCE_MEM) && + strcmp(ptr->name, "System RAM") == 0) { + DBG("Found system RAM at %08lx..%08lx\n", + ptr->start, ptr->end); + arg = (fn)(ptr, arg); + } + + ptr = ptr->sibling; + } +} + +static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg) +{ + s3c2410_pm_run_res(&iomem_resource, fn, arg); +} + +static u32 *s3c2410_pm_countram(struct resource *res, u32 *val) +{ + u32 size = (u32)(res->end - res->start)+1; + + size += CHECK_CHUNKSIZE-1; + size /= CHECK_CHUNKSIZE; + + DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size); + + *val += size * sizeof(u32); + return val; +} + +/* s3c2410_pm_prepare_check + * + * prepare the necessary information for creating the CRCs. This + * must be done before the final save, as it will require memory + * allocating, and thus touching bits of the kernel we do not + * know about. +*/ + +static void s3c2410_pm_check_prepare(void) +{ + crc_size = 0; + + s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size); + + DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size); + + crcs = kmalloc(crc_size+4, GFP_KERNEL); + if (crcs == NULL) + printk(KERN_ERR "Cannot allocated CRC save area\n"); +} + +static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val) +{ + unsigned long addr, left; + + for (addr = res->start; addr < res->end; + addr += CHECK_CHUNKSIZE) { + left = res->end - addr; + + if (left > CHECK_CHUNKSIZE) + left = CHECK_CHUNKSIZE; + + *val = crc32_le(~0, phys_to_virt(addr), left); + val++; + } + + return val; +} + +/* s3c2410_pm_check_store + * + * compute the CRC values for the memory blocks before the final + * sleep. +*/ + +static void s3c2410_pm_check_store(void) +{ + if (crcs != NULL) + s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs); +} + +/* in_region + * + * return TRUE if the area defined by ptr..ptr+size contatins the + * what..what+whatsz +*/ + +static inline int in_region(void *ptr, int size, void *what, size_t whatsz) +{ + if ((what+whatsz) < ptr) + return 0; + + if (what > (ptr+size)) + return 0; + + return 1; +} + +static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val) +{ + void *save_at = phys_to_virt(s3c2410_sleep_save_phys); + unsigned long addr; + unsigned long left; + void *ptr; + u32 calc; + + for (addr = res->start; addr < res->end; + addr += CHECK_CHUNKSIZE) { + left = res->end - addr; + + if (left > CHECK_CHUNKSIZE) + left = CHECK_CHUNKSIZE; + + ptr = phys_to_virt(addr); + + if (in_region(ptr, left, crcs, crc_size)) { + DBG("skipping %08lx, has crc block in\n", addr); + goto skip_check; + } + + if (in_region(ptr, left, save_at, 32*4 )) { + DBG("skipping %08lx, has save block in\n", addr); + goto skip_check; + } + + /* calculate and check the checksum */ + + calc = crc32_le(~0, ptr, left); + if (calc != *val) { + printk(KERN_ERR PFX "Restore CRC error at " + "%08lx (%08x vs %08x)\n", addr, calc, *val); + + DBG("Restore CRC error at %08lx (%08x vs %08x)\n", + addr, calc, *val); + } + + skip_check: + val++; + } + + return val; +} + +/* s3c2410_pm_check_restore + * + * check the CRCs after the restore event and free the memory used + * to hold them +*/ + +static void s3c2410_pm_check_restore(void) +{ + if (crcs != NULL) { + s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs); + kfree(crcs); + crcs = NULL; + } +} + +#else + +#define s3c2410_pm_check_prepare() do { } while(0) +#define s3c2410_pm_check_restore() do { } while(0) +#define s3c2410_pm_check_store() do { } while(0) +#endif + +/* helper functions to save and restore register state */ + +void s3c2410_pm_do_save(struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) { + ptr->val = __raw_readl(ptr->reg); + DBG("saved %p value %08lx\n", ptr->reg, ptr->val); + } +} + +/* s3c2410_pm_do_restore + * + * restore the system from the given list of saved registers + * + * Note, we do not use DBG() in here, as the system may not have + * restore the UARTs state yet +*/ + +void s3c2410_pm_do_restore(struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) { + printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", + ptr->reg, ptr->val, __raw_readl(ptr->reg)); + + __raw_writel(ptr->val, ptr->reg); + } +} + +/* s3c2410_pm_do_restore_core + * + * similar to s3c2410_pm_do_restore_core + * + * WARNING: Do not put any debug in here that may effect memory or use + * peripherals, as things may be changing! +*/ + +static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) { + __raw_writel(ptr->val, ptr->reg); + } +} + +/* s3c2410_pm_show_resume_irqs + * + * print any IRQs asserted at resume time (ie, we woke from) +*/ + +static void s3c2410_pm_show_resume_irqs(int start, unsigned long which, + unsigned long mask) +{ + int i; + + which &= ~mask; + + for (i = 0; i <= 31; i++) { + if ((which) & (1L< + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * +*/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +/* camera irq */ + +static void s3c_irq_demux_cam(unsigned int irq, + struct irq_desc *desc) +{ + unsigned int subsrc, submsk; + struct irq_desc *mydesc; + + /* read the current pending interrupts, and the mask + * for what it is available */ + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + subsrc &= ~submsk; + subsrc >>= 11; + subsrc &= 3; + + if (subsrc != 0) { + if (subsrc & 1) { + mydesc = irq_desc + IRQ_S3C2440_CAM_C; + desc_handle_irq(IRQ_S3C2440_CAM_C, mydesc); + } + if (subsrc & 2) { + mydesc = irq_desc + IRQ_S3C2440_CAM_P; + desc_handle_irq(IRQ_S3C2440_CAM_P, mydesc); + } + } +} + +#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0)) + +static void +s3c_irq_cam_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11); +} + +static void +s3c_irq_cam_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_CAM); +} + +static void +s3c_irq_cam_ack(unsigned int irqno) +{ + s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11); +} + +static struct irq_chip s3c_irq_cam = { + .mask = s3c_irq_cam_mask, + .unmask = s3c_irq_cam_unmask, + .ack = s3c_irq_cam_ack, +}; + +static int s3c244x_irq_add(struct sys_device *sysdev) +{ + unsigned int irqno; + + set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); + set_irq_handler(IRQ_NFCON, handle_level_irq); + set_irq_flags(IRQ_NFCON, IRQF_VALID); + + /* add chained handler for camera */ + + set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); + set_irq_handler(IRQ_CAM, handle_level_irq); + set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); + + for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { + set_irq_chip(irqno, &s3c_irq_cam); + set_irq_handler(irqno, handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } + + return 0; +} + +static struct sysdev_driver s3c2440_irq_driver = { + .add = s3c244x_irq_add, + .suspend = s3c24xx_irq_suspend, + .resume = s3c24xx_irq_resume, +}; + +static int s3c2440_irq_init(void) +{ + return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver); +} + +arch_initcall(s3c2440_irq_init); + +static struct sysdev_driver s3c2442_irq_driver = { + .add = s3c244x_irq_add, + .suspend = s3c24xx_irq_suspend, + .resume = s3c24xx_irq_resume, +}; + + +static int s3c2442_irq_init(void) +{ + return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_irq_driver); +} + +arch_initcall(s3c2442_irq_init); diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c new file mode 100644 index 000000000000..87aace4c8f8c --- /dev/null +++ b/arch/arm/plat-s3c24xx/s3c244x.c @@ -0,0 +1,184 @@ +/* linux/arch/arm/plat-s3c24xx/s3c244x.c + * + * Copyright (c) 2004-2006 Simtec Electronics + * Ben Dooks + * + * Samsung S3C2440 and S3C2442 Mobile CPU support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include "s3c244x.h" +#include +#include +#include +#include + +static struct map_desc s3c244x_iodesc[] __initdata = { + IODESC_ENT(CLKPWR), + IODESC_ENT(TIMER), + IODESC_ENT(WATCHDOG), + IODESC_ENT(LCD), +}; + +/* uart initialisation */ + +void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no); +} + +void __init s3c244x_map_io(struct map_desc *mach_desc, int size) +{ + /* register our io-tables */ + + iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc)); + iotable_init(mach_desc, size); + + /* rename any peripherals used differing from the s3c2410 */ + + s3c_device_i2c.name = "s3c2440-i2c"; + s3c_device_nand.name = "s3c2440-nand"; + s3c_device_usbgadget.name = "s3c2440-usbgadget"; +} + +void __init s3c244x_init_clocks(int xtal) +{ + unsigned long clkdiv; + unsigned long camdiv; + unsigned long hclk, fclk, pclk; + int hdiv = 1; + + /* now we've got our machine bits initialised, work out what + * clocks we've got */ + + fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; + + clkdiv = __raw_readl(S3C2410_CLKDIVN); + camdiv = __raw_readl(S3C2440_CAMDIVN); + + /* work out clock scalings */ + + switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) { + case S3C2440_CLKDIVN_HDIVN_1: + hdiv = 1; + break; + + case S3C2440_CLKDIVN_HDIVN_2: + hdiv = 2; + break; + + case S3C2440_CLKDIVN_HDIVN_4_8: + hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4; + break; + + case S3C2440_CLKDIVN_HDIVN_3_6: + hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3; + break; + } + + hclk = fclk / hdiv; + pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1); + + /* print brief summary of clocks, etc */ + + printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", + print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); + + /* initialise the clocks here, to allow other things like the + * console to use them, and to add new ones after the initialisation + */ + + s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); + s3c2410_baseclk_add(); +} + +#ifdef CONFIG_PM + +static struct sleep_save s3c244x_sleep[] = { + SAVE_ITEM(S3C2440_DSC0), + SAVE_ITEM(S3C2440_DSC1), + SAVE_ITEM(S3C2440_GPJDAT), + SAVE_ITEM(S3C2440_GPJCON), + SAVE_ITEM(S3C2440_GPJUP) +}; + +static int s3c244x_suspend(struct sys_device *dev, pm_message_t state) +{ + s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); + return 0; +} + +static int s3c244x_resume(struct sys_device *dev) +{ + s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); + return 0; +} + +#else +#define s3c244x_suspend NULL +#define s3c244x_resume NULL +#endif + +/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */ + +struct sysdev_class s3c2440_sysclass = { + set_kset_name("s3c2440-core"), + .suspend = s3c244x_suspend, + .resume = s3c244x_resume +}; + +struct sysdev_class s3c2442_sysclass = { + set_kset_name("s3c2442-core"), + .suspend = s3c244x_suspend, + .resume = s3c244x_resume +}; + +/* need to register class before we actually register the device, and + * we also need to ensure that it has been initialised before any of the + * drivers even try to use it (even if not on an s3c2440 based system) + * as a driver which may support both 2410 and 2440 may try and use it. +*/ + +static int __init s3c2440_core_init(void) +{ + return sysdev_class_register(&s3c2440_sysclass); +} + +core_initcall(s3c2440_core_init); + +static int __init s3c2442_core_init(void) +{ + return sysdev_class_register(&s3c2442_sysclass); +} + +core_initcall(s3c2442_core_init); diff --git a/arch/arm/plat-s3c24xx/s3c244x.h b/arch/arm/plat-s3c24xx/s3c244x.h new file mode 100644 index 000000000000..f8ed17676a35 --- /dev/null +++ b/arch/arm/plat-s3c24xx/s3c244x.h @@ -0,0 +1,25 @@ +/* linux/arch/arm/plat-s3c24xx/s3c244x.h + * + * Copyright (c) 2004-2005 Simtec Electronics + * Ben Dooks + * + * Header file for S3C2440 and S3C2442 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) + +extern void s3c244x_map_io(struct map_desc *mach_desc, int size); + +extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +extern void s3c244x_init_clocks(int xtal); + +#else +#define s3c244x_init_clocks NULL +#define s3c244x_init_uarts NULL +#define s3c244x_map_io NULL +#endif diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S new file mode 100644 index 000000000000..2018c2e1dcc5 --- /dev/null +++ b/arch/arm/plat-s3c24xx/sleep.S @@ -0,0 +1,159 @@ +/* linux/arch/arm/mach-s3c2410/sleep.S + * + * Copyright (c) 2004 Simtec Electronics + * Ben Dooks + * + * S3C2410 Power Manager (Suspend-To-RAM) support + * + * Based on PXA/SA1100 sleep code by: + * Nicolas Pitre, (c) 2002 Monta Vista Software Inc + * Cliff Brake, (c) 2001 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include +#include + +#include +#include +#include +#include + +/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not + * reset the UART configuration, only enable if you really need this! +*/ +//#define CONFIG_DEBUG_RESUME + + .text + + /* s3c2410_cpu_save + * + * save enough of the CPU state to allow us to re-start + * pm.c code. as we store items like the sp/lr, we will + * end up returning from this function when the cpu resumes + * so the return value is set to mark this. + * + * This arangement means we avoid having to flush the cache + * from this code. + * + * entry: + * r0 = pointer to save block + * + * exit: + * r0 = 0 => we stored everything + * 1 => resumed from sleep + */ + +ENTRY(s3c2410_cpu_save) + stmfd sp!, { r4 - r12, lr } + + @@ store co-processor registers + + mrc p15, 0, r4, c15, c1, 0 @ CP access register + mrc p15, 0, r5, c13, c0, 0 @ PID + mrc p15, 0, r6, c3, c0, 0 @ Domain ID + mrc p15, 0, r7, c2, c0, 0 @ translation table base address + mrc p15, 0, r8, c1, c0, 0 @ control register + + stmia r0, { r4 - r13 } + + mov r0, #0 + ldmfd sp, { r4 - r12, pc } + + @@ return to the caller, after having the MMU + @@ turned on, this restores the last bits from the + @@ stack +resume_with_mmu: + mov r0, #1 + ldmfd sp!, { r4 - r12, pc } + + .ltorg + + @@ the next bits sit in the .data segment, even though they + @@ happen to be code... the s3c2410_sleep_save_phys needs to be + @@ accessed by the resume code before it can restore the MMU. + @@ This means that the variable has to be close enough for the + @@ code to read it... since the .text segment needs to be RO, + @@ the data segment can be the only place to put this code. + + .data + + .global s3c2410_sleep_save_phys +s3c2410_sleep_save_phys: + .word 0 + + /* s3c2410_cpu_resume + * + * resume code entry for bootloader to call + * + * we must put this code here in the data segment as we have no + * other way of restoring the stack pointer after sleep, and we + * must not write to the code segment (code is read-only) + */ + +ENTRY(s3c2410_cpu_resume) + mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE + msr cpsr_c, r0 + + @@ load UART to allow us to print the two characters for + @@ resume debug + + mov r2, #S3C24XX_PA_UART & 0xff000000 + orr r2, r2, #S3C24XX_PA_UART & 0xff000 + +#if 0 + /* SMDK2440 LED set */ + mov r14, #S3C24XX_PA_GPIO + ldr r12, [ r14, #0x54 ] + bic r12, r12, #3<<4 + orr r12, r12, #1<<7 + str r12, [ r14, #0x54 ] +#endif + +#ifdef CONFIG_DEBUG_RESUME + mov r3, #'L' + strb r3, [ r2, #S3C2410_UTXH ] +1001: + ldrb r14, [ r3, #S3C2410_UTRSTAT ] + tst r14, #S3C2410_UTRSTAT_TXE + beq 1001b +#endif /* CONFIG_DEBUG_RESUME */ + + mov r1, #0 + mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs + mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches + + ldr r0, s3c2410_sleep_save_phys @ address of restore block + ldmia r0, { r4 - r13 } + + mcr p15, 0, r4, c15, c1, 0 @ CP access register + mcr p15, 0, r5, c13, c0, 0 @ PID + mcr p15, 0, r6, c3, c0, 0 @ Domain ID + mcr p15, 0, r7, c2, c0, 0 @ translation table base + +#ifdef CONFIG_DEBUG_RESUME + mov r3, #'R' + strb r3, [ r2, #S3C2410_UTXH ] +#endif + + ldr r2, =resume_with_mmu + mcr p15, 0, r8, c1, c0, 0 @ turn on MMU, etc + nop @ second-to-last before mmu + mov pc, r2 @ go back to virtual address + + .ltorg diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c new file mode 100644 index 000000000000..c523d1c9cce5 --- /dev/null +++ b/arch/arm/plat-s3c24xx/time.c @@ -0,0 +1,262 @@ +/* linux/arch/arm/plat-s3c24xx/time.c + * + * Copyright (C) 2003-2005 Simtec Electronics + * Ben Dooks, + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +static unsigned long timer_startval; +static unsigned long timer_usec_ticks; + +#define TIMER_USEC_SHIFT 16 + +/* we use the shifted arithmetic to work out the ratio of timer ticks + * to usecs, as often the peripheral clock is not a nice even multiple + * of 1MHz. + * + * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok + * for the current HZ value of 200 without producing overflows. + * + * Original patch by Dimitry Andric, updated by Ben Dooks +*/ + + +/* timer_mask_usec_ticks + * + * given a clock and divisor, make the value to pass into timer_ticks_to_usec + * to scale the ticks into usecs +*/ + +static inline unsigned long +timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk) +{ + unsigned long den = pclk / 1000; + + return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den; +} + +/* timer_ticks_to_usec + * + * convert timer ticks to usec. +*/ + +static inline unsigned long timer_ticks_to_usec(unsigned long ticks) +{ + unsigned long res; + + res = ticks * timer_usec_ticks; + res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */ + + return res >> TIMER_USEC_SHIFT; +} + +/*** + * Returns microsecond since last clock interrupt. Note that interrupts + * will have been disabled by do_gettimeoffset() + * IRQs are disabled before entering here from do_gettimeofday() + */ + +#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) + +static unsigned long s3c2410_gettimeoffset (void) +{ + unsigned long tdone; + unsigned long irqpend; + unsigned long tval; + + /* work out how many ticks have gone since last timer interrupt */ + + tval = __raw_readl(S3C2410_TCNTO(4)); + tdone = timer_startval - tval; + + /* check to see if there is an interrupt pending */ + + irqpend = __raw_readl(S3C2410_SRCPND); + if (irqpend & SRCPND_TIMER4) { + /* re-read the timer, and try and fix up for the missed + * interrupt. Note, the interrupt may go off before the + * timer has re-loaded from wrapping. + */ + + tval = __raw_readl(S3C2410_TCNTO(4)); + tdone = timer_startval - tval; + + if (tval != 0) + tdone += timer_startval; + } + + return timer_ticks_to_usec(tdone); +} + + +/* + * IRQ handler for the timer + */ +static irqreturn_t +s3c2410_timer_interrupt(int irq, void *dev_id) +{ + write_seqlock(&xtime_lock); + timer_tick(); + write_sequnlock(&xtime_lock); + return IRQ_HANDLED; +} + +static struct irqaction s3c2410_timer_irq = { + .name = "S3C2410 Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = s3c2410_timer_interrupt, +}; + +#define use_tclk1_12() ( \ + machine_is_bast() || \ + machine_is_vr1000() || \ + machine_is_anubis() || \ + machine_is_osiris() ) + +/* + * Set up timer interrupt, and return the current time in seconds. + * + * Currently we only use timer4, as it is the only timer which has no + * other function that can be exploited externally + */ +static void s3c2410_timer_setup (void) +{ + unsigned long tcon; + unsigned long tcnt; + unsigned long tcfg1; + unsigned long tcfg0; + + tcnt = 0xffff; /* default value for tcnt */ + + /* read the current timer configuration bits */ + + tcon = __raw_readl(S3C2410_TCON); + tcfg1 = __raw_readl(S3C2410_TCFG1); + tcfg0 = __raw_readl(S3C2410_TCFG0); + + /* configure the system for whichever machine is in use */ + + if (use_tclk1_12()) { + /* timer is at 12MHz, scaler is 1 */ + timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); + tcnt = 12000000 / HZ; + + tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; + tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1; + } else { + unsigned long pclk; + struct clk *clk; + + /* for the h1940 (and others), we use the pclk from the core + * to generate the timer values. since values around 50 to + * 70MHz are not values we can directly generate the timer + * value from, we need to pre-scale and divide before using it. + * + * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz + * (8.45 ticks per usec) + */ + + /* this is used as default if no other timer can be found */ + + clk = clk_get(NULL, "timers"); + if (IS_ERR(clk)) + panic("failed to get clock for system timer"); + + clk_enable(clk); + + pclk = clk_get_rate(clk); + + /* configure clock tick */ + + timer_usec_ticks = timer_mask_usec_ticks(6, pclk); + + tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; + tcfg1 |= S3C2410_TCFG1_MUX4_DIV2; + + tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; + tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT; + + tcnt = (pclk / 6) / HZ; + } + + /* timers reload after counting zero, so reduce the count by 1 */ + + tcnt--; + + printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n", + tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks); + + /* check to see if timer is within 16bit range... */ + if (tcnt > 0xffff) { + panic("setup_timer: HZ is too small, cannot configure timer!"); + return; + } + + __raw_writel(tcfg1, S3C2410_TCFG1); + __raw_writel(tcfg0, S3C2410_TCFG0); + + timer_startval = tcnt; + __raw_writel(tcnt, S3C2410_TCNTB(4)); + + /* ensure timer is stopped... */ + + tcon &= ~(7<<20); + tcon |= S3C2410_TCON_T4RELOAD; + tcon |= S3C2410_TCON_T4MANUALUPD; + + __raw_writel(tcon, S3C2410_TCON); + __raw_writel(tcnt, S3C2410_TCNTB(4)); + __raw_writel(tcnt, S3C2410_TCMPB(4)); + + /* start the timer running */ + tcon |= S3C2410_TCON_T4START; + tcon &= ~S3C2410_TCON_T4MANUALUPD; + __raw_writel(tcon, S3C2410_TCON); +} + +static void __init s3c2410_timer_init (void) +{ + s3c2410_timer_setup(); + setup_irq(IRQ_TIMER4, &s3c2410_timer_irq); +} + +struct sys_timer s3c24xx_timer = { + .init = s3c2410_timer_init, + .offset = s3c2410_gettimeoffset, + .resume = s3c2410_timer_setup +}; diff --git a/include/asm-arm/plat-s3c24xx/clock.h b/include/asm-arm/plat-s3c24xx/clock.h new file mode 100644 index 000000000000..f6135dbb9fa9 --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/clock.h @@ -0,0 +1,63 @@ +/* linux/include/asm-arm/plat-s3c24xx/clock.h + * linux/arch/arm/mach-s3c2410/clock.h + * + * Copyright (c) 2004-2005 Simtec Electronics + * http://www.simtec.co.uk/products/SWLINUX/ + * Written by Ben Dooks, + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct clk { + struct list_head list; + struct module *owner; + struct clk *parent; + const char *name; + int id; + int usage; + unsigned long rate; + unsigned long ctrlbit; + + int (*enable)(struct clk *, int enable); + int (*set_rate)(struct clk *c, unsigned long rate); + unsigned long (*get_rate)(struct clk *c); + unsigned long (*round_rate)(struct clk *c, unsigned long rate); + int (*set_parent)(struct clk *c, struct clk *parent); +}; + +/* other clocks which may be registered by board support */ + +extern struct clk s3c24xx_dclk0; +extern struct clk s3c24xx_dclk1; +extern struct clk s3c24xx_clkout0; +extern struct clk s3c24xx_clkout1; +extern struct clk s3c24xx_uclk; + +extern struct clk clk_usb_bus; + +/* core clock support */ + +extern struct clk clk_f; +extern struct clk clk_h; +extern struct clk clk_p; +extern struct clk clk_mpll; +extern struct clk clk_upll; +extern struct clk clk_xtal; + +/* exports for arch/arm/mach-s3c2410 + * + * Please DO NOT use these outside of arch/arm/mach-s3c2410 +*/ + +extern struct mutex clocks_mutex; + +extern int s3c2410_clkcon_enable(struct clk *clk, int enable); + +extern int s3c24xx_register_clock(struct clk *clk); + +extern int s3c24xx_setup_clocks(unsigned long xtal, + unsigned long fclk, + unsigned long hclk, + unsigned long pclk); diff --git a/include/asm-arm/plat-s3c24xx/common-smdk.h b/include/asm-arm/plat-s3c24xx/common-smdk.h new file mode 100644 index 000000000000..58d9094c935c --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/common-smdk.h @@ -0,0 +1,15 @@ +/* linux/include/asm-arm/plat-s3c24xx/common-smdk.h + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * Common code for SMDK2410 and SMDK2440 boards + * + * http://www.fluff.org/ben/smdk2440/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +extern void smdk_machine_init(void); diff --git a/include/asm-arm/plat-s3c24xx/cpu.h b/include/asm-arm/plat-s3c24xx/cpu.h new file mode 100644 index 000000000000..8181b22532bd --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/cpu.h @@ -0,0 +1,69 @@ +/* linux/include/asm-arm/plat-s3c24xx/cpu.h + * + * Copyright (c) 2004-2005 Simtec Electronics + * Ben Dooks + * + * Header file for S3C24XX CPU support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* todo - fix when rmk changes iodescs to use `void __iomem *` */ + +#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } + +#ifndef MHZ +#define MHZ (1000*1000) +#endif + +#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000) + +/* forward declaration */ +struct s3c24xx_uart_resources; +struct platform_device; +struct s3c2410_uartcfg; +struct map_desc; + +/* core initialisation functions */ + +extern void s3c24xx_init_irq(void); + +extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); + +extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +extern void s3c24xx_init_clocks(int xtal); + +extern void s3c24xx_init_uartdevs(char *name, + struct s3c24xx_uart_resources *res, + struct s3c2410_uartcfg *cfg, int no); + +/* the board structure is used at first initialsation time + * to get info such as the devices to register for this + * board. This is done because platfrom_add_devices() cannot + * be called from the map_io entry. +*/ + +struct s3c24xx_board { + struct platform_device **devices; + unsigned int devices_count; + + struct clk **clocks; + unsigned int clocks_count; +}; + +extern void s3c24xx_set_board(struct s3c24xx_board *board); + +/* timer for 2410/2440 */ + +struct sys_timer; +extern struct sys_timer s3c24xx_timer; + +/* system device classes */ + +extern struct sysdev_class s3c2410_sysclass; +extern struct sysdev_class s3c2412_sysclass; +extern struct sysdev_class s3c2440_sysclass; +extern struct sysdev_class s3c2442_sysclass; diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h new file mode 100644 index 000000000000..dddf485fc067 --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/devs.h @@ -0,0 +1,51 @@ +/* linux/include/asm-arm/plat-s3c24xx/devs.h + * + * Copyright (c) 2004 Simtec Electronics + * Ben Dooks + * + * Header file for s3c2410 standard platform devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +#include + +struct s3c24xx_uart_resources { + struct resource *resources; + unsigned long nr_resources; +}; + +extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; + +extern struct platform_device *s3c24xx_uart_devs[]; +extern struct platform_device *s3c24xx_uart_src[]; + +extern struct platform_device s3c_device_usb; +extern struct platform_device s3c_device_lcd; +extern struct platform_device s3c_device_wdt; +extern struct platform_device s3c_device_i2c; +extern struct platform_device s3c_device_iis; +extern struct platform_device s3c_device_rtc; +extern struct platform_device s3c_device_adc; +extern struct platform_device s3c_device_sdi; + +extern struct platform_device s3c_device_spi0; +extern struct platform_device s3c_device_spi1; + +extern struct platform_device s3c_device_nand; + +extern struct platform_device s3c_device_timer0; +extern struct platform_device s3c_device_timer1; +extern struct platform_device s3c_device_timer2; +extern struct platform_device s3c_device_timer3; + +extern struct platform_device s3c_device_usbgadget; + +/* s3c2440 specific devices */ + +#ifdef CONFIG_CPU_S3C2440 + +extern struct platform_device s3c_device_camif; + +#endif diff --git a/include/asm-arm/plat-s3c24xx/dma.h b/include/asm-arm/plat-s3c24xx/dma.h new file mode 100644 index 000000000000..421b567fa019 --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/dma.h @@ -0,0 +1,45 @@ +/* linux/include/asm-arm/plat-s3c24xx/dma.h + * + * Copyright (C) 2006 Simtec Electronics + * Ben Dooks + * + * Samsung S3C24XX DMA support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +extern struct sysdev_class dma_sysclass; +extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; + +#define DMA_CH_VALID (1<<31) + +struct s3c24xx_dma_addr { + unsigned long from; + unsigned long to; +}; + +/* struct s3c24xx_dma_map + * + * this holds the mapping information for the channel selected + * to be connected to the specified device +*/ + +struct s3c24xx_dma_map { + const char *name; + struct s3c24xx_dma_addr hw_addr; + + unsigned long channels[S3C2410_DMA_CHANNELS]; +}; + +struct s3c24xx_dma_selection { + struct s3c24xx_dma_map *map; + unsigned long map_size; + unsigned long dcon_mask; + + void (*select)(struct s3c2410_dma_chan *chan, + struct s3c24xx_dma_map *map); +}; + +extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel); diff --git a/include/asm-arm/plat-s3c24xx/irq.h b/include/asm-arm/plat-s3c24xx/irq.h new file mode 100644 index 000000000000..8af6d9579b31 --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/irq.h @@ -0,0 +1,107 @@ +/* linux/include/asm-arm/plat-s3c24xx/irq.h + * + * Copyright (c) 2004-2005 Simtec Electronics + * Ben Dooks + * + * Header file for S3C24XX CPU IRQ support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define irqdbf(x...) +#define irqdbf2(x...) + +#define EXTINT_OFF (IRQ_EINT4 - 4) + +extern struct irq_chip s3c_irq_level_chip; + +static inline void +s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, + int subcheck) +{ + unsigned long mask; + unsigned long submask; + + submask = __raw_readl(S3C2410_INTSUBMSK); + mask = __raw_readl(S3C2410_INTMSK); + + submask |= (1UL << (irqno - IRQ_S3CUART_RX0)); + + /* check to see if we need to mask the parent IRQ */ + + if ((submask & subcheck) == subcheck) { + __raw_writel(mask | parentbit, S3C2410_INTMSK); + } + + /* write back masks */ + __raw_writel(submask, S3C2410_INTSUBMSK); + +} + +static inline void +s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit) +{ + unsigned long mask; + unsigned long submask; + + submask = __raw_readl(S3C2410_INTSUBMSK); + mask = __raw_readl(S3C2410_INTMSK); + + submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0)); + mask &= ~parentbit; + + /* write back masks */ + __raw_writel(submask, S3C2410_INTSUBMSK); + __raw_writel(mask, S3C2410_INTMSK); +} + + +static inline void +s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group) +{ + unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); + + s3c_irqsub_mask(irqno, parentmask, group); + + __raw_writel(bit, S3C2410_SUBSRCPND); + + /* only ack parent if we've got all the irqs (seems we must + * ack, all and hope that the irq system retriggers ok when + * the interrupt goes off again) + */ + + if (1) { + __raw_writel(parentmask, S3C2410_SRCPND); + __raw_writel(parentmask, S3C2410_INTPND); + } +} + +static inline void +s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group) +{ + unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); + + __raw_writel(bit, S3C2410_SUBSRCPND); + + /* only ack parent if we've got all the irqs (seems we must + * ack, all and hope that the irq system retriggers ok when + * the interrupt goes off again) + */ + + if (1) { + __raw_writel(parentmask, S3C2410_SRCPND); + __raw_writel(parentmask, S3C2410_INTPND); + } +} + +/* exported for use in arch/arm/mach-s3c2410 */ + +#ifdef CONFIG_PM +extern int s3c_irq_wake(unsigned int irqno, unsigned int state); +#else +#define s3c_irq_wake NULL +#endif + +extern int s3c_irqext_type(unsigned int irq, unsigned int type); diff --git a/include/asm-arm/plat-s3c24xx/pm.h b/include/asm-arm/plat-s3c24xx/pm.h new file mode 100644 index 000000000000..cc623667e48a --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/pm.h @@ -0,0 +1,73 @@ +/* linux/include/asm-arm/plat-s3c24xx/pm.h + * + * Copyright (c) 2004 Simtec Electronics + * Written by Ben Dooks, + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* s3c2410_pm_init + * + * called from board at initialisation time to setup the power + * management +*/ + +#ifdef CONFIG_PM + +extern __init int s3c2410_pm_init(void); + +#else + +static inline int s3c2410_pm_init(void) +{ + return 0; +} +#endif + +/* configuration for the IRQ mask over sleep */ +extern unsigned long s3c_irqwake_intmask; +extern unsigned long s3c_irqwake_eintmask; + +/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */ +extern unsigned long s3c_irqwake_intallow; +extern unsigned long s3c_irqwake_eintallow; + +/* per-cpu sleep functions */ + +extern void (*pm_cpu_prep)(void); +extern void (*pm_cpu_sleep)(void); + +/* Flags for PM Control */ + +extern unsigned long s3c_pm_flags; + +/* from sleep.S */ + +extern int s3c2410_cpu_save(unsigned long *saveblk); +extern void s3c2410_cpu_suspend(void); +extern void s3c2410_cpu_resume(void); + +extern unsigned long s3c2410_sleep_save_phys; + +/* sleep save info */ + +struct sleep_save { + void __iomem *reg; + unsigned long val; +}; + +#define SAVE_ITEM(x) \ + { .reg = (x) } + +extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count); +extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count); + +#ifdef CONFIG_PM +extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state); +extern int s3c24xx_irq_resume(struct sys_device *dev); +#else +#define s3c24xx_irq_suspend NULL +#define s3c24xx_irq_resume NULL +#endif diff --git a/include/asm-arm/plat-s3c24xx/s3c2400.h b/include/asm-arm/plat-s3c24xx/s3c2400.h new file mode 100644 index 000000000000..3a5a16821af8 --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/s3c2400.h @@ -0,0 +1,31 @@ +/* linux/include/asm-arm/plat-s3c24xx/s3c2400.h + * + * Copyright (c) 2004 Simtec Electronics + * Ben Dooks + * + * Header file for S3C2400 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Modifications: + * 09-Fev-2006 LCVR First version, based on s3c2410.h +*/ + +#ifdef CONFIG_CPU_S3C2400 + +extern int s3c2400_init(void); + +extern void s3c2400_map_io(struct map_desc *mach_desc, int size); + +extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +extern void s3c2400_init_clocks(int xtal); + +#else +#define s3c2400_init_clocks NULL +#define s3c2400_init_uarts NULL +#define s3c2400_map_io NULL +#define s3c2400_init NULL +#endif diff --git a/include/asm-arm/plat-s3c24xx/s3c2410.h b/include/asm-arm/plat-s3c24xx/s3c2410.h new file mode 100644 index 000000000000..36de0b835873 --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/s3c2410.h @@ -0,0 +1,31 @@ +/* linux/include/asm-arm/plat-s3c24xx/s3c2410.h + * + * Copyright (c) 2004 Simtec Electronics + * Ben Dooks + * + * Header file for s3c2410 machine directory + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#ifdef CONFIG_CPU_S3C2410 + +extern int s3c2410_init(void); + +extern void s3c2410_map_io(struct map_desc *mach_desc, int size); + +extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +extern void s3c2410_init_clocks(int xtal); + +extern int s3c2410_baseclk_add(void); + +#else +#define s3c2410_init_clocks NULL +#define s3c2410_init_uarts NULL +#define s3c2410_map_io NULL +#define s3c2410_init NULL +#endif diff --git a/include/asm-arm/plat-s3c24xx/s3c2412.h b/include/asm-arm/plat-s3c24xx/s3c2412.h new file mode 100644 index 000000000000..3ec97685e781 --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/s3c2412.h @@ -0,0 +1,29 @@ +/* linux/include/asm-arm/plat-s3c24xx/s3c2412.h + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * Header file for s3c2412 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifdef CONFIG_CPU_S3C2412 + +extern int s3c2412_init(void); + +extern void s3c2412_map_io(struct map_desc *mach_desc, int size); + +extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +extern void s3c2412_init_clocks(int xtal); + +extern int s3c2412_baseclk_add(void); +#else +#define s3c2412_init_clocks NULL +#define s3c2412_init_uarts NULL +#define s3c2412_map_io NULL +#define s3c2412_init NULL +#endif diff --git a/include/asm-arm/plat-s3c24xx/s3c2440.h b/include/asm-arm/plat-s3c24xx/s3c2440.h new file mode 100644 index 000000000000..107853bf9481 --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/s3c2440.h @@ -0,0 +1,17 @@ +/* linux/include/asm-arm/plat-s3c24xx/s3c2440.h + * + * Copyright (c) 2004-2005 Simtec Electronics + * Ben Dooks + * + * Header file for s3c2440 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifdef CONFIG_CPU_S3C2440 +extern int s3c2440_init(void); +#else +#define s3c2440_init NULL +#endif diff --git a/include/asm-arm/plat-s3c24xx/s3c2442.h b/include/asm-arm/plat-s3c24xx/s3c2442.h new file mode 100644 index 000000000000..451a23a2092a --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/s3c2442.h @@ -0,0 +1,17 @@ +/* linux/include/asm-arm/plat-s3c24xx/s3c2442.h + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * Header file for s3c2442 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifdef CONFIG_CPU_S3C2442 +extern int s3c2442_init(void); +#else +#define s3c2442_init NULL +#endif -- cgit v1.2.3 From e4d06e39530559513c7e335ef7ca4675f8146220 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 16 Feb 2007 12:12:31 +0100 Subject: [ARM] 4198/2: S3C2443: arch/arm/mach-s3c2443 and related support Add arch/arm/mach-s3c2443 for support of the Samsung S3C2443 SoC This patch adds the core CPU support, clock framework, times and initial IRQ support, as well as adding the directory into the build tree. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/Kconfig | 3 +- arch/arm/Makefile | 1 + arch/arm/mach-s3c2443/Kconfig | 18 + arch/arm/mach-s3c2443/Makefile | 16 + arch/arm/mach-s3c2443/clock.c | 1007 ++++++++++++++++++++++++++++++++ arch/arm/mach-s3c2443/irq.c | 130 +++++ arch/arm/mach-s3c2443/s3c2443.c | 87 +++ arch/arm/plat-s3c24xx/cpu.c | 11 + arch/arm/plat-s3c24xx/s3c244x.c | 2 +- include/asm-arm/plat-s3c24xx/cpu.h | 1 + include/asm-arm/plat-s3c24xx/s3c2443.h | 32 + 11 files changed, 1306 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-s3c2443/Kconfig create mode 100644 arch/arm/mach-s3c2443/Makefile create mode 100644 arch/arm/mach-s3c2443/clock.c create mode 100644 arch/arm/mach-s3c2443/irq.c create mode 100644 arch/arm/mach-s3c2443/s3c2443.c create mode 100644 include/asm-arm/plat-s3c24xx/s3c2443.h (limited to 'arch/arm/Makefile') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 51ee13e7c74c..0f711c4394a9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -303,7 +303,7 @@ config ARCH_SA1100 Support for StrongARM 11x0 based boards. config ARCH_S3C2410 - bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442" + bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443" help Samsung S3C2410X CPU based systems, such as the Simtec Electronics BAST (), the IPAQ 1940 or @@ -371,6 +371,7 @@ source "arch/arm/mach-s3c2410/Kconfig" source "arch/arm/mach-s3c2412/Kconfig" source "arch/arm/mach-s3c2440/Kconfig" source "arch/arm/mach-s3c2442/Kconfig" +source "arch/arm/mach-s3c2443/Kconfig" endif source "arch/arm/mach-lh7a40x/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 2df1ea0a0c2d..93e474726725 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -165,6 +165,7 @@ core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2400/ core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2412/ core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2440/ core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2442/ +core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2443/ core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/ core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ) core-$(CONFIG_VFP) += arch/arm/vfp/ diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig new file mode 100644 index 000000000000..0d8d7bf9a96b --- /dev/null +++ b/arch/arm/mach-s3c2443/Kconfig @@ -0,0 +1,18 @@ +# arch/arm/mach-s3c2443/Kconfig +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + +config CPU_S3C2443 + bool + depends on ARCH_S3C2410 + select S3C2443_PM if PM + select S3C2443_DMA if S3C2410_DMA + help + Support for the S3C2443 SoC from the S3C24XX line + +menu "S3C2443 Machines" + +endmenu + diff --git a/arch/arm/mach-s3c2443/Makefile b/arch/arm/mach-s3c2443/Makefile new file mode 100644 index 000000000000..397475affbe1 --- /dev/null +++ b/arch/arm/mach-s3c2443/Makefile @@ -0,0 +1,16 @@ +# arch/arm/mach-s3c2443/Makefile +# +# Copyright 2007 Simtec Electronics +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +obj-$(CONFIG_CPU_S3C2443) += s3c2443.o +obj-$(CONFIG_CPU_S3C2443) += irq.o +obj-$(CONFIG_CPU_S3C2443) += clock.o + +# Machine support diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c new file mode 100644 index 000000000000..dd2272fb1131 --- /dev/null +++ b/arch/arm/mach-s3c2443/clock.c @@ -0,0 +1,1007 @@ +/* linux/arch/arm/mach-s3c2443/clock.c + * + * Copyright (c) 2007 Simtec Electronics + * Ben Dooks + * + * S3C2443 Clock control support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include + +#include +#include +#include + +/* We currently have to assume that the system is running + * from the XTPll input, and that all ***REFCLKs are being + * fed from it, as we cannot read the state of OM[4] from + * software. + * + * It would be possible for each board initialisation to + * set the correct muxing at initialisation +*/ + +static int s3c2443_clkcon_enable_h(struct clk *clk, int enable) +{ + unsigned int clocks = clk->ctrlbit; + unsigned long clkcon; + + clkcon = __raw_readl(S3C2443_HCLKCON); + + if (enable) + clkcon |= clocks; + else + clkcon &= ~clocks; + + __raw_writel(clkcon, S3C2443_HCLKCON); + + return 0; +} + +static int s3c2443_clkcon_enable_p(struct clk *clk, int enable) +{ + unsigned int clocks = clk->ctrlbit; + unsigned long clkcon; + + clkcon = __raw_readl(S3C2443_PCLKCON); + + if (enable) + clkcon |= clocks; + else + clkcon &= ~clocks; + + __raw_writel(clkcon, S3C2443_HCLKCON); + + return 0; +} + +static int s3c2443_clkcon_enable_s(struct clk *clk, int enable) +{ + unsigned int clocks = clk->ctrlbit; + unsigned long clkcon; + + clkcon = __raw_readl(S3C2443_SCLKCON); + + if (enable) + clkcon |= clocks; + else + clkcon &= ~clocks; + + __raw_writel(clkcon, S3C2443_SCLKCON); + + return 0; +} + +static unsigned long s3c2443_roundrate_clksrc(struct clk *clk, + unsigned long rate, + unsigned int max) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + int div; + + if (rate > parent_rate) + return parent_rate; + + /* note, we remove the +/- 1 calculations as they cancel out */ + + div = (rate / parent_rate); + + if (div < 1) + div = 1; + else if (div > max) + div = max; + + return parent_rate / div; +} + +static unsigned long s3c2443_roundrate_clksrc4(struct clk *clk, + unsigned long rate) +{ + return s3c2443_roundrate_clksrc(clk, rate, 4); +} + +static unsigned long s3c2443_roundrate_clksrc16(struct clk *clk, + unsigned long rate) +{ + return s3c2443_roundrate_clksrc(clk, rate, 16); +} + +static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk, + unsigned long rate) +{ + return s3c2443_roundrate_clksrc(clk, rate, 256); +} + +/* clock selections */ + +/* CPU EXTCLK input */ +static struct clk clk_ext = { + .name = "ext", + .id = -1, +}; + +static struct clk clk_mpllref = { + .name = "mpllref", + .parent = &clk_xtal, + .id = -1, +}; + +#if 0 +static struct clk clk_mpll = { + .name = "mpll", + .parent = &clk_mpllref, + .id = -1, +}; +#endif + +static struct clk clk_epllref; + +static struct clk clk_epll = { + .name = "epll", + .parent = &clk_epllref, + .id = -1, +}; + +static struct clk clk_i2s_ext = { + .name = "i2s-ext", + .id = -1, +}; + +static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent) +{ + unsigned long clksrc = __raw_readl(S3C2443_CLKSRC); + + clksrc &= ~S3C2443_CLKSRC_EPLLREF_MASK; + + if (parent == &clk_xtal) + clksrc |= S3C2443_CLKSRC_EPLLREF_XTAL; + else if (parent == &clk_ext) + clksrc |= S3C2443_CLKSRC_EPLLREF_EXTCLK; + else if (parent != &clk_mpllref) + return -EINVAL; + + __raw_writel(clksrc, S3C2443_CLKSRC); + clk->parent = parent; + + return 0; +} + +static struct clk clk_epllref = { + .name = "epllref", + .id = -1, + .set_parent = s3c2443_setparent_epllref, +}; + +static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2443_CLKDIV0); + + div &= S3C2443_CLKDIV0_EXTDIV_MASK; + div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */ + + return parent_rate / (div + 1); +} + +static struct clk clk_mdivclk = { + .name = "mdivclk", + .parent = &clk_mpllref, + .id = -1, + .get_rate = s3c2443_getrate_mdivclk, +}; + + +static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent) +{ + unsigned long clksrc = __raw_readl(S3C2443_CLKSRC); + + clksrc &= ~(S3C2443_CLKSRC_MSYSCLK_MPLL | + S3C2443_CLKSRC_EXTCLK_DIV); + + if (parent == &clk_mpll) + clksrc |= S3C2443_CLKSRC_MSYSCLK_MPLL; + else if (parent == &clk_mdivclk) + clksrc |= S3C2443_CLKSRC_EXTCLK_DIV; + else if (parent != &clk_mpllref) + return -EINVAL; + + __raw_writel(clksrc, S3C2443_CLKSRC); + clk->parent = parent; + + return 0; +} + +static struct clk clk_msysclk = { + .name = "msysclk", + .parent = &clk_xtal, + .id = -1, + .set_parent = s3c2443_setparent_msysclk, +}; + + +/* esysclk + * + * this is sourced from either the EPLL or the EPLLref clock +*/ + +static int s3c2443_setparent_esysclk(struct clk *clk, struct clk *parent) +{ + unsigned long clksrc = __raw_readl(S3C2443_CLKSRC); + + if (parent == &clk_epll) + clksrc |= S3C2443_CLKSRC_ESYSCLK_EPLL; + else if (parent == &clk_epllref) + clksrc &= ~S3C2443_CLKSRC_ESYSCLK_EPLL; + else + return -EINVAL; + + __raw_writel(clksrc, S3C2443_CLKSRC); + clk->parent = parent; + + return 0; +} + +static struct clk clk_esysclk = { + .name = "esysclk", + .parent = &clk_epll, + .id = -1, + .set_parent = s3c2443_setparent_esysclk, +}; + +/* uartclk + * + * UART baud-rate clock sourced from esysclk via a divisor +*/ + +static unsigned long s3c2443_getrate_uart(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2443_CLKDIV1); + + div &= S3C2443_CLKDIV1_UARTDIV_MASK; + div >>= S3C2443_CLKDIV1_UARTDIV_SHIFT; + + return parent_rate / (div + 1); +} + + +static int s3c2443_setrate_uart(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1); + + rate = s3c2443_roundrate_clksrc16(clk, rate); + rate = parent_rate / rate; + + clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK; + clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT; + + __raw_writel(clkdivn, S3C2443_CLKDIV1); + return 0; +} + +static struct clk clk_uart = { + .name = "uartclk", + .id = -1, + .parent = &clk_esysclk, + .get_rate = s3c2443_getrate_uart, + .set_rate = s3c2443_setrate_uart, + .round_rate = s3c2443_roundrate_clksrc16, +}; + +/* hsspi + * + * high-speed spi clock, sourced from esysclk +*/ + +static unsigned long s3c2443_getrate_hsspi(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2443_CLKDIV1); + + div &= S3C2443_CLKDIV1_HSSPIDIV_MASK; + div >>= S3C2443_CLKDIV1_HSSPIDIV_SHIFT; + + return parent_rate / (div + 1); +} + + +static int s3c2443_setrate_hsspi(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1); + + rate = s3c2443_roundrate_clksrc4(clk, rate); + rate = parent_rate / rate; + + clkdivn &= ~S3C2443_CLKDIV1_HSSPIDIV_MASK; + clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSSPIDIV_SHIFT; + + __raw_writel(clkdivn, S3C2443_CLKDIV1); + return 0; +} + +static struct clk clk_hsspi = { + .name = "hsspi", + .id = -1, + .parent = &clk_esysclk, + .ctrlbit = S3C2443_SCLKCON_HSSPICLK, + .enable = s3c2443_clkcon_enable_s, + .get_rate = s3c2443_getrate_hsspi, + .set_rate = s3c2443_setrate_hsspi, + .round_rate = s3c2443_roundrate_clksrc4, +}; + +/* usbhost + * + * usb host bus-clock, usually 48MHz to provide USB bus clock timing +*/ + +static unsigned long s3c2443_getrate_usbhost(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2443_CLKDIV1); + + div &= S3C2443_CLKDIV1_USBHOSTDIV_MASK; + div >>= S3C2443_CLKDIV1_USBHOSTDIV_SHIFT; + + return parent_rate / (div + 1); +} + +static int s3c2443_setrate_usbhost(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1); + + rate = s3c2443_roundrate_clksrc4(clk, rate); + rate = parent_rate / rate; + + clkdivn &= ~S3C2443_CLKDIV1_USBHOSTDIV_MASK; + clkdivn |= (rate - 1) << S3C2443_CLKDIV1_USBHOSTDIV_SHIFT; + + __raw_writel(clkdivn, S3C2443_CLKDIV1); + return 0; +} + +struct clk clk_usb_bus_host = { + .name = "usb-bus-host-parent", + .id = -1, + .parent = &clk_esysclk, + .ctrlbit = S3C2443_SCLKCON_USBHOST, + .enable = s3c2443_clkcon_enable_s, + .get_rate = s3c2443_getrate_usbhost, + .set_rate = s3c2443_setrate_usbhost, + .round_rate = s3c2443_roundrate_clksrc4, +}; + +/* clk_hsmcc_div + * + * this clock is sourced from epll, and is fed through a divider, + * to a mux controlled by sclkcon where either it or a extclk can + * be fed to the hsmmc block +*/ + +static unsigned long s3c2443_getrate_hsmmc_div(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2443_CLKDIV1); + + div &= S3C2443_CLKDIV1_HSMMCDIV_MASK; + div >>= S3C2443_CLKDIV1_HSMMCDIV_SHIFT; + + return parent_rate / (div + 1); +} + +static int s3c2443_setrate_hsmmc_div(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1); + + rate = s3c2443_roundrate_clksrc4(clk, rate); + rate = parent_rate / rate; + + clkdivn &= ~S3C2443_CLKDIV1_HSMMCDIV_MASK; + clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSMMCDIV_SHIFT; + + __raw_writel(clkdivn, S3C2443_CLKDIV1); + return 0; +} + +static struct clk clk_hsmmc_div = { + .name = "hsmmc-div", + .id = -1, + .parent = &clk_esysclk, + .get_rate = s3c2443_getrate_hsmmc_div, + .set_rate = s3c2443_setrate_hsmmc_div, + .round_rate = s3c2443_roundrate_clksrc4, +}; + +static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) +{ + unsigned long clksrc = __raw_readl(S3C2443_SCLKCON); + + clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT | + S3C2443_SCLKCON_HSMMCCLK_EPLL); + + if (parent == &clk_epll) + clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL; + else if (parent == &clk_ext) + clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT; + else + return -EINVAL; + + if (clk->usage > 0) { + __raw_writel(clksrc, S3C2443_SCLKCON); + } + + clk->parent = parent; + return 0; +} + +static int s3c2443_enable_hsmmc(struct clk *clk, int enable) +{ + return s3c2443_setparent_hsmmc(clk, clk->parent); +} + +static struct clk clk_hsmmc = { + .name = "hsmmc-if", + .id = -1, + .parent = &clk_hsmmc_div, + .enable = s3c2443_enable_hsmmc, + .set_parent = s3c2443_setparent_hsmmc, +}; + +/* i2s_eplldiv + * + * this clock is the output from the i2s divisor of esysclk +*/ + +static unsigned long s3c2443_getrate_i2s_eplldiv(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2443_CLKDIV1); + + div &= S3C2443_CLKDIV1_I2SDIV_MASK; + div >>= S3C2443_CLKDIV1_I2SDIV_SHIFT; + + return parent_rate / (div + 1); +} + +static int s3c2443_setrate_i2s_eplldiv(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1); + + rate = s3c2443_roundrate_clksrc16(clk, rate); + rate = parent_rate / rate; + + clkdivn &= ~S3C2443_CLKDIV1_I2SDIV_MASK; + clkdivn |= (rate - 1) << S3C2443_CLKDIV1_I2SDIV_SHIFT; + + __raw_writel(clkdivn, S3C2443_CLKDIV1); + return 0; +} + +static struct clk clk_i2s_eplldiv = { + .name = "i2s-eplldiv", + .id = -1, + .parent = &clk_esysclk, + .get_rate = s3c2443_getrate_i2s_eplldiv, + .set_rate = s3c2443_setrate_i2s_eplldiv, + .round_rate = s3c2443_roundrate_clksrc16, +}; + +/* i2s-ref + * + * i2s bus reference clock, selectable from external, esysclk or epllref +*/ + +static int s3c2443_setparent_i2s(struct clk *clk, struct clk *parent) +{ + unsigned long clksrc = __raw_readl(S3C2443_CLKSRC); + + clksrc &= ~S3C2443_CLKSRC_I2S_MASK; + + if (parent == &clk_epllref) + clksrc |= S3C2443_CLKSRC_I2S_EPLLREF; + else if (parent == &clk_i2s_ext) + clksrc |= S3C2443_CLKSRC_I2S_EXT; + else if (parent != &clk_i2s_eplldiv) + return -EINVAL; + + clk->parent = parent; + __raw_writel(clksrc, S3C2443_CLKSRC); + + return 0; +} + +static struct clk clk_i2s = { + .name = "i2s-if", + .id = -1, + .parent = &clk_i2s_eplldiv, + .ctrlbit = S3C2443_SCLKCON_I2SCLK, + .enable = s3c2443_clkcon_enable_s, + .set_parent = s3c2443_setparent_i2s, +}; + +/* cam-if + * + * camera interface bus-clock, divided down from esysclk +*/ + +static unsigned long s3c2443_getrate_cam(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2443_CLKDIV1); + + div &= S3C2443_CLKDIV1_CAMDIV_MASK; + div >>= S3C2443_CLKDIV1_CAMDIV_SHIFT; + + return parent_rate / (div + 1); +} + +static int s3c2443_setrate_cam(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long clkdiv1 = __raw_readl(S3C2443_CLKDIV1); + + rate = s3c2443_roundrate_clksrc16(clk, rate); + rate = parent_rate / rate; + + clkdiv1 &= ~S3C2443_CLKDIV1_CAMDIV_MASK; + clkdiv1 |= (rate - 1) << S3C2443_CLKDIV1_CAMDIV_SHIFT; + + __raw_writel(clkdiv1, S3C2443_CLKDIV1); + return 0; +} + +static struct clk clk_cam = { + .name = "camif-upll", /* same as 2440 name */ + .id = -1, + .parent = &clk_esysclk, + .ctrlbit = S3C2443_SCLKCON_CAMCLK, + .enable = s3c2443_clkcon_enable_s, + .get_rate = s3c2443_getrate_cam, + .set_rate = s3c2443_setrate_cam, + .round_rate = s3c2443_roundrate_clksrc16, +}; + +/* display-if + * + * display interface clock, divided from esysclk +*/ + +static unsigned long s3c2443_getrate_display(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long div = __raw_readl(S3C2443_CLKDIV1); + + div &= S3C2443_CLKDIV1_DISPDIV_MASK; + div >>= S3C2443_CLKDIV1_DISPDIV_SHIFT; + + return parent_rate / (div + 1); +} + +static int s3c2443_setrate_display(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1); + + rate = s3c2443_roundrate_clksrc256(clk, rate); + rate = parent_rate / rate; + + clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK; + clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT; + + __raw_writel(clkdivn, S3C2443_CLKDIV1); + return 0; +} + +static struct clk clk_display = { + .name = "display-if", + .id = -1, + .parent = &clk_esysclk, + .ctrlbit = S3C2443_SCLKCON_DISPCLK, + .enable = s3c2443_clkcon_enable_s, + .get_rate = s3c2443_getrate_display, + .set_rate = s3c2443_setrate_display, + .round_rate = s3c2443_roundrate_clksrc256, +}; + +/* standard clock definitions */ + +static struct clk init_clocks_disable[] = { + { + .name = "nand", + .id = -1, + .parent = &clk_h, + }, { + .name = "sdi", + .id = -1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_SDI, + }, { + .name = "adc", + .id = -1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_ADC, + }, { + .name = "i2c", + .id = -1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_IIC, + }, { + .name = "iis", + .id = -1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_IIS, + }, { + .name = "spi", + .id = 0, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_SPI0, + }, { + .name = "spi", + .id = 1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_SPI1, + } +}; + +static struct clk init_clocks[] = { + { + .name = "dma", + .id = 0, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_DMA0, + }, { + .name = "dma", + .id = 1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_DMA1, + }, { + .name = "dma", + .id = 2, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_DMA2, + }, { + .name = "dma", + .id = 3, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_DMA3, + }, { + .name = "dma", + .id = 4, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_DMA4, + }, { + .name = "dma", + .id = 5, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_DMA5, + }, { + .name = "lcd", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_LCDC, + }, { + .name = "gpio", + .id = -1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_GPIO, + }, { + .name = "usb-host", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_USBH, + }, { + .name = "usb-device", + .id = -1, + .parent = &clk_h, + .enable = s3c2443_clkcon_enable_h, + .ctrlbit = S3C2443_HCLKCON_USBD, + }, { + .name = "timers", + .id = -1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_PWMT, + }, { + .name = "uart", + .id = 0, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_UART0, + }, { + .name = "uart", + .id = 1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_UART1, + }, { + .name = "uart", + .id = 2, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_UART2, + }, { + .name = "uart", + .id = 3, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_UART3, + }, { + .name = "rtc", + .id = -1, + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_RTC, + }, { + .name = "watchdog", + .id = -1, + .parent = &clk_p, + .ctrlbit = S3C2443_PCLKCON_WDT, + }, { + .name = "usb-bus-host", + .id = -1, + .parent = &clk_usb_bus_host, + } +}; + +/* clocks to add where we need to check their parentage */ + +/* s3c2443_clk_initparents + * + * Initialise the parents for the clocks that we get at start-time +*/ + +static int __init clk_init_set_parent(struct clk *clk, struct clk *parent) +{ + printk(KERN_DEBUG "clock %s: parent %s\n", clk->name, parent->name); + return clk_set_parent(clk, parent); +} + +static void __init s3c2443_clk_initparents(void) +{ + unsigned long clksrc = __raw_readl(S3C2443_CLKSRC); + struct clk *parent; + + switch (clksrc & S3C2443_CLKSRC_EPLLREF_MASK) { + case S3C2443_CLKSRC_EPLLREF_EXTCLK: + parent = &clk_ext; + break; + + case S3C2443_CLKSRC_EPLLREF_XTAL: + default: + parent = &clk_xtal; + break; + + case S3C2443_CLKSRC_EPLLREF_MPLLREF: + case S3C2443_CLKSRC_EPLLREF_MPLLREF2: + parent = &clk_mpllref; + break; + } + + clk_init_set_parent(&clk_epllref, parent); + + switch (clksrc & S3C2443_CLKSRC_I2S_MASK) { + case S3C2443_CLKSRC_I2S_EXT: + parent = &clk_i2s_ext; + break; + + case S3C2443_CLKSRC_I2S_EPLLDIV: + default: + parent = &clk_i2s_eplldiv; + break; + + case S3C2443_CLKSRC_I2S_EPLLREF: + case S3C2443_CLKSRC_I2S_EPLLREF3: + parent = &clk_epllref; + } + + clk_init_set_parent(&clk_i2s, &clk_epllref); + + /* esysclk source */ + + parent = (clksrc & S3C2443_CLKSRC_ESYSCLK_EPLL) ? + &clk_epll : &clk_epllref; + + clk_init_set_parent(&clk_esysclk, parent); + + /* msysclk source */ + + if (clksrc & S3C2443_CLKSRC_MSYSCLK_MPLL) { + parent = &clk_mpll; + } else { + parent = (clksrc & S3C2443_CLKSRC_EXTCLK_DIV) ? + &clk_mdivclk : &clk_mpllref; + } + + clk_init_set_parent(&clk_msysclk, parent); +} + +/* armdiv divisor table */ + +static unsigned int armdiv[16] = { + [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1, + [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2, + [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3, + [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4, + [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6, + [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8, + [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12, + [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16, +}; + +static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0) +{ + clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK; + + return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]; +} + +static inline unsigned long s3c2443_get_prediv(unsigned long clkcon0) +{ + clkcon0 &= S3C2443_CLKDIV0_PREDIV_MASK; + clkcon0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT; + + return clkcon0 + 1; +} + +/* clocks to add straight away */ + +static struct clk *clks[] __initdata = { + &clk_ext, + &clk_epll, + &clk_usb_bus_host, + &clk_usb_bus, + &clk_esysclk, + &clk_epllref, + &clk_mpllref, + &clk_msysclk, + &clk_uart, + &clk_display, + &clk_cam, + &clk_i2s_eplldiv, + &clk_i2s, + &clk_hsspi, + &clk_hsmmc_div, + &clk_hsmmc, +}; + +void __init s3c2443_init_clocks(int xtal) +{ + unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); + unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); + unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); + unsigned long pll; + unsigned long fclk; + unsigned long hclk; + unsigned long pclk; + struct clk *clkp; + int ret; + int ptr; + + pll = s3c2443_get_mpll(mpllcon, xtal); + + fclk = pll / s3c2443_fclk_div(clkdiv0); + hclk = fclk / s3c2443_get_prediv(clkdiv0); + hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1); + pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); + + s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); + + printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", + (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", + print_mhz(pll), print_mhz(fclk), + print_mhz(hclk), print_mhz(pclk)); + + s3c2443_clk_initparents(); + + for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { + clkp = clks[ptr]; + + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + } + + clk_epll.rate = s3c2443_get_epll(epllcon, xtal); + + clk_usb_bus.parent = &clk_usb_bus_host; + + /* ensure usb bus clock is within correct rate of 48MHz */ + + if (clk_get_rate(&clk_usb_bus_host) != (48 * 1000 * 1000)) { + printk(KERN_INFO "Warning: USB host bus not at 48MHz\n"); + clk_set_rate(&clk_usb_bus_host, 48*1000*1000); + } + + printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", + (epllcon & S3C2443_PLLCON_OFF) ? "off":"on", + print_mhz(clk_get_rate(&clk_epll)), + print_mhz(clk_get_rate(&clk_usb_bus))); + + /* register clocks from clock array */ + + clkp = init_clocks; + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + } + + /* We must be careful disabling the clocks we are not intending to + * be using at boot time, as subsytems such as the LCD which do + * their own DMA requests to the bus can cause the system to lockup + * if they where in the middle of requesting bus access. + * + * Disabling the LCD clock if the LCD is active is very dangerous, + * and therefore the bootloader should be careful to not enable + * the LCD clock if it is not needed. + */ + + /* install (and disable) the clocks we do not need immediately */ + + clkp = init_clocks_disable; + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { + + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + + (clkp->enable)(clkp, 0); + } +} diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c new file mode 100644 index 000000000000..f7058823a0e1 --- /dev/null +++ b/arch/arm/mach-s3c2443/irq.c @@ -0,0 +1,130 @@ +/* linux/arch/arm/mach-s3c2443/irq.c + * + * Copyright (c) 2007 Simtec Electronics + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * +*/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +/* WDT/AC97 */ + +static void s3c_irq_demux_wdtac97(unsigned int irq, + struct irq_desc *desc) +{ + unsigned int subsrc, submsk; + struct irq_desc *mydesc; + + /* read the current pending interrupts, and the mask + * for what it is available */ + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + subsrc &= ~submsk; + subsrc >>= 27; + subsrc &= 3; + + if (subsrc != 0) { + if (subsrc & 1) { + mydesc = irq_desc + IRQ_S3C2443_WDT; + desc_handle_irq(IRQ_S3C2443_WDT, mydesc); + } + if (subsrc & 2) { + mydesc = irq_desc + IRQ_S3C2443_AC97; + desc_handle_irq(IRQ_S3C2443_AC97, mydesc); + } + } +} + + +#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0)) + +static void +s3c_irq_wdtac97_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<27); +} + +static void +s3c_irq_wdtac97_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_WDT); +} + +static void +s3c_irq_wdtac97_ack(unsigned int irqno) +{ + s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<27); +} + +static struct irq_chip s3c_irq_wdtac97 = { + .mask = s3c_irq_wdtac97_mask, + .unmask = s3c_irq_wdtac97_unmask, + .ack = s3c_irq_wdtac97_ack, +}; + +static int s3c2443_irq_add(struct sys_device *sysdev) +{ + unsigned int irqno; + + printk("S3C2443: IRQ Support\n"); + + /* add new chained handler for wdt, ac7 */ + + set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); + set_irq_handler(IRQ_WDT, handle_level_irq); + set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); + + for (irqno = IRQ_S3C2443_WDT; irqno <= IRQ_S3C2443_AC97; irqno++) { + set_irq_chip(irqno, &s3c_irq_wdtac97); + set_irq_handler(irqno, handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } + + return 0; +} + +static struct sysdev_driver s3c2443_irq_driver = { + .add = s3c2443_irq_add, +}; + +static int s3c2443_irq_init(void) +{ + return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_irq_driver); +} + +arch_initcall(s3c2443_irq_init); + diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c new file mode 100644 index 000000000000..bc14f772ff24 --- /dev/null +++ b/arch/arm/mach-s3c2443/s3c2443.c @@ -0,0 +1,87 @@ +/* linux/arch/arm/mach-s3c2443/s3c2443.c + * + * Copyright (c) 2007 Simtec Electronics + * Ben Dooks + * + * Samsung S3C2443 Mobile CPU support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include +#include + +static struct map_desc s3c2443_iodesc[] __initdata = { + IODESC_ENT(WATCHDOG), + IODESC_ENT(CLKPWR), + IODESC_ENT(TIMER), +}; + +struct sysdev_class s3c2443_sysclass = { + set_kset_name("s3c2443-core"), +}; + +static struct sys_device s3c2443_sysdev = { + .cls = &s3c2443_sysclass, +}; + +int __init s3c2443_init(void) +{ + printk("S3C2443: Initialising architecture\n"); + + return sysdev_register(&s3c2443_sysdev); +} + +void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no); +} + +/* s3c2443_map_io + * + * register the standard cpu IO areas, and any passed in from the + * machine specific initialisation. + */ + +void __init s3c2443_map_io(struct map_desc *mach_desc, int mach_size) +{ + iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc)); + iotable_init(mach_desc, mach_size); +} + +/* need to register class before we actually register the device, and + * we also need to ensure that it has been initialised before any of the + * drivers even try to use it (even if not on an s3c2443 based system) + * as a driver which may support both 2443 and 2440 may try and use it. +*/ + +static int __init s3c2443_core_init(void) +{ + return sysdev_class_register(&s3c2443_sysclass); +} + +core_initcall(s3c2443_core_init); diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index 2fbb74969379..6a2d1070e5a0 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c @@ -49,6 +49,7 @@ #include "s3c244x.h" #include #include +#include struct cpu_table { unsigned long idcode; @@ -67,6 +68,7 @@ static const char name_s3c2410[] = "S3C2410"; static const char name_s3c2412[] = "S3C2412"; static const char name_s3c2440[] = "S3C2440"; static const char name_s3c2442[] = "S3C2442"; +static const char name_s3c2443[] = "S3C2443"; static const char name_s3c2410a[] = "S3C2410A"; static const char name_s3c2440a[] = "S3C2440A"; @@ -134,6 +136,15 @@ static struct cpu_table cpu_ids[] __initdata = { .init = s3c2412_init, .name = name_s3c2412, }, + { + .idcode = 0x32443001, + .idmask = 0xffffffff, + .map_io = s3c2443_map_io, + .init_clocks = s3c2443_init_clocks, + .init_uarts = s3c2443_init_uarts, + .init = s3c2443_init, + .name = name_s3c2443, + }, { .idcode = 0x0, /* S3C2400 doesn't have an idcode */ .idmask = 0xffffffff, diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c index 87aace4c8f8c..767f2e9a3a55 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.c +++ b/arch/arm/plat-s3c24xx/s3c244x.c @@ -3,7 +3,7 @@ * Copyright (c) 2004-2006 Simtec Electronics * Ben Dooks * - * Samsung S3C2440 and S3C2442 Mobile CPU support + * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/include/asm-arm/plat-s3c24xx/cpu.h b/include/asm-arm/plat-s3c24xx/cpu.h index 8181b22532bd..15dd18810905 100644 --- a/include/asm-arm/plat-s3c24xx/cpu.h +++ b/include/asm-arm/plat-s3c24xx/cpu.h @@ -67,3 +67,4 @@ extern struct sysdev_class s3c2410_sysclass; extern struct sysdev_class s3c2412_sysclass; extern struct sysdev_class s3c2440_sysclass; extern struct sysdev_class s3c2442_sysclass; +extern struct sysdev_class s3c2443_sysclass; diff --git a/include/asm-arm/plat-s3c24xx/s3c2443.h b/include/asm-arm/plat-s3c24xx/s3c2443.h new file mode 100644 index 000000000000..11d83b5c84e6 --- /dev/null +++ b/include/asm-arm/plat-s3c24xx/s3c2443.h @@ -0,0 +1,32 @@ +/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h + * + * Copyright (c) 2004-2005 Simtec Electronics + * Ben Dooks + * + * Header file for s3c2443 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifdef CONFIG_CPU_S3C2443 + +struct s3c2410_uartcfg; + +extern int s3c2443_init(void); + +extern void s3c2443_map_io(struct map_desc *mach_desc, int size); + +extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +extern void s3c2443_init_clocks(int xtal); + +extern int s3c2443_baseclk_add(void); + +#else +#define s3c2443_init_clocks NULL +#define s3c2443_init_uarts NULL +#define s3c2443_map_io NULL +#define s3c2443_init NULL +#endif -- cgit v1.2.3