From 83be81e3b0b6eb5df2fba66baa7a25f7e7dc9775 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Thu, 16 May 2019 09:29:40 -0700 Subject: ARM: dts: rockchip: raise CPU trip point temperature for veyron to 100 degC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This value matches what is used by the downstream Chrome OS 3.14 kernel, the 'official' kernel for veyron devices. Keep the temperature for 'speedy' at 90°C, as in the downstream kernel. Increase the temperature for a hardware shutdown to 125°C, which matches the downstream configuration and gives the system a chance to shut down orderly at the criticial trip point. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 1252522392c7..e81f1a0cac83 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -123,6 +123,10 @@ cpu0-supply = <&vdd_cpu>; }; +&cpu_crit { + temperature = <100000>; +}; + /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */ &cpu_opp_table { /delete-node/ opp-312000000; @@ -394,6 +398,7 @@ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-temp = <125000>; }; &uart0 { -- cgit v1.2.3 From 0f637e2565d175eeff664991be9a6d0753d0e484 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Thu, 16 May 2019 09:29:41 -0700 Subject: ARM: dts: rockchip: raise GPU trip point temperatures for veyron MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The values match those used by the downstream Chrome OS 3.14 kernel, the 'official' kernel for veyron devices. Keep the critical trip point for speedy at 90°C as in the downstream configuration. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-speedy.dts | 4 ++++ arch/arm/boot/dts/rk3288-veyron.dtsi | 8 ++++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi') diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts index b07a07e81551..aae37c535444 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -75,6 +75,10 @@ force-hpd; }; +&gpu_crit { + temperature = <90000>; +}; + &panel { power-supply= <&panel_regulator>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index e81f1a0cac83..90c8312d01ff 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -166,6 +166,14 @@ status = "okay"; }; +&gpu_alert0 { + temperature = <72500>; +}; + +&gpu_crit { + temperature = <100000>; +}; + &hdmi { ddc-i2c-bus = <&i2c5>; status = "okay"; -- cgit v1.2.3 From bf09924f21767e6bb7cb3aae48c48c2c2ab8261a Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 2 May 2019 15:53:34 -0700 Subject: ARM: dts: rockchip: Switch to builtin HDMI DDC bus on rk3288-veyron Downstream Chrome OS kernels use the builtin DDC bus from dw_hdmi on veyron. This is the only way to get them to negotiate HDCP. Although HDCP isn't currently all supported upstream, it still seems like it makes sense to use dw_hdmi's builtin I2C. Maybe eventually we can get HDCP negotiation working. Signed-off-by: Douglas Anderson Reviewed-by: Sean Paul Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 90c8312d01ff..99e2771d4d31 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -175,7 +175,8 @@ }; &hdmi { - ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ddc>; status = "okay"; }; @@ -346,14 +347,6 @@ i2c-scl-rising-time-ns = <300>; /* 225ns measured */ }; -&i2c5 { - status = "okay"; - - clock-frequency = <100000>; - i2c-scl-falling-time-ns = <300>; - i2c-scl-rising-time-ns = <1000>; -}; - &io_domains { status = "okay"; -- cgit v1.2.3 From cd6386087d826b9421ed97b778676f4177ffdfbd Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 2 May 2019 15:53:36 -0700 Subject: ARM: dts: rockchip: Add HDMI i2c unwedging for rk3288-veyron Veyron uses the builtin i2c controller that's part of dw-hdmi. Hook up the unwedging feature. Signed-off-by: Douglas Anderson Reviewed-by: Sean Paul Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 99e2771d4d31..c574844a6bb2 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -175,8 +175,9 @@ }; &hdmi { - pinctrl-names = "default"; + pinctrl-names = "default", "unwedge"; pinctrl-0 = <&hdmi_ddc>; + pinctrl-1 = <&hdmi_ddc_unwedge>; status = "okay"; }; -- cgit v1.2.3 From b8925b7c2f867df6ce3e20deb4b3e2b9b32b20ff Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 5 Jun 2019 13:43:19 -0700 Subject: ARM: dts: rockchip: Split GPIO keys for veyron into multiple devices With a single device DT overrides can become messy, especially when keys are added or removed. Multiple devices also allow to enable/disable wakeup per key/group. Signed-off-by: Matthias Kaehlcke [used actual switch+event constants in new lid-switch entry] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 27 ++++++++++-------- arch/arm/boot/dts/rk3288-veyron-minnie.dts | 38 +++++++++++++------------ arch/arm/boot/dts/rk3288-veyron-pinky.dts | 2 +- arch/arm/boot/dts/rk3288-veyron.dtsi | 4 +-- 4 files changed, 38 insertions(+), 33 deletions(-) (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi') diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index fbef34578100..5727017f34b2 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -70,6 +70,21 @@ pinctrl-0 = <&ac_present_ap>; }; + lid_switch: lid-switch { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&ap_lid_int_l>; + + lid { + label = "Lid"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + wakeup-source; + linux,code = ; + linux,input-type = ; + debounce-interval = <1>; + }; + }; + panel: panel { compatible ="innolux,n116bge", "simple-panel"; status = "okay"; @@ -149,18 +164,6 @@ status = "okay"; }; -&gpio_keys { - pinctrl-0 = <&pwr_key_l &ap_lid_int_l>; - lid { - label = "Lid"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = <0>; /* SW_LID */ - linux,input-type = <5>; /* EV_SW */ - debounce-interval = <1>; - }; -}; - &pwm0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index a65099b4aef1..b2cc70a08554 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -48,6 +48,26 @@ regulator-boot-on; vin-supply = <&vcc18_wl>; }; + + volume_buttons: volume-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&volum_down_l &volum_up_l>; + + volum_down { + label = "Volum_down"; + gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <100>; + }; + + volum_up { + label = "Volum_up"; + gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <100>; + }; + }; }; &backlight { @@ -90,24 +110,6 @@ pwm-off-delay-ms = <200>; }; -&gpio_keys { - pinctrl-0 = <&pwr_key_l &ap_lid_int_l &volum_down_l &volum_up_l>; - - volum_down { - label = "Volum_down"; - gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - }; - - volum_up { - label = "Volum_up"; - gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - }; -}; - &i2c_tunnel { battery: bq27500@55 { compatible = "ti,bq27500"; diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts index 9645be7b3d8c..9b6f4d9b03b6 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts @@ -35,7 +35,7 @@ force-hpd; }; -&gpio_keys { +&lid_switch { pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; power { diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index c574844a6bb2..3257ca90f0e8 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -23,11 +23,11 @@ reg = <0x0 0x0 0x0 0x80000000>; }; - gpio_keys: gpio-keys { + power_button: power-button { compatible = "gpio-keys"; - pinctrl-names = "default"; pinctrl-0 = <&pwr_key_l>; + power { label = "Power"; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -- cgit v1.2.3 From f497ab6b4bb813aca439b7f3a72a060b58b147c4 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 10 Jun 2019 16:51:44 -0700 Subject: ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on veyron This enables wake up on Bluetooth activity when the device is suspended. The BT_HOST_WAKE signal is only connected on devices with BT module that are connected through UART. Signed-off-by: Douglas Anderson Signed-off-by: Matthias Kaehlcke Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 3257ca90f0e8..e2635ad574e7 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -23,6 +23,31 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + bt_activity: bt-activity { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake>; + + /* + * HACK: until we have an LPM driver, we'll use an + * ugly GPIO key to allow Bluetooth to wake from S3. + * This is expected to only be used by BT modules that + * use UART for comms. For BT modules that talk over + * SDIO we should use a wakeup mechanism related to SDIO. + * + * Use KEY_RESERVED here since that will work as a wakeup but + * doesn't get reported to higher levels (so doesn't confuse + * Chrome). + */ + bt-wake { + label = "BT Wakeup"; + gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>; + linux,code = ; + wakeup-source; + }; + + }; + power_button: power-button { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -549,6 +574,10 @@ rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; + bt_host_wake: bt-host-wake { + rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + /* * We run sdio0 at max speed; bump up drive strength. * We also have external pulls, so disable the internal ones. -- cgit v1.2.3 From 4db11c378ab1e170c3a197ea3719ffe54cd06637 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 19 Jun 2019 11:34:25 -0700 Subject: ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron This is the other half of the hacky solution from commit f497ab6b4bb8 ("ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on veyron"). Specifically the LPM driver that the Broadcom Bluetooth expects to have (but is missing in mainline) has two halves of the equation: BT_HOST_WAKE and BT_DEV_WAKE. The BT_HOST_WAKE (which was handled in the previous commit) is the one that lets the Bluetooth wake the system up. The BT_DEV_WAKE (this patch) tells the Bluetooth that it's OK to go into a low power mode. That means we were burning a bit of extra power in S3 without this patch. Measurements are a bit noisy, but it appears to be a few mA worth of difference. NOTE: Though these pins don't do much on systems with Marvell Bluetooth, downstream kernels set it on all veyron boards so we'll do the same. Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 2 ++ arch/arm/boot/dts/rk3288-veyron.dtsi | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi') diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index 5727017f34b2..1cadb522fd0d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -237,6 +237,7 @@ /* Wake only */ &suspend_l_wake + &bt_dev_wake_awake >; pinctrl-1 = < /* Common for sleep and wake, but no owners */ @@ -246,6 +247,7 @@ /* Sleep only */ &suspend_l_sleep + &bt_dev_wake_sleep >; backlight { diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index e2635ad574e7..53d2f2452868 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -485,12 +485,18 @@ &ddr0_retention &ddrio_pwroff &global_pwroff + + /* Wake only */ + &bt_dev_wake_awake >; pinctrl-1 = < /* Common for sleep and wake, but no owners */ &ddr0_retention &ddrio_pwroff &global_pwroff + + /* Sleep only */ + &bt_dev_wake_sleep >; pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { @@ -596,6 +602,20 @@ sdio0_clk: sdio0-clk { rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>; }; + + /* + * These pins are only present on very new veyron boards; on + * older boards bt_dev_wake is simply always high. Note that + * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt + * to map this pin everywhere + */ + bt_dev_wake_sleep: bt-dev-wake-sleep { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + bt_dev_wake_awake: bt-dev-wake-awake { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; + }; }; tpm { -- cgit v1.2.3