From abf80c276dca1bf40b342b4ebf7815be0f6ba564 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 23 Jan 2013 09:43:49 -0700 Subject: ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot/dts/tegra30.dtsi') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index ff4a0ca45983..313fa71e099d 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -234,6 +234,7 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <0 36 0x04>; + clock-frequency = <408000000>; nvidia,dma-request-selector = <&apbdma 8>; clocks = <&tegra_car 6>; status = "disabled"; @@ -243,6 +244,7 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; + clock-frequency = <408000000>; interrupts = <0 37 0x04>; nvidia,dma-request-selector = <&apbdma 9>; clocks = <&tegra_car 160>; @@ -253,6 +255,7 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; + clock-frequency = <408000000>; interrupts = <0 46 0x04>; nvidia,dma-request-selector = <&apbdma 10>; clocks = <&tegra_car 55>; @@ -263,6 +266,7 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; + clock-frequency = <408000000>; interrupts = <0 90 0x04>; nvidia,dma-request-selector = <&apbdma 19>; clocks = <&tegra_car 65>; @@ -273,6 +277,7 @@ compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; reg = <0x70006400 0x100>; reg-shift = <2>; + clock-frequency = <408000000>; interrupts = <0 91 0x04>; nvidia,dma-request-selector = <&apbdma 20>; clocks = <&tegra_car 66>; -- cgit v1.2.3