From fa94bd57b5a5b2206e5fdd0ed2dbacff199121f2 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Wed, 18 Sep 2013 11:48:38 -0700 Subject: arm: zynq: Enable arm_global_timer Zynq is based on an ARM Cortex-A9 MPCore, which features the arm_global_timer in its SCU. Therefore enable the timer for Zynq. Signed-off-by: Soren Brinkmann Acked-by: Daniel Lezcano Signed-off-by: Daniel Lezcano Acked-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index e32b92b949d2..e7f73b2e4550 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -92,6 +92,14 @@ }; }; + global_timer: timer@f8f00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf8f00200 0x20>; + interrupts = <1 11 0x301>; + interrupt-parent = <&intc>; + clocks = <&clkc 4>; + }; + ttc0: ttc0@f8001000 { interrupt-parent = <&intc>; interrupts = < 0 10 4 0 11 4 0 12 4 >; -- cgit v1.2.3 From fb85f4290ddf646548ac30848863f3211c3d2e54 Mon Sep 17 00:00:00 2001 From: Qipan Li Date: Sun, 29 Sep 2013 22:27:57 +0800 Subject: pinctrl: sirf: add lost uart0-no-stream-control pingroup for prima2 the old codes defined uart0_nostreamctrl_pins, but missed pingroup and padmux definition for it. this patch fixes it. Signed-off-by: Qipan Li Signed-off-by: Barry Song Signed-off-by: Linus Walleij --- arch/arm/boot/dts/prima2.dtsi | 6 ++++++ drivers/pinctrl/sirf/pinctrl-prima2.c | 3 +++ 2 files changed, 9 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index bbeb623fc2c6..766aa395f85c 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -341,6 +341,12 @@ sirf,function = "uart0"; }; }; + uart0_noflow_pins_a: uart0@1 { + uart { + sirf,pins = "uart0_nostreamctrlgrp"; + sirf,function = "uart0_nostreamctrl"; + }; + }; uart1_pins_a: uart1@0 { uart { sirf,pins = "uart1grp"; diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c index 1f0ad1ef5a3a..29fc842b6d91 100644 --- a/drivers/pinctrl/sirf/pinctrl-prima2.c +++ b/drivers/pinctrl/sirf/pinctrl-prima2.c @@ -764,6 +764,7 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins), SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins), SIRFSOC_PIN_GROUP("uart0grp", uart0_pins), + SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins), SIRFSOC_PIN_GROUP("uart1grp", uart1_pins), SIRFSOC_PIN_GROUP("uart2grp", uart2_pins), SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), @@ -803,6 +804,7 @@ static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; static const char * const lcdromgrp[] = { "lcdromgrp" }; static const char * const uart0grp[] = { "uart0grp" }; +static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" }; static const char * const uart1grp[] = { "uart1grp" }; static const char * const uart2grp[] = { "uart2grp" }; static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; @@ -842,6 +844,7 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), + SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux), SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), -- cgit v1.2.3 From af614b2301f0e30423240a754ec2812a4c793201 Mon Sep 17 00:00:00 2001 From: Qipan Li Date: Sun, 29 Sep 2013 22:27:58 +0800 Subject: pinctrl: sirf: add lost USP-based UART pin groups for prima2 USP(Universal Serial Ports) can be UART as commit 5df831117b85a08e7aa, this patch defines the USP-based UART function pin groups for prima2. Signed-off-by: Qipan Li Signed-off-by: Barry Song Signed-off-by: Linus Walleij --- arch/arm/boot/dts/prima2.dtsi | 24 ++++++++++++++ drivers/pinctrl/sirf/pinctrl-prima2.c | 60 +++++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 766aa395f85c..569763a0e788 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -485,18 +485,42 @@ sirf,function = "usp0"; }; }; + usp0_uart_nostreamctrl_pins_a: usp0@1 { + usp0 { + sirf,pins = + "usp0_uart_nostreamctrl_grp"; + sirf,function = + "usp0_uart_nostreamctrl"; + }; + }; usp1_pins_a: usp1@0 { usp1 { sirf,pins = "usp1grp"; sirf,function = "usp1"; }; }; + usp1_uart_nostreamctrl_pins_a: usp1@1 { + usp1 { + sirf,pins = + "usp1_uart_nostreamctrl_grp"; + sirf,function = + "usp1_uart_nostreamctrl"; + }; + }; usp2_pins_a: usp2@0 { usp2 { sirf,pins = "usp2grp"; sirf,function = "usp2"; }; }; + usp2_uart_nostreamctrl_pins_a: usp2@1 { + usp2 { + sirf,pins = + "usp2_uart_nostreamctrl_grp"; + sirf,function = + "usp2_uart_nostreamctrl"; + }; + }; usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { usb0_utmi_drvbus { sirf,pins = "usb0_utmi_drvbusgrp"; diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c index 29fc842b6d91..241d83992692 100644 --- a/drivers/pinctrl/sirf/pinctrl-prima2.c +++ b/drivers/pinctrl/sirf/pinctrl-prima2.c @@ -485,6 +485,20 @@ static const struct sirfsoc_padmux usp0_padmux = { static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; +static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = { + { + .group = 1, + .mask = BIT(20) | BIT(21), + }, +}; + +static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask), + .muxmask = usp0_uart_nostreamctrl_muxmask, +}; + +static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 }; + static const struct sirfsoc_muxmask usp1_muxmask[] = { { .group = 1, @@ -501,6 +515,20 @@ static const struct sirfsoc_padmux usp1_padmux = { static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 }; +static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = { + { + .group = 1, + .mask = BIT(25) | BIT(26), + }, +}; + +static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask), + .muxmask = usp1_uart_nostreamctrl_muxmask, +}; + +static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 }; + static const struct sirfsoc_muxmask usp2_muxmask[] = { { .group = 1, @@ -520,6 +548,20 @@ static const struct sirfsoc_padmux usp2_padmux = { static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 }; +static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = { + { + .group = 1, + .mask = BIT(30) | BIT(31), + }, +}; + +static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = { + .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask), + .muxmask = usp2_uart_nostreamctrl_muxmask, +}; + +static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 }; + static const struct sirfsoc_muxmask nand_muxmask[] = { { .group = 2, @@ -769,8 +811,14 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("uart2grp", uart2_pins), SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), + SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp", + usp0_uart_nostreamctrl_pins), SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), + SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp", + usp1_uart_nostreamctrl_pins), SIRFSOC_PIN_GROUP("usp2grp", usp2_pins), + SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp", + usp2_uart_nostreamctrl_pins), SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins), SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins), SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins), @@ -809,8 +857,14 @@ static const char * const uart1grp[] = { "uart1grp" }; static const char * const uart2grp[] = { "uart2grp" }; static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; static const char * const usp0grp[] = { "usp0grp" }; +static const char * const usp0_uart_nostreamctrl_grp[] = + { "usp0_uart_nostreamctrl_grp" }; static const char * const usp1grp[] = { "usp1grp" }; +static const char * const usp1_uart_nostreamctrl_grp[] = + { "usp1_uart_nostreamctrl_grp" }; static const char * const usp2grp[] = { "usp2grp" }; +static const char * const usp2_uart_nostreamctrl_grp[] = + { "usp2_uart_nostreamctrl_grp" }; static const char * const i2c0grp[] = { "i2c0grp" }; static const char * const i2c1grp[] = { "i2c1grp" }; static const char * const pwm0grp[] = { "pwm0grp" }; @@ -849,8 +903,14 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), + SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", + usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux), SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), + SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl", + usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux), SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux), + SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl", + usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux), SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux), SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux), SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux), -- cgit v1.2.3 From 6a08a92ec45782e5543addf5f8785e2560a078f6 Mon Sep 17 00:00:00 2001 From: Rong Wang Date: Sun, 29 Sep 2013 22:27:59 +0800 Subject: pinctrl: sirf: add USB1/UART1 pinmux usb/uart share dn and dp of USB1 can share with UART1(UART1 can route rx,tx to dn and dp pins of USB1). here we add this pinmux capability. USB1/UART1 mode selection has dedicated control register in RSC module, here we attach the register offset of private data of related pin groups. Signed-off-by: Rong Wang Signed-off-by: Barry Song Signed-off-by: Linus Walleij --- arch/arm/boot/dts/atlas6.dtsi | 12 ++++++++ arch/arm/boot/dts/prima2.dtsi | 12 ++++++++ drivers/pinctrl/sirf/pinctrl-atlas6.c | 56 +++++++++++++++++++++++++++++++++++ drivers/pinctrl/sirf/pinctrl-prima2.c | 52 ++++++++++++++++++++++++++++++++ drivers/pinctrl/sirf/pinctrl-sirf.c | 8 ++--- drivers/pinctrl/sirf/pinctrl-sirf.h | 6 ++-- 6 files changed, 140 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 8678e0c11119..378d4116dbf2 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -515,6 +515,18 @@ sirf,function = "usb1_utmi_drvbus"; }; }; + usb1_dp_dn_pins_a: usb1_dp_dn@0 { + usb1_dp_dn { + sirf,pins = "usb1_dp_dngrp"; + sirf,function = "usb1_dp_dn"; + }; + }; + uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { + uart1_route_io_usb1 { + sirf,pins = "uart1_route_io_usb1grp"; + sirf,function = "uart1_route_io_usb1"; + }; + }; warm_rst_pins_a: warm_rst@0 { warm_rst { sirf,pins = "warm_rstgrp"; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 569763a0e788..fb2ffaeaefbc 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -533,6 +533,18 @@ sirf,function = "usb1_utmi_drvbus"; }; }; + usb1_dp_dn_pins_a: usb1_dp_dn@0 { + usb1_dp_dn { + sirf,pins = "usb1_dp_dngrp"; + sirf,function = "usb1_dp_dn"; + }; + }; + uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { + uart1_route_io_usb1 { + sirf,pins = "uart1_route_io_usb1grp"; + sirf,function = "uart1_route_io_usb1"; + }; + }; warm_rst_pins_a: warm_rst@0 { warm_rst { sirf,pins = "warm_rstgrp"; diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c index edf45a6940ca..8ab7898d21be 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas6.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c @@ -122,6 +122,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = { PINCTRL_PIN(100, "ac97_dout"), PINCTRL_PIN(101, "ac97_din"), PINCTRL_PIN(102, "x_rtc_io"), + + PINCTRL_PIN(103, "x_usb1_dp"), + PINCTRL_PIN(104, "x_usb1_dn"), }; static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { @@ -139,6 +142,7 @@ static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { static const struct sirfsoc_padmux lcd_16bits_padmux = { .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), .muxmask = lcd_16bits_sirfsoc_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(4), .funcval = 0, }; @@ -164,6 +168,7 @@ static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { static const struct sirfsoc_padmux lcd_18bits_padmux = { .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), .muxmask = lcd_18bits_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(4) | BIT(15), .funcval = 0, }; @@ -189,6 +194,7 @@ static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { static const struct sirfsoc_padmux lcd_24bits_padmux = { .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), .muxmask = lcd_24bits_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(4) | BIT(15), .funcval = 0, }; @@ -214,6 +220,7 @@ static const struct sirfsoc_muxmask lcdrom_muxmask[] = { static const struct sirfsoc_padmux lcdrom_padmux = { .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), .muxmask = lcdrom_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(4), .funcval = BIT(4), }; @@ -237,6 +244,7 @@ static const struct sirfsoc_muxmask uart0_muxmask[] = { static const struct sirfsoc_padmux uart0_padmux = { .muxmask_counts = ARRAY_SIZE(uart0_muxmask), .muxmask = uart0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(9), .funcval = BIT(9), }; @@ -284,6 +292,7 @@ static const struct sirfsoc_muxmask uart2_muxmask[] = { static const struct sirfsoc_padmux uart2_padmux = { .muxmask_counts = ARRAY_SIZE(uart2_muxmask), .muxmask = uart2_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(10), .funcval = BIT(10), }; @@ -317,6 +326,7 @@ static const struct sirfsoc_muxmask sdmmc3_muxmask[] = { static const struct sirfsoc_padmux sdmmc3_padmux = { .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), .muxmask = sdmmc3_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(7), .funcval = 0, }; @@ -336,6 +346,7 @@ static const struct sirfsoc_muxmask spi0_muxmask[] = { static const struct sirfsoc_padmux spi0_padmux = { .muxmask_counts = ARRAY_SIZE(spi0_muxmask), .muxmask = spi0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(7), .funcval = BIT(7), }; @@ -352,6 +363,7 @@ static const struct sirfsoc_muxmask cko1_muxmask[] = { static const struct sirfsoc_padmux cko1_padmux = { .muxmask_counts = ARRAY_SIZE(cko1_muxmask), .muxmask = cko1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(3), .funcval = 0, }; @@ -371,6 +383,7 @@ static const struct sirfsoc_muxmask i2s_muxmask[] = { static const struct sirfsoc_padmux i2s_padmux = { .muxmask_counts = ARRAY_SIZE(i2s_muxmask), .muxmask = i2s_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(3), .funcval = BIT(3), }; @@ -390,6 +403,7 @@ static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = { static const struct sirfsoc_padmux i2s_no_din_padmux = { .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask), .muxmask = i2s_no_din_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(3), .funcval = BIT(3), }; @@ -409,6 +423,7 @@ static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = { static const struct sirfsoc_padmux i2s_6chn_padmux = { .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask), .muxmask = i2s_6chn_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(1) | BIT(3) | BIT(9), .funcval = BIT(1) | BIT(3) | BIT(9), }; @@ -439,6 +454,7 @@ static const struct sirfsoc_muxmask spi1_muxmask[] = { static const struct sirfsoc_padmux spi1_padmux = { .muxmask_counts = ARRAY_SIZE(spi1_muxmask), .muxmask = spi1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(16), .funcval = 0, }; @@ -455,6 +471,7 @@ static const struct sirfsoc_muxmask sdmmc1_muxmask[] = { static const struct sirfsoc_padmux sdmmc1_padmux = { .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask), .muxmask = sdmmc1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(5), .funcval = BIT(5), }; @@ -471,6 +488,7 @@ static const struct sirfsoc_muxmask gps_muxmask[] = { static const struct sirfsoc_padmux gps_padmux = { .muxmask_counts = ARRAY_SIZE(gps_muxmask), .muxmask = gps_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(13), .funcval = 0, }; @@ -487,6 +505,7 @@ static const struct sirfsoc_muxmask sdmmc5_muxmask[] = { static const struct sirfsoc_padmux sdmmc5_padmux = { .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), .muxmask = sdmmc5_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(13), .funcval = BIT(13), }; @@ -503,6 +522,7 @@ static const struct sirfsoc_muxmask usp0_muxmask[] = { static const struct sirfsoc_padmux usp0_padmux = { .muxmask_counts = ARRAY_SIZE(usp0_muxmask), .muxmask = usp0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(1) | BIT(2) | BIT(9), .funcval = 0, }; @@ -535,6 +555,7 @@ static const struct sirfsoc_muxmask usp1_muxmask[] = { static const struct sirfsoc_padmux usp1_padmux = { .muxmask_counts = ARRAY_SIZE(usp1_muxmask), .muxmask = usp1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(16), .funcval = BIT(16), }; @@ -554,6 +575,7 @@ static const struct sirfsoc_muxmask nand_muxmask[] = { static const struct sirfsoc_padmux nand_padmux = { .muxmask_counts = ARRAY_SIZE(nand_muxmask), .muxmask = nand_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(5) | BIT(19), .funcval = 0, }; @@ -570,6 +592,7 @@ static const struct sirfsoc_muxmask sdmmc0_muxmask[] = { static const struct sirfsoc_padmux sdmmc0_padmux = { .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask), .muxmask = sdmmc0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(5) | BIT(19), .funcval = BIT(19), }; @@ -586,6 +609,7 @@ static const struct sirfsoc_muxmask sdmmc2_muxmask[] = { static const struct sirfsoc_padmux sdmmc2_padmux = { .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), .muxmask = sdmmc2_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(11), .funcval = 0, }; @@ -602,6 +626,7 @@ static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = { static const struct sirfsoc_padmux sdmmc2_nowp_padmux = { .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask), .muxmask = sdmmc2_nowp_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(11), .funcval = 0, }; @@ -634,6 +659,7 @@ static const struct sirfsoc_muxmask vip_muxmask[] = { static const struct sirfsoc_padmux vip_padmux = { .muxmask_counts = ARRAY_SIZE(vip_muxmask), .muxmask = vip_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(18), .funcval = BIT(18), }; @@ -654,6 +680,7 @@ static const struct sirfsoc_muxmask vip_noupli_muxmask[] = { static const struct sirfsoc_padmux vip_noupli_padmux = { .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask), .muxmask = vip_noupli_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(15), .funcval = BIT(15), }; @@ -684,6 +711,7 @@ static const struct sirfsoc_muxmask i2c1_muxmask[] = { static const struct sirfsoc_padmux i2c1_padmux = { .muxmask_counts = ARRAY_SIZE(i2c1_muxmask), .muxmask = i2c1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(16), .funcval = 0, }; @@ -700,6 +728,7 @@ static const struct sirfsoc_muxmask pwm0_muxmask[] = { static const struct sirfsoc_padmux pwm0_padmux = { .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), .muxmask = pwm0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(12), .funcval = 0, }; @@ -772,6 +801,7 @@ static const struct sirfsoc_muxmask warm_rst_muxmask[] = { static const struct sirfsoc_padmux warm_rst_padmux = { .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask), .muxmask = warm_rst_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(4), .funcval = 0, }; @@ -789,6 +819,7 @@ static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = { static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = { .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask), .muxmask = usb0_upli_drvbus_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(18), .funcval = 0, }; @@ -805,12 +836,31 @@ static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), .muxmask = usb1_utmi_drvbus_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(11), .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ }; static const unsigned usb1_utmi_drvbus_pins[] = { 28 }; +static const struct sirfsoc_padmux usb1_dp_dn_padmux = { + .muxmask_counts = 0, + .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE, + .funcmask = BIT(2), + .funcval = BIT(2), +}; + +static const unsigned usb1_dp_dn_pins[] = { 103, 104 }; + +static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = { + .muxmask_counts = 0, + .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE, + .funcmask = BIT(2), + .funcval = 0, +}; + +static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 }; + static const struct sirfsoc_muxmask pulse_count_muxmask[] = { { .group = 0, @@ -859,6 +909,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins), SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), + SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins), + SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins), @@ -903,6 +955,8 @@ static const char * const sdmmc5grp[] = { "sdmmc5grp" }; static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" }; static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" }; static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; +static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; +static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; static const char * const pulse_countgrp[] = { "pulse_countgrp" }; static const char * const i2sgrp[] = { "i2sgrp" }; static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; @@ -949,6 +1003,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux), SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux), SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), + SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), + SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c index 241d83992692..050777be0f1e 100644 --- a/drivers/pinctrl/sirf/pinctrl-prima2.c +++ b/drivers/pinctrl/sirf/pinctrl-prima2.c @@ -126,6 +126,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = { PINCTRL_PIN(112, "x_ldd[13]"), PINCTRL_PIN(113, "x_ldd[14]"), PINCTRL_PIN(114, "x_ldd[15]"), + + PINCTRL_PIN(115, "x_usb1_dp"), + PINCTRL_PIN(116, "x_usb1_dn"), }; static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { @@ -143,6 +146,7 @@ static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { static const struct sirfsoc_padmux lcd_16bits_padmux = { .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), .muxmask = lcd_16bits_sirfsoc_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(4), .funcval = 0, }; @@ -168,6 +172,7 @@ static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { static const struct sirfsoc_padmux lcd_18bits_padmux = { .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), .muxmask = lcd_18bits_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(4), .funcval = 0, }; @@ -193,6 +198,7 @@ static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { static const struct sirfsoc_padmux lcd_24bits_padmux = { .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), .muxmask = lcd_24bits_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(4), .funcval = 0, }; @@ -218,6 +224,7 @@ static const struct sirfsoc_muxmask lcdrom_muxmask[] = { static const struct sirfsoc_padmux lcdrom_padmux = { .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), .muxmask = lcdrom_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(4), .funcval = BIT(4), }; @@ -238,6 +245,7 @@ static const struct sirfsoc_muxmask uart0_muxmask[] = { static const struct sirfsoc_padmux uart0_padmux = { .muxmask_counts = ARRAY_SIZE(uart0_muxmask), .muxmask = uart0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(9), .funcval = BIT(9), }; @@ -282,6 +290,7 @@ static const struct sirfsoc_muxmask uart2_muxmask[] = { static const struct sirfsoc_padmux uart2_padmux = { .muxmask_counts = ARRAY_SIZE(uart2_muxmask), .muxmask = uart2_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(10), .funcval = BIT(10), }; @@ -315,6 +324,7 @@ static const struct sirfsoc_muxmask sdmmc3_muxmask[] = { static const struct sirfsoc_padmux sdmmc3_padmux = { .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), .muxmask = sdmmc3_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(7), .funcval = 0, }; @@ -331,6 +341,7 @@ static const struct sirfsoc_muxmask spi0_muxmask[] = { static const struct sirfsoc_padmux spi0_padmux = { .muxmask_counts = ARRAY_SIZE(spi0_muxmask), .muxmask = spi0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(7), .funcval = BIT(7), }; @@ -361,6 +372,7 @@ static const struct sirfsoc_muxmask cko1_muxmask[] = { static const struct sirfsoc_padmux cko1_padmux = { .muxmask_counts = ARRAY_SIZE(cko1_muxmask), .muxmask = cko1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(3), .funcval = 0, }; @@ -379,6 +391,7 @@ static const struct sirfsoc_muxmask i2s_muxmask[] = { static const struct sirfsoc_padmux i2s_padmux = { .muxmask_counts = ARRAY_SIZE(i2s_muxmask), .muxmask = i2s_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(3) | BIT(9), .funcval = BIT(3), }; @@ -395,6 +408,7 @@ static const struct sirfsoc_muxmask ac97_muxmask[] = { static const struct sirfsoc_padmux ac97_padmux = { .muxmask_counts = ARRAY_SIZE(ac97_muxmask), .muxmask = ac97_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(8), .funcval = 0, }; @@ -411,6 +425,7 @@ static const struct sirfsoc_muxmask spi1_muxmask[] = { static const struct sirfsoc_padmux spi1_padmux = { .muxmask_counts = ARRAY_SIZE(spi1_muxmask), .muxmask = spi1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(8), .funcval = BIT(8), }; @@ -441,6 +456,7 @@ static const struct sirfsoc_muxmask gps_muxmask[] = { static const struct sirfsoc_padmux gps_padmux = { .muxmask_counts = ARRAY_SIZE(gps_muxmask), .muxmask = gps_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(12) | BIT(13) | BIT(14), .funcval = BIT(12), }; @@ -463,6 +479,7 @@ static const struct sirfsoc_muxmask sdmmc5_muxmask[] = { static const struct sirfsoc_padmux sdmmc5_padmux = { .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), .muxmask = sdmmc5_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(13) | BIT(14), .funcval = BIT(13) | BIT(14), }; @@ -479,6 +496,7 @@ static const struct sirfsoc_muxmask usp0_muxmask[] = { static const struct sirfsoc_padmux usp0_padmux = { .muxmask_counts = ARRAY_SIZE(usp0_muxmask), .muxmask = usp0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9), .funcval = 0, }; @@ -509,6 +527,7 @@ static const struct sirfsoc_muxmask usp1_muxmask[] = { static const struct sirfsoc_padmux usp1_padmux = { .muxmask_counts = ARRAY_SIZE(usp1_muxmask), .muxmask = usp1_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11), .funcval = 0, }; @@ -542,6 +561,7 @@ static const struct sirfsoc_muxmask usp2_muxmask[] = { static const struct sirfsoc_padmux usp2_padmux = { .muxmask_counts = ARRAY_SIZE(usp2_muxmask), .muxmask = usp2_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(13) | BIT(14), .funcval = 0, }; @@ -572,6 +592,7 @@ static const struct sirfsoc_muxmask nand_muxmask[] = { static const struct sirfsoc_padmux nand_padmux = { .muxmask_counts = ARRAY_SIZE(nand_muxmask), .muxmask = nand_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(5), .funcval = 0, }; @@ -580,6 +601,7 @@ static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 }; static const struct sirfsoc_padmux sdmmc0_padmux = { .muxmask_counts = 0, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(5), .funcval = 0, }; @@ -596,6 +618,7 @@ static const struct sirfsoc_muxmask sdmmc2_muxmask[] = { static const struct sirfsoc_padmux sdmmc2_padmux = { .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), .muxmask = sdmmc2_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(5), .funcval = BIT(5), }; @@ -628,6 +651,7 @@ static const struct sirfsoc_muxmask vip_muxmask[] = { static const struct sirfsoc_padmux vip_padmux = { .muxmask_counts = ARRAY_SIZE(vip_muxmask), .muxmask = vip_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(0), .funcval = 0, }; @@ -677,6 +701,7 @@ static const struct sirfsoc_muxmask viprom_muxmask[] = { static const struct sirfsoc_padmux viprom_padmux = { .muxmask_counts = ARRAY_SIZE(viprom_muxmask), .muxmask = viprom_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(0), .funcval = BIT(0), }; @@ -693,6 +718,7 @@ static const struct sirfsoc_muxmask pwm0_muxmask[] = { static const struct sirfsoc_padmux pwm0_padmux = { .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), .muxmask = pwm0_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(12), .funcval = 0, }; @@ -764,6 +790,7 @@ static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = { static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = { .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask), .muxmask = usb0_utmi_drvbus_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(6), .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */ }; @@ -780,12 +807,31 @@ static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), .muxmask = usb1_utmi_drvbus_muxmask, + .ctrlreg = SIRFSOC_RSC_PIN_MUX, .funcmask = BIT(11), .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ }; static const unsigned usb1_utmi_drvbus_pins[] = { 59 }; +static const struct sirfsoc_padmux usb1_dp_dn_padmux = { + .muxmask_counts = 0, + .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE, + .funcmask = BIT(2), + .funcval = BIT(2), +}; + +static const unsigned usb1_dp_dn_pins[] = { 115, 116 }; + +static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = { + .muxmask_counts = 0, + .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE, + .funcmask = BIT(2), + .funcval = 0, +}; + +static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 }; + static const struct sirfsoc_muxmask pulse_count_muxmask[] = { { .group = 0, @@ -838,6 +884,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins), SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), + SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins), + SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), @@ -884,6 +932,8 @@ static const char * const sdmmc4grp[] = { "sdmmc4grp" }; static const char * const sdmmc5grp[] = { "sdmmc5grp" }; static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" }; static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; +static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; +static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; static const char * const pulse_countgrp[] = { "pulse_countgrp" }; static const char * const i2sgrp[] = { "i2sgrp" }; static const char * const ac97grp[] = { "ac97grp" }; @@ -930,6 +980,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), + SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), + SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 26f946af7933..b81e388c50de 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -166,12 +166,12 @@ static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector if (mux->funcmask && enable) { u32 func_en_val; + func_en_val = - readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); + readl(spmx->rsc_virtbase + mux->ctrlreg); func_en_val = - (func_en_val & ~mux->funcmask) | (mux-> - funcval); - writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); + (func_en_val & ~mux->funcmask) | (mux->funcval); + writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg); } } diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h index 17cc108510ba..d7f16b499ad9 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.h +++ b/drivers/pinctrl/sirf/pinctrl-sirf.h @@ -9,8 +9,9 @@ #ifndef __PINMUX_SIRF_H__ #define __PINMUX_SIRF_H__ -#define SIRFSOC_NUM_PADS 622 -#define SIRFSOC_RSC_PIN_MUX 0x4 +#define SIRFSOC_NUM_PADS 622 +#define SIRFSOC_RSC_USB_UART_SHARE 0 +#define SIRFSOC_RSC_PIN_MUX 0x4 #define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) #define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90) @@ -61,6 +62,7 @@ struct sirfsoc_padmux { unsigned long muxmask_counts; const struct sirfsoc_muxmask *muxmask; /* RSC_PIN_MUX set */ + unsigned long ctrlreg; unsigned long funcmask; unsigned long funcval; }; -- cgit v1.2.3 From a9f10ca76d784023fc45f01f025b54e9960f4ec1 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Fri, 11 Oct 2013 22:04:23 +0100 Subject: of: Add testcases for interrupt parsing This patch extends the DT selftest code with some test cases for the interrupt parsing functions. Signed-off-by: Grant Likely --- arch/arm/boot/dts/testcases/tests-interrupts.dtsi | 41 ++++++++++ arch/arm/boot/dts/testcases/tests.dtsi | 1 + drivers/of/selftest.c | 91 +++++++++++++++++++++-- 3 files changed, 127 insertions(+), 6 deletions(-) create mode 100644 arch/arm/boot/dts/testcases/tests-interrupts.dtsi (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi b/arch/arm/boot/dts/testcases/tests-interrupts.dtsi new file mode 100644 index 000000000000..6ecda716e9d4 --- /dev/null +++ b/arch/arm/boot/dts/testcases/tests-interrupts.dtsi @@ -0,0 +1,41 @@ + +/ { + testcase-data { + interrupts { + #address-cells = <0>; + test_intc0: intc0 { + interrupt-controller; + #interrupt-cells = <1>; + }; + + test_intc1: intc1 { + interrupt-controller; + #interrupt-cells = <3>; + }; + + test_intc2: intc2 { + interrupt-controller; + #interrupt-cells = <2>; + }; + + test_intmap0: intmap0 { + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-map = <1 &test_intc0 9>, + <2 &test_intc1 10 11 12>, + <3 &test_intc2 13 14>, + <4 &test_intc2 15 16>; + }; + + interrupts0 { + interrupt-parent = <&test_intc0>; + interrupts = <1>, <2>, <3>, <4>; + }; + + interrupts1 { + interrupt-parent = <&test_intmap0>; + interrupts = <1>, <2>, <3>, <4>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/testcases/tests.dtsi b/arch/arm/boot/dts/testcases/tests.dtsi index a7c5067622e8..3f123ecc9dd7 100644 --- a/arch/arm/boot/dts/testcases/tests.dtsi +++ b/arch/arm/boot/dts/testcases/tests.dtsi @@ -1 +1,2 @@ /include/ "tests-phandle.dtsi" +/include/ "tests-interrupts.dtsi" diff --git a/drivers/of/selftest.c b/drivers/of/selftest.c index 0eb5c38b4e07..9c80f0b7556b 100644 --- a/drivers/of/selftest.c +++ b/drivers/of/selftest.c @@ -9,18 +9,24 @@ #include #include #include +#include #include #include #include #include -static bool selftest_passed = true; +static struct selftest_results { + int passed; + int failed; +} selftest_results; + #define selftest(result, fmt, ...) { \ if (!(result)) { \ - pr_err("FAIL %s:%i " fmt, __FILE__, __LINE__, ##__VA_ARGS__); \ - selftest_passed = false; \ + selftest_results.failed++; \ + pr_err("FAIL %s():%i " fmt, __func__, __LINE__, ##__VA_ARGS__); \ } else { \ - pr_info("pass %s:%i\n", __FILE__, __LINE__); \ + selftest_results.passed++; \ + pr_debug("pass %s():%i\n", __func__, __LINE__); \ } \ } @@ -131,7 +137,6 @@ static void __init of_selftest_property_match_string(void) struct device_node *np; int rc; - pr_info("start\n"); np = of_find_node_by_path("/testcase-data/phandle-tests/consumer-a"); if (!np) { pr_err("No testcase data in device tree\n"); @@ -154,6 +159,78 @@ static void __init of_selftest_property_match_string(void) selftest(rc == -EILSEQ, "unterminated string; rc=%i", rc); } +static void __init of_selftest_parse_interrupts(void) +{ + struct device_node *np; + struct of_phandle_args args; + int i, rc; + + np = of_find_node_by_path("/testcase-data/interrupts/interrupts0"); + if (!np) { + pr_err("missing testcase data\n"); + return; + } + + for (i = 0; i < 4; i++) { + bool passed = true; + args.args_count = 0; + rc = of_irq_parse_one(np, i, &args); + + passed &= !rc; + passed &= (args.args_count == 1); + passed &= (args.args[0] == (i + 1)); + + selftest(passed, "index %i - data error on node %s rc=%i\n", + i, args.np->full_name, rc); + } + of_node_put(np); + + np = of_find_node_by_path("/testcase-data/interrupts/interrupts1"); + if (!np) { + pr_err("missing testcase data\n"); + return; + } + + for (i = 0; i < 4; i++) { + bool passed = true; + args.args_count = 0; + rc = of_irq_parse_one(np, i, &args); + + /* Test the values from tests-phandle.dtsi */ + switch (i) { + case 0: + passed &= !rc; + passed &= (args.args_count == 1); + passed &= (args.args[0] == 9); + break; + case 1: + passed &= !rc; + passed &= (args.args_count == 3); + passed &= (args.args[0] == 10); + passed &= (args.args[1] == 11); + passed &= (args.args[2] == 12); + break; + case 2: + passed &= !rc; + passed &= (args.args_count == 2); + passed &= (args.args[0] == 13); + passed &= (args.args[1] == 14); + break; + case 3: + passed &= !rc; + passed &= (args.args_count == 2); + passed &= (args.args[0] == 15); + passed &= (args.args[1] == 16); + break; + default: + passed = false; + } + selftest(passed, "index %i - data error on node %s rc=%i\n", + i, args.np->full_name, rc); + } + of_node_put(np); +} + static int __init of_selftest(void) { struct device_node *np; @@ -168,7 +245,9 @@ static int __init of_selftest(void) pr_info("start of selftest - you will see error messages\n"); of_selftest_parse_phandle_with_args(); of_selftest_property_match_string(); - pr_info("end of selftest - %s\n", selftest_passed ? "PASS" : "FAIL"); + of_selftest_parse_interrupts(); + pr_info("end of selftest - %i passed, %i failed\n", + selftest_results.passed, selftest_results.failed); return 0; } late_initcall(of_selftest); -- cgit v1.2.3 From 79d9701559a9f3e9b2021fbd292f5e70ad75f686 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 19 Sep 2013 16:47:37 -0500 Subject: of/irq: create interrupts-extended property The standard interrupts property in device tree can only handle interrupts coming from a single interrupt parent. If a device is wired to multiple interrupt controllers, then it needs to be attached to a node with an interrupt-map property to demux the interrupt specifiers which is confusing. It would be a lot easier if there was a form of the interrupts property that allows for a separate interrupt phandle for each interrupt specifier. This patch does exactly that by creating a new interrupts-extended property which reuses the phandle+arguments pattern used by GPIOs and other core bindings. Signed-off-by: Grant Likely Acked-by: Tony Lindgren Acked-by: Kumar Gala [grant.likely: removed versatile platform hunks into separate patch] Cc: Rob Herring --- .../bindings/interrupt-controller/interrupts.txt | 29 +++++++-- arch/arm/boot/dts/testcases/tests-interrupts.dtsi | 16 +++++ drivers/of/irq.c | 16 +++-- drivers/of/selftest.c | 70 ++++++++++++++++++++++ 4 files changed, 120 insertions(+), 11 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt index 72a06c0ab1db..1486497a24c1 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt @@ -4,16 +4,33 @@ Specifying interrupt information for devices 1) Interrupt client nodes ------------------------- -Nodes that describe devices which generate interrupts must contain an -"interrupts" property. This property must contain a list of interrupt -specifiers, one per output interrupt. The format of the interrupt specifier is -determined by the interrupt controller to which the interrupts are routed; see -section 2 below for details. +Nodes that describe devices which generate interrupts must contain an either an +"interrupts" property or an "interrupts-extended" property. These properties +contain a list of interrupt specifiers, one per output interrupt. The format of +the interrupt specifier is determined by the interrupt controller to which the +interrupts are routed; see section 2 below for details. + + Example: + interrupt-parent = <&intc1>; + interrupts = <5 0>, <6 0>; The "interrupt-parent" property is used to specify the controller to which interrupts are routed and contains a single phandle referring to the interrupt controller node. This property is inherited, so it may be specified in an -interrupt client node or in any of its parent nodes. +interrupt client node or in any of its parent nodes. Interrupts listed in the +"interrupts" property are always in reference to the node's interrupt parent. + +The "interrupts-extended" property is a special form for use when a node needs +to reference multiple interrupt parents. Each entry in this property contains +both the parent phandle and the interrupt specifier. "interrupts-extended" +should only be used when a device has multiple interrupt parents. + + Example: + interrupts-extended = <&intc1 5 1>, <&intc2 1 0>; + +A device node may contain either "interrupts" or "interrupts-extended", but not +both. If both properties are present, then the operating system should log an +error and use only the data in "interrupts". 2) Interrupt controller nodes ----------------------------- diff --git a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi b/arch/arm/boot/dts/testcases/tests-interrupts.dtsi index 6ecda716e9d4..560d6bf680b6 100644 --- a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi +++ b/arch/arm/boot/dts/testcases/tests-interrupts.dtsi @@ -27,6 +27,12 @@ <4 &test_intc2 15 16>; }; + test_intmap1: intmap1 { + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-map = <1 2 &test_intc0 15>; + }; + interrupts0 { interrupt-parent = <&test_intc0>; interrupts = <1>, <2>, <3>, <4>; @@ -36,6 +42,16 @@ interrupt-parent = <&test_intmap0>; interrupts = <1>, <2>, <3>, <4>; }; + + interrupts-extended0 { + interrupts-extended = <&test_intc0 1>, + <&test_intc1 2 3 4>, + <&test_intc2 5 6>, + <&test_intmap0 1>, + <&test_intmap0 2>, + <&test_intmap0 3>, + <&test_intmap1 1 2>; + }; }; }; }; diff --git a/drivers/of/irq.c b/drivers/of/irq.c index 7c4ff122785f..8cc62b4a7988 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -292,17 +292,23 @@ int of_irq_parse_one(struct device_node *device, int index, struct of_phandle_ar if (of_irq_workarounds & OF_IMAP_OLDWORLD_MAC) return of_irq_parse_oldworld(device, index, out_irq); + /* Get the reg property (if any) */ + addr = of_get_property(device, "reg", NULL); + /* Get the interrupts property */ intspec = of_get_property(device, "interrupts", &intlen); - if (intspec == NULL) - return -EINVAL; + if (intspec == NULL) { + /* Try the new-style interrupts-extended */ + res = of_parse_phandle_with_args(device, "interrupts-extended", + "#interrupt-cells", index, out_irq); + if (res) + return -EINVAL; + return of_irq_parse_raw(addr, out_irq); + } intlen /= sizeof(*intspec); pr_debug(" intspec=%d intlen=%d\n", be32_to_cpup(intspec), intlen); - /* Get the reg property (if any) */ - addr = of_get_property(device, "reg", NULL); - /* Look for the interrupt parent. */ p = of_irq_find_parent(device); if (p == NULL) diff --git a/drivers/of/selftest.c b/drivers/of/selftest.c index 9c80f0b7556b..e21012bde639 100644 --- a/drivers/of/selftest.c +++ b/drivers/of/selftest.c @@ -231,6 +231,75 @@ static void __init of_selftest_parse_interrupts(void) of_node_put(np); } +static void __init of_selftest_parse_interrupts_extended(void) +{ + struct device_node *np; + struct of_phandle_args args; + int i, rc; + + np = of_find_node_by_path("/testcase-data/interrupts/interrupts-extended0"); + if (!np) { + pr_err("missing testcase data\n"); + return; + } + + for (i = 0; i < 7; i++) { + bool passed = true; + rc = of_irq_parse_one(np, i, &args); + + /* Test the values from tests-phandle.dtsi */ + switch (i) { + case 0: + passed &= !rc; + passed &= (args.args_count == 1); + passed &= (args.args[0] == 1); + break; + case 1: + passed &= !rc; + passed &= (args.args_count == 3); + passed &= (args.args[0] == 2); + passed &= (args.args[1] == 3); + passed &= (args.args[2] == 4); + break; + case 2: + passed &= !rc; + passed &= (args.args_count == 2); + passed &= (args.args[0] == 5); + passed &= (args.args[1] == 6); + break; + case 3: + passed &= !rc; + passed &= (args.args_count == 1); + passed &= (args.args[0] == 9); + break; + case 4: + passed &= !rc; + passed &= (args.args_count == 3); + passed &= (args.args[0] == 10); + passed &= (args.args[1] == 11); + passed &= (args.args[2] == 12); + break; + case 5: + passed &= !rc; + passed &= (args.args_count == 2); + passed &= (args.args[0] == 13); + passed &= (args.args[1] == 14); + break; + case 6: + passed &= !rc; + passed &= (args.args_count == 1); + passed &= (args.args[0] == 15); + break; + default: + passed = false; + } + + selftest(passed, "index %i - data error on node %s rc=%i\n", + i, args.np->full_name, rc); + } + of_node_put(np); +} + static int __init of_selftest(void) { struct device_node *np; @@ -246,6 +315,7 @@ static int __init of_selftest(void) of_selftest_parse_phandle_with_args(); of_selftest_property_match_string(); of_selftest_parse_interrupts(); + of_selftest_parse_interrupts_extended(); pr_info("end of selftest - %i passed, %i failed\n", selftest_results.passed, selftest_results.failed); return 0; -- cgit v1.2.3 From 0976c946a610d06e907335b7a3afa6db046f8e1b Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Mon, 28 Oct 2013 16:50:11 -0700 Subject: arm/versatile: Fix versatile irq specifications. Two of the versatile irq definitions are incorrect, mostly because two devices have connections to more than one interrupt controller. Fix them by using the new interrupts-extended property to fan out without using an awful interrupt-map nexus node. Signed-off-by: Grant Likely --- arch/arm/boot/dts/versatile-ab.dts | 2 +- arch/arm/boot/dts/versatile-pb.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index dde75ae8b4b1..e01e5a081def 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts @@ -185,7 +185,7 @@ mmc@5000 { compatible = "arm,primecell"; reg = < 0x5000 0x1000>; - interrupts = <22 34>; + interrupts-extended = <&vic 22 &sic 2>; }; kmi@6000 { compatible = "arm,pl050", "arm,primecell"; diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts index 7e8175269064..f43907c40c93 100644 --- a/arch/arm/boot/dts/versatile-pb.dts +++ b/arch/arm/boot/dts/versatile-pb.dts @@ -41,7 +41,7 @@ mmc@b000 { compatible = "arm,primecell"; reg = <0xb000 0x1000>; - interrupts = <23 34>; + interrupts-extended = <&vic 23 &sic 2>; }; }; }; -- cgit v1.2.3 From 78119fd1068cc068f6112a57a5f6de0e5b20245a Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Fri, 1 Nov 2013 10:50:50 -0700 Subject: of/irq: Fix bug in interrupt parsing refactor. Commit 2361613206e6, "of/irq: Refactor interrupt-map parsing" introduced a bug. The irq parsing will fail for some nodes that don't have a reg property. It is fixed by deferring the check for reg until it is actually needed. Also adjust the testcase data to catch the bug. Signed-off-by: Grant Likely Tested-by: Stephen Warren Tested-by: Ming Lei Tested-by: Stephen Warren Cc: Rob Herring --- arch/arm/boot/dts/testcases/tests-interrupts.dtsi | 7 ++++--- drivers/of/irq.c | 20 ++++++++++---------- 2 files changed, 14 insertions(+), 13 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi b/arch/arm/boot/dts/testcases/tests-interrupts.dtsi index 560d6bf680b6..c843720bd3e5 100644 --- a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi +++ b/arch/arm/boot/dts/testcases/tests-interrupts.dtsi @@ -2,7 +2,8 @@ / { testcase-data { interrupts { - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <1>; test_intc0: intc0 { interrupt-controller; #interrupt-cells = <1>; @@ -29,8 +30,7 @@ test_intmap1: intmap1 { #interrupt-cells = <2>; - #address-cells = <0>; - interrupt-map = <1 2 &test_intc0 15>; + interrupt-map = <0x5000 1 2 &test_intc0 15>; }; interrupts0 { @@ -44,6 +44,7 @@ }; interrupts-extended0 { + reg = <0x5000 0x100>; interrupts-extended = <&test_intc0 1>, <&test_intc1 2 3 4>, <&test_intc2 5 6>, diff --git a/drivers/of/irq.c b/drivers/of/irq.c index 8cc62b4a7988..52dba6a01423 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -147,18 +147,9 @@ int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq) pr_debug(" -> addrsize=%d\n", addrsize); - /* If we were passed no "reg" property and we attempt to parse - * an interrupt-map, then #address-cells must be 0. - * Fail if it's not. - */ - if (addr == NULL && addrsize != 0) { - pr_debug(" -> no reg passed in when needed !\n"); - return -EINVAL; - } - /* Precalculate the match array - this simplifies match loop */ for (i = 0; i < addrsize; i++) - initial_match_array[i] = addr[i]; + initial_match_array[i] = addr ? addr[i] : 0; for (i = 0; i < intsize; i++) initial_match_array[addrsize + i] = cpu_to_be32(out_irq->args[i]); @@ -174,6 +165,15 @@ int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq) return 0; } + /* + * interrupt-map parsing does not work without a reg + * property when #address-cells != 0 + */ + if (addrsize && !addr) { + pr_debug(" -> no reg passed in when needed !\n"); + goto fail; + } + /* Now look for an interrupt-map */ imap = of_get_property(ipar, "interrupt-map", &imaplen); /* No interrupt map, check for an interrupt parent */ -- cgit v1.2.3