From 4a5a27116b447d00d0a0d3f554ea37ffe387657f Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Date: Sun, 17 Sep 2017 18:45:22 +0200 Subject: ARM: dts: meson8: add support for booting the secondary CPU cores Booting the secondary CPU cores involves the following nodes/devices: - SCU (Snoop-Control-Unit, for which we already have a DT node) - a reset line for each CPU core, provided by the reset-controller which is built into the clock-controller - the PMU (power management unit) which controls the power of the CPU cores - a range in the SRAM specifically reserved for booting secondary CPU cores - the "enable-method" which activates booting the secondary CPU cores This adds all required nodes and properties to boot the secondary CPU cores. Suggested-by: Carlo Caione <carlo@caione.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> --- arch/arm/boot/dts/meson8.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index e6abcc7a1084..871d48d67190 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -45,6 +45,7 @@ #include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/gpio/meson8-gpio.h> +#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> #include "meson.dtsi" / { @@ -60,6 +61,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x200>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; }; cpu@201 { @@ -67,6 +70,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x201>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; }; cpu@202 { @@ -74,6 +79,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x202>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; }; cpu@203 { @@ -81,6 +88,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x203>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; }; }; @@ -118,6 +127,11 @@ }; /* end of / */ &aobus { + pmu: pmu@e0 { + compatible = "amlogic,meson8-pmu", "syscon"; + reg = <0xe0 0x8>; + }; + pinctrl_aobus: pinctrl@84 { compatible = "amlogic,meson8-aobus-pinctrl"; reg = <0x84 0xc>; @@ -254,6 +268,13 @@ }; }; +&ahb_sram { + smp-sram@1ff80 { + compatible = "amlogic,meson8-smp-sram"; + reg = <0x1ff80 0x8>; + }; +}; + ðmac { clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; -- cgit v1.2.3