From 4fa5518c65df7a2c4b6c58061ac53d0b01228042 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Sat, 5 Jun 2010 15:16:17 +0800 Subject: [ARM] pxa: remove now unnecessary dma_needs_bounce() With a correct dev->dma_mask before calling dmabounce_register_dev(), dma_needs_bounce() is not necessary. The sa1111, though, is a bit complicated. Until it's fully understood and fixed, dma_needs_bounce() for sa1111 is kept if CONFIG_SA1111 is enabled with no side effect (with the condition of machine_is_*) Thanks for Mike Rapoport to fix one error in the original version of the patch and get this tested. Acked-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/include/asm/dma-mapping.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 69ce0727edb5..b5ccc6a993d5 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -298,7 +298,15 @@ extern void dmabounce_unregister_dev(struct device *); * DMA access and 1 if the buffer needs to be bounced. * */ +#ifdef CONFIG_SA1111 extern int dma_needs_bounce(struct device*, dma_addr_t, size_t); +#else +static inline int dma_needs_bounce(struct device *dev, dma_addr_t addr, + size_t size) +{ + return 0; +} +#endif /* * The DMA API, implemented by dmabounce.c. See below for descriptions. -- cgit v1.2.3 From 983536e7b5275d5d8a63c18b5632d9ce0771caa0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 24 Jun 2010 16:02:11 +0200 Subject: [ARM] scoop: Add CPR register bit definitions Add bit definitions of the CPR register of the SCOOP chip into scoop.h. Also, cleanup the GPCR definitions to match coding style. Signed-off-by: Marek Vasut Signed-off-by: Eric Miao --- arch/arm/include/asm/hardware/scoop.h | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h index 46492a63a7c4..ebb3ceaa8fac 100644 --- a/arch/arm/include/asm/hardware/scoop.h +++ b/arch/arm/include/asm/hardware/scoop.h @@ -22,18 +22,23 @@ #define SCOOP_GPWR 0x24 #define SCOOP_GPRR 0x28 -#define SCOOP_GPCR_PA22 ( 1 << 12 ) -#define SCOOP_GPCR_PA21 ( 1 << 11 ) -#define SCOOP_GPCR_PA20 ( 1 << 10 ) -#define SCOOP_GPCR_PA19 ( 1 << 9 ) -#define SCOOP_GPCR_PA18 ( 1 << 8 ) -#define SCOOP_GPCR_PA17 ( 1 << 7 ) -#define SCOOP_GPCR_PA16 ( 1 << 6 ) -#define SCOOP_GPCR_PA15 ( 1 << 5 ) -#define SCOOP_GPCR_PA14 ( 1 << 4 ) -#define SCOOP_GPCR_PA13 ( 1 << 3 ) -#define SCOOP_GPCR_PA12 ( 1 << 2 ) -#define SCOOP_GPCR_PA11 ( 1 << 1 ) +#define SCOOP_CPR_OUT (1 << 7) +#define SCOOP_CPR_SD_3V (1 << 2) +#define SCOOP_CPR_CF_XV (1 << 1) +#define SCOOP_CPR_CF_3V (1 << 0) + +#define SCOOP_GPCR_PA22 (1 << 12) +#define SCOOP_GPCR_PA21 (1 << 11) +#define SCOOP_GPCR_PA20 (1 << 10) +#define SCOOP_GPCR_PA19 (1 << 9) +#define SCOOP_GPCR_PA18 (1 << 8) +#define SCOOP_GPCR_PA17 (1 << 7) +#define SCOOP_GPCR_PA16 (1 << 6) +#define SCOOP_GPCR_PA15 (1 << 5) +#define SCOOP_GPCR_PA14 (1 << 4) +#define SCOOP_GPCR_PA13 (1 << 3) +#define SCOOP_GPCR_PA12 (1 << 2) +#define SCOOP_GPCR_PA11 (1 << 1) struct scoop_config { unsigned short io_out; -- cgit v1.2.3 From 8dd47741d191400c46173ed9fba9d14b4033ce23 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 21 Jun 2010 15:10:37 +0100 Subject: ARM: 6189/1: Add support for the MOVW/MOVT relocations in Thumb-2 The patch adds handling case for the R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_ABS relocations in arch/arm/kernel/module.c. Such relocations may appear in Thumb-2 compiled kernel modules. Reported-by: Kyungmin Park Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/include/asm/elf.h | 2 ++ arch/arm/kernel/module.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index 6750b8e45a49..5747a8baa413 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -59,6 +59,8 @@ typedef struct user_fp elf_fpregset_t; #define R_ARM_THM_CALL 10 #define R_ARM_THM_JUMP24 30 +#define R_ARM_THM_MOVW_ABS_NC 47 +#define R_ARM_THM_MOVT_ABS 48 /* * These are used to set parameters in the core dumps. diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index c628bdf6c430..ae3c80453a09 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -237,6 +237,38 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, lower = *(u16 *)(loc + 2); break; + case R_ARM_THM_MOVW_ABS_NC: + case R_ARM_THM_MOVT_ABS: + upper = *(u16 *)loc; + lower = *(u16 *)(loc + 2); + + /* + * MOVT/MOVW instructions encoding in Thumb-2: + * + * i = upper[10] + * imm4 = upper[3:0] + * imm3 = lower[14:12] + * imm8 = lower[7:0] + * + * imm16 = imm4:i:imm3:imm8 + */ + offset = ((upper & 0x000f) << 12) | + ((upper & 0x0400) << 1) | + ((lower & 0x7000) >> 4) | (lower & 0x00ff); + offset = (offset ^ 0x8000) - 0x8000; + offset += sym->st_value; + + if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS) + offset >>= 16; + + *(u16 *)loc = (u16)((upper & 0xfbf0) | + ((offset & 0xf000) >> 12) | + ((offset & 0x0800) >> 1)); + *(u16 *)(loc + 2) = (u16)((lower & 0x8f00) | + ((offset & 0x0700) << 4) | + (offset & 0x00ff)); + break; + default: printk(KERN_ERR "%s: unknown relocation: %u\n", module->name, ELF32_R_TYPE(rel->r_info)); -- cgit v1.2.3 From 9e354ea8e0710baf05804168fdabe90231b3d363 Mon Sep 17 00:00:00 2001 From: Alexander Shishkin Date: Wed, 4 Aug 2010 11:25:20 +0100 Subject: ARM: 6292/1: coresight: add ETM management registers Add notion of ETM OS lock, save and restore registers. Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Alexander Shishkin Signed-off-by: Russell King --- arch/arm/include/asm/hardware/coresight.h | 8 ++++++-- arch/arm/kernel/etm.c | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h index f82b25d4f73e..212e47828c79 100644 --- a/arch/arm/include/asm/hardware/coresight.h +++ b/arch/arm/include/asm/hardware/coresight.h @@ -48,8 +48,6 @@ struct tracectx { /* CoreSight Component Registers */ #define CSCR_CLASS 0xff4 -#define CSCR_PRSR 0x314 - #define UNLOCK_MAGIC 0xc5acce55 /* ETM control register, "ETM Architecture", 3.3.1 */ @@ -132,6 +130,12 @@ struct tracectx { ETMCTRL_BRANCH_OUTPUT | \ ETMCTRL_DO_CONTEXTID) +/* ETM management registers, "ETM Architecture", 3.5.24 */ +#define ETMMR_OSLAR 0x300 +#define ETMMR_OSLSR 0x304 +#define ETMMR_OSSRR 0x308 +#define ETMMR_PDSR 0x314 + /* ETB registers, "CoreSight Components TRM", 9.3 */ #define ETBR_DEPTH 0x04 #define ETBR_STATUS 0x0c diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c index 827753966301..9e9db63c298a 100644 --- a/arch/arm/kernel/etm.c +++ b/arch/arm/kernel/etm.c @@ -543,7 +543,7 @@ static int __init etm_probe(struct amba_device *dev, struct amba_id *id) t->etm_portsz = 1; etm_unlock(t); - ret = etm_readl(t, CSCR_PRSR); + ret = etm_readl(t, ETMMR_PDSR); t->ncmppairs = etm_readl(t, ETMR_CONFCODE) & 0xf; etm_writel(t, 0x440, ETMR_CTRL); -- cgit v1.2.3 From cdf357f1e13a08a11261edacb3083746f65c1ed9 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Thu, 5 Aug 2010 11:20:51 +0100 Subject: ARM: 6299/1: errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID On versions of the Cortex-A9 prior to r2p0, performing TLB invalidations by ASID match can result in the incorrect ASID being broadcast to other CPUs. As a consequence of this, the targetted TLB entries are not invalidated across the system. This workaround changes the TLB flushing routines to invalidate entries regardless of the ASID. Cc: Tested-by: Rob Clark Acked-by: Catalin Marinas Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/Kconfig | 12 ++++++++++++ arch/arm/include/asm/tlbflush.h | 8 ++++++++ 2 files changed, 20 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 232f0c758252..e3956042892c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1040,6 +1040,18 @@ config PL310_ERRATA_588369 is not correctly implemented in PL310 as clean lines are not invalidated as a result of these operations. Note that this errata uses Texas Instrument's secure monitor api. + +config ARM_ERRATA_720789 + bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 720789 Cortex-A9 (prior to + r2p0) erratum. A faulty ASID can be sent to the other CPUs for the + broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. + As a consequence of this erratum, some TLB entries which should be + invalidated are not, resulting in an incoherency in the system page + tables. The workaround changes the TLB flushing routines to invalidate + entries regardless of the ASID. endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index bd863d8608cd..33b546ae72d4 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -378,7 +378,11 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) if (tlb_flag(TLB_V6_I_ASID)) asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); if (tlb_flag(TLB_V7_UIS_ASID)) +#ifdef CONFIG_ARM_ERRATA_720789 + asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc"); +#else asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc"); +#endif if (tlb_flag(TLB_BTB)) { /* flush the branch target cache */ @@ -424,7 +428,11 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) if (tlb_flag(TLB_V6_I_PAGE)) asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); if (tlb_flag(TLB_V7_UIS_PAGE)) +#ifdef CONFIG_ARM_ERRATA_720789 + asm("mcr p15, 0, %0, c8, c3, 3" : : "r" (uaddr & PAGE_MASK) : "cc"); +#else asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc"); +#endif if (tlb_flag(TLB_BTB)) { /* flush the branch target cache */ -- cgit v1.2.3