From ae51e609843f7d0aaeb1c2ad9f89d252a4899885 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Thu, 7 May 2009 16:18:40 +0100 Subject: [ARM] 5507/1: support R_ARM_MOVW_ABS_NC and MOVT_ABS relocation types From: Bruce Ashfield To fully support the armv7-a instruction set/optimizations, support for the R_ARM_MOVW_ABS_NC and R_ARM_MOVT_ABS relocation types is required. The MOVW and MOVT are both load-immediate instructions, MOVW loads 16 bits into the bottom half of a register, and MOVT loads 16 bits into the top half of a register. The relocation information for these instructions has a full 32 bit value, plus an addend which is stored in the 16 immediate bits in the instruction itself. The immediate bits in the instruction are not contiguous (the register # splits it into a 4 bit and 12 bit value), so the addend has to be extracted accordingly and added to the value. The value is then split and put into the instruction; a MOVW uses the bottom 16 bits of the value, and a MOVT uses the top 16 bits. Signed-off-by: David Borman Signed-off-by: Bruce Ashfield Signed-off-by: Paul Gortmaker Signed-off-by: Russell King --- arch/arm/kernel/module.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/kernel') diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index d1731e39b496..bac03c81489d 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -169,6 +169,21 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, *(u32 *)loc = offset & 0x7fffffff; break; + case R_ARM_MOVW_ABS_NC: + case R_ARM_MOVT_ABS: + offset = *(u32 *)loc; + offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff); + offset = (offset ^ 0x8000) - 0x8000; + + offset += sym->st_value; + if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS) + offset >>= 16; + + *(u32 *)loc &= 0xfff0f000; + *(u32 *)loc |= ((offset & 0xf000) << 4) | + (offset & 0x0fff); + break; + default: printk(KERN_ERR "%s: unknown relocation: %u\n", module->name, ELF32_R_TYPE(rel->r_info)); -- cgit v1.2.3