From a2a571b74a3881963d8d09deb272d13afe5b49e3 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 22 Oct 2010 18:55:39 +0200 Subject: AT91: pm: make sure that r0 is 0 when dealing with cache operations When using CP15 cache operations (c7), we make sure that Rd (r0) is actually 0 as ARM 926 TRM is saying. Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/pm.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-at91/pm.h') diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 2c4424bfa6c4..ce9a20699111 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -21,7 +21,8 @@ static inline u32 sdram_selfrefresh_enable(void) } #define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) -#define wait_for_interrupt_enable() asm("mcr p15, 0, r0, c7, c0, 4") +#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \ + : : "r" (0)) #elif defined(CONFIG_ARCH_AT91CAP9) #include -- cgit v1.2.3