From 0a26344440b5f9940c99112fdc3804f073b1f5a7 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Jul 2014 06:11:15 -0600 Subject: ARM: OMAP2+: clock: allow omap2_dpll_round_rate() to round to next-lowest rate Change the behavior of omap2_dpll_round_rate() to round to either the exact rate requested, or the next lowest rate that the clock is able to provide. This is not an ideal fix, but is intended to provide a relatively safe way for drivers to set PLL rates, until a better solution can be implemented. For the time being, omap3_noncore_dpll_set_rate() is still allowed to set its rate to something other than what the caller requested; but will warn when this occurs. Cc: Tomi Valkeinen Cc: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/dpll3xxx.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2/dpll3xxx.c') diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 6d7ba37e2257..b6860bfb05b3 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -478,6 +478,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct clk *new_parent = NULL; + unsigned long rrate; u16 freqsel = 0; struct dpll_data *dd; int ret; @@ -505,8 +506,16 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, __clk_prepare(dd->clk_ref); clk_enable(dd->clk_ref); - if (dd->last_rounded_rate != rate) - rate = __clk_round_rate(hw->clk, rate); + /* XXX this check is probably pointless in the CCF context */ + if (dd->last_rounded_rate != rate) { + rrate = __clk_round_rate(hw->clk, rate); + if (rrate != rate) { + pr_warn("%s: %s: final rate %lu does not match desired rate %lu\n", + __func__, __clk_get_name(hw->clk), + rrate, rate); + rate = rrate; + } + } if (dd->last_rounded_rate == 0) return -EINVAL; -- cgit v1.2.3