From 1721c70235f59ce75bfb34d7fa9fc11143ecdb78 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Tue, 20 Aug 2013 18:54:09 -0600 Subject: ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS In the original hwmod data file, DebugSS entry was disabled, since we didn't (and do not) have SW to control it. This patch enables it back with right data, so that it can be controlled by different ways; and the suggested method it to have modular driver for debugSS as well. Refer to the link for more discussion on handling of debugSS - https://patchwork.kernel.org/patch/2212111/ Signed-off-by: Vaibhav Hiremath Cc: Paul Walmsley Cc: Tony Lindgren Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 69 ++++++++++++++++++++---------- 1 file changed, 47 insertions(+), 22 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index eb2f3b93b51c..215894f8910d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -325,7 +325,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = { * * - cEFUSE (doesn't fall under any ocp_if) * - clkdiv32k - * - debugss * - ocp watch point */ #if 0 @@ -369,27 +368,6 @@ static struct omap_hwmod am33xx_clkdiv32k_hwmod = { }, }; -/* - * 'debugss' class - * debug sub system - */ -static struct omap_hwmod_class am33xx_debugss_hwmod_class = { - .name = "debugss", -}; - -static struct omap_hwmod am33xx_debugss_hwmod = { - .name = "debugss", - .class = &am33xx_debugss_hwmod_class, - .clkdm_name = "l3_aon_clkdm", - .main_clk = "debugss_ick", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* ocpwp */ static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { .name = "ocpwp", @@ -482,6 +460,34 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = { }, }; +/* + * 'debugss' class + * debug sub system + */ +static struct omap_hwmod_opt_clk debugss_opt_clks[] = { + { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" }, + { .role = "dbg_clka", .clk = "dbg_clka_ck" }, +}; + +static struct omap_hwmod_class am33xx_debugss_hwmod_class = { + .name = "debugss", +}; + +static struct omap_hwmod am33xx_debugss_hwmod = { + .name = "debugss", + .class = &am33xx_debugss_hwmod_class, + .clkdm_name = "l3_aon_clkdm", + .main_clk = "trace_clk_div_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = debugss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks), +}; + /* 'smartreflex' class */ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { .name = "smartreflex", @@ -1796,6 +1802,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main -> debugss */ +static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = { + { + .pa_start = 0x4b000000, + .pa_end = 0x4b000000 + SZ_16M - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_debugss_hwmod, + .clk = "dpll_core_m4_ck", + .addr = am33xx_debugss_addrs, + .user = OCP_USER_MPU, +}; + /* l4 wkup -> smartreflex0 */ static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { .master = &am33xx_l4_wkup_hwmod, @@ -2470,6 +2494,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_pruss__l3_main, &am33xx_wkup_m3__l4_wkup, &am33xx_gfx__l3_main, + &am33xx_l3_main__debugss, &am33xx_l4_wkup__wkup_m3, &am33xx_l4_wkup__control, &am33xx_l4_wkup__smartreflex0, -- cgit v1.2.3 From eeb6603fdde253a8e9129712ce24128d732bd4e7 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 23 Aug 2013 04:48:42 -0600 Subject: ARM: OMAP4: clock: Lock PLLs in the right sequence On OMAP4 we have clk_set_rate()s being done for a few DPLL clock nodes, as part of the clock init code, since the bootloaders no longer locks these DPLLs. So we have a clk_set_rate() done for a ABE DPLL node (which inturn locks it) followed by a clk_set_rate() for the USB DPLL. With USB DPLL being in bypass, we have this parent->child relationship thats formed while the clocks get registered. dpll_abe_ck | V dpll_abe_x2_ck | V dpll_abe_m3x2_ck | V usb_hs_clk_div_ck | V dpll_usb_ck This is because usb_hs_clk_div_ck is bypass clock for dpll_usb_ck. So with this parent->child relationship in place, a clk_set_rate() on ABE DPLL results eventually in a clk_set_rate() call on USB DPLL, because CCF does a clk_change_rate() (as part of clk_set_rate()) on all downstream clocks resulting from a rate change on the top clock. So its important that we lock USB DPLL before we lock ABE DPLL. Without which we see these error logs at boot. [These error logs will not be seen if using a bootloader that locks USB DPLL] [ 0.000000] clock: dpll_usb_ck failed transition to 'locked' [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack+0x10/0x14) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0+0x8/0x10) from [] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [] (clk_divider_set_rate+0x10/0x114) from [] (clk_change_rate+0x38/0xb8) [ 0.000000] [] (clk_change_rate+0x38/0xb8) from [] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack+0x10/0x14) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0+0x8/0x10) from [] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [] (clk_divider_set_rate+0x10/0x114) from [] (clk_change_rate+0x38/0xb8) [ 0.000000] [] (clk_change_rate+0x38/0xb8) from [] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack+0x10/0x14) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0+0x8/0x10) from [] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [] (clk_divider_set_rate+0x10/0x114) from [] (clk_change_rate+0x38/0xb8) [ 0.000000] [] (clk_change_rate+0x38/0xb8) from [] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack+0x10/0x14) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0+0x8/0x10) from [] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [] (clk_divider_set_rate+0x10/0x114) from [] (clk_change_rate+0x38/0xb8) [ 0.000000] [] (clk_change_rate+0x38/0xb8) from [] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack+0x10/0x14) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0+0x8/0x10) from [] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [] (clk_divider_set_rate+0x10/0x114) from [] (clk_change_rate+0x38/0xb8) [ 0.000000] [] (clk_change_rate+0x38/0xb8) from [] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [] (unwind_backtrace+0x0/0xf4) from [] (show_stack+0x10/0x14) [ 0.000000] [] (show_stack+0x10/0x14) from [] (Ldiv0+0x8/0x10) [ 0.000000] [] (Ldiv0+0x8/0x10) from [] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [] (clk_divider_set_rate+0x10/0x114) from [] (clk_change_rate+0x38/0xb8) [ 0.000000] [] (clk_change_rate+0x38/0xb8) from [] (clk_change_rate+0xa0/0xb8) [ 0.000000] clock: trace_clk_div_ck: could not find divisor for target rate 0 for parent pmd_trace_clk_mux_ck [ 0.000000] Division by zero in kernel. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/cclock44xx_data.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c index 88e37a474334..1d5b5290d2af 100644 --- a/arch/arm/mach-omap2/cclock44xx_data.c +++ b/arch/arm/mach-omap2/cclock44xx_data.c @@ -1706,6 +1706,18 @@ int __init omap4xxx_clk_init(void) omap2_clk_disable_autoidle_all(); + /* + * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL + * when its in bypass. So always lock USB before ABE DPLL. + */ + /* + * Lock USB DPLL on OMAP4 devices so that the L3INIT power + * domain can transition to retention state when not in use. + */ + rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ); + if (rc) + pr_err("%s: failed to configure USB DPLL!\n", __func__); + /* * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power * state when turning the ABE clock domain. Workaround this by @@ -1718,13 +1730,5 @@ int __init omap4xxx_clk_init(void) if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); - /* - * Lock USB DPLL on OMAP4 devices so that the L3INIT power - * domain can transition to retention state when not in use. - */ - rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ); - if (rc) - pr_err("%s: failed to configure USB DPLL!\n", __func__); - return 0; } -- cgit v1.2.3 From 0f0dd08932d4eb0fb336e6c2a48f27855b99ead2 Mon Sep 17 00:00:00 2001 From: Aida Mynzhasova Date: Fri, 23 Aug 2013 04:48:42 -0600 Subject: ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX This patch adds alwon powerdomain support for TI81XX, which is required for stable functioning of a big number of TI81XX subsystems. Signed-off-by: Aida Mynzhasova Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/powerdomains3xxx_data.c | 8 ++++++++ arch/arm/mach-omap2/prcm-common.h | 1 + 2 files changed, 9 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index e2d4bd804523..328c1037cb60 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -336,6 +336,13 @@ static struct powerdomain dpll5_pwrdm = { .voltdm = { .name = "core" }, }; +static struct powerdomain alwon_81xx_pwrdm = { + .name = "alwon_pwrdm", + .prcm_offs = TI81XX_PRM_ALWON_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "core" }, +}; + static struct powerdomain device_81xx_pwrdm = { .name = "device_pwrdm", .prcm_offs = TI81XX_PRM_DEVICE_MOD, @@ -442,6 +449,7 @@ static struct powerdomain *powerdomains_am35x[] __initdata = { }; static struct powerdomain *powerdomains_ti81xx[] __initdata = { + &alwon_81xx_pwrdm, &device_81xx_pwrdm, &active_816x_pwrdm, &default_816x_pwrdm, diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index ff1ac4a82a04..0e841fd9498a 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -58,6 +58,7 @@ #define TI816X_PRM_IVAHD1_MOD 0x0d00 #define TI816X_PRM_IVAHD2_MOD 0x0e00 #define TI816X_PRM_SGX_MOD 0x0f00 +#define TI81XX_PRM_ALWON_MOD 0x1800 /* 24XX register bits shared between CM & PRM registers */ -- cgit v1.2.3 From b84a76ae73b915124a5466035f187ab20a49fb6e Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 6 Aug 2013 14:03:03 +0530 Subject: ARM: OMAP: AM33xx: clock: Add RNG clock data Add clock data for RNG module on AM33xx SoC. Signed-off-by: Lokesh Vutla Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/cclock33xx_data.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index ba6534d7f155..865d30ee812f 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -421,6 +421,10 @@ static struct clk aes0_fck; DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL); DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null); +static struct clk rng_fck; +DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL); +DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null); + /* * Modules clock nodes * @@ -966,6 +970,7 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), CLK(NULL, "sha0_fck", &sha0_fck), CLK(NULL, "aes0_fck", &aes0_fck), + CLK(NULL, "rng_fck", &rng_fck), CLK(NULL, "timer1_fck", &timer1_fck), CLK(NULL, "timer2_fck", &timer2_fck), CLK(NULL, "timer3_fck", &timer3_fck), -- cgit v1.2.3