From e88ba436e5615f5bb94deecbbb924227b15bbebb Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 29 Apr 2020 17:30:02 +0300 Subject: ARM: OMAP5: Make L4SEC clock domain SWSUP only Commit c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP only') made DRA7 SoC L4SEC clock domain SWSUP only because of power state transition issues detected with HWSUP mode. Based on experimentation similar issue exists on OMAP5, so do the same change for OMAP5 also. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clockdomains54xx_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c index 3ab41fc89dd3..5611e08018a2 100644 --- a/arch/arm/mach-omap2/clockdomains54xx_data.c +++ b/arch/arm/mach-omap2/clockdomains54xx_data.c @@ -170,7 +170,7 @@ static struct clockdomain l4sec_54xx_clkdm = { .dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT, .wkdep_srcs = l4sec_wkup_sleep_deps, .sleepdep_srcs = l4sec_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain iva_54xx_clkdm = { -- cgit v1.2.3