From d3cd7d02e7133e2c0809c25d5321af21af695da4 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 17 Jan 2020 17:08:55 -0600 Subject: arm64: tegra: Kill off "simple-panel" compatibles "simple-panel" is a Linux driver and has never been an accepted upstream compatible string, so remove it. Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-tegra@vger.kernel.org Signed-off-by: Rob Herring Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index a0385a386a3f..9f3206c63900 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -990,7 +990,7 @@ }; panel: panel { - compatible = "innolux,n116bge", "simple-panel"; + compatible = "innolux,n116bge"; backlight = <&backlight>; ddc-i2c-bus = <&dpaux>; }; -- cgit v1.2.3 From bc8788b2f3a0c1adf1bdcde12bb5b5642e3e043e Mon Sep 17 00:00:00 2001 From: Nagarjuna Kristam Date: Thu, 16 Apr 2020 13:04:18 +0530 Subject: arm64: tegra: Add XUDC node on Tegra194 Tegra194 has one XUSB device mode controller which can be operated in HS and SS modes. Add a DT node for this XUSB device mode controller. Signed-off-by: Nagarjuna Kristam Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f4ede86e32b4..e1ae01c2d039 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -644,6 +644,24 @@ }; }; + usb@3550000 { + compatible = "nvidia,tegra194-xudc"; + reg = <0x03550000 0x8000>, + <0x03558000 0x1000>; + reg-names = "base", "fpci"; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA194_CLK_XUSB_SS>, + <&bpmp TEGRA194_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; + usb@3610000 { compatible = "nvidia,tegra194-xusb"; reg = <0x03610000 0x40000>, -- cgit v1.2.3 From cd9350c55b5b76a758eadd057891f1c4c4986fce Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Wed, 29 May 2019 16:21:39 +0800 Subject: arm64: tegra: Add external memory controller node for Tegra210 Add external memory controller (EMC) node for Tegra210 Signed-off-by: Joseph Lo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 64c46ce3849d..3fa92dd8350b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -895,6 +895,17 @@ #iommu-cells = <1>; }; + external-memory-controller@7001b000 { + compatible = "nvidia,tegra210-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>, + <0x0 0x7001e000 0x0 0x1000>, + <0x0 0x7001f000 0x0 0x1000>; + clocks = <&tegra_car TEGRA210_CLK_EMC>; + clock-names = "emc"; + interrupts = ; + nvidia,memory-controller = <&mc>; + }; + sata@70020000 { compatible = "nvidia,tegra210-ahci"; reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ -- cgit v1.2.3 From e12325f699e6fb396870e9479007fb0069574235 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 9 Apr 2020 19:34:29 +0200 Subject: arm64: tegra: Hook up EMC cooling device The external memory controller can be used as a cooling device for the LPDDR chips. Hook it up to the "mem" thermal zone of the SOCTHERM block so that temperature polling can be enabled on the EMC when a given temperature is exceeded. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 3fa92dd8350b..a550e7b828e6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -895,7 +895,7 @@ #iommu-cells = <1>; }; - external-memory-controller@7001b000 { + emc: external-memory-controller@7001b000 { compatible = "nvidia,tegra210-emc"; reg = <0x0 0x7001b000 0x0 0x1000>, <0x0 0x7001e000 0x0 0x1000>, @@ -904,6 +904,7 @@ clock-names = "emc"; interrupts = ; nvidia,memory-controller = <&mc>; + #cooling-cells = <2>; }; sata@70020000 { @@ -1561,6 +1562,18 @@ <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; trips { + dram_nominal: mem-nominal-trip { + temperature = <50000>; + hysteresis = <1000>; + type = "passive"; + }; + + dram_throttle: mem-throttle-trip { + temperature = <70000>; + hysteresis = <1000>; + type = "active"; + }; + mem-shutdown-trip { temperature = <103000>; hysteresis = <0>; @@ -1569,10 +1582,15 @@ }; cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ + dram-passive { + cooling-device = <&emc 0 0>; + trip = <&dram_nominal>; + }; + + dram-active { + cooling-device = <&emc 1 1>; + trip = <&dram_throttle>; + }; }; }; -- cgit v1.2.3 From bba25915b172c72f6fa635f091624d799e3c9cae Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 1 May 2020 08:27:56 +0100 Subject: arm64: tegra: Fix ethernet phy-mode for Jetson Xavier The 'phy-mode' property is currently defined as 'rgmii' for Jetson Xavier. This indicates that the RGMII RX and TX delays are set by the MAC and the internal delays set by the PHY are not used. If the Marvell PHY driver is enabled, such that it is used and not the generic PHY, ethernet failures are seen (DHCP is failing to obtain an IP address) and this is caused because the Marvell PHY driver is disabling the internal RX and TX delays. For Jetson Xavier the internal PHY RX and TX delay should be used and so fix this by setting the 'phy-mode' to 'rgmii-id' and not 'rgmii'. Fixes: f89b58ce71a9 ("arm64: tegra: Add ethernet controller on Tegra194") Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 623f7d7d216b..8e3136dfdd62 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -33,7 +33,7 @@ phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>; phy-handle = <&phy>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; mdio { #address-cells = <1>; -- cgit v1.2.3 From 4012ab12b3cbd3efbd7254f04de40903c624a237 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 7 May 2020 11:13:49 +0100 Subject: arm64: tegra: Allow the PMIC RTC to wakeup Jetson Xavier The PMIC RTC is currently unable to wakeup Tegra194 on the Jetson Xavier platform because the interrupt from the PMIC is not usin the PMC as the interrupt parent but the GIC directly. Update the PMIC interrupt to use the PMC as the interrupt parent so that the PMIC RTC alarms can wakeup the device. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 8e3136dfdd62..b96eb4e14556 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -111,7 +111,8 @@ compatible = "maxim,max20024"; reg = <0x3c>; - interrupts = ; + interrupt-parent = <&pmc>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; #interrupt-cells = <2>; interrupt-controller; -- cgit v1.2.3 From b4f99176a501ac34c7f5c9322910e248a2f43397 Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Mon, 4 May 2020 19:31:52 -0700 Subject: arm64: tegra: Fix SOR powergate clocks and reset Tegra210 device tree lists CSI clock and reset under SOR powergate node. But Tegra210 has CSICIL in SOR partition and CSI in VENC partition. So, this patch includes fix for SOR powergate node. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a550e7b828e6..909960ac8ce9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -796,7 +796,9 @@ pd_sor: sor { clocks = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, <&tegra_car TEGRA210_CLK_DSIA>, <&tegra_car TEGRA210_CLK_DSIB>, <&tegra_car TEGRA210_CLK_DPAUX>, @@ -804,7 +806,6 @@ <&tegra_car TEGRA210_CLK_MIPI_CAL>; resets = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, <&tegra_car TEGRA210_CLK_DSIA>, <&tegra_car TEGRA210_CLK_DSIB>, <&tegra_car TEGRA210_CLK_DPAUX>, -- cgit v1.2.3 From 2eb8e1a4b1dad1331e438923fefd56a7d6ca6488 Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Mon, 4 May 2020 19:31:53 -0700 Subject: arm64: tegra: Add reset-cells to memory controller Tegra210 device tree is missing reset-cells property for the memory controller node. This patch adds it. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 909960ac8ce9..29a43d726f5b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -894,6 +894,7 @@ interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; }; emc: external-memory-controller@7001b000 { -- cgit v1.2.3 From c415388539495479ad5f905d939cc28d28c567ab Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Mon, 4 May 2020 19:32:00 -0700 Subject: arm64: tegra: Add Tegra VI CSI support in device tree Tegra210 contains VI controller for video input capture from MIPI CSI camera sensors and also supports built-in test pattern generator. CSI ports can be one-to-one mapped to VI channels for capturing from an external sensor or from built-in test pattern generator. This patch adds support for VI and CSI and enables them in Tegra210 device tree. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 10 ++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 46 +++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 313a4c29d37a..b57d837d5fc7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -14,6 +14,16 @@ status = "okay"; }; + vi@54080000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + + csi@838 { + status = "okay"; + }; + }; + sor@54580000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 29a43d726f5b..08655081f72d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -137,9 +137,44 @@ vi@54080000 { compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x00040000>; + reg = <0x0 0x54080000 0x0 0x700>; interrupts = ; status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>, + <972000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; + power-domains = <&pd_sor>; + }; }; tsec@54100000 { @@ -839,6 +874,15 @@ reset-names = "vic"; #power-domain-cells = <0>; }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA210_CLK_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + resets = <&mc TEGRA210_MC_RESET_VI>, + <&tegra_car 20>, + <&tegra_car 52>; + #power-domain-cells = <0>; + }; }; sdmmc1_3v3: sdmmc1-3v3 { -- cgit v1.2.3 From 3482a7afb261e2de9269a7f9ad0f4a3a82a83a53 Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Thu, 14 May 2020 19:24:37 +0530 Subject: arm64: tegra: Fix flag for 64-bit resources in 'ranges' property Fix flag in PCIe controllers device-tree nodes 'ranges' property to correctly represent 64-bit resources. Fixes: 2602c32f15e7 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT") Signed-off-by: Vidya Sagar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index e1ae01c2d039..4bc187a4eacd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1405,7 +1405,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ + 0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ }; @@ -1450,7 +1450,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ + 0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ }; @@ -1495,7 +1495,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ + 0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ }; @@ -1540,7 +1540,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ + 0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ }; @@ -1585,7 +1585,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ + 0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ }; @@ -1634,7 +1634,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ + 0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ }; -- cgit v1.2.3 From ce8a85968dc492cdabf3eab2ce1b8a13fc102905 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 7 Jun 2019 16:00:20 +0200 Subject: arm64: tegra: Enable VI I2C on Jetson Nano Enable the VI I2C so that the peripherals connected to it (such as the camera connector, an INA3221 power monitor and the USB 3.1 4-port hub) can be accessed. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 21ed1756b889..374ce58b2b38 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -90,6 +90,10 @@ dpaux@545c0000 { status = "okay"; }; + + i2c@546c0000 { + status = "okay"; + }; }; gpu@57000000 { -- cgit v1.2.3 From e9bdccb0bdf9169771d79cd72182210e2b2a0df9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 17 Apr 2020 19:11:17 +0200 Subject: arm64: tegra: Make the RTC a wakeup source on Jetson TX2 The RTC found on the MAX77620 PMIC can be used as a wakeup source on Jetson TX2, which is useful to wake the system from suspend at a given time. Signed-off-by: Thierry Reding Acked-by: Jon Hunter Tested-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index da96de04d003..2fcaa2e64370 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -221,7 +221,8 @@ compatible = "maxim,max77620"; reg = <0x3c>; - interrupts = ; + interrupt-parent = <&pmc>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; #interrupt-cells = <2>; interrupt-controller; -- cgit v1.2.3 From 358a6777f5dd293bc3c075af6fc8c0dd18774c96 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 20 May 2020 16:13:18 +0100 Subject: arm64: tegra: Make the RTC a wakeup source on Jetson Nano and TX1 The RTC found on the MAX77620 PMIC can be used as a wakeup source on Jetson Nano and TX1, which is useful to wake the system from suspend at a given time. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 3 ++- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index f87d2437d11c..cc6ed45a2b48 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -38,7 +38,8 @@ pmic: pmic@3c { compatible = "maxim,max77620"; reg = <0x3c>; - interrupts = ; + interrupt-parent = <&tegra_pmc>; + interrupts = <51 IRQ_TYPE_LEVEL_LOW>; #interrupt-cells = <2>; interrupt-controller; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 374ce58b2b38..9bc52fdb393c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -149,7 +149,8 @@ pmic: pmic@3c { compatible = "maxim,max77620"; reg = <0x3c>; - interrupts = ; + interrupt-parent = <&tegra_pmc>; + interrupts = <51 IRQ_TYPE_LEVEL_LOW>; #interrupt-cells = <2>; interrupt-controller; -- cgit v1.2.3