From 5291fa98565a2f4d27ec59380e8497eba2af948d Mon Sep 17 00:00:00 2001 From: Philippe De Muyter Date: Wed, 27 Oct 2010 14:57:47 +0200 Subject: m68knommu: Create new m54xxacr.h from m5407sim.h subpart The MCF548x have the same cache control registers as the MCF5407. Extract the bit definitions for the ACR and CACR registers from m5407sim.h and move them to a new file m54xxacr.h. Those definitions are not used anywhere yet, so no other file is involved. This is a preparation for m54xx cache support cleanup. Signed-off-by: Philippe De Muyter Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5407sim.h | 34 ------------------------------- arch/m68k/include/asm/m54xxacr.h | 43 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 34 deletions(-) create mode 100644 arch/m68k/include/asm/m54xxacr.h (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index c399abbf953c..2099435e10c7 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -117,39 +117,5 @@ #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ -/* - * Define the Cache register flags. - */ -#define CACR_DEC 0x80000000 /* Enable data cache */ -#define CACR_DWP 0x40000000 /* Data write protection */ -#define CACR_DESB 0x20000000 /* Enable data store buffer */ -#define CACR_DDPI 0x10000000 /* Disable CPUSHL */ -#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ -#define CACR_DDCM_WT 0x00000000 /* Write through cache*/ -#define CACR_DDCM_CP 0x02000000 /* Copyback cache */ -#define CACR_DDCM_P 0x04000000 /* No cache, precise */ -#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ -#define CACR_DCINVA 0x01000000 /* Invalidate data cache */ -#define CACR_BEC 0x00080000 /* Enable branch cache */ -#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ -#define CACR_IEC 0x00008000 /* Enable instruction cache */ -#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ -#define CACR_IDPI 0x00001000 /* Disable CPUSHL */ -#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ -#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ -#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ - -#define ACR_BASE_POS 24 /* Address Base */ -#define ACR_MASK_POS 16 /* Address Mask */ -#define ACR_ENABLE 0x00008000 /* Enable address */ -#define ACR_USER 0x00000000 /* User mode access only */ -#define ACR_SUPER 0x00002000 /* Supervisor mode only */ -#define ACR_ANY 0x00004000 /* Match any access mode */ -#define ACR_CM_WT 0x00000000 /* Write through mode */ -#define ACR_CM_CP 0x00000020 /* Copyback mode */ -#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ -#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ -#define ACR_WPROTECT 0x00000004 /* Write protect */ - /****************************************************************************/ #endif /* m5407sim_h */ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h new file mode 100644 index 000000000000..424d4a677e43 --- /dev/null +++ b/arch/m68k/include/asm/m54xxacr.h @@ -0,0 +1,43 @@ +/* + * Bit definitions for the MCF54xx ACR and CACR registers. + */ + +#ifndef m54xxacr_h +#define m54xxacr_h + +/* + * Define the Cache register flags. + */ +#define CACR_DEC 0x80000000 /* Enable data cache */ +#define CACR_DWP 0x40000000 /* Data write protection */ +#define CACR_DESB 0x20000000 /* Enable data store buffer */ +#define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ +#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ +#define CACR_DDCM_WT 0x00000000 /* Write through cache*/ +#define CACR_DDCM_CP 0x02000000 /* Copyback cache */ +#define CACR_DDCM_P 0x04000000 /* No cache, precise */ +#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ +#define CACR_DCINVA 0x01000000 /* Invalidate data cache */ +#define CACR_BEC 0x00080000 /* Enable branch cache */ +#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ +#define CACR_IEC 0x00008000 /* Enable instruction cache */ +#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ +#define CACR_IDPI 0x00001000 /* Disable CPUSHL */ +#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ +#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ +#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ + +#define ACR_BASE_POS 24 /* Address Base */ +#define ACR_MASK_POS 16 /* Address Mask */ +#define ACR_ENABLE 0x00008000 /* Enable address */ +#define ACR_USER 0x00000000 /* User mode access only */ +#define ACR_SUPER 0x00002000 /* Supervisor mode only */ +#define ACR_ANY 0x00004000 /* Match any access mode */ +#define ACR_CM_WT 0x00000000 /* Write through mode */ +#define ACR_CM_CP 0x00000020 /* Copyback mode */ +#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ +#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ +#define ACR_CM 0x00000060 /* Cache mode mask */ +#define ACR_WPROTECT 0x00000004 /* Write protect */ + +#endif /* m54xxacr_h */ -- cgit v1.2.3 From b3d75b09bf8998fd302ba339eebbc768a110741b Mon Sep 17 00:00:00 2001 From: Philippe De Muyter Date: Wed, 27 Oct 2010 14:57:48 +0200 Subject: m68knommu: Move __flush_cache_all definition for m54xx in m54xxacr.h __flush_cache_all for m54xx is intrinsically related to the bit definitions in m54xxacr.h. Move it there from cacheflush_no.h, for easier maintenance. Signed-off-by: Philippe De Muyter Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/cacheflush_no.h | 28 +++++----------------------- arch/m68k/include/asm/m54xxacr.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 23 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 7085bd51668b..8fda331f8a83 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -5,6 +5,9 @@ * (C) Copyright 2000-2004, Greg Ungerer */ #include +#if defined(CONFIG_M5407) || defined(CONFIG_M548x) +#include +#endif #define flush_cache_all() __flush_cache_all() #define flush_cache_mm(mm) do { } while (0) @@ -27,31 +30,9 @@ #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ memcpy(dst, src, len) +#ifndef __flush_cache_all static inline void __flush_cache_all(void) { -#if defined(CONFIG_M5407) || defined(CONFIG_M548x) - /* - * Use cpushl to push and invalidate all cache lines. - * Gas doesn't seem to know how to generate the ColdFire - * cpushl instruction... Oh well, bit stuff it for now. - */ - __asm__ __volatile__ ( - "nop\n\t" - "clrl %%d0\n\t" - "1:\n\t" - "movel %%d0,%%a0\n\t" - "2:\n\t" - ".word 0xf468\n\t" - "addl #0x10,%%a0\n\t" - "cmpl #0x00000800,%%a0\n\t" - "blt 2b\n\t" - "addql #1,%%d0\n\t" - "cmpil #4,%%d0\n\t" - "bne 1b\n\t" - "movel #0xb6088500,%%d0\n\t" - "movec %%d0,%%CACR\n\t" - : : : "d0", "a0" ); -#endif /* CONFIG_M5407 */ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) __asm__ __volatile__ ( "movel #0x81400100, %%d0\n\t" @@ -88,5 +69,6 @@ static inline void __flush_cache_all(void) : : : "d0" ); #endif /* CONFIG_M532x */ } +#endif /* __flush_cache_all */ #endif /* _M68KNOMMU_CACHEFLUSH_H */ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 424d4a677e43..da713d22dd0f 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -40,4 +40,35 @@ #define ACR_CM 0x00000060 /* Cache mode mask */ #define ACR_WPROTECT 0x00000004 /* Write protect */ +#ifndef __ASSEMBLY__ + +static inline void __m54xx_flush_cache_all(void) +{ + /* + * Use cpushl to push and invalidate all cache lines. + * Gas doesn't seem to know how to generate the ColdFire + * cpushl instruction... Oh well, bit stuff it for now. + */ + __asm__ __volatile__ ( + "nop\n\t" + "clrl %%d0\n\t" + "1:\n\t" + "movel %%d0,%%a0\n\t" + "2:\n\t" + ".word 0xf468\n\t" + "addl #0x10,%%a0\n\t" + "cmpl #0x00000800,%%a0\n\t" + "blt 2b\n\t" + "addql #1,%%d0\n\t" + "cmpil #4,%%d0\n\t" + "bne 1b\n\t" + "movel #0xb6088500,%%d0\n\t" + "movec %%d0,%%CACR\n\t" + : : : "d0", "a0" ); +} + +#define __flush_cache_all() __m54xx_flush_cache_all() + +#endif /* __ASSEMBLY__ */ + #endif /* m54xxacr_h */ -- cgit v1.2.3 From 9c68015b149d45a35114b4a1ed44c21fa66bc430 Mon Sep 17 00:00:00 2001 From: Philippe De Muyter Date: Wed, 27 Oct 2010 14:57:49 +0200 Subject: m68knommu: Use symbolic constants for cache operations on M54xx Now that we have meaningfull symbolic constants for bit definitions of the cache registers of m5407 and m548x chips, use them to improve readability, portability and efficiency of the cache operations. This also fixes __flush_cache_all for m548x chips : implicit DCACHE_SIZE was exact for m5407, but wrong for m548x. Signed-off-by: Philippe De Muyter Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/cacheflush_no.h | 2 ++ arch/m68k/include/asm/m54xxacr.h | 58 ++++++++++++++++++++++++++++++----- arch/m68k/include/asm/mcfcache.h | 22 +++++++------ 3 files changed, 65 insertions(+), 17 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 8fda331f8a83..29f76204ce1d 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -14,7 +14,9 @@ #define flush_cache_dup_mm(mm) do { } while (0) #define flush_cache_range(vma, start, end) __flush_cache_all() #define flush_cache_page(vma, vmaddr) do { } while (0) +#ifndef flush_dcache_range #define flush_dcache_range(start,len) __flush_cache_all() +#endif #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 #define flush_dcache_page(page) do { } while (0) #define flush_dcache_mmap_lock(mapping) do { } while (0) diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index da713d22dd0f..7d28da4d622a 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -40,31 +40,75 @@ #define ACR_CM 0x00000060 /* Cache mode mask */ #define ACR_WPROTECT 0x00000004 /* Write protect */ +#if defined(CONFIG_M5407) + +#define ICACHE_SIZE 0x4000 /* instruction - 16k */ +#define DCACHE_SIZE 0x2000 /* data - 8k */ + +#elif defined(CONFIG_M548x) + +#define ICACHE_SIZE 0x8000 /* instruction - 32k */ +#define DCACHE_SIZE 0x8000 /* data - 32k */ + +#endif + +#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ +#define CACHE_WAYS 4 /* 4 ways */ + +/* + * Version 4 cores have a true harvard style separate instruction + * and data cache. Enable data and instruction caches, also enable write + * buffers and branch accelerator. + */ +/* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */ +/* use '+' instead of '|' for assembler's sake */ + + /* Enable data cache */ + /* Enable data store buffer */ + /* outside ACRs : No cache, precise */ + /* Enable instruction+branch caches */ +#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC) + +#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) + +#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) + #ifndef __ASSEMBLY__ +#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT) +#define flush_dcache_range(a, l) do { asm("nop"); } while (0) +#endif + static inline void __m54xx_flush_cache_all(void) { + __asm__ __volatile__ ( +#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) /* * Use cpushl to push and invalidate all cache lines. * Gas doesn't seem to know how to generate the ColdFire * cpushl instruction... Oh well, bit stuff it for now. */ - __asm__ __volatile__ ( - "nop\n\t" "clrl %%d0\n\t" "1:\n\t" "movel %%d0,%%a0\n\t" "2:\n\t" ".word 0xf468\n\t" - "addl #0x10,%%a0\n\t" - "cmpl #0x00000800,%%a0\n\t" + "addl %0,%%a0\n\t" + "cmpl %1,%%a0\n\t" "blt 2b\n\t" "addql #1,%%d0\n\t" - "cmpil #4,%%d0\n\t" + "cmpil %2,%%d0\n\t" "bne 1b\n\t" - "movel #0xb6088500,%%d0\n\t" +#endif + "movel %3,%%d0\n\t" "movec %%d0,%%CACR\n\t" - : : : "d0", "a0" ); + "nop\n\t" /* forces flush of Store Buffer */ + : /* No output */ + : "i" (CACHE_LINE_SIZE), + "i" (DCACHE_SIZE / CACHE_WAYS), + "i" (CACHE_WAYS), + "i" (CACHE_MODE|CACR_DCINVA|CACR_BCINVA|CACR_ICINVA) + : "d0", "a0" ); } #define __flush_cache_all() __m54xx_flush_cache_all() diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h index f49dfc09f70a..7acb406d601b 100644 --- a/arch/m68k/include/asm/mcfcache.h +++ b/arch/m68k/include/asm/mcfcache.h @@ -108,28 +108,30 @@ #endif /* CONFIG_M532x */ #if defined(CONFIG_M5407) || defined(CONFIG_M548x) -/* - * Version 4 cores have a true harvard style separate instruction - * and data cache. Invalidate and enable cache, also enable write - * buffers and branch accelerator. - */ + +#include + .macro CACHE_ENABLE - movel #0x01040100,%d0 /* invalidate whole cache */ + /* invalidate whole cache */ + movel #(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA),%d0 movec %d0,%CACR nop - movel #0x000fc000,%d0 /* set SDRAM cached only */ + /* addresses range for data cache : 0x00000000-0x0fffffff */ + movel #(0x000f0000+DATA_CACHE_MODE),%d0 /* set SDRAM cached */ movec %d0, %ACR0 movel #0x00000000,%d0 /* no other regions cached */ movec %d0, %ACR1 - movel #0x000fc000,%d0 /* set SDRAM cached only */ + /* addresses range for instruction cache : 0x00000000-0x0fffffff */ + movel #(0x000f0000+INSN_CACHE_MODE),%d0 /* set SDRAM cached */ movec %d0, %ACR2 movel #0x00000000,%d0 /* no other regions cached */ movec %d0, %ACR3 - movel #0xb6088400,%d0 /* enable caches */ + /* enable caches */ + movel #(CACHE_MODE),%d0 movec %d0,%CACR nop .endm -#endif /* CONFIG_M5407 */ +#endif /* CONFIG_M5407 || CONFIG_M548x */ #if defined(CONFIG_M520x) .macro CACHE_ENABLE -- cgit v1.2.3 From 5b2e6555ac3eb58a4e5eb5020471df08f0c42c01 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 2 Nov 2010 12:05:29 +1000 Subject: m68knommu: make Coldfire 548x support more generic The ColdFire 547x family of processors is very similar to the ColdFire 548x series. Almost all of the support for them is the same. Make the code supporting the 548x more gneric, so it will be capable of supporting both families. For the most part this is a renaming excerise to make the support code more obviously apply to both families. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/cacheflush_no.h | 2 +- arch/m68k/include/asm/coldfire.h | 2 +- arch/m68k/include/asm/gpio.h | 2 +- arch/m68k/include/asm/m548xgpt.h | 88 ----------------------- arch/m68k/include/asm/m548xsim.h | 55 -------------- arch/m68k/include/asm/m54xxacr.h | 2 +- arch/m68k/include/asm/m54xxgpt.h | 88 +++++++++++++++++++++++ arch/m68k/include/asm/m54xxsim.h | 55 ++++++++++++++ arch/m68k/include/asm/mcfcache.h | 4 +- arch/m68k/include/asm/mcfsim.h | 4 +- arch/m68k/include/asm/mcfuart.h | 12 ++-- arch/m68knommu/Kconfig | 7 +- arch/m68knommu/Makefile | 6 +- arch/m68knommu/platform/548x/Makefile | 18 ----- arch/m68knommu/platform/548x/config.c | 115 ------------------------------ arch/m68knommu/platform/54xx/Makefile | 18 +++++ arch/m68knommu/platform/54xx/config.c | 115 ++++++++++++++++++++++++++++++ arch/m68knommu/platform/coldfire/Makefile | 2 +- 18 files changed, 300 insertions(+), 295 deletions(-) delete mode 100644 arch/m68k/include/asm/m548xgpt.h delete mode 100644 arch/m68k/include/asm/m548xsim.h create mode 100644 arch/m68k/include/asm/m54xxgpt.h create mode 100644 arch/m68k/include/asm/m54xxsim.h delete mode 100644 arch/m68knommu/platform/548x/Makefile delete mode 100644 arch/m68knommu/platform/548x/config.c create mode 100644 arch/m68knommu/platform/54xx/Makefile create mode 100644 arch/m68knommu/platform/54xx/config.c (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 29f76204ce1d..9246392e1372 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -5,7 +5,7 @@ * (C) Copyright 2000-2004, Greg Ungerer */ #include -#if defined(CONFIG_M5407) || defined(CONFIG_M548x) +#if defined(CONFIG_M5407) || defined(CONFIG_M54xx) #include #endif diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h index 3b0a34d0fe33..213028cbe110 100644 --- a/arch/m68k/include/asm/coldfire.h +++ b/arch/m68k/include/asm/coldfire.h @@ -32,7 +32,7 @@ */ #define MCF_MBAR 0x10000000 #define MCF_MBAR2 0x80000000 -#if defined(CONFIG_M548x) +#if defined(CONFIG_M54xx) #define MCF_IPSBAR MCF_MBAR #elif defined(CONFIG_M520x) #define MCF_IPSBAR 0xFC000000 diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index 1b57adbafad5..c64c7b74cf86 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h @@ -37,7 +37,7 @@ #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M532x) || defined(CONFIG_M548x) + defined(CONFIG_M532x) || defined(CONFIG_M54xx) /* These parts have GPIO organized by 8 bit ports */ diff --git a/arch/m68k/include/asm/m548xgpt.h b/arch/m68k/include/asm/m548xgpt.h deleted file mode 100644 index c8ef158a1c4e..000000000000 --- a/arch/m68k/include/asm/m548xgpt.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * File: m548xgpt.h - * Purpose: Register and bit definitions for the MCF548X - * - * Notes: - * - */ - -#ifndef m548xgpt_h -#define m548xgpt_h - -/********************************************************************* -* -* General Purpose Timers (GPT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPT_GMS0 0x000800 -#define MCF_GPT_GCIR0 0x000804 -#define MCF_GPT_GPWM0 0x000808 -#define MCF_GPT_GSR0 0x00080C -#define MCF_GPT_GMS1 0x000810 -#define MCF_GPT_GCIR1 0x000814 -#define MCF_GPT_GPWM1 0x000818 -#define MCF_GPT_GSR1 0x00081C -#define MCF_GPT_GMS2 0x000820 -#define MCF_GPT_GCIR2 0x000824 -#define MCF_GPT_GPWM2 0x000828 -#define MCF_GPT_GSR2 0x00082C -#define MCF_GPT_GMS3 0x000830 -#define MCF_GPT_GCIR3 0x000834 -#define MCF_GPT_GPWM3 0x000838 -#define MCF_GPT_GSR3 0x00083C -#define MCF_GPT_GMS(x) (0x000800+((x)*0x010)) -#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010)) -#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010)) -#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010)) - -/* Bit definitions and macros for MCF_GPT_GMS */ -#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) -#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) -#define MCF_GPT_GMS_IEN (0x00000100) -#define MCF_GPT_GMS_OD (0x00000200) -#define MCF_GPT_GMS_SC (0x00000400) -#define MCF_GPT_GMS_CE (0x00001000) -#define MCF_GPT_GMS_WDEN (0x00008000) -#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) -#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) -#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) -#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000) -#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000) -#define MCF_GPT_GMS_OCT_PULSELO (0x00200000) -#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000) -#define MCF_GPT_GMS_ICT_ANY (0x00000000) -#define MCF_GPT_GMS_ICT_RISE (0x00010000) -#define MCF_GPT_GMS_ICT_FALL (0x00020000) -#define MCF_GPT_GMS_ICT_PULSE (0x00030000) -#define MCF_GPT_GMS_GPIO_INPUT (0x00000000) -#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020) -#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030) -#define MCF_GPT_GMS_TMS_DISABLE (0x00000000) -#define MCF_GPT_GMS_TMS_INCAPT (0x00000001) -#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002) -#define MCF_GPT_GMS_TMS_PWM (0x00000003) -#define MCF_GPT_GMS_TMS_GPIO (0x00000004) - -/* Bit definitions and macros for MCF_GPT_GCIR */ -#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) -#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_GPT_GPWM */ -#define MCF_GPT_GPWM_LOAD (0x00000001) -#define MCF_GPT_GPWM_PWMOP (0x00000100) -#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_GPT_GSR */ -#define MCF_GPT_GSR_CAPT (0x00000001) -#define MCF_GPT_GSR_COMP (0x00000002) -#define MCF_GPT_GSR_PWMP (0x00000004) -#define MCF_GPT_GSR_TEXP (0x00000008) -#define MCF_GPT_GSR_PIN (0x00000100) -#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) -#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) - -/********************************************************************/ - -#endif /* m548xgpt_h */ diff --git a/arch/m68k/include/asm/m548xsim.h b/arch/m68k/include/asm/m548xsim.h deleted file mode 100644 index 149135ef30d2..000000000000 --- a/arch/m68k/include/asm/m548xsim.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * m548xsim.h -- ColdFire 547x/548x System Integration Unit support. - */ - -#ifndef m548xsim_h -#define m548xsim_h - -#define MCFINT_VECBASE 64 - -/* - * Interrupt Controller Registers - */ -#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */ -#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ -#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ -#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ -#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ -#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ -#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ -#define MCFINTC_IRLR 0x18 /* */ -#define MCFINTC_IACKL 0x19 /* */ -#define MCFINTC_ICR0 0x40 /* Base ICR register */ - -/* - * Define system peripheral IRQ usage. - */ -#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ -#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */ - -/* - * Generic GPIO support - */ -#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */ -#define MCFGPIO_IRQ_MAX -1 -#define MCFGPIO_IRQ_VECBASE -1 - -/* - * Some PSC related definitions - */ -#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) -#define MCF_PAR_SDA (0x0008) -#define MCF_PAR_SCL (0x0004) -#define MCF_PAR_PSC_TXD (0x04) -#define MCF_PAR_PSC_RXD (0x08) -#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) -#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) -#define MCF_PAR_PSC_CTS_GPIO (0x00) -#define MCF_PAR_PSC_CTS_BCLK (0x80) -#define MCF_PAR_PSC_CTS_CTS (0xC0) -#define MCF_PAR_PSC_RTS_GPIO (0x00) -#define MCF_PAR_PSC_RTS_FSYNC (0x20) -#define MCF_PAR_PSC_RTS_RTS (0x30) -#define MCF_PAR_PSC_CANRX (0x40) - -#endif /* m548xsim_h */ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 7d28da4d622a..76d64906aa62 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -45,7 +45,7 @@ #define ICACHE_SIZE 0x4000 /* instruction - 16k */ #define DCACHE_SIZE 0x2000 /* data - 8k */ -#elif defined(CONFIG_M548x) +#elif defined(CONFIG_M54xx) #define ICACHE_SIZE 0x8000 /* instruction - 32k */ #define DCACHE_SIZE 0x8000 /* data - 32k */ diff --git a/arch/m68k/include/asm/m54xxgpt.h b/arch/m68k/include/asm/m54xxgpt.h new file mode 100644 index 000000000000..47ae5cfec66b --- /dev/null +++ b/arch/m68k/include/asm/m54xxgpt.h @@ -0,0 +1,88 @@ +/* + * File: m54xxgpt.h + * Purpose: Register and bit definitions for the MCF54XX + * + * Notes: + * + */ + +#ifndef m54xxgpt_h +#define m54xxgpt_h + +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT_GMS0 0x000800 +#define MCF_GPT_GCIR0 0x000804 +#define MCF_GPT_GPWM0 0x000808 +#define MCF_GPT_GSR0 0x00080C +#define MCF_GPT_GMS1 0x000810 +#define MCF_GPT_GCIR1 0x000814 +#define MCF_GPT_GPWM1 0x000818 +#define MCF_GPT_GSR1 0x00081C +#define MCF_GPT_GMS2 0x000820 +#define MCF_GPT_GCIR2 0x000824 +#define MCF_GPT_GPWM2 0x000828 +#define MCF_GPT_GSR2 0x00082C +#define MCF_GPT_GMS3 0x000830 +#define MCF_GPT_GCIR3 0x000834 +#define MCF_GPT_GPWM3 0x000838 +#define MCF_GPT_GSR3 0x00083C +#define MCF_GPT_GMS(x) (0x000800+((x)*0x010)) +#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010)) +#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010)) +#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010)) + +/* Bit definitions and macros for MCF_GPT_GMS */ +#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) +#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) +#define MCF_GPT_GMS_IEN (0x00000100) +#define MCF_GPT_GMS_OD (0x00000200) +#define MCF_GPT_GMS_SC (0x00000400) +#define MCF_GPT_GMS_CE (0x00001000) +#define MCF_GPT_GMS_WDEN (0x00008000) +#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) +#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) +#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) +#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000) +#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000) +#define MCF_GPT_GMS_OCT_PULSELO (0x00200000) +#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000) +#define MCF_GPT_GMS_ICT_ANY (0x00000000) +#define MCF_GPT_GMS_ICT_RISE (0x00010000) +#define MCF_GPT_GMS_ICT_FALL (0x00020000) +#define MCF_GPT_GMS_ICT_PULSE (0x00030000) +#define MCF_GPT_GMS_GPIO_INPUT (0x00000000) +#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020) +#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030) +#define MCF_GPT_GMS_TMS_DISABLE (0x00000000) +#define MCF_GPT_GMS_TMS_INCAPT (0x00000001) +#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002) +#define MCF_GPT_GMS_TMS_PWM (0x00000003) +#define MCF_GPT_GMS_TMS_GPIO (0x00000004) + +/* Bit definitions and macros for MCF_GPT_GCIR */ +#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) +#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_GPT_GPWM */ +#define MCF_GPT_GPWM_LOAD (0x00000001) +#define MCF_GPT_GPWM_PWMOP (0x00000100) +#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_GPT_GSR */ +#define MCF_GPT_GSR_CAPT (0x00000001) +#define MCF_GPT_GSR_COMP (0x00000002) +#define MCF_GPT_GSR_PWMP (0x00000004) +#define MCF_GPT_GSR_TEXP (0x00000008) +#define MCF_GPT_GSR_PIN (0x00000100) +#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) +#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) + +/********************************************************************/ + +#endif /* m54xxgpt_h */ diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h new file mode 100644 index 000000000000..c46826c900b3 --- /dev/null +++ b/arch/m68k/include/asm/m54xxsim.h @@ -0,0 +1,55 @@ +/* + * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support. + */ + +#ifndef m54xxsim_h +#define m54xxsim_h + +#define MCFINT_VECBASE 64 + +/* + * Interrupt Controller Registers + */ +#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */ +#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ +#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ +#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ +#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ +#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ +#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ +#define MCFINTC_IRLR 0x18 /* */ +#define MCFINTC_IACKL 0x19 /* */ +#define MCFINTC_ICR0 0x40 /* Base ICR register */ + +/* + * Define system peripheral IRQ usage. + */ +#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ +#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */ + +/* + * Generic GPIO support + */ +#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */ +#define MCFGPIO_IRQ_MAX -1 +#define MCFGPIO_IRQ_VECBASE -1 + +/* + * Some PSC related definitions + */ +#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) +#define MCF_PAR_SDA (0x0008) +#define MCF_PAR_SCL (0x0004) +#define MCF_PAR_PSC_TXD (0x04) +#define MCF_PAR_PSC_RXD (0x08) +#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) +#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) +#define MCF_PAR_PSC_CTS_GPIO (0x00) +#define MCF_PAR_PSC_CTS_BCLK (0x80) +#define MCF_PAR_PSC_CTS_CTS (0xC0) +#define MCF_PAR_PSC_RTS_GPIO (0x00) +#define MCF_PAR_PSC_RTS_FSYNC (0x20) +#define MCF_PAR_PSC_RTS_RTS (0x30) +#define MCF_PAR_PSC_CANRX (0x40) + +#endif /* m54xxsim_h */ diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h index 7acb406d601b..1b66018461b8 100644 --- a/arch/m68k/include/asm/mcfcache.h +++ b/arch/m68k/include/asm/mcfcache.h @@ -107,7 +107,7 @@ .endm #endif /* CONFIG_M532x */ -#if defined(CONFIG_M5407) || defined(CONFIG_M548x) +#if defined(CONFIG_M5407) || defined(CONFIG_M54xx) #include @@ -131,7 +131,7 @@ movec %d0,%CACR nop .endm -#endif /* CONFIG_M5407 || CONFIG_M548x */ +#endif /* CONFIG_M5407 || CONFIG_M54xx */ #if defined(CONFIG_M520x) .macro CACHE_ENABLE diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h index 6901fd68165b..ebd0304054ad 100644 --- a/arch/m68k/include/asm/mcfsim.h +++ b/arch/m68k/include/asm/mcfsim.h @@ -41,8 +41,8 @@ #elif defined(CONFIG_M5407) #include #include -#elif defined(CONFIG_M548x) -#include +#elif defined(CONFIG_M54xx) +#include #endif /****************************************************************************/ diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h index db72e2b889ca..c67dacad7c1c 100644 --- a/arch/m68k/include/asm/mcfuart.h +++ b/arch/m68k/include/asm/mcfuart.h @@ -47,11 +47,11 @@ #define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ #define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ #define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ -#elif defined(CONFIG_M548x) -#define MCFUART_BASE1 0x8600 /* on M548x */ -#define MCFUART_BASE2 0x8700 /* on M548x */ -#define MCFUART_BASE3 0x8800 /* on M548x */ -#define MCFUART_BASE4 0x8900 /* on M548x */ +#elif defined(CONFIG_M54xx) +#define MCFUART_BASE1 0x8600 /* on M54xx */ +#define MCFUART_BASE2 0x8700 /* on M54xx */ +#define MCFUART_BASE3 0x8800 /* on M54xx */ +#define MCFUART_BASE4 0x8900 /* on M54xx */ #endif @@ -217,7 +217,7 @@ struct mcf_platform_uart { #define MCFUART_URF_RXS 0xc0 /* Receiver status */ #endif -#if defined(CONFIG_M548x) +#if defined(CONFIG_M54xx) #define MCFUART_TXFIFOSIZE 512 #elif defined(CONFIG_M5272) #define MCFUART_TXFIFOSIZE 25 diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index fa9f746cf4ae..060f142a1e20 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -181,9 +181,14 @@ config M527x select GENERIC_CLOCKEVENTS default y +config M54xx + bool + depends on M548x + default y + config COLDFIRE bool - depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M548x) + depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M54xx) select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB default y diff --git a/arch/m68knommu/Makefile b/arch/m68knommu/Makefile index 026ef16fa68e..0a0b1ddee4b9 100644 --- a/arch/m68knommu/Makefile +++ b/arch/m68knommu/Makefile @@ -25,7 +25,7 @@ platform-$(CONFIG_M528x) := 528x platform-$(CONFIG_M5307) := 5307 platform-$(CONFIG_M532x) := 532x platform-$(CONFIG_M5407) := 5407 -platform-$(CONFIG_M548x) := 548x +platform-$(CONFIG_M54xx) := 54xx PLATFORM := $(platform-y) board-$(CONFIG_PILOT) := pilot @@ -74,7 +74,7 @@ cpuclass-$(CONFIG_M528x) := coldfire cpuclass-$(CONFIG_M5307) := coldfire cpuclass-$(CONFIG_M532x) := coldfire cpuclass-$(CONFIG_M5407) := coldfire -cpuclass-$(CONFIG_M548x) := coldfire +cpuclass-$(CONFIG_M54xx) := coldfire cpuclass-$(CONFIG_M68328) := 68328 cpuclass-$(CONFIG_M68EZ328) := 68328 cpuclass-$(CONFIG_M68VZ328) := 68328 @@ -102,7 +102,7 @@ cflags-$(CONFIG_M528x) := $(call cc-option,-m528x,-m5307) cflags-$(CONFIG_M5307) := $(call cc-option,-m5307,-m5200) cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307) cflags-$(CONFIG_M5407) := $(call cc-option,-m5407,-m5200) -cflags-$(CONFIG_M548x) := $(call cc-option,-m5407,-m5200) +cflags-$(CONFIG_M54xx) := $(call cc-option,-m5407,-m5200) cflags-$(CONFIG_M68328) := -m68000 cflags-$(CONFIG_M68EZ328) := -m68000 cflags-$(CONFIG_M68VZ328) := -m68000 diff --git a/arch/m68knommu/platform/548x/Makefile b/arch/m68knommu/platform/548x/Makefile deleted file mode 100644 index e6035e7a2d3f..000000000000 --- a/arch/m68knommu/platform/548x/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT -# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o - diff --git a/arch/m68knommu/platform/548x/config.c b/arch/m68knommu/platform/548x/config.c deleted file mode 100644 index 9888846bd1cf..000000000000 --- a/arch/m68knommu/platform/548x/config.c +++ /dev/null @@ -1,115 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/548x/config.c - * - * Copyright (C) 2010, Philippe De Muyter - */ - -/***************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/***************************************************************************/ - -static struct mcf_platform_uart m548x_uart_platform[] = { - { - .mapbase = MCF_MBAR + MCFUART_BASE1, - .irq = 64 + 35, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE2, - .irq = 64 + 34, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE3, - .irq = 64 + 33, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE4, - .irq = 64 + 32, - }, -}; - -static struct platform_device m548x_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m548x_uart_platform, -}; - -static struct platform_device *m548x_devices[] __initdata = { - &m548x_uart, -}; - - -/***************************************************************************/ - -static void __init m548x_uart_init_line(int line, int irq) -{ - int rts_cts; - - /* enable io pins */ - switch (line) { - case 0: - rts_cts = 0; break; - case 1: - rts_cts = MCF_PAR_PSC_RTS_RTS; break; - case 2: - rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break; - case 3: - rts_cts = 0; break; - } - __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD, - MCF_MBAR + MCF_PAR_PSC(line)); -} - -static void __init m548x_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m548x_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m548x_uart_init_line(line, m548x_uart_platform[line].irq); -} - -/***************************************************************************/ - -static void mcf548x_reset(void) -{ - /* disable interrupts and enable the watchdog */ - asm("movew #0x2700, %sr\n"); - __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0); - __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0); - __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4), - MCF_MBAR + MCF_GPT_GMS0); -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ - mach_reset = mcf548x_reset; - m548x_uarts_init(); -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - - platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/54xx/Makefile b/arch/m68knommu/platform/54xx/Makefile new file mode 100644 index 000000000000..e6035e7a2d3f --- /dev/null +++ b/arch/m68knommu/platform/54xx/Makefile @@ -0,0 +1,18 @@ +# +# Makefile for the m68knommu linux kernel. +# + +# +# If you want to play with the HW breakpoints then you will +# need to add define this, which will give you a stack backtrace +# on the console port whenever a DBG interrupt occurs. You have to +# set up you HW breakpoints to trigger a DBG interrupt: +# +# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT +# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT +# + +asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 + +obj-y := config.o + diff --git a/arch/m68knommu/platform/54xx/config.c b/arch/m68knommu/platform/54xx/config.c new file mode 100644 index 000000000000..78130984db95 --- /dev/null +++ b/arch/m68knommu/platform/54xx/config.c @@ -0,0 +1,115 @@ +/***************************************************************************/ + +/* + * linux/arch/m68knommu/platform/54xx/config.c + * + * Copyright (C) 2010, Philippe De Muyter + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +static struct mcf_platform_uart m54xx_uart_platform[] = { + { + .mapbase = MCF_MBAR + MCFUART_BASE1, + .irq = 64 + 35, + }, + { + .mapbase = MCF_MBAR + MCFUART_BASE2, + .irq = 64 + 34, + }, + { + .mapbase = MCF_MBAR + MCFUART_BASE3, + .irq = 64 + 33, + }, + { + .mapbase = MCF_MBAR + MCFUART_BASE4, + .irq = 64 + 32, + }, +}; + +static struct platform_device m54xx_uart = { + .name = "mcfuart", + .id = 0, + .dev.platform_data = m54xx_uart_platform, +}; + +static struct platform_device *m54xx_devices[] __initdata = { + &m54xx_uart, +}; + + +/***************************************************************************/ + +static void __init m54xx_uart_init_line(int line, int irq) +{ + int rts_cts; + + /* enable io pins */ + switch (line) { + case 0: + rts_cts = 0; break; + case 1: + rts_cts = MCF_PAR_PSC_RTS_RTS; break; + case 2: + rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break; + case 3: + rts_cts = 0; break; + } + __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD, + MCF_MBAR + MCF_PAR_PSC(line)); +} + +static void __init m54xx_uarts_init(void) +{ + const int nrlines = ARRAY_SIZE(m54xx_uart_platform); + int line; + + for (line = 0; (line < nrlines); line++) + m54xx_uart_init_line(line, m54xx_uart_platform[line].irq); +} + +/***************************************************************************/ + +static void mcf54xx_reset(void) +{ + /* disable interrupts and enable the watchdog */ + asm("movew #0x2700, %sr\n"); + __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0); + __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0); + __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4), + MCF_MBAR + MCF_GPT_GMS0); +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_reset = mcf54xx_reset; + m54xx_uarts_init(); +} + +/***************************************************************************/ + +static int __init init_BSP(void) +{ + + platform_add_devices(m54xx_devices, ARRAY_SIZE(m54xx_devices)); + return 0; +} + +arch_initcall(init_BSP); + +/***************************************************************************/ diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile index 45f501fa4525..53a27e1a7904 100644 --- a/arch/m68knommu/platform/coldfire/Makefile +++ b/arch/m68knommu/platform/coldfire/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_M528x) += pit.o intc-2.o obj-$(CONFIG_M5307) += timers.o intc.o obj-$(CONFIG_M532x) += timers.o intc-simr.o obj-$(CONFIG_M5407) += timers.o intc.o -obj-$(CONFIG_M548x) += sltimers.o intc-2.o +obj-$(CONFIG_M54xx) += sltimers.o intc-2.o obj-y += pinmux.o gpio.o extra-y := head.o -- cgit v1.2.3 From 7fc82b655a169039d8a58fde609b5e778573d5ab Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 2 Nov 2010 17:13:27 +1000 Subject: m68knommu: move ColdFire CPU names into their headers Move the ColdFire CPU names out of setup.c and into their repsective headers. That way when we add new ones we won't need to modify setup.c any more. Add the missing 548x CPU name. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5206sim.h | 1 + arch/m68k/include/asm/m520xsim.h | 2 ++ arch/m68k/include/asm/m523xsim.h | 1 + arch/m68k/include/asm/m5249sim.h | 2 ++ arch/m68k/include/asm/m5272sim.h | 2 ++ arch/m68k/include/asm/m527xsim.h | 2 ++ arch/m68k/include/asm/m528xsim.h | 1 + arch/m68k/include/asm/m5307sim.h | 2 ++ arch/m68k/include/asm/m532xsim.h | 2 ++ arch/m68k/include/asm/m5407sim.h | 2 ++ arch/m68k/include/asm/m54xxsim.h | 2 ++ arch/m68knommu/kernel/setup.c | 55 ++++++++-------------------------------- 12 files changed, 30 insertions(+), 44 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index 9c384e294af9..6cc7a42cc425 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -12,6 +12,7 @@ #define m5206sim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m5206)" /* * Define the 5206 SIM register set addresses. diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index db824a4b136e..afa211858ecb 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -11,6 +11,8 @@ #define m520xsim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m520x)" + /* * Define the 520x SIM register set addresses. */ diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index e8d06b24a48e..6a2c90d74d15 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -11,6 +11,7 @@ #define m523xsim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m523x)" /* * Define the 523x SIM register set addresses. diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 79b7b402f3c9..6c49ed88845c 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -11,6 +11,8 @@ #define m5249sim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m5249)" + /* * Define the 5249 SIM register set addresses. */ diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index df3332c2317d..7edef8fc1920 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -12,6 +12,8 @@ #define m5272sim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m5272)" + /* * Define the 5272 SIM register set addresses. */ diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 1feb46f108ce..627156a1d96a 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -11,6 +11,8 @@ #define m527xsim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m527x)" + /* * Define the 5270/5271 SIM register set addresses. diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index 891cbedad972..03a6d576787c 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -11,6 +11,7 @@ #define m528xsim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m528x)" /* * Define the 5280/5282 SIM register set addresses. diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index c6830e5b54ce..3e06b8379a49 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -14,6 +14,8 @@ #define m5307sim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m5307)" + /* * Define the 5307 SIM register set addresses. */ diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index c4bf1c81e3cf..9f4688bcc454 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -9,6 +9,8 @@ #define m532xsim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m532x)" + #define MCF_REG32(x) (*(volatile unsigned long *)(x)) #define MCF_REG16(x) (*(volatile unsigned short *)(x)) #define MCF_REG08(x) (*(volatile unsigned char *)(x)) diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index 2099435e10c7..1de44c5affe0 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -14,6 +14,8 @@ #define m5407sim_h /****************************************************************************/ +#define CPU_NAME "COLDFIRE(m5407)" + /* * Define the 5407 SIM register set addresses. */ diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index c46826c900b3..d69a64fd3bde 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -5,6 +5,8 @@ #ifndef m54xxsim_h #define m54xxsim_h +#define CPU_NAME "COLDFIRE(m54xx)" + #define MCFINT_VECBASE 64 /* diff --git a/arch/m68knommu/kernel/setup.c b/arch/m68knommu/kernel/setup.c index c684adf5dc40..f48d9df484d3 100644 --- a/arch/m68knommu/kernel/setup.c +++ b/arch/m68knommu/kernel/setup.c @@ -55,55 +55,22 @@ void (*mach_halt)(void); void (*mach_power_off)(void); #ifdef CONFIG_M68328 - #define CPU "MC68328" +#define CPU_NAME "MC68328" #endif #ifdef CONFIG_M68EZ328 - #define CPU "MC68EZ328" +#define CPU_NAME "MC68EZ328" #endif #ifdef CONFIG_M68VZ328 - #define CPU "MC68VZ328" +#define CPU_NAME "MC68VZ328" #endif #ifdef CONFIG_M68360 - #define CPU "MC68360" +#define CPU_NAME "MC68360" #endif -#if defined(CONFIG_M5206) - #define CPU "COLDFIRE(m5206)" -#endif -#if defined(CONFIG_M5206e) - #define CPU "COLDFIRE(m5206e)" -#endif -#if defined(CONFIG_M520x) - #define CPU "COLDFIRE(m520x)" -#endif -#if defined(CONFIG_M523x) - #define CPU "COLDFIRE(m523x)" -#endif -#if defined(CONFIG_M5249) - #define CPU "COLDFIRE(m5249)" -#endif -#if defined(CONFIG_M5271) - #define CPU "COLDFIRE(m5270/5271)" -#endif -#if defined(CONFIG_M5272) - #define CPU "COLDFIRE(m5272)" -#endif -#if defined(CONFIG_M5275) - #define CPU "COLDFIRE(m5274/5275)" -#endif -#if defined(CONFIG_M528x) - #define CPU "COLDFIRE(m5280/5282)" -#endif -#if defined(CONFIG_M5307) - #define CPU "COLDFIRE(m5307)" -#endif -#if defined(CONFIG_M532x) - #define CPU "COLDFIRE(m532x)" -#endif -#if defined(CONFIG_M5407) - #define CPU "COLDFIRE(m5407)" -#endif -#ifndef CPU - #define CPU "UNKNOWN" +/* + * The ColdFire CPU names are defined in their headers. + */ +#ifndef CPU_NAME +#define CPU_NAME "UNKNOWN" #endif extern int _stext, _etext, _sdata, _edata, _sbss, _ebss, _end; @@ -208,7 +175,7 @@ void __init setup_arch(char **cmdline_p) command_line[sizeof(command_line) - 1] = 0; #endif /* CONFIG_UBOOT */ - printk(KERN_INFO "\x0F\r\n\nuClinux/" CPU "\n"); + printk(KERN_INFO "\x0F\r\n\nuClinux/" CPU_NAME "\n"); #ifdef CONFIG_UCDIMM printk(KERN_INFO "uCdimm by Lineo, Inc. \n"); @@ -303,7 +270,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) char *cpu, *mmu, *fpu; u_long clockfreq; - cpu = CPU; + cpu = CPU_NAME; mmu = "none"; fpu = "none"; -- cgit v1.2.3 From 733f31b764061d976a60c5ee454632d9562900ea Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 2 Nov 2010 17:40:37 +1000 Subject: m68knommu: fix clock rate value reported for ColdFire 54xx parts The instruction timings of the ColdFire 54xx family parts are different to other version 4 parts (or version 2 or 3 parts for that matter too). Move the instruction timing setting into the ColdFire part specific headers, and set the 54xx value appropriately. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5206sim.h | 3 ++- arch/m68k/include/asm/m520xsim.h | 3 ++- arch/m68k/include/asm/m523xsim.h | 3 ++- arch/m68k/include/asm/m5249sim.h | 3 ++- arch/m68k/include/asm/m5272sim.h | 3 ++- arch/m68k/include/asm/m527xsim.h | 3 ++- arch/m68k/include/asm/m528xsim.h | 3 ++- arch/m68k/include/asm/m5307sim.h | 3 ++- arch/m68k/include/asm/m532xsim.h | 3 ++- arch/m68k/include/asm/m5407sim.h | 3 ++- arch/m68k/include/asm/m54xxsim.h | 5 +++-- arch/m68knommu/kernel/setup.c | 20 +++++++++++--------- 12 files changed, 34 insertions(+), 21 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index 6cc7a42cc425..b882a210ee6e 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -12,7 +12,8 @@ #define m5206sim_h /****************************************************************************/ -#define CPU_NAME "COLDFIRE(m5206)" +#define CPU_NAME "COLDFIRE(m5206)" +#define CPU_INSTR_PER_JIFFY 3 /* * Define the 5206 SIM register set addresses. diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index afa211858ecb..85b39edf41a0 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -11,7 +11,8 @@ #define m520xsim_h /****************************************************************************/ -#define CPU_NAME "COLDFIRE(m520x)" +#define CPU_NAME "COLDFIRE(m520x)" +#define CPU_INSTR_PER_JIFFY 3 /* * Define the 520x SIM register set addresses. diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index 6a2c90d74d15..9d597dcb29c0 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -11,7 +11,8 @@ #define m523xsim_h /****************************************************************************/ -#define CPU_NAME "COLDFIRE(m523x)" +#define CPU_NAME "COLDFIRE(m523x)" +#define CPU_INSTR_PER_JIFFY 3 /* * Define the 523x SIM register set addresses. diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 6c49ed88845c..c107228728db 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -11,7 +11,8 @@ #define m5249sim_h /****************************************************************************/ -#define CPU_NAME "COLDFIRE(m5249)" +#define CPU_NAME "COLDFIRE(m5249)" +#define CPU_INSTR_PER_JIFFY 3 /* * Define the 5249 SIM register set addresses. diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index 7edef8fc1920..8cea714dee46 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -12,7 +12,8 @@ #define m5272sim_h /****************************************************************************/ -#define CPU_NAME "COLDFIRE(m5272)" +#define CPU_NAME "COLDFIRE(m5272)" +#define CPU_INSTR_PER_JIFFY 3 /* * Define the 5272 SIM register set addresses. diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 627156a1d96a..5223b71d3432 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -11,7 +11,8 @@ #define m527xsim_h /****************************************************************************/ -#define CPU_NAME "COLDFIRE(m527x)" +#define CPU_NAME "COLDFIRE(m527x)" +#define CPU_INSTR_PER_JIFFY 3 /* diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index 03a6d576787c..4e35f970f662 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -11,7 +11,8 @@ #define m528xsim_h /****************************************************************************/ -#define CPU_NAME "COLDFIRE(m528x)" +#define CPU_NAME "COLDFIRE(m528x)" +#define CPU_INSTR_PER_JIFFY 3 /* * Define the 5280/5282 SIM register set addresses. diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 3e06b8379a49..008f36bd66c3 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -14,7 +14,8 @@ #define m5307sim_h /****************************************************************************/ -#define CPU_NAME "COLDFIRE(m5307)" +#define CPU_NAME "COLDFIRE(m5307)" +#define CPU_INSTR_PER_JIFFY 3 /* * Define the 5307 SIM register set addresses. diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index 9f4688bcc454..b8126d3253e1 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -9,7 +9,8 @@ #define m532xsim_h /****************************************************************************/ -#define CPU_NAME "COLDFIRE(m532x)" +#define CPU_NAME "COLDFIRE(m532x)" +#define CPU_INSTR_PER_JIFFY 3 #define MCF_REG32(x) (*(volatile unsigned long *)(x)) #define MCF_REG16(x) (*(volatile unsigned short *)(x)) diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index 1de44c5affe0..e07d4d8cf31f 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -14,7 +14,8 @@ #define m5407sim_h /****************************************************************************/ -#define CPU_NAME "COLDFIRE(m5407)" +#define CPU_NAME "COLDFIRE(m5407)" +#define CPU_INSTR_PER_JIFFY 3 /* * Define the 5407 SIM register set addresses. diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index d69a64fd3bde..6072248916ac 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -5,9 +5,10 @@ #ifndef m54xxsim_h #define m54xxsim_h -#define CPU_NAME "COLDFIRE(m54xx)" +#define CPU_NAME "COLDFIRE(m54xx)" +#define CPU_INSTR_PER_JIFFY 2 -#define MCFINT_VECBASE 64 +#define MCFINT_VECBASE 64 /* * Interrupt Controller Registers diff --git a/arch/m68knommu/kernel/setup.c b/arch/m68knommu/kernel/setup.c index f48d9df484d3..5c931f9d392c 100644 --- a/arch/m68knommu/kernel/setup.c +++ b/arch/m68knommu/kernel/setup.c @@ -66,13 +66,20 @@ void (*mach_power_off)(void); #ifdef CONFIG_M68360 #define CPU_NAME "MC68360" #endif -/* - * The ColdFire CPU names are defined in their headers. - */ #ifndef CPU_NAME #define CPU_NAME "UNKNOWN" #endif +/* + * Different cores have different instruction execution timings. + * The old/traditional 68000 cores are basically all the same, at 16. + * The ColdFire cores vary a little, their values are defined in their + * headers. We default to the standard 68000 value here. + */ +#ifndef CPU_INSTR_PER_JIFFY +#define CPU_INSTR_PER_JIFFY 16 +#endif + extern int _stext, _etext, _sdata, _edata, _sbss, _ebss, _end; extern int _ramstart, _ramend; @@ -273,12 +280,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) cpu = CPU_NAME; mmu = "none"; fpu = "none"; - -#ifdef CONFIG_COLDFIRE - clockfreq = (loops_per_jiffy * HZ) * 3; -#else - clockfreq = (loops_per_jiffy * HZ) * 16; -#endif + clockfreq = (loops_per_jiffy * HZ) * CPU_INSTR_PER_JIFFY; seq_printf(m, "CPU:\t\t%s\n" "MMU:\t\t%s\n" -- cgit v1.2.3 From 57015421d3f3deafb1f6ccf03a6fe0539763dbee Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 3 Nov 2010 12:50:30 +1000 Subject: m68knommu: move UART addressing to part specific includes The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5206sim.h | 10 +++++++++- arch/m68k/include/asm/m520xsim.h | 9 ++++++++- arch/m68k/include/asm/m523xsim.h | 7 +++++++ arch/m68k/include/asm/m5249sim.h | 5 +++++ arch/m68k/include/asm/m5272sim.h | 3 +++ arch/m68k/include/asm/m527xsim.h | 6 ++++++ arch/m68k/include/asm/m528xsim.h | 7 +++++++ arch/m68k/include/asm/m5307sim.h | 11 ++++++++++ arch/m68k/include/asm/m532xsim.h | 7 +++++++ arch/m68k/include/asm/m5407sim.h | 3 +++ arch/m68k/include/asm/m54xxsim.h | 8 ++++++++ arch/m68k/include/asm/mcfuart.h | 43 ---------------------------------------- 12 files changed, 74 insertions(+), 45 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index b882a210ee6e..aa7ee48d5059 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -90,6 +90,14 @@ #define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */ #define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ +#if defined(CONFIG_NETtel) +#define MCFUART_BASE1 0x180 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#else +#define MCFUART_BASE1 0x140 /* Base address of UART1 */ +#define MCFUART_BASE2 0x180 /* Base address of UART2 */ +#endif + /* * Define system peripheral IRQ usage. */ @@ -97,7 +105,7 @@ #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ /* - * Generic GPIO + * Generic GPIO */ #define MCFGPIO_PIN_MAX 8 #define MCFGPIO_IRQ_VECBASE -1 diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index 85b39edf41a0..8cd8bce38594 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -100,6 +100,7 @@ #define MCFGPIO_PCLRR_UART 0xFC0A402A #define MCFGPIO_PCLRR_FECH 0xFC0A402B #define MCFGPIO_PCLRR_FECL 0xFC0A402C + /* * Generic GPIO support */ @@ -112,7 +113,6 @@ #define MCFGPIO_PIN_MAX 80 #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE -/****************************************************************************/ #define MCF_GPIO_PAR_UART (0xA4036) #define MCF_GPIO_PAR_FECI2C (0xA4033) @@ -128,6 +128,13 @@ #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) +/* + * UART module. + */ +#define MCFUART_BASE1 0x60000 /* Base address of UART1 */ +#define MCFUART_BASE2 0x64000 /* Base address of UART2 */ +#define MCFUART_BASE3 0x68000 /* Base address of UART2 */ + /* * Reset Controll Unit. */ diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index 9d597dcb29c0..4ec0f93a7ece 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -52,6 +52,13 @@ #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ +/* + * UART module. + */ +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x240 /* Base address of UART2 */ +#define MCFUART_BASE3 0x280 /* Base address of UART3 */ + #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index c107228728db..21d0bbfbc0c9 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -59,6 +59,11 @@ #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ +/* + * UART module. + */ +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ /* * Some symbol defines for the above... diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index 8cea714dee46..974c448c098e 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -65,6 +65,9 @@ #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ +#define MCFUART_BASE1 0x100 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ + #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ #define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 5223b71d3432..8a5a1ab57d01 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -58,6 +58,12 @@ #define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ #endif +/* + * UART module. + */ +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x240 /* Base address of UART2 */ +#define MCFUART_BASE3 0x280 /* Base address of UART3 */ #ifdef CONFIG_M5271 #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index 4e35f970f662..47c851ef78d3 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -43,6 +43,13 @@ #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ +/* + * UART module. + */ +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x240 /* Base address of UART2 */ +#define MCFUART_BASE3 0x280 /* Base address of UART3 */ + /* * GPIO registers */ diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 008f36bd66c3..7003d7268ae8 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -96,6 +96,17 @@ #define MCFSIM_PADDR (MCF_MBAR + 0x244) #define MCFSIM_PADAT (MCF_MBAR + 0x248) +/* + * UART module. + */ +#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ +#else +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ +#endif + /* * Generic GPIO support */ diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index b8126d3253e1..45c119c072db 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -103,6 +103,13 @@ #define ACR_CM_OFF_IMP (3<<5) #define ACR_WPROTECT (1<<2) +/* + * UART module. + */ +#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ +#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ +#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */ + /********************************************************************* * * Reset Controller Module diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index e07d4d8cf31f..ddfff88629fe 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -76,6 +76,9 @@ #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ + #define MCFSIM_PADDR (MCF_MBAR + 0x244) #define MCFSIM_PADAT (MCF_MBAR + 0x248) diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index 6072248916ac..a08a7ae776b1 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -24,6 +24,14 @@ #define MCFINTC_IACKL 0x19 /* */ #define MCFINTC_ICR0 0x40 /* Base ICR register */ +/* + * UART module. + */ +#define MCFUART_BASE1 0x8600 /* Base address of UART1 */ +#define MCFUART_BASE2 0x8700 /* Base address of UART2 */ +#define MCFUART_BASE3 0x8800 /* Base address of UART3 */ +#define MCFUART_BASE4 0x8900 /* Base address of UART4 */ + /* * Define system peripheral IRQ usage. */ diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h index c67dacad7c1c..2abedff0a694 100644 --- a/arch/m68k/include/asm/mcfuart.h +++ b/arch/m68k/include/asm/mcfuart.h @@ -12,49 +12,6 @@ #define mcfuart_h /****************************************************************************/ -/* - * Define the base address of the UARTS within the MBAR address - * space. - */ -#if defined(CONFIG_M5272) -#define MCFUART_BASE1 0x100 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ -#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#if defined(CONFIG_NETtel) -#define MCFUART_BASE1 0x180 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ -#else -#define MCFUART_BASE1 0x140 /* Base address of UART1 */ -#define MCFUART_BASE2 0x180 /* Base address of UART2 */ -#endif -#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ -#else -#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ -#define MCFUART_BASE2 0x200 /* Base address of UART2 */ -#endif -#elif defined(CONFIG_M520x) -#define MCFUART_BASE1 0x60000 /* Base address of UART1 */ -#define MCFUART_BASE2 0x64000 /* Base address of UART2 */ -#define MCFUART_BASE3 0x68000 /* Base address of UART2 */ -#elif defined(CONFIG_M532x) -#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ -#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ -#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ -#elif defined(CONFIG_M54xx) -#define MCFUART_BASE1 0x8600 /* on M54xx */ -#define MCFUART_BASE2 0x8700 /* on M54xx */ -#define MCFUART_BASE3 0x8800 /* on M54xx */ -#define MCFUART_BASE4 0x8900 /* on M54xx */ -#endif - - #include #include -- cgit v1.2.3 From 1c83af5f9d7e15a091f11394ad5916a7dcf1a99e Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Thu, 4 Nov 2010 13:53:26 +1000 Subject: m68knommu: use user stack pointer hardware on some ColdFire cores The more modern ColdFire parts (even if based on older version cores) have separate user and supervisor stack pointers (a7 register). Modify the ColdFire CPU setup and exception code to enable and use this on parts that have it. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/cacheflush_no.h | 4 +-- arch/m68k/include/asm/entry_no.h | 59 ++++++++++++++++++-------------- arch/m68k/include/asm/m54xxacr.h | 5 +++ arch/m68k/include/asm/mcfcache.h | 6 ++-- arch/m68k/include/asm/processor.h | 13 ++++--- arch/m68knommu/Kconfig | 10 ++++++ arch/m68knommu/platform/coldfire/entry.S | 30 ++++++---------- 7 files changed, 72 insertions(+), 55 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 9246392e1372..e295923020d3 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -37,7 +37,7 @@ static inline void __flush_cache_all(void) { #if defined(CONFIG_M523x) || defined(CONFIG_M527x) __asm__ __volatile__ ( - "movel #0x81400100, %%d0\n\t" + "movel #0x81400110, %%d0\n\t" "movec %%d0, %%CACR\n\t" "nop\n\t" : : : "d0" ); @@ -65,7 +65,7 @@ static inline void __flush_cache_all(void) #endif /* CONFIG_M5249 */ #ifdef CONFIG_M532x __asm__ __volatile__ ( - "movel #0x81000200, %%d0\n\t" + "movel #0x81000210, %%d0\n\t" "movec %%d0, %%CACR\n\t" "nop\n\t" : : : "d0" ); diff --git a/arch/m68k/include/asm/entry_no.h b/arch/m68k/include/asm/entry_no.h index 26be277394f9..627d69bacc58 100644 --- a/arch/m68k/include/asm/entry_no.h +++ b/arch/m68k/include/asm/entry_no.h @@ -42,12 +42,16 @@ */ #ifdef CONFIG_COLDFIRE +#ifdef CONFIG_COLDFIRE_SW_A7 /* - * This is made a little more tricky on the ColdFire. There is no - * separate kernel and user stack pointers. Need to artificially + * This is made a little more tricky on older ColdFires. There is no + * separate supervisor and user stack pointers. Need to artificially * construct a usp in software... When doing this we need to disable - * interrupts, otherwise bad things could happen. + * interrupts, otherwise bad things will happen. */ +.globl sw_usp +.globl sw_ksp + .macro SAVE_ALL move #0x2700,%sr /* disable intrs */ btst #5,%sp@(2) /* from user? */ @@ -74,9 +78,7 @@ 7: .endm -.macro RESTORE_ALL - btst #5,%sp@(PT_SR) /* going user? */ - bnes 8f /* no, skip */ +.macro RESTORE_USER move #0x2700,%sr /* disable intrs */ movel sw_usp,%a0 /* get usp */ movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */ @@ -91,19 +93,22 @@ subql #8,sw_usp /* set exception */ movel sw_usp,%sp /* restore usp */ rte - 8: - moveml %sp@,%d1-%d5/%a0-%a2 - lea %sp@(32),%sp /* space for 8 regs */ - movel %sp@+,%d0 - addql #4,%sp /* orig d0 */ - addl %sp@+,%sp /* stkadj */ - rte .endm +.macro RDUSP + movel sw_usp,%a2 +.endm + +.macro WRUSP + movel %a0,sw_usp +.endm + +#else /* !CONFIG_COLDFIRE_SW_A7 */ /* - * Quick exception save, use current stack only. + * Modern ColdFire parts have separate supervisor and user stack + * pointers. Simple load and restore macros for this case. */ -.macro SAVE_LOCAL +.macro SAVE_ALL move #0x2700,%sr /* disable intrs */ clrl %sp@- /* stkadj */ movel %d0,%sp@- /* orig d0 */ @@ -112,7 +117,7 @@ moveml %d1-%d5/%a0-%a2,%sp@ .endm -.macro RESTORE_LOCAL +.macro RESTORE_USER moveml %sp@,%d1-%d5/%a0-%a2 lea %sp@(32),%sp /* space for 8 regs */ movel %sp@+,%d0 @@ -121,6 +126,18 @@ rte .endm +.macro RDUSP + /*move %usp,%a2*/ + .word 0x4e6a +.endm + +.macro WRUSP + /*move %a0,%usp*/ + .word 0x4e60 +.endm + +#endif /* !CONFIG_COLDFIRE_SW_A7 */ + .macro SAVE_SWITCH_STACK lea %sp@(-24),%sp /* 6 regs */ moveml %a3-%a6/%d6-%d7,%sp@ @@ -131,14 +148,6 @@ lea %sp@(24),%sp /* 6 regs */ .endm -/* - * Software copy of the user and kernel stack pointers... Ugh... - * Need these to get around ColdFire not having separate kernel - * and user stack pointers. - */ -.globl sw_usp -.globl sw_ksp - #else /* !CONFIG_COLDFIRE */ /* @@ -167,6 +176,6 @@ moveml %sp@+,%a3-%a6/%d6-%d7 .endm -#endif /* !CONFIG_COLDFIRE */ +#endif /* !COLDFIRE_SW_A7 */ #endif /* __ASSEMBLY__ */ #endif /* __M68KNOMMU_ENTRY_H */ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 76d64906aa62..12209c68b904 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -26,6 +26,7 @@ #define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ #define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ +#define CACR_EUSP 0x00000020 /* Enable separate user a7 */ #define ACR_BASE_POS 24 /* Address Base */ #define ACR_MASK_POS 16 /* Address Mask */ @@ -67,7 +68,11 @@ /* Enable data store buffer */ /* outside ACRs : No cache, precise */ /* Enable instruction+branch caches */ +#if defined(CONFIG_M5407) #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC) +#else +#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) +#endif #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h index 1b66018461b8..437686b62fea 100644 --- a/arch/m68k/include/asm/mcfcache.h +++ b/arch/m68k/include/asm/mcfcache.h @@ -46,7 +46,7 @@ movec %d0,%ACR0 movel #0x00000000,%d0 /* no other regions cached */ movec %d0,%ACR1 - movel #0x80400100,%d0 /* configure cache */ + movel #0x80400110,%d0 /* configure cache */ movec %d0,%CACR /* enable cache */ nop .endm @@ -101,7 +101,7 @@ movec %d0,%ACR0 movel #0x00000000,%d0 /* no other regions cached */ movec %d0,%ACR1 - movel #0x80000200,%d0 /* setup cache mask */ + movel #0x80000210,%d0 /* setup cache mask */ movec %d0,%CACR /* enable cache */ nop .endm @@ -142,7 +142,7 @@ movec %d0,%ACR0 move.l #0x00000000,%d0 /* no other regions cached */ movec %d0,%ACR1 - move.l #0x80400000,%d0 /* enable 8K instruction cache */ + move.l #0x80400010,%d0 /* enable 8K instruction cache */ movec %d0,%CACR nop .endm diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h index 7a6a7590cc02..278c69bad57a 100644 --- a/arch/m68k/include/asm/processor.h +++ b/arch/m68k/include/asm/processor.h @@ -20,23 +20,26 @@ static inline unsigned long rdusp(void) { -#ifdef CONFIG_COLDFIRE +#ifdef CONFIG_COLDFIRE_SW_A7 extern unsigned int sw_usp; return sw_usp; #else - unsigned long usp; - __asm__ __volatile__("move %/usp,%0" : "=a" (usp)); + register unsigned long usp __asm__("a0"); + /* move %usp,%a0 */ + __asm__ __volatile__(".word 0x4e68" : "=a" (usp)); return usp; #endif } static inline void wrusp(unsigned long usp) { -#ifdef CONFIG_COLDFIRE +#ifdef CONFIG_COLDFIRE_SW_A7 extern unsigned int sw_usp; sw_usp = usp; #else - __asm__ __volatile__("move %0,%/usp" : : "a" (usp)); + register unsigned long a0 __asm__("a0") = usp; + /* move %a0,%usp */ + __asm__ __volatile__(".word 0x4e60" : : "a" (a0) ); #endif } diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index 266a39eebcad..e6f482d18d05 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -75,6 +75,10 @@ config GENERIC_CLOCKEVENTS config NO_IOPORT def_bool y +config COLDFIRE_SW_A7 + bool + default n + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -107,11 +111,13 @@ config M68360 config M5206 bool "MCF5206" + select COLDFIRE_SW_A7 help Motorola ColdFire 5206 processor support. config M5206e bool "MCF5206e" + select COLDFIRE_SW_A7 help Motorola ColdFire 5206e processor support. @@ -129,6 +135,7 @@ config M523x config M5249 bool "MCF5249" + select COLDFIRE_SW_A7 help Motorola ColdFire 5249 processor support. @@ -139,6 +146,7 @@ config M5271 config M5272 bool "MCF5272" + select COLDFIRE_SW_A7 help Motorola ColdFire 5272 processor support. @@ -155,6 +163,7 @@ config M528x config M5307 bool "MCF5307" + select COLDFIRE_SW_A7 help Motorola ColdFire 5307 processor support. @@ -165,6 +174,7 @@ config M532x config M5407 bool "MCF5407" + select COLDFIRE_SW_A7 help Motorola ColdFire 5407 processor support. diff --git a/arch/m68knommu/platform/coldfire/entry.S b/arch/m68knommu/platform/coldfire/entry.S index b9ce31966181..f90e6173ccd4 100644 --- a/arch/m68knommu/platform/coldfire/entry.S +++ b/arch/m68knommu/platform/coldfire/entry.S @@ -36,13 +36,16 @@ #include #include +#ifdef CONFIG_COLDFIRE_SW_A7 +/* + * Define software copies of the supervisor and user stack pointers. + */ .bss - sw_ksp: .long 0 - sw_usp: .long 0 +#endif /* CONFIG_COLDFIRE_SW_A7 */ .text @@ -52,6 +55,7 @@ sw_usp: .globl ret_from_signal .globl sys_call_table .globl inthandler +.globl fasthandler enosys: mov.l #sys_ni_syscall,%d3 @@ -138,20 +142,7 @@ Luser_return: jne Lwork_to_do /* still work to do */ Lreturn: - move #0x2700,%sr /* disable intrs */ - movel sw_usp,%a0 /* get usp */ - movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */ - movel %sp@(PT_OFF_FORMATVEC),%a0@- /* copy exception format/vector/sr */ - moveml %sp@,%d1-%d5/%a0-%a2 - lea %sp@(32),%sp /* space for 8 regs */ - movel %sp@+,%d0 - addql #4,%sp /* orig d0 */ - addl %sp@+,%sp /* stk adj */ - addql #8,%sp /* remove exception */ - movel %sp,sw_ksp /* save ksp */ - subql #8,sw_usp /* set exception */ - movel sw_usp,%sp /* restore usp */ - rte + RESTORE_USER Lwork_to_do: movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */ @@ -201,9 +192,8 @@ ENTRY(inthandler) */ ENTRY(resume) movel %a0, %d1 /* get prev thread in d1 */ - - movel sw_usp,%d0 /* save usp */ - movel %d0,%a0@(TASK_THREAD+THREAD_USP) + RDUSP + movel %a2,%a0@(TASK_THREAD+THREAD_USP) SAVE_SWITCH_STACK movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack pointer */ @@ -211,5 +201,5 @@ ENTRY(resume) RESTORE_SWITCH_STACK movel %a1@(TASK_THREAD+THREAD_USP),%a0 /* restore thread user stack */ - movel %a0, sw_usp + WRUSP rts -- cgit v1.2.3 From 63e83c8a52031555b1e724f98a33f1838dee6345 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Thu, 4 Nov 2010 16:17:43 +1000 Subject: m68knommu: remove empty __iounmap() it is no used The empty __iounmap() function is not used on m68knommu at all. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/io_no.h | 1 - arch/m68knommu/mm/kmap.c | 9 --------- 2 files changed, 10 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h index 6e2413e518cb..cf20f3097af6 100644 --- a/arch/m68k/include/asm/io_no.h +++ b/arch/m68k/include/asm/io_no.h @@ -145,7 +145,6 @@ static inline void io_insl(unsigned int addr, void *buf, int len) #define IOMAP_WRITETHROUGH 3 extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag); -extern void __iounmap(void *addr, unsigned long size); static inline void *ioremap(unsigned long physaddr, unsigned long size) { diff --git a/arch/m68knommu/mm/kmap.c b/arch/m68knommu/mm/kmap.c index 902c1dfda9e5..ece8d5ad4e6c 100644 --- a/arch/m68knommu/mm/kmap.c +++ b/arch/m68knommu/mm/kmap.c @@ -35,15 +35,6 @@ void iounmap(void *addr) { } -/* - * __iounmap unmaps nearly everything, so be careful - * it doesn't free currently pointer/page tables anymore but it - * wans't used anyway and might be added later. - */ -void __iounmap(void *addr, unsigned long size) -{ -} - /* * Set new cache mode for some kernel address space. * The caller must push data for that range itself, if such data may already -- cgit v1.2.3 From a12cf0a8c6e2763ac865aa31f296557e07432b8a Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 9 Nov 2010 10:12:29 +1000 Subject: m68knommu: create bit definitions for the version 2 ColdFire cache controller The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5206sim.h | 2 ++ arch/m68k/include/asm/m520xsim.h | 5 ++++ arch/m68k/include/asm/m523xsim.h | 2 ++ arch/m68k/include/asm/m5249sim.h | 2 ++ arch/m68k/include/asm/m5272sim.h | 2 ++ arch/m68k/include/asm/m527xsim.h | 1 + arch/m68k/include/asm/m528xsim.h | 2 ++ arch/m68k/include/asm/m52xxacr.h | 56 ++++++++++++++++++++++++++++++++++++++++ 8 files changed, 72 insertions(+) create mode 100644 arch/m68k/include/asm/m52xxacr.h (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index aa7ee48d5059..561b03b5ddf8 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -15,6 +15,8 @@ #define CPU_NAME "COLDFIRE(m5206)" #define CPU_INSTR_PER_JIFFY 3 +#include + /* * Define the 5206 SIM register set addresses. */ diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index 8cd8bce38594..88ed8239fe4e 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -14,6 +14,8 @@ #define CPU_NAME "COLDFIRE(m520x)" #define CPU_INSTR_PER_JIFFY 3 +#include + /* * Define the 520x SIM register set addresses. */ @@ -57,6 +59,9 @@ #define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ #define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ +/* + * EPORT and GPIO registers. + */ #define MCFEPORT_EPDDR 0xFC088002 #define MCFEPORT_EPDR 0xFC088004 #define MCFEPORT_EPPDR 0xFC088005 diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index 4ec0f93a7ece..4ad7a00257a8 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -14,6 +14,8 @@ #define CPU_NAME "COLDFIRE(m523x)" #define CPU_INSTR_PER_JIFFY 3 +#include + /* * Define the 523x SIM register set addresses. */ diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 21d0bbfbc0c9..4908b118f2fd 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -14,6 +14,8 @@ #define CPU_NAME "COLDFIRE(m5249)" #define CPU_INSTR_PER_JIFFY 3 +#include + /* * Define the 5249 SIM register set addresses. */ diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index 974c448c098e..b7cc50abc831 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -15,6 +15,8 @@ #define CPU_NAME "COLDFIRE(m5272)" #define CPU_INSTR_PER_JIFFY 3 +#include + /* * Define the 5272 SIM register set addresses. */ diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 8a5a1ab57d01..e8042e8bc003 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -14,6 +14,7 @@ #define CPU_NAME "COLDFIRE(m527x)" #define CPU_INSTR_PER_JIFFY 3 +#include /* * Define the 5270/5271 SIM register set addresses. diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index 47c851ef78d3..a6d2f4d9aaa0 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -14,6 +14,8 @@ #define CPU_NAME "COLDFIRE(m528x)" #define CPU_INSTR_PER_JIFFY 3 +#include + /* * Define the 5280/5282 SIM register set addresses. */ diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h new file mode 100644 index 000000000000..4c92d999ee01 --- /dev/null +++ b/arch/m68k/include/asm/m52xxacr.h @@ -0,0 +1,56 @@ +/****************************************************************************/ + +/* + * m52xxacr.h -- ColdFire version 2 core cache support + * + * (C) Copyright 2010, Greg Ungerer + */ + +/****************************************************************************/ +#ifndef m52xxacr_h +#define m52xxacr_h +/****************************************************************************/ + +/* + * All varients of the ColdFire using version 2 cores have a similar + * cache setup. Although not absolutely identical the cache register + * definitions are compatible for all of them. Mostly they support a + * configurable cache memory that can be instruction only, data only, + * or split instruction and data. The exception is the very old version 2 + * core based parts, like the 5206(e), 5249 and 5272, which are instruction + * cache only. Cache size varies from 2k up to 16k. + */ + +/* + * Define the Cache Control register flags. + */ +#define CACR_CENB 0x80000000 /* Enable cache */ +#define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */ +#define CACR_CFRZ 0x08000000 /* Cache freeze mode */ +#define CACR_CINV 0x01000000 /* Invalidate cache */ +#define CACR_DISI 0x00800000 /* Disable instruction cache */ +#define CACR_DISD 0x00400000 /* Disable data cache */ +#define CACR_INVI 0x00200000 /* Invalidate instruction cache */ +#define CACR_INVD 0x00100000 /* Invalidate data cache */ +#define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */ +#define CACR_DCM 0x00000200 /* Default cache mode */ +#define CACR_DBWE 0x00000100 /* Buffered write enable */ +#define CACR_DWP 0x00000020 /* Write protection */ +#define CACR_EUSP 0x00000010 /* Enable separate user a7 */ + +/* + * Define the Access Control register flags. + */ +#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */ +#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */ +#define ACR_ENABLE 0x00008000 /* Enable this ACR */ +#define ACR_USER 0x00000000 /* Allow only user accesses */ +#define ACR_SUPER 0x00002000 /* Allow supervisor access only */ +#define ACR_ANY 0x00004000 /* Allow any access type */ +#define ACR_CENB 0x00000000 /* Caching of region enabled */ +#define ACR_CDIS 0x00000040 /* Caching of region disabled */ +#define ACR_BWE 0x00000020 /* Write buffer enabled */ +#define ACR_WPROTECT 0x00000004 /* Write protect region */ + +/****************************************************************************/ +#endif /* m52xxsim_h */ -- cgit v1.2.3 From 278c2cbd59371bc8905d83b7cc3aa0bbe69c00f1 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 9 Nov 2010 10:19:45 +1000 Subject: m68knommu: merge bit definitions for version 3 ColdFire cache controller All version 3 based ColdFire CPU cores have a similar cache controller. Merge all the exitsing definitions into a single file, and make them similar in style and naming to the existing version 2 and version 4 cache controller definitions. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5307sim.h | 29 ++-------------------- arch/m68k/include/asm/m532xsim.h | 29 ++-------------------- arch/m68k/include/asm/m53xxacr.h | 52 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 54 deletions(-) create mode 100644 arch/m68k/include/asm/m53xxacr.h (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 7003d7268ae8..0bf57397e7a9 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -17,6 +17,8 @@ #define CPU_NAME "COLDFIRE(m5307)" #define CPU_INSTR_PER_JIFFY 3 +#include + /* * Define the 5307 SIM register set addresses. */ @@ -160,32 +162,5 @@ #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ -/* - * Define the Cache register flags. - */ -#define CACR_EC (1<<31) -#define CACR_ESB (1<<29) -#define CACR_DPI (1<<28) -#define CACR_HLCK (1<<27) -#define CACR_CINVA (1<<24) -#define CACR_DNFB (1<<10) -#define CACR_DCM_WTHRU (0<<8) -#define CACR_DCM_WBACK (1<<8) -#define CACR_DCM_OFF_PRE (2<<8) -#define CACR_DCM_OFF_IMP (3<<8) -#define CACR_DW (1<<5) - -#define ACR_BASE_POS 24 -#define ACR_MASK_POS 16 -#define ACR_ENABLE (1<<15) -#define ACR_USER (0<<13) -#define ACR_SUPER (1<<13) -#define ACR_ANY (2<<13) -#define ACR_CM_WTHRU (0<<5) -#define ACR_CM_WBACK (1<<5) -#define ACR_CM_OFF_PRE (2<<5) -#define ACR_CM_OFF_IMP (3<<5) -#define ACR_WPROTECT (1<<2) - /****************************************************************************/ #endif /* m5307sim_h */ diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index 45c119c072db..e6470f8ca324 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -12,6 +12,8 @@ #define CPU_NAME "COLDFIRE(m532x)" #define CPU_INSTR_PER_JIFFY 3 +#include + #define MCF_REG32(x) (*(volatile unsigned long *)(x)) #define MCF_REG16(x) (*(volatile unsigned short *)(x)) #define MCF_REG08(x) (*(volatile unsigned char *)(x)) @@ -76,33 +78,6 @@ #define MCF_IRQ_TIMER (64 + 32) /* Timer0 */ #define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */ -/* - * Define the Cache register flags. - */ -#define CACR_EC (1<<31) -#define CACR_ESB (1<<29) -#define CACR_DPI (1<<28) -#define CACR_HLCK (1<<27) -#define CACR_CINVA (1<<24) -#define CACR_DNFB (1<<10) -#define CACR_DCM_WTHRU (0<<8) -#define CACR_DCM_WBACK (1<<8) -#define CACR_DCM_OFF_PRE (2<<8) -#define CACR_DCM_OFF_IMP (3<<8) -#define CACR_DW (1<<5) - -#define ACR_BASE_POS 24 -#define ACR_MASK_POS 16 -#define ACR_ENABLE (1<<15) -#define ACR_USER (0<<13) -#define ACR_SUPER (1<<13) -#define ACR_ANY (2<<13) -#define ACR_CM_WTHRU (0<<5) -#define ACR_CM_WBACK (1<<5) -#define ACR_CM_OFF_PRE (2<<5) -#define ACR_CM_OFF_IMP (3<<5) -#define ACR_WPROTECT (1<<2) - /* * UART module. */ diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h new file mode 100644 index 000000000000..532fbb91185f --- /dev/null +++ b/arch/m68k/include/asm/m53xxacr.h @@ -0,0 +1,52 @@ +/****************************************************************************/ + +/* + * m53xxacr.h -- ColdFire version 3 core cache support + * + * (C) Copyright 2010, Greg Ungerer + */ + +/****************************************************************************/ +#ifndef m53xxacr_h +#define m53xxacr_h +/****************************************************************************/ + +/* + * All varients of the ColdFire using version 3 cores have a similar + * cache setup. They have a unified instruction and data cache, with + * configurable write-through or copy-back operation. + */ + +/* + * Define the Cache Control register flags. + */ +#define CACR_EC 0x80000000 /* Enable cache */ +#define CACR_ESB 0x20000000 /* Enable store buffer */ +#define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */ +#define CACR_HLCK 0x08000000 /* Half cache lock mode */ +#define CACR_CINVA 0x01000000 /* Invalidate cache */ +#define CACR_DNFB 0x00000400 /* Inhibited fill buffer */ +#define CACR_DCM_WT 0x00000000 /* Cacheable write-through */ +#define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */ +#define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */ +#define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */ +#define CACR_WPROTECT 0x00000020 /* Write protect*/ +#define CACR_EUSP 0x00000010 /* Eanble separate user a7 */ + +/* + * Define the Access Control register flags. + */ +#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */ +#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */ +#define ACR_ENABLE 0x00008000 /* Enable this ACR */ +#define ACR_USER 0x00000000 /* Allow only user accesses */ +#define ACR_SUPER 0x00002000 /* Allow supervisor access only */ +#define ACR_ANY 0x00004000 /* Allow any access type */ +#define ACR_CM_WT 0x00000000 /* Cacheable, write-through */ +#define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */ +#define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */ +#define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */ +#define ACR_WPROTECT 0x00000004 /* Write protect region */ + +/****************************************************************************/ +#endif /* m53xxsim_h */ -- cgit v1.2.3 From 3d461401eb5e3a8c471e92500aebd6c115273fba Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 9 Nov 2010 10:40:44 +1000 Subject: m68knommu: move inclusion of ColdFire v4 cache registers Move the inclusion of the version 4 cache controller registers so that it is with all the other register bit flag definitions. This makes it consistent with the other version core inclusion points, and means we don't need "#ifdef"ery in odd-ball places for these definitions. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/cacheflush_no.h | 4 +--- arch/m68k/include/asm/m5407sim.h | 2 ++ arch/m68k/include/asm/m54xxsim.h | 2 ++ arch/m68k/include/asm/mcfcache.h | 2 -- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index e295923020d3..52b11ac9a30c 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -5,9 +5,7 @@ * (C) Copyright 2000-2004, Greg Ungerer */ #include -#if defined(CONFIG_M5407) || defined(CONFIG_M54xx) -#include -#endif +#include #define flush_cache_all() __flush_cache_all() #define flush_cache_mm(mm) do { } while (0) diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index ddfff88629fe..75f5c28a551d 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -17,6 +17,8 @@ #define CPU_NAME "COLDFIRE(m5407)" #define CPU_INSTR_PER_JIFFY 3 +#include + /* * Define the 5407 SIM register set addresses. */ diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index a08a7ae776b1..462ae5328441 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -8,6 +8,8 @@ #define CPU_NAME "COLDFIRE(m54xx)" #define CPU_INSTR_PER_JIFFY 2 +#include + #define MCFINT_VECBASE 64 /* diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h index 437686b62fea..2b3a6cfaaac0 100644 --- a/arch/m68k/include/asm/mcfcache.h +++ b/arch/m68k/include/asm/mcfcache.h @@ -109,8 +109,6 @@ #if defined(CONFIG_M5407) || defined(CONFIG_M54xx) -#include - .macro CACHE_ENABLE /* invalidate whole cache */ movel #(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA),%d0 -- cgit v1.2.3 From 8ce877a8eb8293b5b2c07f259d694026b0f519e4 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 9 Nov 2010 13:35:55 +1000 Subject: m68knommu: clean up ColdFire cache control code The cache control code for the ColdFire CPU's is a big ugly mess of "#ifdef"ery liberally coated with bit constants. Clean it up. The cache controllers in the various ColdFire parts are actually quite similar. Just differing in some bit flags and options supported. Using the header defines now in place it is pretty easy to factor out the small differences and use common setup and flush/invalidate code. I have preserved the cache setups as they where in the old code (except where obviously wrong - like in the case of the 5249). Following from this it should be easy now to extend the possible setups used on the CACHE controllers that support split cacheing or copy-back or write through options. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/cacheflush_no.h | 40 ++------- arch/m68k/include/asm/m52xxacr.h | 27 ++++++ arch/m68k/include/asm/m53xxacr.h | 18 ++++ arch/m68k/include/asm/m54xxacr.h | 11 ++- arch/m68k/include/asm/mcfcache.h | 150 -------------------------------- arch/m68knommu/platform/coldfire/head.S | 26 ++++-- 6 files changed, 80 insertions(+), 192 deletions(-) delete mode 100644 arch/m68k/include/asm/mcfcache.h (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 52b11ac9a30c..8ada4ffc98e5 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -2,7 +2,7 @@ #define _M68KNOMMU_CACHEFLUSH_H /* - * (C) Copyright 2000-2004, Greg Ungerer + * (C) Copyright 2000-2010, Greg Ungerer */ #include #include @@ -10,7 +10,7 @@ #define flush_cache_all() __flush_cache_all() #define flush_cache_mm(mm) do { } while (0) #define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) __flush_cache_all() +#define flush_cache_range(vma, start, end) do { } while (0) #define flush_cache_page(vma, vmaddr) do { } while (0) #ifndef flush_dcache_range #define flush_dcache_range(start,len) __flush_cache_all() @@ -33,41 +33,13 @@ #ifndef __flush_cache_all static inline void __flush_cache_all(void) { -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) +#ifdef CACHE_INVALIDATE __asm__ __volatile__ ( - "movel #0x81400110, %%d0\n\t" + "movel %0, %%d0\n\t" "movec %%d0, %%CACR\n\t" "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M523x || CONFIG_M527x */ -#if defined(CONFIG_M528x) - __asm__ __volatile__ ( - "movel #0x81000200, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M528x */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) - __asm__ __volatile__ ( - "movel #0x81000100, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ -#ifdef CONFIG_M5249 - __asm__ __volatile__ ( - "movel #0xa1000200, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M5249 */ -#ifdef CONFIG_M532x - __asm__ __volatile__ ( - "movel #0x81000210, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M532x */ + : : "i" (CACHE_INVALIDATE) : "d0" ); +#endif } #endif /* __flush_cache_all */ diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h index 4c92d999ee01..52230b5e1e4d 100644 --- a/arch/m68k/include/asm/m52xxacr.h +++ b/arch/m68k/include/asm/m52xxacr.h @@ -52,5 +52,32 @@ #define ACR_BWE 0x00000020 /* Write buffer enabled */ #define ACR_WPROTECT 0x00000004 /* Write protect region */ +/* + * Set the cache controller settings we will use. This code is set to + * only use the instruction cache, even on the controllers that support + * split cache. (This setup is trying to preserve the existing behavior + * for now, in the furture I hope to actually use the split cache mode). + */ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M5249) || defined(CONFIG_M5272) +#define CACHE_INIT (CACR_CINV) +#define CACHE_MODE (CACR_CENB + CACR_DCM) +#else +#ifdef CONFIG_COLDFIRE_SW_A7 +#define CACHE_INIT (CACR_CINV + CACR_DISD) +#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM) +#else +#define CACHE_INIT (CACR_CINV + CACR_DISD + CACR_EUSP) +#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM + CACR_EUSP) +#endif +#endif + +#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) + +#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ + (0x000f0000) + \ + (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE)) +#define ACR1_MODE 0 + /****************************************************************************/ #endif /* m52xxsim_h */ diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h index 532fbb91185f..74c81c9b177e 100644 --- a/arch/m68k/include/asm/m53xxacr.h +++ b/arch/m68k/include/asm/m53xxacr.h @@ -48,5 +48,23 @@ #define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */ #define ACR_WPROTECT 0x00000004 /* Write protect region */ +/* + * Set the cache controller settings we will use. This default in the + * CACR is cache inhibited, we use the ACR register to set cacheing + * enabled on the regions we want (eg RAM). + */ +#ifdef CONFIG_COLDFIRE_SW_A7 +#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE) +#else +#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP) +#endif + +#define CACHE_INIT CACR_CINVA + +#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ + (0x000f0000) + \ + (ACR_ENABLE + ACR_ANY + ACR_CM_CB)) +#define ACR1_MODE 0 + /****************************************************************************/ #endif /* m53xxsim_h */ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 12209c68b904..3c81a7a34a8f 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -73,11 +73,16 @@ #else #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) #endif - #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) - #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) +#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) +#define ACR1_MODE 0 +#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) +#define ACR3_MODE 0 + #ifndef __ASSEMBLY__ #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT) @@ -112,7 +117,7 @@ static inline void __m54xx_flush_cache_all(void) : "i" (CACHE_LINE_SIZE), "i" (DCACHE_SIZE / CACHE_WAYS), "i" (CACHE_WAYS), - "i" (CACHE_MODE|CACR_DCINVA|CACR_BCINVA|CACR_ICINVA) + "i" (CACHE_INVALIDATE) : "d0", "a0" ); } diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h deleted file mode 100644 index 2b3a6cfaaac0..000000000000 --- a/arch/m68k/include/asm/mcfcache.h +++ /dev/null @@ -1,150 +0,0 @@ -/****************************************************************************/ - -/* - * mcfcache.h -- ColdFire CPU cache support code - * - * (C) Copyright 2004, Greg Ungerer - */ - -/****************************************************************************/ -#ifndef __M68KNOMMU_MCFCACHE_H -#define __M68KNOMMU_MCFCACHE_H -/****************************************************************************/ - - -/* - * The different ColdFire families have different cache arrangments. - * Everything from a small instruction only cache, to configurable - * data and/or instruction cache, to unified instruction/data, to - * harvard style separate instruction and data caches. - */ - -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) -/* - * Simple version 2 core cache. These have instruction cache only, - * we just need to invalidate it and enable it. - */ -.macro CACHE_ENABLE - movel #0x01000000,%d0 /* invalidate cache cmd */ - movec %d0,%CACR /* do invalidate cache */ - movel #0x80000100,%d0 /* setup cache mask */ - movec %d0,%CACR /* enable cache */ -.endm -#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ - -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) -/* - * New version 2 cores have a configurable split cache arrangement. - * For now I am just enabling instruction cache - but ultimately I - * think a split instruction/data cache would be better. - */ -.macro CACHE_ENABLE - movel #0x01400000,%d0 - movec %d0,%CACR /* invalidate cache */ - nop - movel #0x0000c000,%d0 /* set SDRAM cached only */ - movec %d0,%ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - movel #0x80400110,%d0 /* configure cache */ - movec %d0,%CACR /* enable cache */ - nop -.endm -#endif /* CONFIG_M523x || CONFIG_M527x */ - -#if defined(CONFIG_M528x) -.macro CACHE_ENABLE - nop - movel #0x01000000, %d0 - movec %d0, %CACR /* Invalidate cache */ - nop - movel #0x0000c020, %d0 /* Set SDRAM cached only */ - movec %d0, %ACR0 - movel #0x00000000, %d0 /* No other regions cached */ - movec %d0, %ACR1 - movel #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop -.endm -#endif /* CONFIG_M528x */ - -#if defined(CONFIG_M5249) || defined(CONFIG_M5307) -/* - * The version 3 core cache. Oddly enough the version 2 core 5249 - * has the same SDRAM and cache setup as the version 3 cores. - * This is a single unified instruction/data cache. - */ -.macro CACHE_ENABLE - movel #0x01000000,%d0 /* invalidate whole cache */ - movec %d0,%CACR - nop -#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3) - movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ -#else - movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */ -#endif - movec %d0,%ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - movel #0xa0000200,%d0 /* enable cache */ - movec %d0,%CACR - nop -.endm -#endif /* CONFIG_M5249 || CONFIG_M5307 */ - -#if defined(CONFIG_M532x) -.macro CACHE_ENABLE - movel #0x01000000,%d0 /* invalidate cache cmd */ - movec %d0,%CACR /* do invalidate cache */ - nop - movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */ - movec %d0,%ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - movel #0x80000210,%d0 /* setup cache mask */ - movec %d0,%CACR /* enable cache */ - nop -.endm -#endif /* CONFIG_M532x */ - -#if defined(CONFIG_M5407) || defined(CONFIG_M54xx) - -.macro CACHE_ENABLE - /* invalidate whole cache */ - movel #(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA),%d0 - movec %d0,%CACR - nop - /* addresses range for data cache : 0x00000000-0x0fffffff */ - movel #(0x000f0000+DATA_CACHE_MODE),%d0 /* set SDRAM cached */ - movec %d0, %ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0, %ACR1 - /* addresses range for instruction cache : 0x00000000-0x0fffffff */ - movel #(0x000f0000+INSN_CACHE_MODE),%d0 /* set SDRAM cached */ - movec %d0, %ACR2 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0, %ACR3 - /* enable caches */ - movel #(CACHE_MODE),%d0 - movec %d0,%CACR - nop -.endm -#endif /* CONFIG_M5407 || CONFIG_M54xx */ - -#if defined(CONFIG_M520x) -.macro CACHE_ENABLE - move.l #0x01000000,%d0 /* invalidate whole cache */ - movec %d0,%CACR - nop - move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ - movec %d0,%ACR0 - move.l #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - move.l #0x80400010,%d0 /* enable 8K instruction cache */ - movec %d0,%CACR - nop -.endm -#endif /* CONFIG_M520x */ - -/****************************************************************************/ -#endif /* __M68KNOMMU_MCFCACHE_H */ diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S index 0b2d7c7adf79..d5977909ae5f 100644 --- a/arch/m68knommu/platform/coldfire/head.S +++ b/arch/m68knommu/platform/coldfire/head.S @@ -3,7 +3,7 @@ /* * head.S -- common startup code for ColdFire CPUs. * - * (C) Copyright 1999-2006, Greg Ungerer . + * (C) Copyright 1999-2010, Greg Ungerer . */ /*****************************************************************************/ @@ -13,7 +13,6 @@ #include #include #include -#include #include #include @@ -173,10 +172,27 @@ _start: /* * Now that we know what the memory is, lets enable cache - * and get things moving. This is Coldfire CPU specific. + * and get things moving. This is Coldfire CPU specific. Not + * all version cores have identical cache register setup. But + * it is very similar. Define the exact settings in the headers + * then the code here is the same for all. */ - CACHE_ENABLE /* enable CPU cache */ - + movel #CACHE_INIT,%d0 /* invalidate whole cache */ + movec %d0,%CACR + nop + movel #ACR0_MODE,%d0 /* set RAM region for caching */ + movec %d0,%ACR0 + movel #ACR1_MODE,%d0 /* anything else to cache? */ + movec %d0,%ACR1 +#ifdef ACR2_MODE + movel #ACR2_MODE,%d0 + movec %d0,%ACR2 + movel #ACR3_MODE,%d0 + movec %d0,%ACR3 +#endif + movel #CACHE_MODE,%d0 /* enable cache */ + movec %d0,%CACR + nop #ifdef CONFIG_ROMFS_FS /* -- cgit v1.2.3 From d475e3e4739ce465df740b51decbbea3b1b51823 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 9 Nov 2010 14:27:50 +1000 Subject: m68knommu: make cache push code ColdFire generic Currently the code to push cache lines is only available to version 4 cores. Version 3 cores may also need to use this if we support copy- back caches on them. Move this code to make it more generic, and useful for all version ColdFire cores. With this in place we can now have a single cache_flush_all() code path that does all the right things on all version cores. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/cacheflush_no.h | 7 +++-- arch/m68k/include/asm/m54xxacr.h | 38 ++---------------------- arch/m68knommu/platform/coldfire/Makefile | 2 +- arch/m68knommu/platform/coldfire/cache.c | 48 +++++++++++++++++++++++++++++++ 4 files changed, 56 insertions(+), 39 deletions(-) create mode 100644 arch/m68knommu/platform/coldfire/cache.c (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 8ada4ffc98e5..f931e1829835 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -30,9 +30,13 @@ #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ memcpy(dst, src, len) -#ifndef __flush_cache_all +void mcf_cache_push(void); + static inline void __flush_cache_all(void) { +#ifdef CACHE_PUSH + mcf_cache_push(); +#endif #ifdef CACHE_INVALIDATE __asm__ __volatile__ ( "movel %0, %%d0\n\t" @@ -41,6 +45,5 @@ static inline void __flush_cache_all(void) : : "i" (CACHE_INVALIDATE) : "d0" ); #endif } -#endif /* __flush_cache_all */ #endif /* _M68KNOMMU_CACHEFLUSH_H */ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 3c81a7a34a8f..6bce82fdb9c3 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -83,46 +83,12 @@ #define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) #define ACR3_MODE 0 -#ifndef __ASSEMBLY__ - #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT) #define flush_dcache_range(a, l) do { asm("nop"); } while (0) #endif - -static inline void __m54xx_flush_cache_all(void) -{ - __asm__ __volatile__ ( #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) - /* - * Use cpushl to push and invalidate all cache lines. - * Gas doesn't seem to know how to generate the ColdFire - * cpushl instruction... Oh well, bit stuff it for now. - */ - "clrl %%d0\n\t" - "1:\n\t" - "movel %%d0,%%a0\n\t" - "2:\n\t" - ".word 0xf468\n\t" - "addl %0,%%a0\n\t" - "cmpl %1,%%a0\n\t" - "blt 2b\n\t" - "addql #1,%%d0\n\t" - "cmpil %2,%%d0\n\t" - "bne 1b\n\t" +/* Copyback cache mode must push dirty cache lines first */ +#define CACHE_PUSH #endif - "movel %3,%%d0\n\t" - "movec %%d0,%%CACR\n\t" - "nop\n\t" /* forces flush of Store Buffer */ - : /* No output */ - : "i" (CACHE_LINE_SIZE), - "i" (DCACHE_SIZE / CACHE_WAYS), - "i" (CACHE_WAYS), - "i" (CACHE_INVALIDATE) - : "d0", "a0" ); -} - -#define __flush_cache_all() __m54xx_flush_cache_all() - -#endif /* __ASSEMBLY__ */ #endif /* m54xxacr_h */ diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile index 53a27e1a7904..a8967baabd72 100644 --- a/arch/m68knommu/platform/coldfire/Makefile +++ b/arch/m68knommu/platform/coldfire/Makefile @@ -14,7 +14,7 @@ asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 -obj-$(CONFIG_COLDFIRE) += clk.o dma.o entry.o vectors.o +obj-$(CONFIG_COLDFIRE) += cache.o clk.o dma.o entry.o vectors.o obj-$(CONFIG_M5206) += timers.o intc.o obj-$(CONFIG_M5206e) += timers.o intc.o obj-$(CONFIG_M520x) += pit.o intc-simr.o diff --git a/arch/m68knommu/platform/coldfire/cache.c b/arch/m68knommu/platform/coldfire/cache.c new file mode 100644 index 000000000000..235d3c4f4f0f --- /dev/null +++ b/arch/m68knommu/platform/coldfire/cache.c @@ -0,0 +1,48 @@ +/***************************************************************************/ + +/* + * cache.c -- general ColdFire Cache maintainence code + * + * Copyright (C) 2010, Greg Ungerer (gerg@snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include + +/***************************************************************************/ +#ifdef CACHE_PUSH +/***************************************************************************/ + +/* + * Use cpushl to push all dirty cache lines back to memory. + * Older versions of GAS don't seem to know how to generate the + * ColdFire cpushl instruction... Oh well, bit stuff it for now. + */ + +void mcf_cache_push(void) +{ + __asm__ __volatile__ ( + "clrl %%d0\n\t" + "1:\n\t" + "movel %%d0,%%a0\n\t" + "2:\n\t" + ".word 0xf468\n\t" + "addl %0,%%a0\n\t" + "cmpl %1,%%a0\n\t" + "blt 2b\n\t" + "addql #1,%%d0\n\t" + "cmpil %2,%%d0\n\t" + "bne 1b\n\t" + : /* No output */ + : "i" (CACHE_LINE_SIZE), + "i" (DCACHE_SIZE / CACHE_WAYS), + "i" (CACHE_WAYS) + : "d0", "a0" ); +} + +/***************************************************************************/ +#endif /* CACHE_PUSH */ +/***************************************************************************/ -- cgit v1.2.3 From 0ef6c9b8f7bf62ea05be5b26ee14b18a116b0c2a Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 9 Nov 2010 15:31:08 +1000 Subject: m68knommu: support version 2 ColdFire split cache The newer version 2 ColdFire CPU cores support a configurable cache arrangement. The cache memory can be used as all instruction cache, all data cache, or split in half for both instruction and data caching. Support this setup via a Kconfig time menu that allows a kernel builder to choose the arrangement they want to use. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m52xxacr.h | 30 ++++++++++++++++-------------- arch/m68knommu/Kconfig | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 14 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h index 52230b5e1e4d..701f680bced9 100644 --- a/arch/m68k/include/asm/m52xxacr.h +++ b/arch/m68k/include/asm/m52xxacr.h @@ -53,23 +53,25 @@ #define ACR_WPROTECT 0x00000004 /* Write protect region */ /* - * Set the cache controller settings we will use. This code is set to - * only use the instruction cache, even on the controllers that support - * split cache. (This setup is trying to preserve the existing behavior - * for now, in the furture I hope to actually use the split cache mode). + * Set the cache controller settings we will use. On the cores that support + * a split cache configuration we allow all the combinations at Kconfig + * time. For those cores that only have an instruction cache we just set + * that as on. */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ - defined(CONFIG_M5249) || defined(CONFIG_M5272) -#define CACHE_INIT (CACR_CINV) -#define CACHE_MODE (CACR_CENB + CACR_DCM) +#if defined(CONFIG_CACHE_I) +#define CACHE_TYPE CACR_DISD +#elif defined(CONFIG_CACHE_D) +#define CACHE_TYPE CACR_DISI #else -#ifdef CONFIG_COLDFIRE_SW_A7 -#define CACHE_INIT (CACR_CINV + CACR_DISD) -#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM) -#else -#define CACHE_INIT (CACR_CINV + CACR_DISD + CACR_EUSP) -#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM + CACR_EUSP) +#define CACHE_TYPE #endif + +#if defined(CONFIG_HAVE_CACHE_SPLIT) +#define CACHE_INIT (CACR_CINV + CACHE_TYPE + CACR_EUSP) +#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM + CACR_EUSP) +#else +#define CACHE_INIT (CACR_CINV) +#define CACHE_MODE (CACR_CENB + CACR_DCM) #endif #define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index e6f482d18d05..61c29081b998 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -79,6 +79,9 @@ config COLDFIRE_SW_A7 bool default n +config HAVE_CACHE_SPLIT + bool + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -124,12 +127,14 @@ config M5206e config M520x bool "MCF520x" select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT help Freescale Coldfire 5207/5208 processor support. config M523x bool "MCF523x" select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT help Freescale Coldfire 5230/1/2/4/5 processor support @@ -141,6 +146,7 @@ config M5249 config M5271 bool "MCF5271" + select HAVE_CACHE_SPLIT help Freescale (Motorola) ColdFire 5270/5271 processor support. @@ -152,12 +158,14 @@ config M5272 config M5275 bool "MCF5275" + select HAVE_CACHE_SPLIT help Freescale (Motorola) ColdFire 5274/5275 processor support. config M528x bool "MCF528x" select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT help Motorola ColdFire 5280/5282 processor support. @@ -250,6 +258,30 @@ config OLDMASK Build support for the older revision ColdFire 5307 silicon. Specifically this is the 1H55J mask revision. +if HAVE_CACHE_SPLIT +choice + prompt "Split Cache Configuration" + default CACHE_I + +config CACHE_I + bool "Instruction" + help + Use all of the ColdFire CPU cache memory as an instruction cache. + +config CACHE_D + bool "Data" + help + Use all of the ColdFire CPU cache memory as a data cache. + +config CACHE_BOTH + bool "Both" + help + Split the ColdFire CPU cache, and use half as an instruction cache + and half as a data cache. +endchoice + +endif + comment "Platform" config PILOT3 -- cgit v1.2.3 From 4a5bae416562a8224707a1ff30e83ddab1474fb3 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 9 Nov 2010 16:00:17 +1000 Subject: m68knommu: support ColdFire caches that do copyback and write-through The version 3 and version 4 ColdFire cache controllers support both write-through and copy-back modes on the data cache. Allow for Kconfig time configuration of this, and set the cache mode appropriately. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m53xxacr.h | 8 +++++++- arch/m68k/include/asm/m54xxacr.h | 4 ++++ arch/m68knommu/Kconfig | 24 ++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h index 74c81c9b177e..d8b8dd68368f 100644 --- a/arch/m68k/include/asm/m53xxacr.h +++ b/arch/m68k/include/asm/m53xxacr.h @@ -53,6 +53,12 @@ * CACR is cache inhibited, we use the ACR register to set cacheing * enabled on the regions we want (eg RAM). */ +#if defined(CONFIG_CACHE_COPYBACK) +#define CACHE_TYPE ACR_CM_CB +#else +#define CACHE_TYPE ACR_CM_WT +#endif + #ifdef CONFIG_COLDFIRE_SW_A7 #define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE) #else @@ -63,7 +69,7 @@ #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ (0x000f0000) + \ - (ACR_ENABLE + ACR_ANY + ACR_CM_CB)) + (ACR_ENABLE + ACR_ANY + CACHE_TYPE)) #define ACR1_MODE 0 /****************************************************************************/ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 6bce82fdb9c3..29d4713f796b 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -73,7 +73,11 @@ #else #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) #endif +#if defined(CONFIG_CACHE_COPYBACK) +#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP) +#else #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) +#endif #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) #define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index 61c29081b998..89b12237e1ed 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -82,6 +82,9 @@ config COLDFIRE_SW_A7 config HAVE_CACHE_SPLIT bool +config HAVE_CACHE_CB + bool + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -172,27 +175,32 @@ config M528x config M5307 bool "MCF5307" select COLDFIRE_SW_A7 + select HAVE_CACHE_CB help Motorola ColdFire 5307 processor support. config M532x bool "MCF532x" + select HAVE_CACHE_CB help Freescale (Motorola) ColdFire 532x processor support. config M5407 bool "MCF5407" select COLDFIRE_SW_A7 + select HAVE_CACHE_CB help Motorola ColdFire 5407 processor support. config M547x bool "MCF547x" + select HAVE_CACHE_CB help Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support. config M548x bool "MCF548x" + select HAVE_CACHE_CB help Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. @@ -279,7 +287,23 @@ config CACHE_BOTH Split the ColdFire CPU cache, and use half as an instruction cache and half as a data cache. endchoice +endif + +if HAVE_CACHE_CB +choice + prompt "Data cache mode" + default CACHE_WRITETHRU +config CACHE_WRITETHRU + bool "Write-through" + help + The ColdFire CPU cache is set into Write-through mode. + +config CACHE_COPYBACK + bool "Copy-back" + help + The ColdFire CPU cache is set into Copy-back mode. +endchoice endif comment "Platform" -- cgit v1.2.3 From 07ffee59a756e3d16295fa1e0a4849c7a2273a13 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 10 Nov 2010 15:22:19 +1000 Subject: m68knommu: create optimal separate instruction and data cache for ColdFire Create separate functions to deal with instruction and data cache flushing. This way we can optimize them for the vairous cache types and arrangements used across the ColdFire family. For example the unified caches in the version 3 cores means we don't need to flush the instruction cache. For the version 2 cores that do not do data cacheing (or where we choose instruction cache only) we don't need to do any data flushing. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/cacheflush_no.h | 38 +++++++++++++++++++++++++++++++---- arch/m68k/include/asm/m52xxacr.h | 31 ++++++++++++++++++---------- arch/m68k/include/asm/m53xxacr.h | 27 ++++++++++++++++++++++++- arch/m68k/include/asm/m54xxacr.h | 7 +++---- 4 files changed, 83 insertions(+), 20 deletions(-) (limited to 'arch/m68k/include/asm') diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index f931e1829835..cb88aa96c4f1 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -12,14 +12,12 @@ #define flush_cache_dup_mm(mm) do { } while (0) #define flush_cache_range(vma, start, end) do { } while (0) #define flush_cache_page(vma, vmaddr) do { } while (0) -#ifndef flush_dcache_range -#define flush_dcache_range(start,len) __flush_cache_all() -#endif +#define flush_dcache_range(start, len) __flush_dcache_all() #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 #define flush_dcache_page(page) do { } while (0) #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define flush_icache_range(start,len) __flush_cache_all() +#define flush_icache_range(start, len) __flush_icache_all() #define flush_icache_page(vma,pg) do { } while (0) #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) #define flush_cache_vmap(start, end) do { } while (0) @@ -46,4 +44,36 @@ static inline void __flush_cache_all(void) #endif } +/* + * Some ColdFire parts implement separate instruction and data caches, + * on those we should just flush the appropriate cache. If we don't need + * to do any specific flushing then this will be optimized away. + */ +static inline void __flush_icache_all(void) +{ +#ifdef CACHE_INVALIDATEI + __asm__ __volatile__ ( + "movel %0, %%d0\n\t" + "movec %%d0, %%CACR\n\t" + "nop\n\t" + : : "i" (CACHE_INVALIDATEI) : "d0" ); +#endif +} + +static inline void __flush_dcache_all(void) +{ +#ifdef CACHE_PUSH + mcf_cache_push(); +#endif +#ifdef CACHE_INVALIDATED + __asm__ __volatile__ ( + "movel %0, %%d0\n\t" + "movec %%d0, %%CACR\n\t" + "nop\n\t" + : : "i" (CACHE_INVALIDATED) : "d0" ); +#else + /* Flush the wrtite buffer */ + __asm__ __volatile__ ( "nop" ); +#endif +} #endif /* _M68KNOMMU_CACHEFLUSH_H */ diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h index 701f680bced9..abc391a9ae8d 100644 --- a/arch/m68k/include/asm/m52xxacr.h +++ b/arch/m68k/include/asm/m52xxacr.h @@ -59,22 +59,31 @@ * that as on. */ #if defined(CONFIG_CACHE_I) -#define CACHE_TYPE CACR_DISD +#define CACHE_TYPE (CACR_DISD + CACR_EUSP) +#define CACHE_INVTYPEI 0 #elif defined(CONFIG_CACHE_D) -#define CACHE_TYPE CACR_DISI +#define CACHE_TYPE (CACR_DISI + CACR_EUSP) +#define CACHE_INVTYPED 0 +#elif defined(CONFIG_CACHE_BOTH) +#define CACHE_TYPE CACR_EUSP +#define CACHE_INVTYPEI CACR_INVI +#define CACHE_INVTYPED CACR_INVD #else -#define CACHE_TYPE +/* This is the instruction cache only devices (no split cache, no eusp) */ +#define CACHE_TYPE 0 +#define CACHE_INVTYPEI 0 #endif -#if defined(CONFIG_HAVE_CACHE_SPLIT) -#define CACHE_INIT (CACR_CINV + CACHE_TYPE + CACR_EUSP) -#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM + CACR_EUSP) -#else -#define CACHE_INIT (CACR_CINV) -#define CACHE_MODE (CACR_CENB + CACR_DCM) -#endif +#define CACHE_INIT (CACR_CINV + CACHE_TYPE) +#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM) -#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) +#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) +#if defined(CACHE_INVTYPEI) +#define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI) +#endif +#if defined(CACHE_INVTYPED) +#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED) +#endif #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ (0x000f0000) + \ diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h index d8b8dd68368f..cd952b0a8bd3 100644 --- a/arch/m68k/include/asm/m53xxacr.h +++ b/arch/m68k/include/asm/m53xxacr.h @@ -48,6 +48,22 @@ #define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */ #define ACR_WPROTECT 0x00000004 /* Write protect region */ +/* + * Define the cache type and arrangement (needed for pushes). + */ +#if defined(CONFIG_M5307) +#define CACHE_SIZE 0x2000 /* 8k of unified cache */ +#define ICACHE_SIZE CACHE_SIZE +#define DCACHE_SIZE CACHE_SIZE +#elif defined(CONFIG_M532x) +#define CACHE_SIZE 0x4000 /* 32k of unified cache */ +#define ICACHE_SIZE CACHE_SIZE +#define DCACHE_SIZE CACHE_SIZE +#endif + +#define CACHE_LINE_SIZE 16 /* 16 byte line size */ +#define CACHE_WAYS 4 /* 4 ways - set associative */ + /* * Set the cache controller settings we will use. This default in the * CACR is cache inhibited, we use the ACR register to set cacheing @@ -55,6 +71,7 @@ */ #if defined(CONFIG_CACHE_COPYBACK) #define CACHE_TYPE ACR_CM_CB +#define CACHE_PUSH #else #define CACHE_TYPE ACR_CM_WT #endif @@ -65,7 +82,15 @@ #define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP) #endif -#define CACHE_INIT CACR_CINVA +/* + * Unified cache means we will never need to flush for coherency of + * instruction fetch. We will need to flush to maintain memory/DMA + * coherency though in all cases. And for copyback caches we will need + * to push cached data as well. + */ +#define CACHE_INIT CACR_CINVA +#define CACHE_INVALIDATE CACR_CINVA +#define CACHE_INVALIDATED CACR_CINVA #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ (0x000f0000) + \ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 29d4713f796b..16a1835f9b2a 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -81,15 +81,14 @@ #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) #define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) -#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) #define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) #define ACR1_MODE 0 #define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) #define ACR3_MODE 0 -#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT) -#define flush_dcache_range(a, l) do { asm("nop"); } while (0) -#endif #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) /* Copyback cache mode must push dirty cache lines first */ #define CACHE_PUSH -- cgit v1.2.3