From 6c7a2676f594ca9a30203b4fd5dc26b53682cffe Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 9 Dec 2011 10:45:20 +0100 Subject: microblaze: Change NO_IRQ to 0 As has been discussed many times[1], Using NO_IRQ set to anything other than 0 is bug waiting to happen since many drivers follow the pattern "if (!irq)" for testing whether or not an irq has been set. This patch changes the Microblaze NO_IRQ setting from -1 to 0 to bring it in line with most of the rest of the kernel. It also prepares for Microblaze eventually supporting multiple interrupt controllers by breaking the assumption that hwirq# == Linux IRQ#. The Linux IRQ number is just a cookie with no guarantee of a direct relationship with the hardware irq arrangement. At this point, Microblaze interrupt handling only supports only one instance of one kind of interrupt controller (xilinx_intc). This change shouldn't affect any architecture code outside of the interrupt controller driver and the irq_of mapping. Updated to 3.2 and to use irq_data.hwirq by Rob Herring. Tested and fixed by Michal Simek. [1] http://lkml.org/lkml/2005/11/21/221 Signed-off-by: Grant Likely Signed-off-by: Rob Herring Signed-off-by: Michal Simek --- arch/microblaze/kernel/intc.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) (limited to 'arch/microblaze/kernel/intc.c') diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c index 1293098ff70d..44b177e2ab12 100644 --- a/arch/microblaze/kernel/intc.c +++ b/arch/microblaze/kernel/intc.c @@ -42,8 +42,9 @@ unsigned int nr_irq; static void intc_enable_or_unmask(struct irq_data *d) { - unsigned long mask = 1 << d->irq; - pr_debug("enable_or_unmask: %d\n", d->irq); + unsigned long mask = 1 << d->hwirq; + + pr_debug("enable_or_unmask: %ld\n", d->hwirq); out_be32(INTC_BASE + SIE, mask); /* ack level irqs because they can't be acked during @@ -56,20 +57,21 @@ static void intc_enable_or_unmask(struct irq_data *d) static void intc_disable_or_mask(struct irq_data *d) { - pr_debug("disable: %d\n", d->irq); - out_be32(INTC_BASE + CIE, 1 << d->irq); + pr_debug("disable: %ld\n", d->hwirq); + out_be32(INTC_BASE + CIE, 1 << d->hwirq); } static void intc_ack(struct irq_data *d) { - pr_debug("ack: %d\n", d->irq); - out_be32(INTC_BASE + IAR, 1 << d->irq); + pr_debug("ack: %ld\n", d->hwirq); + out_be32(INTC_BASE + IAR, 1 << d->hwirq); } static void intc_mask_ack(struct irq_data *d) { - unsigned long mask = 1 << d->irq; - pr_debug("disable_and_ack: %d\n", d->irq); + unsigned long mask = 1 << d->hwirq; + + pr_debug("disable_and_ack: %ld\n", d->hwirq); out_be32(INTC_BASE + CIE, mask); out_be32(INTC_BASE + IAR, mask); } @@ -91,7 +93,7 @@ unsigned int get_irq(struct pt_regs *regs) * order to handle multiple interrupt controllers. It currently * is hardcoded to check for interrupts only on the first INTC. */ - irq = in_be32(INTC_BASE + IVR); + irq = in_be32(INTC_BASE + IVR) + NO_IRQ_OFFSET; pr_debug("get_irq: %d\n", irq); return irq; @@ -116,8 +118,7 @@ void __init init_IRQ(void) intc = of_find_compatible_node(NULL, NULL, "xlnx,xps-intc-1.00.a"); BUG_ON(!intc); - intc_baseaddr = be32_to_cpup(of_get_property(intc, - "reg", NULL)); + intc_baseaddr = be32_to_cpup(of_get_property(intc, "reg", NULL)); intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE); nr_irq = be32_to_cpup(of_get_property(intc, "xlnx,num-intr-inputs", NULL)); @@ -145,8 +146,8 @@ void __init init_IRQ(void) /* Turn on the Master Enable. */ out_be32(intc_baseaddr + MER, MER_HIE | MER_ME); - for (i = 0; i < nr_irq; ++i) { - if (intr_mask & (0x00000001 << i)) { + for (i = IRQ_OFFSET; i < (nr_irq + IRQ_OFFSET); ++i) { + if (intr_mask & (0x00000001 << (i - IRQ_OFFSET))) { irq_set_chip_and_handler_name(i, &intc_dev, handle_edge_irq, "edge"); irq_clear_status_flags(i, IRQ_LEVEL); @@ -155,5 +156,6 @@ void __init init_IRQ(void) handle_level_irq, "level"); irq_set_status_flags(i, IRQ_LEVEL); } + irq_get_irq_data(i)->hwirq = i - IRQ_OFFSET; } } -- cgit v1.2.3